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PCI: Fix whitespace, capitalization, and spelling errors
[deliverable/linux.git] / drivers / pci / host / pcie-designware.c
CommitLineData
340cba60 1/*
4b1ced84 2 * Synopsys Designware PCIe host controller driver
340cba60
JH		 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
f342d940
JH		 14#include <linux/irq.h>
15#include <linux/irqdomain.h>
340cba60 16#include <linux/kernel.h>
340cba60 17#include <linux/module.h>
f342d940 18#include <linux/msi.h>
340cba60 19#include <linux/of_address.h>
340cba60
JH		 20#include <linux/pci.h>
21#include <linux/pci_regs.h>
340cba60
JH		 22#include <linux/types.h>
23
4b1ced84 24#include "pcie-designware.h"
340cba60
JH		 25
26/* Synopsis specific PCIE configuration registers */
27#define PCIE_PORT_LINK_CONTROL 0x710
28#define PORT_LINK_MODE_MASK (0x3f << 16)
4b1ced84
JH		 29#define PORT_LINK_MODE_1_LANES (0x1 << 16)
30#define PORT_LINK_MODE_2_LANES (0x3 << 16)
340cba60
JH		 31#define PORT_LINK_MODE_4_LANES (0x7 << 16)
32
33#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
34#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
35#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
4b1ced84
JH		 36#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
37#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
38#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
340cba60
JH		 39
40#define PCIE_MSI_ADDR_LO 0x820
41#define PCIE_MSI_ADDR_HI 0x824
42#define PCIE_MSI_INTR0_ENABLE 0x828
43#define PCIE_MSI_INTR0_MASK 0x82C
44#define PCIE_MSI_INTR0_STATUS 0x830
45
46#define PCIE_ATU_VIEWPORT 0x900
47#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
48#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
49#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
50#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
51#define PCIE_ATU_CR1 0x904
52#define PCIE_ATU_TYPE_MEM (0x0 << 0)
53#define PCIE_ATU_TYPE_IO (0x2 << 0)
54#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
55#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
56#define PCIE_ATU_CR2 0x908
57#define PCIE_ATU_ENABLE (0x1 << 31)
58#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
59#define PCIE_ATU_LOWER_BASE 0x90C
60#define PCIE_ATU_UPPER_BASE 0x910
61#define PCIE_ATU_LIMIT 0x914
62#define PCIE_ATU_LOWER_TARGET 0x918
63#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
64#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
65#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
66#define PCIE_ATU_UPPER_TARGET 0x91C
67
4b1ced84
JH		 68static struct hw_pci dw_pci;
69
73e40850 70static unsigned long global_io_offset;
340cba60
JH		 71
72static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
73{
74 return sys->private_data;
75}
76
4b1ced84 77int cfg_read(void __iomem *addr, int where, int size, u32 *val)
340cba60
JH		 78{
79 *val = readl(addr);
80
81 if (size == 1)
82 *val = (*val >> (8 * (where & 3))) & 0xff;
83 else if (size == 2)
84 *val = (*val >> (8 * (where & 3))) & 0xffff;
85 else if (size != 4)
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87
88 return PCIBIOS_SUCCESSFUL;
89}
90
4b1ced84 91int cfg_write(void __iomem *addr, int where, int size, u32 val)
340cba60
JH		 92{
93 if (size == 4)
94 writel(val, addr);
95 else if (size == 2)
96 writew(val, addr + (where & 2));
97 else if (size == 1)
98 writeb(val, addr + (where & 3));
99 else
100 return PCIBIOS_BAD_REGISTER_NUMBER;
101
102 return PCIBIOS_SUCCESSFUL;
103}
104
f7b7868c 105static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
340cba60 106{
4b1ced84 107 if (pp->ops->readl_rc)
f7b7868c 108 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
4b1ced84 109 else
f7b7868c 110 *val = readl(pp->dbi_base + reg);
340cba60
JH		 111}
112
f7b7868c 113static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
340cba60 114{
4b1ced84 115 if (pp->ops->writel_rc)
f7b7868c 116 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
4b1ced84 117 else
f7b7868c 118 writel(val, pp->dbi_base + reg);
340cba60
JH		 119}
120
73e40850
BH		 121static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
122 u32 *val)
340cba60
JH		 123{
124 int ret;
125
4b1ced84
JH		 126 if (pp->ops->rd_own_conf)
127 ret = pp->ops->rd_own_conf(pp, where, size, val);
128 else
129 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
130
340cba60
JH		 131 return ret;
132}
133
73e40850
BH		 134static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
135 u32 val)
340cba60
JH		 136{
137 int ret;
138
4b1ced84
JH		 139 if (pp->ops->wr_own_conf)
140 ret = pp->ops->wr_own_conf(pp, where, size, val);
141 else
142 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
143 val);
144
340cba60
JH		 145 return ret;
146}
147
f342d940
JH		 148static struct irq_chip dw_msi_irq_chip = {
149 .name = "PCI-MSI",
150 .irq_enable = unmask_msi_irq,
151 .irq_disable = mask_msi_irq,
152 .irq_mask = mask_msi_irq,
153 .irq_unmask = unmask_msi_irq,
154};
155
156/* MSI int handler */
157void dw_handle_msi_irq(struct pcie_port *pp)
158{
159 unsigned long val;
904d0e78 160 int i, pos, irq;
f342d940
JH		 161
162 for (i = 0; i < MAX_MSI_CTRLS; i++) {
163 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
164 (u32 *)&val);
165 if (val) {
166 pos = 0;
167 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
904d0e78
PA		 168 irq = irq_find_mapping(pp->irq_domain,
169 i * 32 + pos);
170 generic_handle_irq(irq);
f342d940
JH		 171 pos++;
172 }
173 }
174 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
175 }
176}
177
178void dw_pcie_msi_init(struct pcie_port *pp)
179{
180 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
181
182 /* program the msi_data */
183 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
184 virt_to_phys((void *)pp->msi_data));
185 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
186}
187
188static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
189{
190 int flag = 1;
191
192 do {
193 pos = find_next_zero_bit(pp->msi_irq_in_use,
194 MAX_MSI_IRQS, pos);
195 /*if you have reached to the end then get out from here.*/
196 if (pos == MAX_MSI_IRQS)
197 return -ENOSPC;
198 /*
199 * Check if this position is at correct offset.nvec is always a
f7625980 200 * power of two. pos0 must be nvec bit aligned.
f342d940
JH		 201 */
202 if (pos % msgvec)
203 pos += msgvec - (pos % msgvec);
204 else
205 flag = 0;
206 } while (flag);
207
208 *pos0 = pos;
209 return 0;
210}
211
212static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
213{
214 int res, bit, irq, pos0, pos1, i;
215 u32 val;
216 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
217
218 if (!pp) {
219 BUG();
220 return -EINVAL;
221 }
222
223 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
224 MAX_MSI_IRQS);
225 if (pos0 % no_irqs) {
226 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
227 goto no_valid_irq;
228 }
229 if (no_irqs > 1) {
230 pos1 = find_next_bit(pp->msi_irq_in_use,
231 MAX_MSI_IRQS, pos0);
232 /* there must be nvec number of consecutive free bits */
233 while ((pos1 - pos0) < no_irqs) {
234 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
235 goto no_valid_irq;
236 pos1 = find_next_bit(pp->msi_irq_in_use,
237 MAX_MSI_IRQS, pos0);
238 }
239 }
240
904d0e78
PA		 241 irq = irq_find_mapping(pp->irq_domain, pos0);
242 if (!irq)
f342d940
JH		 243 goto no_valid_irq;
244
245 i = 0;
246 while (i < no_irqs) {
247 set_bit(pos0 + i, pp->msi_irq_in_use);
248 irq_alloc_descs((irq + i), (irq + i), 1, 0);
249 irq_set_msi_desc(irq + i, desc);
250 /*Enable corresponding interrupt in MSI interrupt controller */
251 res = ((pos0 + i) / 32) * 12;
252 bit = (pos0 + i) % 32;
253 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
254 val |= 1 << bit;
255 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
256 i++;
257 }
258
259 *pos = pos0;
260 return irq;
261
262no_valid_irq:
263 *pos = pos0;
264 return -ENOSPC;
265}
266
267static void clear_irq(unsigned int irq)
268{
269 int res, bit, val, pos;
270 struct irq_desc *desc;
271 struct msi_desc *msi;
272 struct pcie_port *pp;
904d0e78 273 struct irq_data *data = irq_get_irq_data(irq);
f342d940
JH		 274
275 /* get the port structure */
276 desc = irq_to_desc(irq);
277 msi = irq_desc_get_msi_desc(desc);
278 pp = sys_to_pcie(msi->dev->bus->sysdata);
279 if (!pp) {
280 BUG();
281 return;
282 }
283
904d0e78 284 pos = data->hwirq;
f342d940
JH		 285
286 irq_free_desc(irq);
287
288 clear_bit(pos, pp->msi_irq_in_use);
289
290 /* Disable corresponding interrupt on MSI interrupt controller */
291 res = (pos / 32) * 12;
292 bit = pos % 32;
293 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
294 val &= ~(1 << bit);
295 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
296}
297
298static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
299 struct msi_desc *desc)
300{
301 int irq, pos, msgvec;
302 u16 msg_ctr;
303 struct msi_msg msg;
304 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
305
306 if (!pp) {
307 BUG();
308 return -EINVAL;
309 }
310
311 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
312 &msg_ctr);
313 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
314 if (msgvec == 0)
315 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
316 if (msgvec > 5)
317 msgvec = 0;
318
319 irq = assign_irq((1 << msgvec), desc, &pos);
320 if (irq < 0)
321 return irq;
322
323 msg_ctr &= ~PCI_MSI_FLAGS_QSIZE;
324 msg_ctr |= msgvec << 4;
325 pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
326 msg_ctr);
327 desc->msi_attrib.multiple = msgvec;
328
329 msg.address_lo = virt_to_phys((void *)pp->msi_data);
330 msg.address_hi = 0x0;
331 msg.data = pos;
332 write_msi_msg(irq, &msg);
333
334 return 0;
335}
336
337static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
338{
339 clear_irq(irq);
340}
341
342static struct msi_chip dw_pcie_msi_chip = {
343 .setup_irq = dw_msi_setup_irq,
344 .teardown_irq = dw_msi_teardown_irq,
345};
346
4b1ced84
JH		 347int dw_pcie_link_up(struct pcie_port *pp)
348{
349 if (pp->ops->link_up)
350 return pp->ops->link_up(pp);
351 else
352 return 0;
353}
354
f342d940
JH		 355static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
356 irq_hw_number_t hwirq)
357{
358 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
359 irq_set_chip_data(irq, domain->host_data);
360 set_irq_flags(irq, IRQF_VALID);
361
362 return 0;
363}
364
365static const struct irq_domain_ops msi_domain_ops = {
366 .map = dw_pcie_msi_map,
367};
368
4b1ced84
JH		 369int __init dw_pcie_host_init(struct pcie_port *pp)
370{
371 struct device_node *np = pp->dev->of_node;
372 struct of_pci_range range;
373 struct of_pci_range_parser parser;
374 u32 val;
904d0e78 375 int i;
f342d940 376
4b1ced84
JH		 377 if (of_pci_range_parser_init(&parser, np)) {
378 dev_err(pp->dev, "missing ranges property\n");
379 return -EINVAL;
380 }
381
382 /* Get the I/O and memory ranges from DT */
383 for_each_of_pci_range(&parser, &range) {
384 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
385 if (restype == IORESOURCE_IO) {
386 of_pci_range_to_resource(&range, np, &pp->io);
387 pp->io.name = "I/O";
388 pp->io.start = max_t(resource_size_t,
389 PCIBIOS_MIN_IO,
390 range.pci_addr + global_io_offset);
391 pp->io.end = min_t(resource_size_t,
392 IO_SPACE_LIMIT,
393 range.pci_addr + range.size
394 + global_io_offset);
395 pp->config.io_size = resource_size(&pp->io);
396 pp->config.io_bus_addr = range.pci_addr;
397 }
398 if (restype == IORESOURCE_MEM) {
399 of_pci_range_to_resource(&range, np, &pp->mem);
400 pp->mem.name = "MEM";
401 pp->config.mem_size = resource_size(&pp->mem);
402 pp->config.mem_bus_addr = range.pci_addr;
403 }
404 if (restype == 0) {
405 of_pci_range_to_resource(&range, np, &pp->cfg);
406 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
407 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
408 }
409 }
410
411 if (!pp->dbi_base) {
412 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
413 resource_size(&pp->cfg));
414 if (!pp->dbi_base) {
415 dev_err(pp->dev, "error with ioremap\n");
416 return -ENOMEM;
417 }
418 }
419
420 pp->cfg0_base = pp->cfg.start;
421 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
422 pp->io_base = pp->io.start;
423 pp->mem_base = pp->mem.start;
424
425 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
426 pp->config.cfg0_size);
427 if (!pp->va_cfg0_base) {
428 dev_err(pp->dev, "error with ioremap in function\n");
429 return -ENOMEM;
430 }
431 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
432 pp->config.cfg1_size);
433 if (!pp->va_cfg1_base) {
434 dev_err(pp->dev, "error with ioremap\n");
435 return -ENOMEM;
436 }
437
438 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
439 dev_err(pp->dev, "Failed to parse the number of lanes\n");
440 return -EINVAL;
441 }
442
f342d940 443 if (IS_ENABLED(CONFIG_PCI_MSI)) {
904d0e78 444 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
f342d940
JH		 445 MAX_MSI_IRQS, &msi_domain_ops,
446 &dw_pcie_msi_chip);
904d0e78 447 if (!pp->irq_domain) {
f342d940
JH		 448 dev_err(pp->dev, "irq domain init failed\n");
449 return -ENXIO;
450 }
451
904d0e78
PA		 452 for (i = 0; i < MAX_MSI_IRQS; i++)
453 irq_create_mapping(pp->irq_domain, i);
f342d940
JH		 454 }
455
4b1ced84
JH		 456 if (pp->ops->host_init)
457 pp->ops->host_init(pp);
458
459 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
460
461 /* program correct class for RC */
462 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
463
464 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
465 val |= PORT_LOGIC_SPEED_CHANGE;
466 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
467
468 dw_pci.nr_controllers = 1;
469 dw_pci.private_data = (void **)&pp;
470
471 pci_common_init(&dw_pci);
472 pci_assign_unassigned_resources();
473#ifdef CONFIG_PCI_DOMAINS
474 dw_pci.domain++;
475#endif
476
477 return 0;
478}
479
480static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
340cba60 481{
340cba60 482 /* Program viewport 0 : OUTBOUND : CFG0 */
f7b7868c
SJ		 483 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
484 PCIE_ATU_VIEWPORT);
485 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
486 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 487 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
f7b7868c
SJ		 488 PCIE_ATU_LIMIT);
489 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
490 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
491 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
492 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
340cba60
JH		 493}
494
4b1ced84 495static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
340cba60 496{
340cba60 497 /* Program viewport 1 : OUTBOUND : CFG1 */
f7b7868c
SJ		 498 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
499 PCIE_ATU_VIEWPORT);
500 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
501 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
502 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
503 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 504 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
f7b7868c
SJ		 505 PCIE_ATU_LIMIT);
506 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
507 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
340cba60
JH		 508}
509
4b1ced84 510static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
340cba60 511{
340cba60 512 /* Program viewport 0 : OUTBOUND : MEM */
f7b7868c
SJ		 513 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
514 PCIE_ATU_VIEWPORT);
515 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
516 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
517 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
518 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 519 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
f7b7868c
SJ		 520 PCIE_ATU_LIMIT);
521 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 522 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
f7b7868c 523 PCIE_ATU_UPPER_TARGET);
340cba60
JH		 524}
525
4b1ced84 526static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
340cba60 527{
340cba60 528 /* Program viewport 1 : OUTBOUND : IO */
f7b7868c
SJ		 529 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
530 PCIE_ATU_VIEWPORT);
531 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
532 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
533 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
534 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
4b1ced84 535 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
f7b7868c
SJ		 536 PCIE_ATU_LIMIT);
537 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
4b1ced84 538 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
f7b7868c 539 PCIE_ATU_UPPER_TARGET);
340cba60
JH		 540}
541
4b1ced84 542static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 543 u32 devfn, int where, int size, u32 *val)
544{
545 int ret = PCIBIOS_SUCCESSFUL;
546 u32 address, busdev;
547
548 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
549 PCIE_ATU_FUNC(PCI_FUNC(devfn));
550 address = where & ~0x3;
551
552 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 553 dw_pcie_prog_viewport_cfg0(pp, busdev);
340cba60 554 ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
4b1ced84 555 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 556 } else {
4b1ced84 557 dw_pcie_prog_viewport_cfg1(pp, busdev);
340cba60 558 ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
4b1ced84 559 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 560 }
561
562 return ret;
563}
564
4b1ced84 565static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
340cba60
JH		 566 u32 devfn, int where, int size, u32 val)
567{
568 int ret = PCIBIOS_SUCCESSFUL;
569 u32 address, busdev;
570
571 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
572 PCIE_ATU_FUNC(PCI_FUNC(devfn));
573 address = where & ~0x3;
574
575 if (bus->parent->number == pp->root_bus_nr) {
4b1ced84 576 dw_pcie_prog_viewport_cfg0(pp, busdev);
340cba60 577 ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
4b1ced84 578 dw_pcie_prog_viewport_mem_outbound(pp);
340cba60 579 } else {
4b1ced84 580 dw_pcie_prog_viewport_cfg1(pp, busdev);
340cba60 581 ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
4b1ced84 582 dw_pcie_prog_viewport_io_outbound(pp);
340cba60
JH		 583 }
584
585 return ret;
586}
587
340cba60 588
4b1ced84 589static int dw_pcie_valid_config(struct pcie_port *pp,
340cba60
JH		 590 struct pci_bus *bus, int dev)
591{
592 /* If there is no link, then there is no device */
593 if (bus->number != pp->root_bus_nr) {
4b1ced84 594 if (!dw_pcie_link_up(pp))
340cba60
JH		 595 return 0;
596 }
597
598 /* access only one slot on each root port */
599 if (bus->number == pp->root_bus_nr && dev > 0)
600 return 0;
601
602 /*
603 * do not read more than one device on the bus directly attached
604 * to RC's (Virtual Bridge's) DS side.
605 */
606 if (bus->primary == pp->root_bus_nr && dev > 0)
607 return 0;
608
609 return 1;
610}
611
4b1ced84 612static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
340cba60
JH		 613 int size, u32 *val)
614{
615 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
616 unsigned long flags;
617 int ret;
618
619 if (!pp) {
620 BUG();
621 return -EINVAL;
622 }
623
4b1ced84 624 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
340cba60
JH		 625 *val = 0xffffffff;
626 return PCIBIOS_DEVICE_NOT_FOUND;
627 }
628
629 spin_lock_irqsave(&pp->conf_lock, flags);
630 if (bus->number != pp->root_bus_nr)
4b1ced84 631 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
340cba60
JH		 632 where, size, val);
633 else
4b1ced84 634 ret = dw_pcie_rd_own_conf(pp, where, size, val);
340cba60
JH		 635 spin_unlock_irqrestore(&pp->conf_lock, flags);
636
637 return ret;
638}
639
4b1ced84 640static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
340cba60
JH		 641 int where, int size, u32 val)
642{
643 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
644 unsigned long flags;
645 int ret;
646
647 if (!pp) {
648 BUG();
649 return -EINVAL;
650 }
651
4b1ced84 652 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
340cba60
JH		 653 return PCIBIOS_DEVICE_NOT_FOUND;
654
655 spin_lock_irqsave(&pp->conf_lock, flags);
656 if (bus->number != pp->root_bus_nr)
4b1ced84 657 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
340cba60
JH		 658 where, size, val);
659 else
4b1ced84 660 ret = dw_pcie_wr_own_conf(pp, where, size, val);
340cba60
JH		 661 spin_unlock_irqrestore(&pp->conf_lock, flags);
662
663 return ret;
664}
665
4b1ced84
JH		 666static struct pci_ops dw_pcie_ops = {
667 .read = dw_pcie_rd_conf,
668 .write = dw_pcie_wr_conf,
340cba60
JH		 669};
670
73e40850 671static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
4b1ced84
JH		 672{
673 struct pcie_port *pp;
674
675 pp = sys_to_pcie(sys);
676
677 if (!pp)
678 return 0;
679
680 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
681 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
682 pci_ioremap_io(sys->io_offset, pp->io.start);
683 global_io_offset += SZ_64K;
684 pci_add_resource_offset(&sys->resources, &pp->io,
685 sys->io_offset);
686 }
687
688 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
689 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
690
691 return 1;
692}
693
73e40850 694static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
340cba60
JH		 695{
696 struct pci_bus *bus;
697 struct pcie_port *pp = sys_to_pcie(sys);
698
699 if (pp) {
700 pp->root_bus_nr = sys->busnr;
4b1ced84 701 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
340cba60
JH		 702 sys, &sys->resources);
703 } else {
704 bus = NULL;
705 BUG();
706 }
707
708 return bus;
709}
710
73e40850 711static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
340cba60
JH		 712{
713 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
714
715 return pp->irq;
716}
717
f342d940
JH		 718static void dw_pcie_add_bus(struct pci_bus *bus)
719{
720 if (IS_ENABLED(CONFIG_PCI_MSI)) {
721 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
722
723 dw_pcie_msi_chip.dev = pp->dev;
724 bus->msi = &dw_pcie_msi_chip;
725 }
726}
727
4b1ced84
JH		 728static struct hw_pci dw_pci = {
729 .setup = dw_pcie_setup,
730 .scan = dw_pcie_scan_bus,
731 .map_irq = dw_pcie_map_irq,
f342d940 732 .add_bus = dw_pcie_add_bus,
340cba60
JH		 733};
734
4b1ced84 735void dw_pcie_setup_rc(struct pcie_port *pp)
340cba60
JH		 736{
737 struct pcie_port_info *config = &pp->config;
340cba60
JH		 738 u32 val;
739 u32 membase;
740 u32 memlimit;
741
742 /* set the number of lines as 4 */
f7b7868c 743 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
340cba60 744 val &= ~PORT_LINK_MODE_MASK;
4b1ced84
JH		 745 switch (pp->lanes) {
746 case 1:
747 val |= PORT_LINK_MODE_1_LANES;
748 break;
749 case 2:
750 val |= PORT_LINK_MODE_2_LANES;
751 break;
752 case 4:
753 val |= PORT_LINK_MODE_4_LANES;
754 break;
755 }
f7b7868c 756 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
340cba60
JH		 757
758 /* set link width speed control register */
f7b7868c 759 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
340cba60 760 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
4b1ced84
JH		 761 switch (pp->lanes) {
762 case 1:
763 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
764 break;
765 case 2:
766 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
767 break;
768 case 4:
769 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
770 break;
771 }
f7b7868c 772 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
340cba60
JH		 773
774 /* setup RC BARs */
f7b7868c
SJ		 775 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
776 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
340cba60
JH		 777
778 /* setup interrupt pins */
f7b7868c 779 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
340cba60
JH		 780 val &= 0xffff00ff;
781 val |= 0x00000100;
f7b7868c 782 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
340cba60
JH		 783
784 /* setup bus numbers */
f7b7868c 785 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
340cba60
JH		 786 val &= 0xff000000;
787 val |= 0x00010100;
f7b7868c 788 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
340cba60
JH		 789
790 /* setup memory base, memory limit */
791 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
792 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
793 val = memlimit | membase;
f7b7868c 794 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
340cba60
JH		 795
796 /* setup command register */
f7b7868c 797 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
340cba60
JH		 798 val &= 0xffff0000;
799 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
800 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
f7b7868c 801 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
340cba60 802}
340cba60
JH		 803
804MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
4b1ced84 805MODULE_DESCRIPTION("Designware PCIe host controller driver");
340cba60 806MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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