projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4b1ced84 JH |
1 | /* |
| 2 | * Synopsys Designware PCIe host controller driver | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
| 5 | * http://www.samsung.com | |
| 6 | * | |
| 7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 18edf451 SJ |
14 | #ifndef _PCIE_DESIGNWARE_H |
| 15 | #define _PCIE_DESIGNWARE_H | |
| 16 | ||
| 4b1ced84 JH |
17 | struct pcie_port_info { |
| 18 | u32 cfg0_size; | |
| 19 | u32 cfg1_size; | |
| 20 | u32 io_size; | |
| 21 | u32 mem_size; | |
| 22 | phys_addr_t io_bus_addr; | |
| 23 | phys_addr_t mem_bus_addr; | |
| 24 | }; | |
| 25 | ||
| f342d940 JH |
26 | /* |
| 27 | * Maximum number of MSI IRQs can be 256 per controller. But keep | |
| 28 | * it 32 as of now. Probably we will never need more than 32. If needed, | |
| 29 | * then increment it in multiple of 32. | |
| 30 | */ | |
| 31 | #define MAX_MSI_IRQS 32 | |
| 32 | #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) | |
| 33 | ||
| 4b1ced84 JH |
34 | struct pcie_port { |
| 35 | struct device *dev; | |
| 36 | u8 root_bus_nr; | |
| 37 | void __iomem *dbi_base; | |
| 38 | u64 cfg0_base; | |
| f4c55c5a | 39 | u64 cfg0_mod_base; |
| 4b1ced84 JH |
40 | void __iomem *va_cfg0_base; |
| 41 | u64 cfg1_base; | |
| f4c55c5a | 42 | u64 cfg1_mod_base; |
| 4b1ced84 JH |
43 | void __iomem *va_cfg1_base; |
| 44 | u64 io_base; | |
| f4c55c5a | 45 | u64 io_mod_base; |
| 4b1ced84 | 46 | u64 mem_base; |
| f4c55c5a | 47 | u64 mem_mod_base; |
| 4b1ced84 JH |
48 | struct resource cfg; |
| 49 | struct resource io; | |
| 50 | struct resource mem; | |
| 4f2ebe00 | 51 | struct resource busn; |
| 4b1ced84 JH |
52 | struct pcie_port_info config; |
| 53 | int irq; | |
| 54 | u32 lanes; | |
| 55 | struct pcie_host_ops *ops; | |
| f342d940 | 56 | int msi_irq; |
| 904d0e78 | 57 | struct irq_domain *irq_domain; |
| f342d940 JH |
58 | unsigned long msi_data; |
| 59 | DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); | |
| 4b1ced84 JH |
60 | }; |
| 61 | ||
| 62 | struct pcie_host_ops { | |
| 63 | void (*readl_rc)(struct pcie_port *pp, | |
| 64 | void __iomem *dbi_base, u32 *val); | |
| 65 | void (*writel_rc)(struct pcie_port *pp, | |
| 66 | u32 val, void __iomem *dbi_base); | |
| 67 | int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); | |
| 68 | int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); | |
| a1c0ae9c MK |
69 | int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, |
| 70 | unsigned int devfn, int where, int size, u32 *val); | |
| 71 | int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, | |
| 72 | unsigned int devfn, int where, int size, u32 val); | |
| 4b1ced84 JH |
73 | int (*link_up)(struct pcie_port *pp); |
| 74 | void (*host_init)(struct pcie_port *pp); | |
| 2f37c5a8 MK |
75 | void (*msi_set_irq)(struct pcie_port *pp, int irq); |
| 76 | void (*msi_clear_irq)(struct pcie_port *pp, int irq); | |
| 77 | u32 (*get_msi_data)(struct pcie_port *pp); | |
| b14a3d17 MK |
78 | void (*scan_bus)(struct pcie_port *pp); |
| 79 | int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip); | |
| 4b1ced84 JH |
80 | }; |
| 81 | ||
| a01ef59e PA |
82 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); |
| 83 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); | |
| 7f4f16ee | 84 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); |
| f342d940 | 85 | void dw_pcie_msi_init(struct pcie_port *pp); |
| 4b1ced84 JH |
86 | int dw_pcie_link_up(struct pcie_port *pp); |
| 87 | void dw_pcie_setup_rc(struct pcie_port *pp); | |
| 88 | int dw_pcie_host_init(struct pcie_port *pp); | |
| 18edf451 SJ |
89 | |
| 90 | #endif /* _PCIE_DESIGNWARE_H */ |