[deliverable/linux.git] / drivers / pci / host / pcie-iproc.c

/*
 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
 * Copyright (C) 2015 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mbus.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>

#include "pcie-iproc.h"

#define EP_PERST_SOURCE_SELECT_SHIFT 2
#define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
#define EP_MODE_SURVIVE_PERST_SHIFT  1
#define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
#define RC_PCIE_RST_OUTPUT_SHIFT     0
#define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)
#define PAXC_RESET_MASK              0x7f

#define CFG_IND_ADDR_MASK            0x00001ffc

#define CFG_ADDR_BUS_NUM_SHIFT       20
#define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT       15
#define CFG_ADDR_DEV_NUM_MASK        0x000f8000
#define CFG_ADDR_FUNC_NUM_SHIFT      12
#define CFG_ADDR_FUNC_NUM_MASK       0x00007000
#define CFG_ADDR_REG_NUM_SHIFT       2
#define CFG_ADDR_REG_NUM_MASK        0x00000ffc
#define CFG_ADDR_CFG_TYPE_SHIFT      0
#define CFG_ADDR_CFG_TYPE_MASK       0x00000003

#define SYS_RC_INTX_MASK             0xf

#define PCIE_PHYLINKUP_SHIFT         3
#define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
#define PCIE_DL_ACTIVE_SHIFT         2
#define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)

#define OARR_VALID_SHIFT             0
#define OARR_VALID                   BIT(OARR_VALID_SHIFT)
#define OARR_SIZE_CFG_SHIFT          1
#define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)

#define MAX_NUM_OB_WINDOWS           2

#define IPROC_PCIE_REG_INVALID 0xffff

enum iproc_pcie_reg {
	IPROC_PCIE_CLK_CTRL = 0,
	IPROC_PCIE_CFG_IND_ADDR,
	IPROC_PCIE_CFG_IND_DATA,
	IPROC_PCIE_CFG_ADDR,
	IPROC_PCIE_CFG_DATA,
	IPROC_PCIE_INTX_EN,
	IPROC_PCIE_OARR_LO,
	IPROC_PCIE_OARR_HI,
	IPROC_PCIE_OMAP_LO,
	IPROC_PCIE_OMAP_HI,
	IPROC_PCIE_LINK_STATUS,
};

/* iProc PCIe PAXB registers */
static const u16 iproc_pcie_reg_paxb[] = {
	[IPROC_PCIE_CLK_CTRL]     = 0x000,
	[IPROC_PCIE_CFG_IND_ADDR] = 0x120,
	[IPROC_PCIE_CFG_IND_DATA] = 0x124,
	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
	[IPROC_PCIE_INTX_EN]      = 0x330,
	[IPROC_PCIE_OARR_LO]      = 0xd20,
	[IPROC_PCIE_OARR_HI]      = 0xd24,
	[IPROC_PCIE_OMAP_LO]      = 0xd40,
	[IPROC_PCIE_OMAP_HI]      = 0xd44,
	[IPROC_PCIE_LINK_STATUS]  = 0xf0c,
};

/* iProc PCIe PAXC v1 registers */
static const u16 iproc_pcie_reg_paxc[] = {
	[IPROC_PCIE_CLK_CTRL]     = 0x000,
	[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
	[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
	[IPROC_PCIE_INTX_EN]      = IPROC_PCIE_REG_INVALID,
	[IPROC_PCIE_OARR_LO]      = IPROC_PCIE_REG_INVALID,
	[IPROC_PCIE_OARR_HI]      = IPROC_PCIE_REG_INVALID,
	[IPROC_PCIE_OMAP_LO]      = IPROC_PCIE_REG_INVALID,
	[IPROC_PCIE_OMAP_HI]      = IPROC_PCIE_REG_INVALID,
	[IPROC_PCIE_LINK_STATUS]  = IPROC_PCIE_REG_INVALID,
};

static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
{
	struct iproc_pcie *pcie;
#ifdef CONFIG_ARM
	struct pci_sys_data *sys = bus->sysdata;

	pcie = sys->private_data;
#else
	pcie = bus->sysdata;
#endif
	return pcie;
}

static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
{
	return !!(reg_offset == IPROC_PCIE_REG_INVALID);
}

static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
					enum iproc_pcie_reg reg)
{
	return pcie->reg_offsets[reg];
}

static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
				      enum iproc_pcie_reg reg)
{
	u16 offset = iproc_pcie_reg_offset(pcie, reg);

	if (iproc_pcie_reg_is_invalid(offset))
		return 0;

	return readl(pcie->base + offset);
}

static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
					enum iproc_pcie_reg reg, u32 val)
{
	u16 offset = iproc_pcie_reg_offset(pcie, reg);

	if (iproc_pcie_reg_is_invalid(offset))
		return;

	writel(val, pcie->base + offset);
}

static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
				       enum iproc_pcie_reg reg,
				       unsigned window, u32 val)
{
	u16 offset = iproc_pcie_reg_offset(pcie, reg);

	if (iproc_pcie_reg_is_invalid(offset))
		return;

	writel(val, pcie->base + offset + (window * 8));
}

/**
 * Note access to the configuration registers are protected at the higher layer
 * by 'pci_lock' in drivers/pci/access.c
 */
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
					    unsigned int devfn,
					    int where)
{
	struct iproc_pcie *pcie = iproc_data(bus);
	unsigned slot = PCI_SLOT(devfn);
	unsigned fn = PCI_FUNC(devfn);
	unsigned busno = bus->number;
	u32 val;
	u16 offset;

	/* root complex access */
	if (busno == 0) {
		if (slot > 0 || fn > 0)
			return NULL;

		iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
				     where & CFG_IND_ADDR_MASK);
		offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
		if (iproc_pcie_reg_is_invalid(offset))
			return NULL;
		else
			return (pcie->base + offset);
	}

	/*
	 * PAXC is connected to an internally emulated EP within the SoC.  It
	 * allows only one device.
	 */
	if (pcie->type == IPROC_PCIE_PAXC)
		if (slot > 0)
			return NULL;

	/* EP device access */
	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
		(where & CFG_ADDR_REG_NUM_MASK) |
		(1 & CFG_ADDR_CFG_TYPE_MASK);
	iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
	offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
	if (iproc_pcie_reg_is_invalid(offset))
		return NULL;
	else
		return (pcie->base + offset);
}

static struct pci_ops iproc_pcie_ops = {
	.map_bus = iproc_pcie_map_cfg_bus,
	.read = pci_generic_config_read32,
	.write = pci_generic_config_write32,
};

static void iproc_pcie_reset(struct iproc_pcie *pcie)
{
	u32 val;

	if (pcie->type == IPROC_PCIE_PAXC) {
		val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
		val &= ~PAXC_RESET_MASK;
		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
		udelay(100);
		val |= PAXC_RESET_MASK;
		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
		udelay(100);
		return;
	}

	/*
	 * Select perst_b signal as reset source. Put the device into reset,
	 * and then bring it out of reset
	 */
	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
		~RC_PCIE_RST_OUTPUT;
	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
	udelay(250);

	val |= RC_PCIE_RST_OUTPUT;
	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
	msleep(100);
}

static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
{
	u8 hdr_type;
	u32 link_ctrl, class, val;
	u16 pos, link_status;
	bool link_is_active = false;

	/*
	 * PAXC connects to emulated endpoint devices directly and does not
	 * have a Serdes.  Therefore skip the link detection logic here.
	 */
	if (pcie->type == IPROC_PCIE_PAXC)
		return 0;

	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
		return -ENODEV;
	}

	/* make sure we are not in EP mode */
	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
		dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
		return -EFAULT;
	}

	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
#define PCI_CLASS_BRIDGE_MASK      0xffff00
#define PCI_CLASS_BRIDGE_SHIFT     8
	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
	class &= ~PCI_CLASS_BRIDGE_MASK;
	class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);

	/* check link status to see if link is active */
	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	if (link_status & PCI_EXP_LNKSTA_NLW)
		link_is_active = true;

	if (!link_is_active) {
		/* try GEN 1 link speed */
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
#define PCI_TARGET_LINK_SPEED_MASK    0xf
#define PCI_TARGET_LINK_SPEED_GEN2    0x2
#define PCI_TARGET_LINK_SPEED_GEN1    0x1
		pci_bus_read_config_dword(bus, 0,
					  PCI_LINK_STATUS_CTRL_2_OFFSET,
					  &link_ctrl);
		if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
		    PCI_TARGET_LINK_SPEED_GEN2) {
			link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
			link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
			pci_bus_write_config_dword(bus, 0,
					   PCI_LINK_STATUS_CTRL_2_OFFSET,
					   link_ctrl);
			msleep(100);

			pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
						 &link_status);
			if (link_status & PCI_EXP_LNKSTA_NLW)
				link_is_active = true;
		}
	}

	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");

	return link_is_active ? 0 : -ENODEV;
}

static void iproc_pcie_enable(struct iproc_pcie *pcie)
{
	iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
}

/**
 * Some iProc SoCs require the SW to configure the outbound address mapping
 *
 * Outbound address translation:
 *
 * iproc_pcie_address = axi_address - axi_offset
 * OARR = iproc_pcie_address
 * OMAP = pci_addr
 *
 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
 */
static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
			       u64 pci_addr, resource_size_t size)
{
	struct iproc_pcie_ob *ob = &pcie->ob;
	unsigned i;
	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
	u64 remainder;

	if (size > max_size) {
		dev_err(pcie->dev,
			"res size %pap exceeds max supported size 0x%llx\n",
			&size, max_size);
		return -EINVAL;
	}

	div64_u64_rem(size, ob->window_size, &remainder);
	if (remainder) {
		dev_err(pcie->dev,
			"res size %pap needs to be multiple of window size %pap\n",
			&size, &ob->window_size);
		return -EINVAL;
	}

	if (axi_addr < ob->axi_offset) {
		dev_err(pcie->dev,
			"axi address %pap less than offset %pap\n",
			&axi_addr, &ob->axi_offset);
		return -EINVAL;
	}

	/*
	 * Translate the AXI address to the internal address used by the iProc
	 * PCIe core before programming the OARR
	 */
	axi_addr -= ob->axi_offset;

	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
				    lower_32_bits(axi_addr) | OARR_VALID |
				    (ob->set_oarr_size ? 1 : 0));
		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
				    upper_32_bits(axi_addr));
		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
				    lower_32_bits(pci_addr));
		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
				    upper_32_bits(pci_addr));

		size -= ob->window_size;
		if (size == 0)
			break;

		axi_addr += ob->window_size;
		pci_addr += ob->window_size;
	}

	return 0;
}

static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
				 struct list_head *resources)
{
	struct resource_entry *window;
	int ret;

	resource_list_for_each_entry(window, resources) {
		struct resource *res = window->res;
		u64 res_type = resource_type(res);

		switch (res_type) {
		case IORESOURCE_IO:
		case IORESOURCE_BUS:
			break;
		case IORESOURCE_MEM:
			ret = iproc_pcie_setup_ob(pcie, res->start,
						  res->start - window->offset,
						  resource_size(res));
			if (ret)
				return ret;
			break;
		default:
			dev_err(pcie->dev, "invalid resource %pR\n", res);
			return -EINVAL;
		}
	}

	return 0;
}

static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
{
	struct device_node *msi_node;

	msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
	if (!msi_node)
		return -ENODEV;

	/*
	 * If another MSI controller is being used, the call below should fail
	 * but that is okay
	 */
	return iproc_msi_init(pcie, msi_node);
}

static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
{
	iproc_msi_exit(pcie);
}

int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
{
	int ret;
	void *sysdata;
	struct pci_bus *bus;

	if (!pcie || !pcie->dev || !pcie->base)
		return -EINVAL;

	ret = devm_request_pci_bus_resources(pcie->dev, res);
	if (ret)
		return ret;

	ret = phy_init(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
		return ret;
	}

	ret = phy_power_on(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to power on PCIe PHY\n");
		goto err_exit_phy;
	}

	switch (pcie->type) {
	case IPROC_PCIE_PAXB:
		pcie->reg_offsets = iproc_pcie_reg_paxb;
		break;
	case IPROC_PCIE_PAXC:
		pcie->reg_offsets = iproc_pcie_reg_paxc;
		break;
	default:
		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
		ret = -EINVAL;
		goto err_power_off_phy;
	}

	iproc_pcie_reset(pcie);

	if (pcie->need_ob_cfg) {
		ret = iproc_pcie_map_ranges(pcie, res);
		if (ret) {
			dev_err(pcie->dev, "map failed\n");
			goto err_power_off_phy;
		}
	}

#ifdef CONFIG_ARM
	pcie->sysdata.private_data = pcie;
	sysdata = &pcie->sysdata;
#else
	sysdata = pcie;
#endif

	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
	if (!bus) {
		dev_err(pcie->dev, "unable to create PCI root bus\n");
		ret = -ENOMEM;
		goto err_power_off_phy;
	}
	pcie->root_bus = bus;

	ret = iproc_pcie_check_link(pcie, bus);
	if (ret) {
		dev_err(pcie->dev, "no PCIe EP device detected\n");
		goto err_rm_root_bus;
	}

	iproc_pcie_enable(pcie);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		if (iproc_pcie_msi_enable(pcie))
			dev_info(pcie->dev, "not using iProc MSI\n");

	pci_scan_child_bus(bus);
	pci_assign_unassigned_bus_resources(bus);
	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
	pci_bus_add_devices(bus);

	return 0;

err_rm_root_bus:
	pci_stop_root_bus(bus);
	pci_remove_root_bus(bus);

err_power_off_phy:
	phy_power_off(pcie->phy);
err_exit_phy:
	phy_exit(pcie->phy);
	return ret;
}
EXPORT_SYMBOL(iproc_pcie_setup);

int iproc_pcie_remove(struct iproc_pcie *pcie)
{
	pci_stop_root_bus(pcie->root_bus);
	pci_remove_root_bus(pcie->root_bus);

	iproc_pcie_msi_disable(pcie);

	phy_power_off(pcie->phy);
	phy_exit(pcie->phy);

	return 0;
}
EXPORT_SYMBOL(iproc_pcie_remove);

MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1fb37a81 RJ	1	/*
1fb37a81 RJ	2	* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
be908d21	3	* Copyright (C) 2015 Broadcom Corporation
1fb37a81 RJ	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation version 2.
	8	*
	9	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	10	* kind, whether express or implied; without even the implied warranty
	11	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/msi.h>
	18	#include <linux/clk.h>
	19	#include <linux/module.h>
	20	#include <linux/mbus.h>
	21	#include <linux/slab.h>
	22	#include <linux/delay.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_pci.h>
	27	#include <linux/of_irq.h>
	28	#include <linux/of_platform.h>
	29	#include <linux/phy/phy.h>
	30
	31	#include "pcie-iproc.h"
	32
199ff141 RJ	33	#define EP_PERST_SOURCE_SELECT_SHIFT 2
199ff141 RJ	34	#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
1fb37a81 RJ	35	#define EP_MODE_SURVIVE_PERST_SHIFT 1
	36	#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
	37	#define RC_PCIE_RST_OUTPUT_SHIFT 0
	38	#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
943ebae7	39	#define PAXC_RESET_MASK 0x7f
1fb37a81	40
1fb37a81 RJ	41	#define CFG_IND_ADDR_MASK 0x00001ffc
1fb37a81 RJ	42
1fb37a81 RJ	43	#define CFG_ADDR_BUS_NUM_SHIFT 20
	44	#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
	45	#define CFG_ADDR_DEV_NUM_SHIFT 15
	46	#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
	47	#define CFG_ADDR_FUNC_NUM_SHIFT 12
	48	#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
	49	#define CFG_ADDR_REG_NUM_SHIFT 2
	50	#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
	51	#define CFG_ADDR_CFG_TYPE_SHIFT 0
	52	#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
	53
1fb37a81 RJ	54	#define SYS_RC_INTX_MASK 0xf
1fb37a81 RJ	55
aaf22ab4 RJ	56	#define PCIE_PHYLINKUP_SHIFT 3
	57	#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
	58	#define PCIE_DL_ACTIVE_SHIFT 2
	59	#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
	60
e99a187b RJ	61	#define OARR_VALID_SHIFT 0
	62	#define OARR_VALID BIT(OARR_VALID_SHIFT)
	63	#define OARR_SIZE_CFG_SHIFT 1
	64	#define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
	65
e99a187b	66	#define MAX_NUM_OB_WINDOWS 2
943ebae7 RJ	67
	68	#define IPROC_PCIE_REG_INVALID 0xffff
	69
	70	enum iproc_pcie_reg {
	71	IPROC_PCIE_CLK_CTRL = 0,
	72	IPROC_PCIE_CFG_IND_ADDR,
	73	IPROC_PCIE_CFG_IND_DATA,
	74	IPROC_PCIE_CFG_ADDR,
	75	IPROC_PCIE_CFG_DATA,
	76	IPROC_PCIE_INTX_EN,
	77	IPROC_PCIE_OARR_LO,
	78	IPROC_PCIE_OARR_HI,
	79	IPROC_PCIE_OMAP_LO,
	80	IPROC_PCIE_OMAP_HI,
	81	IPROC_PCIE_LINK_STATUS,
	82	};
	83
	84	/* iProc PCIe PAXB registers */
	85	static const u16 iproc_pcie_reg_paxb[] = {
	86	[IPROC_PCIE_CLK_CTRL] = 0x000,
	87	[IPROC_PCIE_CFG_IND_ADDR] = 0x120,
	88	[IPROC_PCIE_CFG_IND_DATA] = 0x124,
	89	[IPROC_PCIE_CFG_ADDR] = 0x1f8,
	90	[IPROC_PCIE_CFG_DATA] = 0x1fc,
	91	[IPROC_PCIE_INTX_EN] = 0x330,
	92	[IPROC_PCIE_OARR_LO] = 0xd20,
	93	[IPROC_PCIE_OARR_HI] = 0xd24,
	94	[IPROC_PCIE_OMAP_LO] = 0xd40,
	95	[IPROC_PCIE_OMAP_HI] = 0xd44,
	96	[IPROC_PCIE_LINK_STATUS] = 0xf0c,
	97	};
	98
	99	/* iProc PCIe PAXC v1 registers */
	100	static const u16 iproc_pcie_reg_paxc[] = {
	101	[IPROC_PCIE_CLK_CTRL] = 0x000,
	102	[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
	103	[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
	104	[IPROC_PCIE_CFG_ADDR] = 0x1f8,
	105	[IPROC_PCIE_CFG_DATA] = 0x1fc,
	106	[IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID,
	107	[IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID,
	108	[IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID,
	109	[IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID,
	110	[IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID,
	111	[IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID,
	112	};
e99a187b	113
8d9bfe37	114	static inline struct iproc_pcie iproc_data(struct pci_bus bus)
1fb37a81	115	{
8d9bfe37 RJ	116	struct iproc_pcie *pcie;
	117	#ifdef CONFIG_ARM
	118	struct pci_sys_data *sys = bus->sysdata;
	119
	120	pcie = sys->private_data;
	121	#else
	122	pcie = bus->sysdata;
	123	#endif
	124	return pcie;
1fb37a81 RJ	125	}
1fb37a81 RJ	126
943ebae7 RJ	127	static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
	128	{
	129	return !!(reg_offset == IPROC_PCIE_REG_INVALID);
	130	}
	131
	132	static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
	133	enum iproc_pcie_reg reg)
	134	{
	135	return pcie->reg_offsets[reg];
	136	}
	137
	138	static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
	139	enum iproc_pcie_reg reg)
	140	{
	141	u16 offset = iproc_pcie_reg_offset(pcie, reg);
	142
	143	if (iproc_pcie_reg_is_invalid(offset))
	144	return 0;
	145
	146	return readl(pcie->base + offset);
	147	}
	148
	149	static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
	150	enum iproc_pcie_reg reg, u32 val)
	151	{
	152	u16 offset = iproc_pcie_reg_offset(pcie, reg);
	153
	154	if (iproc_pcie_reg_is_invalid(offset))
	155	return;
	156
	157	writel(val, pcie->base + offset);
	158	}
	159
	160	static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
	161	enum iproc_pcie_reg reg,
	162	unsigned window, u32 val)
	163	{
	164	u16 offset = iproc_pcie_reg_offset(pcie, reg);
	165
	166	if (iproc_pcie_reg_is_invalid(offset))
	167	return;
	168
	169	writel(val, pcie->base + offset + (window * 8));
	170	}
	171
1fb37a81 RJ	172	/**
	173	* Note access to the configuration registers are protected at the higher layer
	174	* by 'pci_lock' in drivers/pci/access.c
	175	*/
	176	static void __iomem iproc_pcie_map_cfg_bus(struct pci_bus bus,
	177	unsigned int devfn,
	178	int where)
	179	{
8d9bfe37	180	struct iproc_pcie *pcie = iproc_data(bus);
1fb37a81 RJ	181	unsigned slot = PCI_SLOT(devfn);
	182	unsigned fn = PCI_FUNC(devfn);
	183	unsigned busno = bus->number;
	184	u32 val;
943ebae7 RJ	185	u16 offset;
943ebae7 RJ	186
1fb37a81 RJ	187	/* root complex access */
1fb37a81 RJ	188	if (busno == 0) {
46560388 RJ	189	if (slot > 0 \|\| fn > 0)
	190	return NULL;
	191
943ebae7 RJ	192	iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
	193	where & CFG_IND_ADDR_MASK);
	194	offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
	195	if (iproc_pcie_reg_is_invalid(offset))
1fb37a81	196	return NULL;
943ebae7 RJ	197	else
943ebae7 RJ	198	return (pcie->base + offset);
1fb37a81 RJ	199	}
1fb37a81 RJ	200
46560388 RJ	201	/*
	202	* PAXC is connected to an internally emulated EP within the SoC. It
	203	* allows only one device.
	204	*/
	205	if (pcie->type == IPROC_PCIE_PAXC)
	206	if (slot > 0)
	207	return NULL;
	208
1fb37a81 RJ	209	/* EP device access */
	210	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) \|
	211	(slot << CFG_ADDR_DEV_NUM_SHIFT) \|
	212	(fn << CFG_ADDR_FUNC_NUM_SHIFT) \|
	213	(where & CFG_ADDR_REG_NUM_MASK) \|
	214	(1 & CFG_ADDR_CFG_TYPE_MASK);
943ebae7 RJ	215	iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
	216	offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
	217	if (iproc_pcie_reg_is_invalid(offset))
	218	return NULL;
	219	else
	220	return (pcie->base + offset);
1fb37a81 RJ	221	}
	222
	223	static struct pci_ops iproc_pcie_ops = {
	224	.map_bus = iproc_pcie_map_cfg_bus,
	225	.read = pci_generic_config_read32,
	226	.write = pci_generic_config_write32,
	227	};
	228
	229	static void iproc_pcie_reset(struct iproc_pcie *pcie)
	230	{
	231	u32 val;
	232
943ebae7 RJ	233	if (pcie->type == IPROC_PCIE_PAXC) {
	234	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
	235	val &= ~PAXC_RESET_MASK;
	236	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
	237	udelay(100);
	238	val \|= PAXC_RESET_MASK;
	239	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
	240	udelay(100);
	241	return;
	242	}
	243
1fb37a81	244	/*
199ff141 RJ	245	* Select perst_b signal as reset source. Put the device into reset,
199ff141 RJ	246	* and then bring it out of reset
1fb37a81	247	*/
943ebae7	248	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
199ff141 RJ	249	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
199ff141 RJ	250	~RC_PCIE_RST_OUTPUT;
943ebae7	251	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
1fb37a81	252	udelay(250);
199ff141 RJ	253
199ff141 RJ	254	val \|= RC_PCIE_RST_OUTPUT;
943ebae7	255	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
199ff141	256	msleep(100);
1fb37a81 RJ	257	}
	258
	259	static int iproc_pcie_check_link(struct iproc_pcie pcie, struct pci_bus bus)
	260	{
	261	u8 hdr_type;
aaf22ab4	262	u32 link_ctrl, class, val;
1fb37a81	263	u16 pos, link_status;
aaf22ab4 RJ	264	bool link_is_active = false;
aaf22ab4 RJ	265
943ebae7 RJ	266	/*
	267	* PAXC connects to emulated endpoint devices directly and does not
	268	* have a Serdes. Therefore skip the link detection logic here.
	269	*/
	270	if (pcie->type == IPROC_PCIE_PAXC)
	271	return 0;
	272
	273	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
aaf22ab4 RJ	274	if (!(val & PCIE_PHYLINKUP) \|\| !(val & PCIE_DL_ACTIVE)) {
	275	dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
	276	return -ENODEV;
	277	}
1fb37a81 RJ	278
	279	/* make sure we are not in EP mode */
	280	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	281	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
	282	dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
	283	return -EFAULT;
	284	}
	285
	286	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
aaf22ab4 RJ	287	#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
	288	#define PCI_CLASS_BRIDGE_MASK 0xffff00
	289	#define PCI_CLASS_BRIDGE_SHIFT 8
	290	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
	291	class &= ~PCI_CLASS_BRIDGE_MASK;
	292	class \|= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
	293	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
1fb37a81 RJ	294
	295	/* check link status to see if link is active */
	296	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	297	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	298	if (link_status & PCI_EXP_LNKSTA_NLW)
aaf22ab4	299	link_is_active = true;
1fb37a81 RJ	300
	301	if (!link_is_active) {
	302	/* try GEN 1 link speed */
	303	#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
	304	#define PCI_TARGET_LINK_SPEED_MASK 0xf
	305	#define PCI_TARGET_LINK_SPEED_GEN2 0x2
	306	#define PCI_TARGET_LINK_SPEED_GEN1 0x1
	307	pci_bus_read_config_dword(bus, 0,
	308	PCI_LINK_STATUS_CTRL_2_OFFSET,
	309	&link_ctrl);
	310	if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
	311	PCI_TARGET_LINK_SPEED_GEN2) {
	312	link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
	313	link_ctrl \|= PCI_TARGET_LINK_SPEED_GEN1;
	314	pci_bus_write_config_dword(bus, 0,
	315	PCI_LINK_STATUS_CTRL_2_OFFSET,
	316	link_ctrl);
	317	msleep(100);
	318
	319	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	320	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
	321	&link_status);
	322	if (link_status & PCI_EXP_LNKSTA_NLW)
aaf22ab4	323	link_is_active = true;
1fb37a81 RJ	324	}
	325	}
	326
	327	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
	328
	329	return link_is_active ? 0 : -ENODEV;
	330	}
	331
	332	static void iproc_pcie_enable(struct iproc_pcie *pcie)
	333	{
943ebae7	334	iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
1fb37a81 RJ	335	}
1fb37a81 RJ	336
e99a187b RJ	337	/**
	338	* Some iProc SoCs require the SW to configure the outbound address mapping
	339	*
	340	* Outbound address translation:
	341	*
	342	* iproc_pcie_address = axi_address - axi_offset
	343	* OARR = iproc_pcie_address
	344	* OMAP = pci_addr
	345	*
	346	* axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
	347	*/
	348	static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
	349	u64 pci_addr, resource_size_t size)
	350	{
	351	struct iproc_pcie_ob *ob = &pcie->ob;
	352	unsigned i;
	353	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
	354	u64 remainder;
	355
	356	if (size > max_size) {
	357	dev_err(pcie->dev,
57303e92	358	"res size %pap exceeds max supported size 0x%llx\n",
e99a187b RJ	359	&size, max_size);
	360	return -EINVAL;
	361	}
	362
	363	div64_u64_rem(size, ob->window_size, &remainder);
	364	if (remainder) {
	365	dev_err(pcie->dev,
	366	"res size %pap needs to be multiple of window size %pap\n",
	367	&size, &ob->window_size);
	368	return -EINVAL;
	369	}
	370
	371	if (axi_addr < ob->axi_offset) {
	372	dev_err(pcie->dev,
	373	"axi address %pap less than offset %pap\n",
	374	&axi_addr, &ob->axi_offset);
	375	return -EINVAL;
	376	}
	377
	378	/*
	379	* Translate the AXI address to the internal address used by the iProc
	380	* PCIe core before programming the OARR
	381	*/
	382	axi_addr -= ob->axi_offset;
	383
	384	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
943ebae7 RJ	385	iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
	386	lower_32_bits(axi_addr) \| OARR_VALID \|
	387	(ob->set_oarr_size ? 1 : 0));
	388	iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
	389	upper_32_bits(axi_addr));
	390	iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
	391	lower_32_bits(pci_addr));
	392	iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
	393	upper_32_bits(pci_addr));
e99a187b RJ	394
	395	size -= ob->window_size;
	396	if (size == 0)
	397	break;
	398
	399	axi_addr += ob->window_size;
	400	pci_addr += ob->window_size;
	401	}
	402
	403	return 0;
	404	}
	405
	406	static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
	407	struct list_head *resources)
	408	{
	409	struct resource_entry *window;
	410	int ret;
	411
	412	resource_list_for_each_entry(window, resources) {
	413	struct resource *res = window->res;
	414	u64 res_type = resource_type(res);
	415
	416	switch (res_type) {
	417	case IORESOURCE_IO:
	418	case IORESOURCE_BUS:
	419	break;
	420	case IORESOURCE_MEM:
	421	ret = iproc_pcie_setup_ob(pcie, res->start,
	422	res->start - window->offset,
	423	resource_size(res));
	424	if (ret)
	425	return ret;
	426	break;
	427	default:
	428	dev_err(pcie->dev, "invalid resource %pR\n", res);
	429	return -EINVAL;
	430	}
	431	}
	432
	433	return 0;
	434	}
	435
3bc2b234 RJ	436	static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
	437	{
	438	struct device_node *msi_node;
	439
	440	msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
	441	if (!msi_node)
	442	return -ENODEV;
	443
	444	/*
	445	* If another MSI controller is being used, the call below should fail
	446	* but that is okay
	447	*/
	448	return iproc_msi_init(pcie, msi_node);
	449	}
	450
	451	static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
	452	{
	453	iproc_msi_exit(pcie);
	454	}
	455
18c4342a	456	int iproc_pcie_setup(struct iproc_pcie pcie, struct list_head res)
1fb37a81 RJ	457	{
1fb37a81 RJ	458	int ret;
8d9bfe37	459	void *sysdata;
1fb37a81 RJ	460	struct pci_bus *bus;
	461
	462	if (!pcie \|\| !pcie->dev \|\| !pcie->base)
	463	return -EINVAL;
	464
c3245a56 BH	465	ret = devm_request_pci_bus_resources(pcie->dev, res);
	466	if (ret)
	467	return ret;
	468
93972d18 ME	469	ret = phy_init(pcie->phy);
	470	if (ret) {
	471	dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
	472	return ret;
	473	}
1fb37a81	474
93972d18 ME	475	ret = phy_power_on(pcie->phy);
	476	if (ret) {
	477	dev_err(pcie->dev, "unable to power on PCIe PHY\n");
	478	goto err_exit_phy;
1fb37a81 RJ	479	}
1fb37a81 RJ	480
943ebae7 RJ	481	switch (pcie->type) {
	482	case IPROC_PCIE_PAXB:
	483	pcie->reg_offsets = iproc_pcie_reg_paxb;
	484	break;
	485	case IPROC_PCIE_PAXC:
	486	pcie->reg_offsets = iproc_pcie_reg_paxc;
	487	break;
	488	default:
	489	dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
	490	ret = -EINVAL;
	491	goto err_power_off_phy;
	492	}
	493
1fb37a81 RJ	494	iproc_pcie_reset(pcie);
1fb37a81 RJ	495
e99a187b RJ	496	if (pcie->need_ob_cfg) {
	497	ret = iproc_pcie_map_ranges(pcie, res);
	498	if (ret) {
	499	dev_err(pcie->dev, "map failed\n");
	500	goto err_power_off_phy;
	501	}
	502	}
	503
8d9bfe37	504	#ifdef CONFIG_ARM
1fb37a81	505	pcie->sysdata.private_data = pcie;
8d9bfe37 RJ	506	sysdata = &pcie->sysdata;
	507	#else
	508	sysdata = pcie;
	509	#endif
1fb37a81	510
8d9bfe37	511	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
1fb37a81 RJ	512	if (!bus) {
	513	dev_err(pcie->dev, "unable to create PCI root bus\n");
	514	ret = -ENOMEM;
	515	goto err_power_off_phy;
	516	}
	517	pcie->root_bus = bus;
	518
	519	ret = iproc_pcie_check_link(pcie, bus);
	520	if (ret) {
	521	dev_err(pcie->dev, "no PCIe EP device detected\n");
	522	goto err_rm_root_bus;
	523	}
	524
	525	iproc_pcie_enable(pcie);
	526
3bc2b234 RJ	527	if (IS_ENABLED(CONFIG_PCI_MSI))
	528	if (iproc_pcie_msi_enable(pcie))
	529	dev_info(pcie->dev, "not using iProc MSI\n");
	530
1fb37a81 RJ	531	pci_scan_child_bus(bus);
1fb37a81 RJ	532	pci_assign_unassigned_bus_resources(bus);
c1e02cea	533	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
1fb37a81 RJ	534	pci_bus_add_devices(bus);
	535
	536	return 0;
	537
	538	err_rm_root_bus:
	539	pci_stop_root_bus(bus);
	540	pci_remove_root_bus(bus);
	541
	542	err_power_off_phy:
93972d18	543	phy_power_off(pcie->phy);
1fb37a81	544	err_exit_phy:
93972d18	545	phy_exit(pcie->phy);
1fb37a81 RJ	546	return ret;
	547	}
	548	EXPORT_SYMBOL(iproc_pcie_setup);
	549
	550	int iproc_pcie_remove(struct iproc_pcie *pcie)
	551	{
	552	pci_stop_root_bus(pcie->root_bus);
	553	pci_remove_root_bus(pcie->root_bus);
	554
3bc2b234 RJ	555	iproc_pcie_msi_disable(pcie);
3bc2b234 RJ	556
93972d18 ME	557	phy_power_off(pcie->phy);
93972d18 ME	558	phy_exit(pcie->phy);
1fb37a81 RJ	559
	560	return 0;
	561	}
	562	EXPORT_SYMBOL(iproc_pcie_remove);
	563
	564	MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
	565	MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
	566	MODULE_LICENSE("GPL v2");