[deliverable/linux.git] / drivers / pci / host / pcie-iproc.c

/*
 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
 * Copyright (C) 2015 Broadcom Corporatcommon ion
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mbus.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>

#include "pcie-iproc.h"

#define CLK_CONTROL_OFFSET           0x000
#define EP_MODE_SURVIVE_PERST_SHIFT  1
#define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
#define RC_PCIE_RST_OUTPUT_SHIFT     0
#define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)

#define CFG_IND_ADDR_OFFSET          0x120
#define CFG_IND_ADDR_MASK            0x00001ffc

#define CFG_IND_DATA_OFFSET          0x124

#define CFG_ADDR_OFFSET              0x1f8
#define CFG_ADDR_BUS_NUM_SHIFT       20
#define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT       15
#define CFG_ADDR_DEV_NUM_MASK        0x000f8000
#define CFG_ADDR_FUNC_NUM_SHIFT      12
#define CFG_ADDR_FUNC_NUM_MASK       0x00007000
#define CFG_ADDR_REG_NUM_SHIFT       2
#define CFG_ADDR_REG_NUM_MASK        0x00000ffc
#define CFG_ADDR_CFG_TYPE_SHIFT      0
#define CFG_ADDR_CFG_TYPE_MASK       0x00000003

#define CFG_DATA_OFFSET              0x1fc

#define SYS_RC_INTX_EN               0x330
#define SYS_RC_INTX_MASK             0xf

static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
{
	return sys->private_data;
}

/**
 * Note access to the configuration registers are protected at the higher layer
 * by 'pci_lock' in drivers/pci/access.c
 */
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
					    unsigned int devfn,
					    int where)
{
	struct pci_sys_data *sys = bus->sysdata;
	struct iproc_pcie *pcie = sys_to_pcie(sys);
	unsigned slot = PCI_SLOT(devfn);
	unsigned fn = PCI_FUNC(devfn);
	unsigned busno = bus->number;
	u32 val;

	/* root complex access */
	if (busno == 0) {
		if (slot >= 1)
			return NULL;
		writel(where & CFG_IND_ADDR_MASK,
		       pcie->base + CFG_IND_ADDR_OFFSET);
		return (pcie->base + CFG_IND_DATA_OFFSET);
	}

	if (fn > 1)
		return NULL;

	/* EP device access */
	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
		(where & CFG_ADDR_REG_NUM_MASK) |
		(1 & CFG_ADDR_CFG_TYPE_MASK);
	writel(val, pcie->base + CFG_ADDR_OFFSET);

	return (pcie->base + CFG_DATA_OFFSET);
}

static struct pci_ops iproc_pcie_ops = {
	.map_bus = iproc_pcie_map_cfg_bus,
	.read = pci_generic_config_read32,
	.write = pci_generic_config_write32,
};

static void iproc_pcie_reset(struct iproc_pcie *pcie)
{
	u32 val;

	/*
	 * Configure the PCIe controller as root complex and send a downstream
	 * reset
	 */
	val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	udelay(250);
	val &= ~EP_MODE_SURVIVE_PERST;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	msleep(250);
}

static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
{
	u8 hdr_type;
	u32 link_ctrl;
	u16 pos, link_status;
	int link_is_active = 0;

	/* make sure we are not in EP mode */
	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
		dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
		return -EFAULT;
	}

	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
				  PCI_CLASS_BRIDGE_PCI);

	/* check link status to see if link is active */
	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	if (link_status & PCI_EXP_LNKSTA_NLW)
		link_is_active = 1;

	if (!link_is_active) {
		/* try GEN 1 link speed */
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
#define PCI_TARGET_LINK_SPEED_MASK    0xf
#define PCI_TARGET_LINK_SPEED_GEN2    0x2
#define PCI_TARGET_LINK_SPEED_GEN1    0x1
		pci_bus_read_config_dword(bus, 0,
					  PCI_LINK_STATUS_CTRL_2_OFFSET,
					  &link_ctrl);
		if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
		    PCI_TARGET_LINK_SPEED_GEN2) {
			link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
			link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
			pci_bus_write_config_dword(bus, 0,
					   PCI_LINK_STATUS_CTRL_2_OFFSET,
					   link_ctrl);
			msleep(100);

			pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
						 &link_status);
			if (link_status & PCI_EXP_LNKSTA_NLW)
				link_is_active = 1;
		}
	}

	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");

	return link_is_active ? 0 : -ENODEV;
}

static void iproc_pcie_enable(struct iproc_pcie *pcie)
{
	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
}

int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
{
	int ret;
	struct pci_bus *bus;

	if (!pcie || !pcie->dev || !pcie->base)
		return -EINVAL;

	ret = phy_init(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
		return ret;
	}

	ret = phy_power_on(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to power on PCIe PHY\n");
		goto err_exit_phy;
	}

	iproc_pcie_reset(pcie);

	pcie->sysdata.private_data = pcie;

	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
				  &pcie->sysdata, res);
	if (!bus) {
		dev_err(pcie->dev, "unable to create PCI root bus\n");
		ret = -ENOMEM;
		goto err_power_off_phy;
	}
	pcie->root_bus = bus;

	ret = iproc_pcie_check_link(pcie, bus);
	if (ret) {
		dev_err(pcie->dev, "no PCIe EP device detected\n");
		goto err_rm_root_bus;
	}

	iproc_pcie_enable(pcie);

	pci_scan_child_bus(bus);
	pci_assign_unassigned_bus_resources(bus);
	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
	pci_bus_add_devices(bus);

	return 0;

err_rm_root_bus:
	pci_stop_root_bus(bus);
	pci_remove_root_bus(bus);

err_power_off_phy:
	phy_power_off(pcie->phy);
err_exit_phy:
	phy_exit(pcie->phy);
	return ret;
}
EXPORT_SYMBOL(iproc_pcie_setup);

int iproc_pcie_remove(struct iproc_pcie *pcie)
{
	pci_stop_root_bus(pcie->root_bus);
	pci_remove_root_bus(pcie->root_bus);

	phy_power_off(pcie->phy);
	phy_exit(pcie->phy);

	return 0;
}
EXPORT_SYMBOL(iproc_pcie_remove);

MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1fb37a81 RJ	1	/*
	2	* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
	3	* Copyright (C) 2015 Broadcom Corporatcommon ion
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation version 2.
	8	*
	9	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	10	* kind, whether express or implied; without even the implied warranty
	11	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/msi.h>
	18	#include <linux/clk.h>
	19	#include <linux/module.h>
	20	#include <linux/mbus.h>
	21	#include <linux/slab.h>
	22	#include <linux/delay.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_pci.h>
	27	#include <linux/of_irq.h>
	28	#include <linux/of_platform.h>
	29	#include <linux/phy/phy.h>
	30
	31	#include "pcie-iproc.h"
	32
	33	#define CLK_CONTROL_OFFSET 0x000
	34	#define EP_MODE_SURVIVE_PERST_SHIFT 1
	35	#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
	36	#define RC_PCIE_RST_OUTPUT_SHIFT 0
	37	#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
	38
	39	#define CFG_IND_ADDR_OFFSET 0x120
	40	#define CFG_IND_ADDR_MASK 0x00001ffc
	41
	42	#define CFG_IND_DATA_OFFSET 0x124
	43
	44	#define CFG_ADDR_OFFSET 0x1f8
	45	#define CFG_ADDR_BUS_NUM_SHIFT 20
	46	#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
	47	#define CFG_ADDR_DEV_NUM_SHIFT 15
	48	#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
	49	#define CFG_ADDR_FUNC_NUM_SHIFT 12
	50	#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
	51	#define CFG_ADDR_REG_NUM_SHIFT 2
	52	#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
	53	#define CFG_ADDR_CFG_TYPE_SHIFT 0
	54	#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
	55
	56	#define CFG_DATA_OFFSET 0x1fc
	57
	58	#define SYS_RC_INTX_EN 0x330
	59	#define SYS_RC_INTX_MASK 0xf
	60
	61	static inline struct iproc_pcie sys_to_pcie(struct pci_sys_data sys)
	62	{
	63	return sys->private_data;
	64	}
65
66	/**
67	* Note access to the configuration registers are protected at the higher layer
68	* by 'pci_lock' in drivers/pci/access.c
69	*/
70	static void __iomem iproc_pcie_map_cfg_bus(struct pci_bus bus,
71	unsigned int devfn,
72	int where)
73	{
74	struct pci_sys_data *sys = bus->sysdata;
75	struct iproc_pcie *pcie = sys_to_pcie(sys);
76	unsigned slot = PCI_SLOT(devfn);
77	unsigned fn = PCI_FUNC(devfn);
78	unsigned busno = bus->number;
79	u32 val;
80
81	/* root complex access */
82	if (busno == 0) {
83	if (slot >= 1)
84	return NULL;
85	writel(where & CFG_IND_ADDR_MASK,
86	pcie->base + CFG_IND_ADDR_OFFSET);
87	return (pcie->base + CFG_IND_DATA_OFFSET);
88	}
89
90	if (fn > 1)
91	return NULL;
92
93	/* EP device access */
94	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) \|
95	(slot << CFG_ADDR_DEV_NUM_SHIFT) \|
96	(fn << CFG_ADDR_FUNC_NUM_SHIFT) \|
97	(where & CFG_ADDR_REG_NUM_MASK) \|
98	(1 & CFG_ADDR_CFG_TYPE_MASK);
99	writel(val, pcie->base + CFG_ADDR_OFFSET);
100
101	return (pcie->base + CFG_DATA_OFFSET);
102	}
103
104	static struct pci_ops iproc_pcie_ops = {
105	.map_bus = iproc_pcie_map_cfg_bus,
106	.read = pci_generic_config_read32,
107	.write = pci_generic_config_write32,
108	};
109
110	static void iproc_pcie_reset(struct iproc_pcie *pcie)
111	{
112	u32 val;
113
114	/*
115	* Configure the PCIe controller as root complex and send a downstream
116	* reset
117	*/
118	val = EP_MODE_SURVIVE_PERST \| RC_PCIE_RST_OUTPUT;
119	writel(val, pcie->base + CLK_CONTROL_OFFSET);
120	udelay(250);
121	val &= ~EP_MODE_SURVIVE_PERST;
122	writel(val, pcie->base + CLK_CONTROL_OFFSET);
123	msleep(250);
124	}
125
126	static int iproc_pcie_check_link(struct iproc_pcie pcie, struct pci_bus bus)
127	{
128	u8 hdr_type;
129	u32 link_ctrl;
130	u16 pos, link_status;
131	int link_is_active = 0;
132
133	/* make sure we are not in EP mode */
134	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
135	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
136	dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
137	return -EFAULT;
138	}
139
140	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
141	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
142	PCI_CLASS_BRIDGE_PCI);
143
144	/* check link status to see if link is active */
145	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
146	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
147	if (link_status & PCI_EXP_LNKSTA_NLW)
148	link_is_active = 1;
149
150	if (!link_is_active) {
151	/* try GEN 1 link speed */
152	#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
153	#define PCI_TARGET_LINK_SPEED_MASK 0xf
154	#define PCI_TARGET_LINK_SPEED_GEN2 0x2
155	#define PCI_TARGET_LINK_SPEED_GEN1 0x1
156	pci_bus_read_config_dword(bus, 0,
157	PCI_LINK_STATUS_CTRL_2_OFFSET,
158	&link_ctrl);
159	if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
160	PCI_TARGET_LINK_SPEED_GEN2) {
161	link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
162	link_ctrl \|= PCI_TARGET_LINK_SPEED_GEN1;
163	pci_bus_write_config_dword(bus, 0,
164	PCI_LINK_STATUS_CTRL_2_OFFSET,
165	link_ctrl);
166	msleep(100);
167
168	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
169	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
170	&link_status);
171	if (link_status & PCI_EXP_LNKSTA_NLW)
172	link_is_active = 1;
173	}
174	}
175
176	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
177
178	return link_is_active ? 0 : -ENODEV;
179	}
180
181	static void iproc_pcie_enable(struct iproc_pcie *pcie)
182	{
183	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
184	}
185
18c4342a	186	int iproc_pcie_setup(struct iproc_pcie pcie, struct list_head res)
1fb37a81 RJ	187	{
	188	int ret;
	189	struct pci_bus *bus;
	190
	191	if (!pcie \|\| !pcie->dev \|\| !pcie->base)
	192	return -EINVAL;
	193
93972d18 ME	194	ret = phy_init(pcie->phy);
	195	if (ret) {
	196	dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
	197	return ret;
	198	}
1fb37a81	199
93972d18 ME	200	ret = phy_power_on(pcie->phy);
	201	if (ret) {
	202	dev_err(pcie->dev, "unable to power on PCIe PHY\n");
	203	goto err_exit_phy;
1fb37a81 RJ	204	}
	205
	206	iproc_pcie_reset(pcie);
	207
	208	pcie->sysdata.private_data = pcie;
	209
	210	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
18c4342a	211	&pcie->sysdata, res);
1fb37a81 RJ	212	if (!bus) {
	213	dev_err(pcie->dev, "unable to create PCI root bus\n");
	214	ret = -ENOMEM;
	215	goto err_power_off_phy;
	216	}
	217	pcie->root_bus = bus;
	218
	219	ret = iproc_pcie_check_link(pcie, bus);
	220	if (ret) {
	221	dev_err(pcie->dev, "no PCIe EP device detected\n");
	222	goto err_rm_root_bus;
	223	}
	224
	225	iproc_pcie_enable(pcie);
	226
	227	pci_scan_child_bus(bus);
	228	pci_assign_unassigned_bus_resources(bus);
c1e02cea	229	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
1fb37a81 RJ	230	pci_bus_add_devices(bus);
	231
	232	return 0;
	233
	234	err_rm_root_bus:
	235	pci_stop_root_bus(bus);
	236	pci_remove_root_bus(bus);
	237
	238	err_power_off_phy:
93972d18	239	phy_power_off(pcie->phy);
1fb37a81	240	err_exit_phy:
93972d18	241	phy_exit(pcie->phy);
1fb37a81 RJ	242	return ret;
	243	}
	244	EXPORT_SYMBOL(iproc_pcie_setup);
	245
	246	int iproc_pcie_remove(struct iproc_pcie *pcie)
	247	{
	248	pci_stop_root_bus(pcie->root_bus);
	249	pci_remove_root_bus(pcie->root_bus);
	250
93972d18 ME	251	phy_power_off(pcie->phy);
93972d18 ME	252	phy_exit(pcie->phy);
1fb37a81 RJ	253
	254	return 0;
	255	}
	256	EXPORT_SYMBOL(iproc_pcie_remove);
	257
	258	MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
	259	MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
	260	MODULE_LICENSE("GPL v2");