[deliverable/linux.git] / drivers / pci / host / pcie-iproc.c

/*
 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
 * Copyright (C) 2015 Broadcom Corporatcommon ion
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mbus.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>

#include "pcie-iproc.h"

#define CLK_CONTROL_OFFSET           0x000
#define EP_MODE_SURVIVE_PERST_SHIFT  1
#define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
#define RC_PCIE_RST_OUTPUT_SHIFT     0
#define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)

#define CFG_IND_ADDR_OFFSET          0x120
#define CFG_IND_ADDR_MASK            0x00001ffc

#define CFG_IND_DATA_OFFSET          0x124

#define CFG_ADDR_OFFSET              0x1f8
#define CFG_ADDR_BUS_NUM_SHIFT       20
#define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT       15
#define CFG_ADDR_DEV_NUM_MASK        0x000f8000
#define CFG_ADDR_FUNC_NUM_SHIFT      12
#define CFG_ADDR_FUNC_NUM_MASK       0x00007000
#define CFG_ADDR_REG_NUM_SHIFT       2
#define CFG_ADDR_REG_NUM_MASK        0x00000ffc
#define CFG_ADDR_CFG_TYPE_SHIFT      0
#define CFG_ADDR_CFG_TYPE_MASK       0x00000003

#define CFG_DATA_OFFSET              0x1fc

#define SYS_RC_INTX_EN               0x330
#define SYS_RC_INTX_MASK             0xf

static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
{
	struct iproc_pcie *pcie;
#ifdef CONFIG_ARM
	struct pci_sys_data *sys = bus->sysdata;

	pcie = sys->private_data;
#else
	pcie = bus->sysdata;
#endif
	return pcie;
}

/**
 * Note access to the configuration registers are protected at the higher layer
 * by 'pci_lock' in drivers/pci/access.c
 */
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
					    unsigned int devfn,
					    int where)
{
	struct iproc_pcie *pcie = iproc_data(bus);
	unsigned slot = PCI_SLOT(devfn);
	unsigned fn = PCI_FUNC(devfn);
	unsigned busno = bus->number;
	u32 val;

	/* root complex access */
	if (busno == 0) {
		if (slot >= 1)
			return NULL;
		writel(where & CFG_IND_ADDR_MASK,
		       pcie->base + CFG_IND_ADDR_OFFSET);
		return (pcie->base + CFG_IND_DATA_OFFSET);
	}

	if (fn > 1)
		return NULL;

	/* EP device access */
	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
		(where & CFG_ADDR_REG_NUM_MASK) |
		(1 & CFG_ADDR_CFG_TYPE_MASK);
	writel(val, pcie->base + CFG_ADDR_OFFSET);

	return (pcie->base + CFG_DATA_OFFSET);
}

static struct pci_ops iproc_pcie_ops = {
	.map_bus = iproc_pcie_map_cfg_bus,
	.read = pci_generic_config_read32,
	.write = pci_generic_config_write32,
};

static void iproc_pcie_reset(struct iproc_pcie *pcie)
{
	u32 val;

	/*
	 * Configure the PCIe controller as root complex and send a downstream
	 * reset
	 */
	val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	udelay(250);
	val &= ~EP_MODE_SURVIVE_PERST;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	msleep(250);
}

static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
{
	u8 hdr_type;
	u32 link_ctrl;
	u16 pos, link_status;
	int link_is_active = 0;

	/* make sure we are not in EP mode */
	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
		dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
		return -EFAULT;
	}

	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
				  PCI_CLASS_BRIDGE_PCI);

	/* check link status to see if link is active */
	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	if (link_status & PCI_EXP_LNKSTA_NLW)
		link_is_active = 1;

	if (!link_is_active) {
		/* try GEN 1 link speed */
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
#define PCI_TARGET_LINK_SPEED_MASK    0xf
#define PCI_TARGET_LINK_SPEED_GEN2    0x2
#define PCI_TARGET_LINK_SPEED_GEN1    0x1
		pci_bus_read_config_dword(bus, 0,
					  PCI_LINK_STATUS_CTRL_2_OFFSET,
					  &link_ctrl);
		if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
		    PCI_TARGET_LINK_SPEED_GEN2) {
			link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
			link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
			pci_bus_write_config_dword(bus, 0,
					   PCI_LINK_STATUS_CTRL_2_OFFSET,
					   link_ctrl);
			msleep(100);

			pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
						 &link_status);
			if (link_status & PCI_EXP_LNKSTA_NLW)
				link_is_active = 1;
		}
	}

	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");

	return link_is_active ? 0 : -ENODEV;
}

static void iproc_pcie_enable(struct iproc_pcie *pcie)
{
	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
}

int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
{
	int ret;
	void *sysdata;
	struct pci_bus *bus;

	if (!pcie || !pcie->dev || !pcie->base)
		return -EINVAL;

	ret = phy_init(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
		return ret;
	}

	ret = phy_power_on(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to power on PCIe PHY\n");
		goto err_exit_phy;
	}

	iproc_pcie_reset(pcie);

#ifdef CONFIG_ARM
	pcie->sysdata.private_data = pcie;
	sysdata = &pcie->sysdata;
#else
	sysdata = pcie;
#endif

	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
	if (!bus) {
		dev_err(pcie->dev, "unable to create PCI root bus\n");
		ret = -ENOMEM;
		goto err_power_off_phy;
	}
	pcie->root_bus = bus;

	ret = iproc_pcie_check_link(pcie, bus);
	if (ret) {
		dev_err(pcie->dev, "no PCIe EP device detected\n");
		goto err_rm_root_bus;
	}

	iproc_pcie_enable(pcie);

	pci_scan_child_bus(bus);
	pci_assign_unassigned_bus_resources(bus);
	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
	pci_bus_add_devices(bus);

	return 0;

err_rm_root_bus:
	pci_stop_root_bus(bus);
	pci_remove_root_bus(bus);

err_power_off_phy:
	phy_power_off(pcie->phy);
err_exit_phy:
	phy_exit(pcie->phy);
	return ret;
}
EXPORT_SYMBOL(iproc_pcie_setup);

int iproc_pcie_remove(struct iproc_pcie *pcie)
{
	pci_stop_root_bus(pcie->root_bus);
	pci_remove_root_bus(pcie->root_bus);

	phy_power_off(pcie->phy);
	phy_exit(pcie->phy);

	return 0;
}
EXPORT_SYMBOL(iproc_pcie_remove);

MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1fb37a81 RJ	1	/*
	2	* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
	3	* Copyright (C) 2015 Broadcom Corporatcommon ion
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation version 2.
	8	*
	9	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	10	* kind, whether express or implied; without even the implied warranty
	11	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/msi.h>
	18	#include <linux/clk.h>
	19	#include <linux/module.h>
	20	#include <linux/mbus.h>
	21	#include <linux/slab.h>
	22	#include <linux/delay.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_pci.h>
	27	#include <linux/of_irq.h>
	28	#include <linux/of_platform.h>
	29	#include <linux/phy/phy.h>
	30
	31	#include "pcie-iproc.h"
	32
	33	#define CLK_CONTROL_OFFSET 0x000
	34	#define EP_MODE_SURVIVE_PERST_SHIFT 1
	35	#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
	36	#define RC_PCIE_RST_OUTPUT_SHIFT 0
	37	#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
	38
	39	#define CFG_IND_ADDR_OFFSET 0x120
	40	#define CFG_IND_ADDR_MASK 0x00001ffc
	41
	42	#define CFG_IND_DATA_OFFSET 0x124
	43
	44	#define CFG_ADDR_OFFSET 0x1f8
	45	#define CFG_ADDR_BUS_NUM_SHIFT 20
	46	#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
	47	#define CFG_ADDR_DEV_NUM_SHIFT 15
	48	#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
	49	#define CFG_ADDR_FUNC_NUM_SHIFT 12
	50	#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
	51	#define CFG_ADDR_REG_NUM_SHIFT 2
	52	#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
	53	#define CFG_ADDR_CFG_TYPE_SHIFT 0
	54	#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
	55
	56	#define CFG_DATA_OFFSET 0x1fc
	57
	58	#define SYS_RC_INTX_EN 0x330
	59	#define SYS_RC_INTX_MASK 0xf
	60
8d9bfe37	61	static inline struct iproc_pcie iproc_data(struct pci_bus bus)
1fb37a81	62	{
8d9bfe37 RJ	63	struct iproc_pcie *pcie;
	64	#ifdef CONFIG_ARM
	65	struct pci_sys_data *sys = bus->sysdata;
	66
	67	pcie = sys->private_data;
	68	#else
	69	pcie = bus->sysdata;
	70	#endif
	71	return pcie;
1fb37a81 RJ	72	}
	73
	74	/**
	75	* Note access to the configuration registers are protected at the higher layer
	76	* by 'pci_lock' in drivers/pci/access.c
	77	*/
	78	static void __iomem iproc_pcie_map_cfg_bus(struct pci_bus bus,
	79	unsigned int devfn,
	80	int where)
	81	{
8d9bfe37	82	struct iproc_pcie *pcie = iproc_data(bus);
1fb37a81 RJ	83	unsigned slot = PCI_SLOT(devfn);
	84	unsigned fn = PCI_FUNC(devfn);
	85	unsigned busno = bus->number;
	86	u32 val;
	87
	88	/* root complex access */
	89	if (busno == 0) {
	90	if (slot >= 1)
	91	return NULL;
	92	writel(where & CFG_IND_ADDR_MASK,
	93	pcie->base + CFG_IND_ADDR_OFFSET);
	94	return (pcie->base + CFG_IND_DATA_OFFSET);
	95	}
	96
	97	if (fn > 1)
	98	return NULL;
	99
	100	/* EP device access */
	101	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) \|
	102	(slot << CFG_ADDR_DEV_NUM_SHIFT) \|
	103	(fn << CFG_ADDR_FUNC_NUM_SHIFT) \|
	104	(where & CFG_ADDR_REG_NUM_MASK) \|
	105	(1 & CFG_ADDR_CFG_TYPE_MASK);
	106	writel(val, pcie->base + CFG_ADDR_OFFSET);
	107
	108	return (pcie->base + CFG_DATA_OFFSET);
	109	}
	110
	111	static struct pci_ops iproc_pcie_ops = {
	112	.map_bus = iproc_pcie_map_cfg_bus,
	113	.read = pci_generic_config_read32,
	114	.write = pci_generic_config_write32,
	115	};
	116
	117	static void iproc_pcie_reset(struct iproc_pcie *pcie)
	118	{
	119	u32 val;
	120
	121	/*
	122	* Configure the PCIe controller as root complex and send a downstream
	123	* reset
	124	*/
	125	val = EP_MODE_SURVIVE_PERST \| RC_PCIE_RST_OUTPUT;
	126	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	127	udelay(250);
	128	val &= ~EP_MODE_SURVIVE_PERST;
	129	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	130	msleep(250);
	131	}
	132
	133	static int iproc_pcie_check_link(struct iproc_pcie pcie, struct pci_bus bus)
	134	{
	135	u8 hdr_type;
	136	u32 link_ctrl;
	137	u16 pos, link_status;
	138	int link_is_active = 0;
	139
	140	/* make sure we are not in EP mode */
	141	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	142	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
	143	dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
	144	return -EFAULT;
	145	}
	146
147	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
148	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
149	PCI_CLASS_BRIDGE_PCI);
150
151	/* check link status to see if link is active */
152	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
153	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
154	if (link_status & PCI_EXP_LNKSTA_NLW)
155	link_is_active = 1;
156
157	if (!link_is_active) {
158	/* try GEN 1 link speed */
159	#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
160	#define PCI_TARGET_LINK_SPEED_MASK 0xf
161	#define PCI_TARGET_LINK_SPEED_GEN2 0x2
162	#define PCI_TARGET_LINK_SPEED_GEN1 0x1
163	pci_bus_read_config_dword(bus, 0,
164	PCI_LINK_STATUS_CTRL_2_OFFSET,
165	&link_ctrl);
166	if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
167	PCI_TARGET_LINK_SPEED_GEN2) {
168	link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
169	link_ctrl \|= PCI_TARGET_LINK_SPEED_GEN1;
170	pci_bus_write_config_dword(bus, 0,
171	PCI_LINK_STATUS_CTRL_2_OFFSET,
172	link_ctrl);
173	msleep(100);
174
175	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
176	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
177	&link_status);
178	if (link_status & PCI_EXP_LNKSTA_NLW)
179	link_is_active = 1;
180	}
181	}
182
183	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
184
185	return link_is_active ? 0 : -ENODEV;
186	}
187
188	static void iproc_pcie_enable(struct iproc_pcie *pcie)
189	{
190	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
191	}
192
18c4342a	193	int iproc_pcie_setup(struct iproc_pcie pcie, struct list_head res)
1fb37a81 RJ	194	{
1fb37a81 RJ	195	int ret;
8d9bfe37	196	void *sysdata;
1fb37a81 RJ	197	struct pci_bus *bus;
	198
	199	if (!pcie \|\| !pcie->dev \|\| !pcie->base)
	200	return -EINVAL;
	201
93972d18 ME	202	ret = phy_init(pcie->phy);
	203	if (ret) {
	204	dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
	205	return ret;
	206	}
1fb37a81	207
93972d18 ME	208	ret = phy_power_on(pcie->phy);
	209	if (ret) {
	210	dev_err(pcie->dev, "unable to power on PCIe PHY\n");
	211	goto err_exit_phy;
1fb37a81 RJ	212	}
	213
	214	iproc_pcie_reset(pcie);
	215
8d9bfe37	216	#ifdef CONFIG_ARM
1fb37a81	217	pcie->sysdata.private_data = pcie;
8d9bfe37 RJ	218	sysdata = &pcie->sysdata;
	219	#else
	220	sysdata = pcie;
	221	#endif
1fb37a81	222
8d9bfe37	223	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
1fb37a81 RJ	224	if (!bus) {
	225	dev_err(pcie->dev, "unable to create PCI root bus\n");
	226	ret = -ENOMEM;
	227	goto err_power_off_phy;
	228	}
	229	pcie->root_bus = bus;
	230
	231	ret = iproc_pcie_check_link(pcie, bus);
	232	if (ret) {
	233	dev_err(pcie->dev, "no PCIe EP device detected\n");
	234	goto err_rm_root_bus;
	235	}
	236
	237	iproc_pcie_enable(pcie);
	238
	239	pci_scan_child_bus(bus);
	240	pci_assign_unassigned_bus_resources(bus);
c1e02cea	241	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
1fb37a81 RJ	242	pci_bus_add_devices(bus);
	243
	244	return 0;
	245
	246	err_rm_root_bus:
	247	pci_stop_root_bus(bus);
	248	pci_remove_root_bus(bus);
	249
	250	err_power_off_phy:
93972d18	251	phy_power_off(pcie->phy);
1fb37a81	252	err_exit_phy:
93972d18	253	phy_exit(pcie->phy);
1fb37a81 RJ	254	return ret;
	255	}
	256	EXPORT_SYMBOL(iproc_pcie_setup);
	257
	258	int iproc_pcie_remove(struct iproc_pcie *pcie)
	259	{
	260	pci_stop_root_bus(pcie->root_bus);
	261	pci_remove_root_bus(pcie->root_bus);
	262
93972d18 ME	263	phy_power_off(pcie->phy);
93972d18 ME	264	phy_exit(pcie->phy);
1fb37a81 RJ	265
	266	return 0;
	267	}
	268	EXPORT_SYMBOL(iproc_pcie_remove);
	269
	270	MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
	271	MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
	272	MODULE_LICENSE("GPL v2");