[deliverable/linux.git] / drivers / pci / host / pcie-iproc.c

/*
 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
 * Copyright (C) 2015 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mbus.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>

#include "pcie-iproc.h"

#define CLK_CONTROL_OFFSET           0x000
#define EP_PERST_SOURCE_SELECT_SHIFT 2
#define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
#define EP_MODE_SURVIVE_PERST_SHIFT  1
#define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
#define RC_PCIE_RST_OUTPUT_SHIFT     0
#define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)

#define CFG_IND_ADDR_OFFSET          0x120
#define CFG_IND_ADDR_MASK            0x00001ffc

#define CFG_IND_DATA_OFFSET          0x124

#define CFG_ADDR_OFFSET              0x1f8
#define CFG_ADDR_BUS_NUM_SHIFT       20
#define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
#define CFG_ADDR_DEV_NUM_SHIFT       15
#define CFG_ADDR_DEV_NUM_MASK        0x000f8000
#define CFG_ADDR_FUNC_NUM_SHIFT      12
#define CFG_ADDR_FUNC_NUM_MASK       0x00007000
#define CFG_ADDR_REG_NUM_SHIFT       2
#define CFG_ADDR_REG_NUM_MASK        0x00000ffc
#define CFG_ADDR_CFG_TYPE_SHIFT      0
#define CFG_ADDR_CFG_TYPE_MASK       0x00000003

#define CFG_DATA_OFFSET              0x1fc

#define SYS_RC_INTX_EN               0x330
#define SYS_RC_INTX_MASK             0xf

#define PCIE_LINK_STATUS_OFFSET      0xf0c
#define PCIE_PHYLINKUP_SHIFT         3
#define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
#define PCIE_DL_ACTIVE_SHIFT         2
#define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)

#define OARR_VALID_SHIFT             0
#define OARR_VALID                   BIT(OARR_VALID_SHIFT)
#define OARR_SIZE_CFG_SHIFT          1
#define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)

#define OARR_LO(window)              (0xd20 + (window) * 8)
#define OARR_HI(window)              (0xd24 + (window) * 8)
#define OMAP_LO(window)              (0xd40 + (window) * 8)
#define OMAP_HI(window)              (0xd44 + (window) * 8)

#define MAX_NUM_OB_WINDOWS           2

static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
{
	struct iproc_pcie *pcie;
#ifdef CONFIG_ARM
	struct pci_sys_data *sys = bus->sysdata;

	pcie = sys->private_data;
#else
	pcie = bus->sysdata;
#endif
	return pcie;
}

/**
 * Note access to the configuration registers are protected at the higher layer
 * by 'pci_lock' in drivers/pci/access.c
 */
static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
					    unsigned int devfn,
					    int where)
{
	struct iproc_pcie *pcie = iproc_data(bus);
	unsigned slot = PCI_SLOT(devfn);
	unsigned fn = PCI_FUNC(devfn);
	unsigned busno = bus->number;
	u32 val;

	/* root complex access */
	if (busno == 0) {
		if (slot >= 1)
			return NULL;
		writel(where & CFG_IND_ADDR_MASK,
		       pcie->base + CFG_IND_ADDR_OFFSET);
		return (pcie->base + CFG_IND_DATA_OFFSET);
	}

	if (fn > 1)
		return NULL;

	/* EP device access */
	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
		(where & CFG_ADDR_REG_NUM_MASK) |
		(1 & CFG_ADDR_CFG_TYPE_MASK);
	writel(val, pcie->base + CFG_ADDR_OFFSET);

	return (pcie->base + CFG_DATA_OFFSET);
}

static struct pci_ops iproc_pcie_ops = {
	.map_bus = iproc_pcie_map_cfg_bus,
	.read = pci_generic_config_read32,
	.write = pci_generic_config_write32,
};

static void iproc_pcie_reset(struct iproc_pcie *pcie)
{
	u32 val;

	/*
	 * Select perst_b signal as reset source. Put the device into reset,
	 * and then bring it out of reset
	 */
	val = readl(pcie->base + CLK_CONTROL_OFFSET);
	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
		~RC_PCIE_RST_OUTPUT;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	udelay(250);

	val |= RC_PCIE_RST_OUTPUT;
	writel(val, pcie->base + CLK_CONTROL_OFFSET);
	msleep(100);
}

static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
{
	u8 hdr_type;
	u32 link_ctrl, class, val;
	u16 pos, link_status;
	bool link_is_active = false;

	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
		return -ENODEV;
	}

	/* make sure we are not in EP mode */
	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
		dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
		return -EFAULT;
	}

	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
#define PCI_CLASS_BRIDGE_MASK      0xffff00
#define PCI_CLASS_BRIDGE_SHIFT     8
	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
	class &= ~PCI_CLASS_BRIDGE_MASK;
	class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);

	/* check link status to see if link is active */
	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	if (link_status & PCI_EXP_LNKSTA_NLW)
		link_is_active = true;

	if (!link_is_active) {
		/* try GEN 1 link speed */
#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
#define PCI_TARGET_LINK_SPEED_MASK    0xf
#define PCI_TARGET_LINK_SPEED_GEN2    0x2
#define PCI_TARGET_LINK_SPEED_GEN1    0x1
		pci_bus_read_config_dword(bus, 0,
					  PCI_LINK_STATUS_CTRL_2_OFFSET,
					  &link_ctrl);
		if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
		    PCI_TARGET_LINK_SPEED_GEN2) {
			link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
			link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
			pci_bus_write_config_dword(bus, 0,
					   PCI_LINK_STATUS_CTRL_2_OFFSET,
					   link_ctrl);
			msleep(100);

			pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
						 &link_status);
			if (link_status & PCI_EXP_LNKSTA_NLW)
				link_is_active = true;
		}
	}

	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");

	return link_is_active ? 0 : -ENODEV;
}

static void iproc_pcie_enable(struct iproc_pcie *pcie)
{
	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
}

/**
 * Some iProc SoCs require the SW to configure the outbound address mapping
 *
 * Outbound address translation:
 *
 * iproc_pcie_address = axi_address - axi_offset
 * OARR = iproc_pcie_address
 * OMAP = pci_addr
 *
 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
 */
static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
			       u64 pci_addr, resource_size_t size)
{
	struct iproc_pcie_ob *ob = &pcie->ob;
	unsigned i;
	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
	u64 remainder;

	if (size > max_size) {
		dev_err(pcie->dev,
			"res size %pap exceeds max supported size 0x%llx\n",
			&size, max_size);
		return -EINVAL;
	}

	div64_u64_rem(size, ob->window_size, &remainder);
	if (remainder) {
		dev_err(pcie->dev,
			"res size %pap needs to be multiple of window size %pap\n",
			&size, &ob->window_size);
		return -EINVAL;
	}

	if (axi_addr < ob->axi_offset) {
		dev_err(pcie->dev,
			"axi address %pap less than offset %pap\n",
			&axi_addr, &ob->axi_offset);
		return -EINVAL;
	}

	/*
	 * Translate the AXI address to the internal address used by the iProc
	 * PCIe core before programming the OARR
	 */
	axi_addr -= ob->axi_offset;

	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
		writel(lower_32_bits(axi_addr) | OARR_VALID |
		       (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
		writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
		writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
		writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));

		size -= ob->window_size;
		if (size == 0)
			break;

		axi_addr += ob->window_size;
		pci_addr += ob->window_size;
	}

	return 0;
}

static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
				 struct list_head *resources)
{
	struct resource_entry *window;
	int ret;

	resource_list_for_each_entry(window, resources) {
		struct resource *res = window->res;
		u64 res_type = resource_type(res);

		switch (res_type) {
		case IORESOURCE_IO:
		case IORESOURCE_BUS:
			break;
		case IORESOURCE_MEM:
			ret = iproc_pcie_setup_ob(pcie, res->start,
						  res->start - window->offset,
						  resource_size(res));
			if (ret)
				return ret;
			break;
		default:
			dev_err(pcie->dev, "invalid resource %pR\n", res);
			return -EINVAL;
		}
	}

	return 0;
}

int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
{
	int ret;
	void *sysdata;
	struct pci_bus *bus;

	if (!pcie || !pcie->dev || !pcie->base)
		return -EINVAL;

	ret = phy_init(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
		return ret;
	}

	ret = phy_power_on(pcie->phy);
	if (ret) {
		dev_err(pcie->dev, "unable to power on PCIe PHY\n");
		goto err_exit_phy;
	}

	iproc_pcie_reset(pcie);

	if (pcie->need_ob_cfg) {
		ret = iproc_pcie_map_ranges(pcie, res);
		if (ret) {
			dev_err(pcie->dev, "map failed\n");
			goto err_power_off_phy;
		}
	}

#ifdef CONFIG_ARM
	pcie->sysdata.private_data = pcie;
	sysdata = &pcie->sysdata;
#else
	sysdata = pcie;
#endif

	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
	if (!bus) {
		dev_err(pcie->dev, "unable to create PCI root bus\n");
		ret = -ENOMEM;
		goto err_power_off_phy;
	}
	pcie->root_bus = bus;

	ret = iproc_pcie_check_link(pcie, bus);
	if (ret) {
		dev_err(pcie->dev, "no PCIe EP device detected\n");
		goto err_rm_root_bus;
	}

	iproc_pcie_enable(pcie);

	pci_scan_child_bus(bus);
	pci_assign_unassigned_bus_resources(bus);
	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
	pci_bus_add_devices(bus);

	return 0;

err_rm_root_bus:
	pci_stop_root_bus(bus);
	pci_remove_root_bus(bus);

err_power_off_phy:
	phy_power_off(pcie->phy);
err_exit_phy:
	phy_exit(pcie->phy);
	return ret;
}
EXPORT_SYMBOL(iproc_pcie_setup);

int iproc_pcie_remove(struct iproc_pcie *pcie)
{
	pci_stop_root_bus(pcie->root_bus);
	pci_remove_root_bus(pcie->root_bus);

	phy_power_off(pcie->phy);
	phy_exit(pcie->phy);

	return 0;
}
EXPORT_SYMBOL(iproc_pcie_remove);

MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1fb37a81 RJ	1	/*
1fb37a81 RJ	2	* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
be908d21	3	* Copyright (C) 2015 Broadcom Corporation
1fb37a81 RJ	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation version 2.
	8	*
	9	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	10	* kind, whether express or implied; without even the implied warranty
	11	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/msi.h>
	18	#include <linux/clk.h>
	19	#include <linux/module.h>
	20	#include <linux/mbus.h>
	21	#include <linux/slab.h>
	22	#include <linux/delay.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_pci.h>
	27	#include <linux/of_irq.h>
	28	#include <linux/of_platform.h>
	29	#include <linux/phy/phy.h>
	30
	31	#include "pcie-iproc.h"
	32
	33	#define CLK_CONTROL_OFFSET 0x000
199ff141 RJ	34	#define EP_PERST_SOURCE_SELECT_SHIFT 2
199ff141 RJ	35	#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
1fb37a81 RJ	36	#define EP_MODE_SURVIVE_PERST_SHIFT 1
	37	#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
	38	#define RC_PCIE_RST_OUTPUT_SHIFT 0
	39	#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
	40
	41	#define CFG_IND_ADDR_OFFSET 0x120
	42	#define CFG_IND_ADDR_MASK 0x00001ffc
	43
	44	#define CFG_IND_DATA_OFFSET 0x124
	45
	46	#define CFG_ADDR_OFFSET 0x1f8
	47	#define CFG_ADDR_BUS_NUM_SHIFT 20
	48	#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
	49	#define CFG_ADDR_DEV_NUM_SHIFT 15
	50	#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
	51	#define CFG_ADDR_FUNC_NUM_SHIFT 12
	52	#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
	53	#define CFG_ADDR_REG_NUM_SHIFT 2
	54	#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
	55	#define CFG_ADDR_CFG_TYPE_SHIFT 0
	56	#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
	57
	58	#define CFG_DATA_OFFSET 0x1fc
	59
	60	#define SYS_RC_INTX_EN 0x330
	61	#define SYS_RC_INTX_MASK 0xf
	62
aaf22ab4 RJ	63	#define PCIE_LINK_STATUS_OFFSET 0xf0c
	64	#define PCIE_PHYLINKUP_SHIFT 3
	65	#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
	66	#define PCIE_DL_ACTIVE_SHIFT 2
	67	#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
	68
e99a187b RJ	69	#define OARR_VALID_SHIFT 0
	70	#define OARR_VALID BIT(OARR_VALID_SHIFT)
	71	#define OARR_SIZE_CFG_SHIFT 1
	72	#define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
	73
	74	#define OARR_LO(window) (0xd20 + (window) * 8)
	75	#define OARR_HI(window) (0xd24 + (window) * 8)
	76	#define OMAP_LO(window) (0xd40 + (window) * 8)
	77	#define OMAP_HI(window) (0xd44 + (window) * 8)
	78
	79	#define MAX_NUM_OB_WINDOWS 2
	80
8d9bfe37	81	static inline struct iproc_pcie iproc_data(struct pci_bus bus)
1fb37a81	82	{
8d9bfe37 RJ	83	struct iproc_pcie *pcie;
	84	#ifdef CONFIG_ARM
	85	struct pci_sys_data *sys = bus->sysdata;
	86
	87	pcie = sys->private_data;
	88	#else
	89	pcie = bus->sysdata;
	90	#endif
	91	return pcie;
1fb37a81 RJ	92	}
	93
	94	/**
	95	* Note access to the configuration registers are protected at the higher layer
	96	* by 'pci_lock' in drivers/pci/access.c
	97	*/
	98	static void __iomem iproc_pcie_map_cfg_bus(struct pci_bus bus,
	99	unsigned int devfn,
	100	int where)
	101	{
8d9bfe37	102	struct iproc_pcie *pcie = iproc_data(bus);
1fb37a81 RJ	103	unsigned slot = PCI_SLOT(devfn);
	104	unsigned fn = PCI_FUNC(devfn);
	105	unsigned busno = bus->number;
	106	u32 val;
	107
	108	/* root complex access */
	109	if (busno == 0) {
	110	if (slot >= 1)
	111	return NULL;
	112	writel(where & CFG_IND_ADDR_MASK,
	113	pcie->base + CFG_IND_ADDR_OFFSET);
	114	return (pcie->base + CFG_IND_DATA_OFFSET);
	115	}
	116
	117	if (fn > 1)
	118	return NULL;
	119
	120	/* EP device access */
	121	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) \|
	122	(slot << CFG_ADDR_DEV_NUM_SHIFT) \|
	123	(fn << CFG_ADDR_FUNC_NUM_SHIFT) \|
	124	(where & CFG_ADDR_REG_NUM_MASK) \|
	125	(1 & CFG_ADDR_CFG_TYPE_MASK);
	126	writel(val, pcie->base + CFG_ADDR_OFFSET);
	127
	128	return (pcie->base + CFG_DATA_OFFSET);
	129	}
	130
	131	static struct pci_ops iproc_pcie_ops = {
	132	.map_bus = iproc_pcie_map_cfg_bus,
	133	.read = pci_generic_config_read32,
	134	.write = pci_generic_config_write32,
	135	};
	136
	137	static void iproc_pcie_reset(struct iproc_pcie *pcie)
	138	{
	139	u32 val;
	140
	141	/*
199ff141 RJ	142	* Select perst_b signal as reset source. Put the device into reset,
199ff141 RJ	143	* and then bring it out of reset
1fb37a81	144	*/
199ff141 RJ	145	val = readl(pcie->base + CLK_CONTROL_OFFSET);
	146	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
	147	~RC_PCIE_RST_OUTPUT;
1fb37a81 RJ	148	writel(val, pcie->base + CLK_CONTROL_OFFSET);
1fb37a81 RJ	149	udelay(250);
199ff141 RJ	150
199ff141 RJ	151	val \|= RC_PCIE_RST_OUTPUT;
1fb37a81	152	writel(val, pcie->base + CLK_CONTROL_OFFSET);
199ff141	153	msleep(100);
1fb37a81 RJ	154	}
	155
	156	static int iproc_pcie_check_link(struct iproc_pcie pcie, struct pci_bus bus)
	157	{
	158	u8 hdr_type;
aaf22ab4	159	u32 link_ctrl, class, val;
1fb37a81	160	u16 pos, link_status;
aaf22ab4 RJ	161	bool link_is_active = false;
	162
	163	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
	164	if (!(val & PCIE_PHYLINKUP) \|\| !(val & PCIE_DL_ACTIVE)) {
	165	dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
	166	return -ENODEV;
	167	}
1fb37a81 RJ	168
	169	/* make sure we are not in EP mode */
	170	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
	171	if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
	172	dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
	173	return -EFAULT;
	174	}
	175
	176	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
aaf22ab4 RJ	177	#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
	178	#define PCI_CLASS_BRIDGE_MASK 0xffff00
	179	#define PCI_CLASS_BRIDGE_SHIFT 8
	180	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
	181	class &= ~PCI_CLASS_BRIDGE_MASK;
	182	class \|= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
	183	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
1fb37a81 RJ	184
	185	/* check link status to see if link is active */
	186	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	187	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
	188	if (link_status & PCI_EXP_LNKSTA_NLW)
aaf22ab4	189	link_is_active = true;
1fb37a81 RJ	190
	191	if (!link_is_active) {
	192	/* try GEN 1 link speed */
	193	#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
	194	#define PCI_TARGET_LINK_SPEED_MASK 0xf
	195	#define PCI_TARGET_LINK_SPEED_GEN2 0x2
	196	#define PCI_TARGET_LINK_SPEED_GEN1 0x1
	197	pci_bus_read_config_dword(bus, 0,
	198	PCI_LINK_STATUS_CTRL_2_OFFSET,
	199	&link_ctrl);
	200	if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
	201	PCI_TARGET_LINK_SPEED_GEN2) {
	202	link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
	203	link_ctrl \|= PCI_TARGET_LINK_SPEED_GEN1;
	204	pci_bus_write_config_dword(bus, 0,
	205	PCI_LINK_STATUS_CTRL_2_OFFSET,
	206	link_ctrl);
	207	msleep(100);
	208
	209	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
	210	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
	211	&link_status);
	212	if (link_status & PCI_EXP_LNKSTA_NLW)
aaf22ab4	213	link_is_active = true;
1fb37a81 RJ	214	}
	215	}
	216
	217	dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
	218
	219	return link_is_active ? 0 : -ENODEV;
	220	}
	221
	222	static void iproc_pcie_enable(struct iproc_pcie *pcie)
	223	{
	224	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
	225	}
	226
e99a187b RJ	227	/**
	228	* Some iProc SoCs require the SW to configure the outbound address mapping
	229	*
	230	* Outbound address translation:
	231	*
	232	* iproc_pcie_address = axi_address - axi_offset
	233	* OARR = iproc_pcie_address
	234	* OMAP = pci_addr
	235	*
	236	* axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
	237	*/
	238	static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
	239	u64 pci_addr, resource_size_t size)
	240	{
	241	struct iproc_pcie_ob *ob = &pcie->ob;
	242	unsigned i;
	243	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
	244	u64 remainder;
	245
	246	if (size > max_size) {
	247	dev_err(pcie->dev,
57303e92	248	"res size %pap exceeds max supported size 0x%llx\n",
e99a187b RJ	249	&size, max_size);
	250	return -EINVAL;
	251	}
	252
	253	div64_u64_rem(size, ob->window_size, &remainder);
	254	if (remainder) {
	255	dev_err(pcie->dev,
	256	"res size %pap needs to be multiple of window size %pap\n",
	257	&size, &ob->window_size);
	258	return -EINVAL;
	259	}
	260
	261	if (axi_addr < ob->axi_offset) {
	262	dev_err(pcie->dev,
	263	"axi address %pap less than offset %pap\n",
	264	&axi_addr, &ob->axi_offset);
	265	return -EINVAL;
	266	}
	267
	268	/*
	269	* Translate the AXI address to the internal address used by the iProc
	270	* PCIe core before programming the OARR
	271	*/
	272	axi_addr -= ob->axi_offset;
	273
	274	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
	275	writel(lower_32_bits(axi_addr) \| OARR_VALID \|
	276	(ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
	277	writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
	278	writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
	279	writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
	280
	281	size -= ob->window_size;
	282	if (size == 0)
	283	break;
	284
	285	axi_addr += ob->window_size;
	286	pci_addr += ob->window_size;
	287	}
	288
	289	return 0;
	290	}
	291
	292	static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
	293	struct list_head *resources)
	294	{
	295	struct resource_entry *window;
	296	int ret;
	297
	298	resource_list_for_each_entry(window, resources) {
	299	struct resource *res = window->res;
	300	u64 res_type = resource_type(res);
	301
	302	switch (res_type) {
	303	case IORESOURCE_IO:
	304	case IORESOURCE_BUS:
	305	break;
	306	case IORESOURCE_MEM:
	307	ret = iproc_pcie_setup_ob(pcie, res->start,
	308	res->start - window->offset,
	309	resource_size(res));
	310	if (ret)
	311	return ret;
	312	break;
313	default:
314	dev_err(pcie->dev, "invalid resource %pR\n", res);
315	return -EINVAL;
316	}
317	}
318
319	return 0;
320	}
321
18c4342a	322	int iproc_pcie_setup(struct iproc_pcie pcie, struct list_head res)
1fb37a81 RJ	323	{
1fb37a81 RJ	324	int ret;
8d9bfe37	325	void *sysdata;
1fb37a81 RJ	326	struct pci_bus *bus;
	327
	328	if (!pcie \|\| !pcie->dev \|\| !pcie->base)
	329	return -EINVAL;
	330
93972d18 ME	331	ret = phy_init(pcie->phy);
	332	if (ret) {
	333	dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
	334	return ret;
	335	}
1fb37a81	336
93972d18 ME	337	ret = phy_power_on(pcie->phy);
	338	if (ret) {
	339	dev_err(pcie->dev, "unable to power on PCIe PHY\n");
	340	goto err_exit_phy;
1fb37a81 RJ	341	}
	342
	343	iproc_pcie_reset(pcie);
	344
e99a187b RJ	345	if (pcie->need_ob_cfg) {
	346	ret = iproc_pcie_map_ranges(pcie, res);
	347	if (ret) {
	348	dev_err(pcie->dev, "map failed\n");
	349	goto err_power_off_phy;
	350	}
	351	}
	352
8d9bfe37	353	#ifdef CONFIG_ARM
1fb37a81	354	pcie->sysdata.private_data = pcie;
8d9bfe37 RJ	355	sysdata = &pcie->sysdata;
	356	#else
	357	sysdata = pcie;
	358	#endif
1fb37a81	359
8d9bfe37	360	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
1fb37a81 RJ	361	if (!bus) {
	362	dev_err(pcie->dev, "unable to create PCI root bus\n");
	363	ret = -ENOMEM;
	364	goto err_power_off_phy;
	365	}
	366	pcie->root_bus = bus;
	367
	368	ret = iproc_pcie_check_link(pcie, bus);
	369	if (ret) {
	370	dev_err(pcie->dev, "no PCIe EP device detected\n");
	371	goto err_rm_root_bus;
	372	}
	373
	374	iproc_pcie_enable(pcie);
	375
	376	pci_scan_child_bus(bus);
	377	pci_assign_unassigned_bus_resources(bus);
c1e02cea	378	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
1fb37a81 RJ	379	pci_bus_add_devices(bus);
	380
	381	return 0;
	382
	383	err_rm_root_bus:
	384	pci_stop_root_bus(bus);
	385	pci_remove_root_bus(bus);
	386
	387	err_power_off_phy:
93972d18	388	phy_power_off(pcie->phy);
1fb37a81	389	err_exit_phy:
93972d18	390	phy_exit(pcie->phy);
1fb37a81 RJ	391	return ret;
	392	}
	393	EXPORT_SYMBOL(iproc_pcie_setup);
	394
	395	int iproc_pcie_remove(struct iproc_pcie *pcie)
	396	{
	397	pci_stop_root_bus(pcie->root_bus);
	398	pci_remove_root_bus(pcie->root_bus);
	399
93972d18 ME	400	phy_power_off(pcie->phy);
93972d18 ME	401	phy_exit(pcie->phy);
1fb37a81 RJ	402
	403	return 0;
	404	}
	405	EXPORT_SYMBOL(iproc_pcie_remove);
	406
	407	MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
	408	MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
	409	MODULE_LICENSE("GPL v2");