[deliverable/linux.git] / drivers / pci / host / pcie-spear13xx.c

/*
 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
 *
 * SPEAr13xx PCIe Glue Layer Source Code
 *
 * Copyright (C) 2010-2014 ST Microelectronics
 * Pratyush Anand <pratyush.anand@gmail.com>
 * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/resource.h>

#include "pcie-designware.h"

struct spear13xx_pcie {
	void __iomem		*app_base;
	struct phy		*phy;
	struct clk		*clk;
	struct pcie_port	pp;
	bool			is_gen1;
};

struct pcie_app_reg {
	u32	app_ctrl_0;		/* cr0 */
	u32	app_ctrl_1;		/* cr1 */
	u32	app_status_0;		/* cr2 */
	u32	app_status_1;		/* cr3 */
	u32	msg_status;		/* cr4 */
	u32	msg_payload;		/* cr5 */
	u32	int_sts;		/* cr6 */
	u32	int_clr;		/* cr7 */
	u32	int_mask;		/* cr8 */
	u32	mst_bmisc;		/* cr9 */
	u32	phy_ctrl;		/* cr10 */
	u32	phy_status;		/* cr11 */
	u32	cxpl_debug_info_0;	/* cr12 */
	u32	cxpl_debug_info_1;	/* cr13 */
	u32	ven_msg_ctrl_0;		/* cr14 */
	u32	ven_msg_ctrl_1;		/* cr15 */
	u32	ven_msg_data_0;		/* cr16 */
	u32	ven_msg_data_1;		/* cr17 */
	u32	ven_msi_0;		/* cr18 */
	u32	ven_msi_1;		/* cr19 */
	u32	mst_rmisc;		/* cr20 */
};

/* CR0 ID */
#define RX_LANE_FLIP_EN_ID			0
#define TX_LANE_FLIP_EN_ID			1
#define SYS_AUX_PWR_DET_ID			2
#define APP_LTSSM_ENABLE_ID			3
#define SYS_ATTEN_BUTTON_PRESSED_ID		4
#define SYS_MRL_SENSOR_STATE_ID			5
#define SYS_PWR_FAULT_DET_ID			6
#define SYS_MRL_SENSOR_CHGED_ID			7
#define SYS_PRE_DET_CHGED_ID			8
#define SYS_CMD_CPLED_INT_ID			9
#define APP_INIT_RST_0_ID			11
#define APP_REQ_ENTR_L1_ID			12
#define APP_READY_ENTR_L23_ID			13
#define APP_REQ_EXIT_L1_ID			14
#define DEVICE_TYPE_EP				(0 << 25)
#define DEVICE_TYPE_LEP				(1 << 25)
#define DEVICE_TYPE_RC				(4 << 25)
#define SYS_INT_ID				29
#define MISCTRL_EN_ID				30
#define REG_TRANSLATION_ENABLE			31

/* CR1 ID */
#define APPS_PM_XMT_TURNOFF_ID			2
#define APPS_PM_XMT_PME_ID			5

/* CR3 ID */
#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
#define XMLH_LTSSM_STATE_L0			0x11
#define XMLH_LTSSM_STATE_L0S			0x12
#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
#define XMLH_LTSSM_STATE_L1_IDLE		0x14
#define XMLH_LTSSM_STATE_L2_IDLE		0x15
#define XMLH_LTSSM_STATE_L2_WAKE		0x16
#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
#define XMLH_LTSSM_STATE_DISABLED		0x19
#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
#define XMLH_LTSSM_STATE_MASK			0x3F
#define XMLH_LINK_UP				(1 << 6)

/* CR4 ID */
#define CFG_MSI_EN_ID				18

/* CR6 */
#define INTA_CTRL_INT				(1 << 7)
#define INTB_CTRL_INT				(1 << 8)
#define INTC_CTRL_INT				(1 << 9)
#define INTD_CTRL_INT				(1 << 10)
#define MSI_CTRL_INT				(1 << 26)

/* CR19 ID */
#define VEN_MSI_REQ_ID				11
#define VEN_MSI_FUN_NUM_ID			8
#define VEN_MSI_TC_ID				5
#define VEN_MSI_VECTOR_ID			0
#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)

#define EXP_CAP_ID_OFFSET			0x70

#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)

static int spear13xx_pcie_establish_link(struct pcie_port *pp)
{
	u32 val;
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
	unsigned int retries;

	if (dw_pcie_link_up(pp)) {
		dev_err(pp->dev, "link already up\n");
		return 0;
	}

	dw_pcie_setup_rc(pp);

	/*
	 * this controller support only 128 bytes read size, however its
	 * default value in capability register is 512 bytes. So force
	 * it to 128 here.
	 */
	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
	val &= ~PCI_EXP_DEVCTL_READRQ;
	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);

	dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
	dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);

	/*
	 * if is_gen1 is set then handle it, so that some buggy card
	 * also works
	 */
	if (spear13xx_pcie->is_gen1) {
		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
					4, &val);
		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
				PCI_EXP_LNKCAP, 4, val);
		}

		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
					2, &val);
		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
					PCI_EXP_LNKCTL2, 2, val);
		}
	}

	/* enable ltssm */
	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
			| (1 << APP_LTSSM_ENABLE_ID)
			| ((u32)1 << REG_TRANSLATION_ENABLE),
			&app_reg->app_ctrl_0);

	/* check if the link is up or not */
	for (retries = 0; retries < 10; retries++) {
		if (dw_pcie_link_up(pp)) {
			dev_info(pp->dev, "link up\n");
			return 0;
		}
		mdelay(100);
	}

	dev_err(pp->dev, "link Fail\n");
	return -EINVAL;
}

static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	unsigned int status;

	status = readl(&app_reg->int_sts);

	if (status & MSI_CTRL_INT) {
		BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
		dw_handle_msi_irq(pp);
	}

	writel(status, &app_reg->int_clr);

	return IRQ_HANDLED;
}

static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
{
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;

	/* Enable MSI interrupt */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		dw_pcie_msi_init(pp);
		writel(readl(&app_reg->int_mask) |
				MSI_CTRL_INT, &app_reg->int_mask);
	}
}

static int spear13xx_pcie_link_up(struct pcie_port *pp)
{
	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;

	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
		return 1;

	return 0;
}

static void spear13xx_pcie_host_init(struct pcie_port *pp)
{
	spear13xx_pcie_establish_link(pp);
	spear13xx_pcie_enable_interrupts(pp);
}

static struct pcie_host_ops spear13xx_pcie_host_ops = {
	.link_up = spear13xx_pcie_link_up,
	.host_init = spear13xx_pcie_host_init,
};

static int spear13xx_add_pcie_port(struct pcie_port *pp,
					 struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	int ret;

	pp->irq = platform_get_irq(pdev, 0);
	if (!pp->irq) {
		dev_err(dev, "failed to get irq\n");
		return -ENODEV;
	}
	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
			       IRQF_SHARED, "spear1340-pcie", pp);
	if (ret) {
		dev_err(dev, "failed to request irq %d\n", pp->irq);
		return ret;
	}

	pp->root_bus_nr = -1;
	pp->ops = &spear13xx_pcie_host_ops;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int spear13xx_pcie_probe(struct platform_device *pdev)
{
	struct spear13xx_pcie *spear13xx_pcie;
	struct pcie_port *pp;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct resource *dbi_base;
	int ret;

	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
	if (!spear13xx_pcie)
		return -ENOMEM;

	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
	if (IS_ERR(spear13xx_pcie->phy)) {
		ret = PTR_ERR(spear13xx_pcie->phy);
		if (ret == -EPROBE_DEFER)
			dev_info(dev, "probe deferred\n");
		else
			dev_err(dev, "couldn't get pcie-phy\n");
		return ret;
	}

	phy_init(spear13xx_pcie->phy);

	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(spear13xx_pcie->clk)) {
		dev_err(dev, "couldn't get clk for pcie\n");
		return PTR_ERR(spear13xx_pcie->clk);
	}
	ret = clk_prepare_enable(spear13xx_pcie->clk);
	if (ret) {
		dev_err(dev, "couldn't enable clk for pcie\n");
		return ret;
	}

	pp = &spear13xx_pcie->pp;

	pp->dev = dev;

	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
	if (IS_ERR(pp->dbi_base)) {
		dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
		ret = PTR_ERR(pp->dbi_base);
		goto fail_clk;
	}
	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;

	if (of_property_read_bool(np, "st,pcie-is-gen1"))
		spear13xx_pcie->is_gen1 = true;

	ret = spear13xx_add_pcie_port(pp, pdev);
	if (ret < 0)
		goto fail_clk;

	platform_set_drvdata(pdev, spear13xx_pcie);
	return 0;

fail_clk:
	clk_disable_unprepare(spear13xx_pcie->clk);

	return ret;
}

static const struct of_device_id spear13xx_pcie_of_match[] = {
	{ .compatible = "st,spear1340-pcie", },
	{},
};
MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);

static struct platform_driver spear13xx_pcie_driver = {
	.probe		= spear13xx_pcie_probe,
	.driver = {
		.name	= "spear-pcie",
		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
	},
};

/* SPEAr13xx PCIe driver does not allow module unload */

static int __init spear13xx_pcie_init(void)
{
	return platform_driver_register(&spear13xx_pcie_driver);
}
module_init(spear13xx_pcie_init);

MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
51b66a6c PA	1	/*
	2	* PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
	3	*
	4	* SPEAr13xx PCIe Glue Layer Source Code
	5	*
	6	* Copyright (C) 2010-2014 ST Microelectronics
e34cadde	7	* Pratyush Anand <pratyush.anand@gmail.com>
9c5dcdd0	8	* Mohit Kumar <mohit.kumar.dhaka@gmail.com>
51b66a6c PA	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/delay.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/pci.h>
	22	#include <linux/phy/phy.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/resource.h>
	25
	26	#include "pcie-designware.h"
	27
	28	struct spear13xx_pcie {
	29	void __iomem *app_base;
	30	struct phy *phy;
	31	struct clk *clk;
	32	struct pcie_port pp;
	33	bool is_gen1;
	34	};
	35
	36	struct pcie_app_reg {
	37	u32 app_ctrl_0; /* cr0 */
	38	u32 app_ctrl_1; /* cr1 */
	39	u32 app_status_0; /* cr2 */
	40	u32 app_status_1; /* cr3 */
	41	u32 msg_status; /* cr4 */
	42	u32 msg_payload; /* cr5 */
	43	u32 int_sts; /* cr6 */
	44	u32 int_clr; /* cr7 */
	45	u32 int_mask; /* cr8 */
	46	u32 mst_bmisc; /* cr9 */
	47	u32 phy_ctrl; /* cr10 */
	48	u32 phy_status; /* cr11 */
	49	u32 cxpl_debug_info_0; /* cr12 */
	50	u32 cxpl_debug_info_1; /* cr13 */
	51	u32 ven_msg_ctrl_0; /* cr14 */
	52	u32 ven_msg_ctrl_1; /* cr15 */
	53	u32 ven_msg_data_0; /* cr16 */
	54	u32 ven_msg_data_1; /* cr17 */
	55	u32 ven_msi_0; /* cr18 */
	56	u32 ven_msi_1; /* cr19 */
	57	u32 mst_rmisc; /* cr20 */
	58	};
	59
	60	/* CR0 ID */
	61	#define RX_LANE_FLIP_EN_ID 0
	62	#define TX_LANE_FLIP_EN_ID 1
	63	#define SYS_AUX_PWR_DET_ID 2
	64	#define APP_LTSSM_ENABLE_ID 3
	65	#define SYS_ATTEN_BUTTON_PRESSED_ID 4
	66	#define SYS_MRL_SENSOR_STATE_ID 5
	67	#define SYS_PWR_FAULT_DET_ID 6
	68	#define SYS_MRL_SENSOR_CHGED_ID 7
	69	#define SYS_PRE_DET_CHGED_ID 8
	70	#define SYS_CMD_CPLED_INT_ID 9
	71	#define APP_INIT_RST_0_ID 11
	72	#define APP_REQ_ENTR_L1_ID 12
73	#define APP_READY_ENTR_L23_ID 13
74	#define APP_REQ_EXIT_L1_ID 14
75	#define DEVICE_TYPE_EP (0 << 25)
76	#define DEVICE_TYPE_LEP (1 << 25)
77	#define DEVICE_TYPE_RC (4 << 25)
78	#define SYS_INT_ID 29
79	#define MISCTRL_EN_ID 30
80	#define REG_TRANSLATION_ENABLE 31
81
82	/* CR1 ID */
83	#define APPS_PM_XMT_TURNOFF_ID 2
84	#define APPS_PM_XMT_PME_ID 5
85
86	/* CR3 ID */
87	#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
88	#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
89	#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
90	#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
91	#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
92	#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
93	#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
94	#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
95	#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
96	#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
97	#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
98	#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
99	#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
100	#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
101	#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
102	#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
103	#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
104	#define XMLH_LTSSM_STATE_L0 0x11
105	#define XMLH_LTSSM_STATE_L0S 0x12
106	#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
107	#define XMLH_LTSSM_STATE_L1_IDLE 0x14
108	#define XMLH_LTSSM_STATE_L2_IDLE 0x15
109	#define XMLH_LTSSM_STATE_L2_WAKE 0x16
110	#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
111	#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
112	#define XMLH_LTSSM_STATE_DISABLED 0x19
113	#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
114	#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
115	#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
116	#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
117	#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
118	#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
119	#define XMLH_LTSSM_STATE_MASK 0x3F
120	#define XMLH_LINK_UP (1 << 6)
121
122	/* CR4 ID */
123	#define CFG_MSI_EN_ID 18
124
125	/* CR6 */
126	#define INTA_CTRL_INT (1 << 7)
127	#define INTB_CTRL_INT (1 << 8)
128	#define INTC_CTRL_INT (1 << 9)
129	#define INTD_CTRL_INT (1 << 10)
130	#define MSI_CTRL_INT (1 << 26)
131
132	/* CR19 ID */
133	#define VEN_MSI_REQ_ID 11
134	#define VEN_MSI_FUN_NUM_ID 8
135	#define VEN_MSI_TC_ID 5
136	#define VEN_MSI_VECTOR_ID 0
137	#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
138	#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
139	#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
140	#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
141
142	#define EXP_CAP_ID_OFFSET 0x70
143
144	#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
145
146	static int spear13xx_pcie_establish_link(struct pcie_port *pp)
147	{
148	u32 val;
51b66a6c PA	149	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	150	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	151	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
6cbb247e	152	unsigned int retries;
51b66a6c PA	153
	154	if (dw_pcie_link_up(pp)) {
	155	dev_err(pp->dev, "link already up\n");
	156	return 0;
	157	}
	158
	159	dw_pcie_setup_rc(pp);
	160
	161	/*
	162	* this controller support only 128 bytes read size, however its
	163	* default value in capability register is 512 bytes. So force
	164	* it to 128 here.
	165	*/
4c45852f	166	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
51b66a6c	167	val &= ~PCI_EXP_DEVCTL_READRQ;
4c45852f	168	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
51b66a6c	169
4c45852f GP	170	dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
4c45852f GP	171	dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
51b66a6c PA	172
	173	/*
	174	* if is_gen1 is set then handle it, so that some buggy card
	175	* also works
	176	*/
	177	if (spear13xx_pcie->is_gen1) {
fa3b7cba	178	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
4c45852f	179	4, &val);
51b66a6c PA	180	if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	181	val &= ~((u32)PCI_EXP_LNKCAP_SLS);
	182	val \|= PCI_EXP_LNKCAP_SLS_2_5GB;
fa3b7cba	183	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
4c45852f	184	PCI_EXP_LNKCAP, 4, val);
51b66a6c PA	185	}
51b66a6c PA	186
fa3b7cba	187	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
4c45852f	188	2, &val);
51b66a6c PA	189	if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
	190	val &= ~((u32)PCI_EXP_LNKCAP_SLS);
	191	val \|= PCI_EXP_LNKCAP_SLS_2_5GB;
fa3b7cba	192	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
4c45852f	193	PCI_EXP_LNKCTL2, 2, val);
51b66a6c PA	194	}
	195	}
	196
	197	/* enable ltssm */
	198	writel(DEVICE_TYPE_RC \| (1 << MISCTRL_EN_ID)
	199	\| (1 << APP_LTSSM_ENABLE_ID)
	200	\| ((u32)1 << REG_TRANSLATION_ENABLE),
	201	&app_reg->app_ctrl_0);
	202
	203	/* check if the link is up or not */
6cbb247e BH	204	for (retries = 0; retries < 10; retries++) {
	205	if (dw_pcie_link_up(pp)) {
	206	dev_info(pp->dev, "link up\n");
	207	return 0;
51b66a6c	208	}
6cbb247e	209	mdelay(100);
51b66a6c	210	}
51b66a6c	211
6cbb247e BH	212	dev_err(pp->dev, "link Fail\n");
6cbb247e BH	213	return -EINVAL;
51b66a6c PA	214	}
	215
	216	static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
	217	{
	218	struct pcie_port *pp = arg;
	219	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	220	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	221	unsigned int status;
	222
	223	status = readl(&app_reg->int_sts);
	224
	225	if (status & MSI_CTRL_INT) {
68ebb7ce	226	BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
51b66a6c PA	227	dw_handle_msi_irq(pp);
	228	}
	229
	230	writel(status, &app_reg->int_clr);
	231
	232	return IRQ_HANDLED;
	233	}
	234
	235	static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
	236	{
	237	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	238	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	239
	240	/* Enable MSI interrupt */
	241	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	242	dw_pcie_msi_init(pp);
	243	writel(readl(&app_reg->int_mask) \|
	244	MSI_CTRL_INT, &app_reg->int_mask);
	245	}
	246	}
	247
	248	static int spear13xx_pcie_link_up(struct pcie_port *pp)
	249	{
	250	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
	251	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
	252
	253	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
	254	return 1;
	255
	256	return 0;
	257	}
	258
	259	static void spear13xx_pcie_host_init(struct pcie_port *pp)
	260	{
	261	spear13xx_pcie_establish_link(pp);
	262	spear13xx_pcie_enable_interrupts(pp);
	263	}
	264
	265	static struct pcie_host_ops spear13xx_pcie_host_ops = {
	266	.link_up = spear13xx_pcie_link_up,
	267	.host_init = spear13xx_pcie_host_init,
	268	};
	269
a43f32d6	270	static int spear13xx_add_pcie_port(struct pcie_port *pp,
992e7bd2	271	struct platform_device *pdev)
51b66a6c PA	272	{
	273	struct device *dev = &pdev->dev;
	274	int ret;
	275
	276	pp->irq = platform_get_irq(pdev, 0);
	277	if (!pp->irq) {
	278	dev_err(dev, "failed to get irq\n");
	279	return -ENODEV;
	280	}
	281	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
	282	IRQF_SHARED, "spear1340-pcie", pp);
	283	if (ret) {
	284	dev_err(dev, "failed to request irq %d\n", pp->irq);
	285	return ret;
	286	}
	287
	288	pp->root_bus_nr = -1;
	289	pp->ops = &spear13xx_pcie_host_ops;
	290
	291	ret = dw_pcie_host_init(pp);
	292	if (ret) {
	293	dev_err(dev, "failed to initialize host\n");
	294	return ret;
	295	}
	296
	297	return 0;
	298	}
	299
a43f32d6	300	static int spear13xx_pcie_probe(struct platform_device *pdev)
51b66a6c PA	301	{
	302	struct spear13xx_pcie *spear13xx_pcie;
	303	struct pcie_port *pp;
	304	struct device *dev = &pdev->dev;
	305	struct device_node *np = pdev->dev.of_node;
	306	struct resource *dbi_base;
	307	int ret;
	308
	309	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
20f9ece1	310	if (!spear13xx_pcie)
51b66a6c	311	return -ENOMEM;
51b66a6c PA	312
	313	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
	314	if (IS_ERR(spear13xx_pcie->phy)) {
	315	ret = PTR_ERR(spear13xx_pcie->phy);
	316	if (ret == -EPROBE_DEFER)
	317	dev_info(dev, "probe deferred\n");
	318	else
	319	dev_err(dev, "couldn't get pcie-phy\n");
	320	return ret;
	321	}
	322
	323	phy_init(spear13xx_pcie->phy);
	324
	325	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
	326	if (IS_ERR(spear13xx_pcie->clk)) {
	327	dev_err(dev, "couldn't get clk for pcie\n");
	328	return PTR_ERR(spear13xx_pcie->clk);
	329	}
	330	ret = clk_prepare_enable(spear13xx_pcie->clk);
	331	if (ret) {
	332	dev_err(dev, "couldn't enable clk for pcie\n");
	333	return ret;
	334	}
	335
	336	pp = &spear13xx_pcie->pp;
	337
	338	pp->dev = dev;
	339
65aaae24	340	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
51b66a6c PA	341	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
	342	if (IS_ERR(pp->dbi_base)) {
	343	dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
	344	ret = PTR_ERR(pp->dbi_base);
	345	goto fail_clk;
	346	}
	347	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
	348
	349	if (of_property_read_bool(np, "st,pcie-is-gen1"))
	350	spear13xx_pcie->is_gen1 = true;
	351
a9875d83	352	ret = spear13xx_add_pcie_port(pp, pdev);
51b66a6c PA	353	if (ret < 0)
	354	goto fail_clk;
	355
	356	platform_set_drvdata(pdev, spear13xx_pcie);
	357	return 0;
	358
	359	fail_clk:
	360	clk_disable_unprepare(spear13xx_pcie->clk);
	361
	362	return ret;
	363	}
	364
51b66a6c PA	365	static const struct of_device_id spear13xx_pcie_of_match[] = {
	366	{ .compatible = "st,spear1340-pcie", },
	367	{},
	368	};
	369	MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
	370
a43f32d6	371	static struct platform_driver spear13xx_pcie_driver = {
51b66a6c	372	.probe = spear13xx_pcie_probe,
51b66a6c PA	373	.driver = {
51b66a6c PA	374	.name = "spear-pcie",
51b66a6c PA	375	.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
	376	},
	377	};
	378
	379	/* SPEAr13xx PCIe driver does not allow module unload */
	380
a9875d83	381	static int __init spear13xx_pcie_init(void)
51b66a6c PA	382	{
	383	return platform_driver_register(&spear13xx_pcie_driver);
	384	}
a9875d83	385	module_init(spear13xx_pcie_init);
51b66a6c PA	386
51b66a6c PA	387	MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
e34cadde	388	MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>");
51b66a6c	389	MODULE_LICENSE("GPL v2");