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drm/cirrus: Constify function pointer structs
[deliverable/linux.git] / drivers / pci / host / pcie-xilinx.c
CommitLineData
8961def5
ST		 1/*
2 * PCIe host controller driver for Xilinx AXI PCIe Bridge
3 *
4 * Copyright (c) 2012 - 2014 Xilinx, Inc.
5 *
6 * Based on the Tegra PCIe driver
7 *
8 * Bits taken from Synopsys Designware Host controller driver and
9 * ARM PCI Host generic driver.
10 *
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_pci.h>
25#include <linux/of_platform.h>
26#include <linux/of_irq.h>
27#include <linux/pci.h>
28#include <linux/platform_device.h>
29
30/* Register definitions */
31#define XILINX_PCIE_REG_BIR 0x00000130
32#define XILINX_PCIE_REG_IDR 0x00000138
33#define XILINX_PCIE_REG_IMR 0x0000013c
34#define XILINX_PCIE_REG_PSCR 0x00000144
35#define XILINX_PCIE_REG_RPSC 0x00000148
36#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
37#define XILINX_PCIE_REG_MSIBASE2 0x00000150
38#define XILINX_PCIE_REG_RPEFR 0x00000154
39#define XILINX_PCIE_REG_RPIFR1 0x00000158
40#define XILINX_PCIE_REG_RPIFR2 0x0000015c
41
42/* Interrupt registers definitions */
43#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
44#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
45#define XILINX_PCIE_INTR_STR_ERR BIT(2)
46#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
47#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
48#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
49#define XILINX_PCIE_INTR_NONFATAL BIT(10)
50#define XILINX_PCIE_INTR_FATAL BIT(11)
51#define XILINX_PCIE_INTR_INTX BIT(16)
52#define XILINX_PCIE_INTR_MSI BIT(17)
53#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
54#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
55#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
56#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
57#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
58#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
59#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
60#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
61#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
62#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
63#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
64
65/* Root Port Error FIFO Read Register definitions */
66#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
67#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
68#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
69
70/* Root Port Interrupt FIFO Read Register 1 definitions */
71#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
72#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
73#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
74#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
75#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
76
77/* Bridge Info Register definitions */
78#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
79#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
80
81/* Root Port Interrupt FIFO Read Register 2 definitions */
82#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
83
84/* Root Port Status/control Register definitions */
85#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
86
87/* Phy Status/Control Register definitions */
88#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
89
90/* ECAM definitions */
91#define ECAM_BUS_NUM_SHIFT 20
92#define ECAM_DEV_NUM_SHIFT 12
93
94/* Number of MSI IRQs */
95#define XILINX_NUM_MSI_IRQS 128
96
97/* Number of Memory Resources */
98#define XILINX_MAX_NUM_RESOURCES 3
99
100/**
101 * struct xilinx_pcie_port - PCIe port information
102 * @reg_base: IO Mapped Register Base
103 * @irq: Interrupt number
104 * @msi_pages: MSI pages
105 * @root_busno: Root Bus number
106 * @dev: Device pointer
107 * @irq_domain: IRQ domain pointer
108 * @bus_range: Bus range
109 * @resources: Bus Resources
110 */
111struct xilinx_pcie_port {
112 void __iomem *reg_base;
113 u32 irq;
114 unsigned long msi_pages;
115 u8 root_busno;
116 struct device *dev;
117 struct irq_domain *irq_domain;
118 struct resource bus_range;
119 struct list_head resources;
120};
121
122static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
123
124static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
125{
126 return sys->private_data;
127}
128
129static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
130{
131 return readl(port->reg_base + reg);
132}
133
134static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
135{
136 writel(val, port->reg_base + reg);
137}
138
139static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
140{
141 return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
142 XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
143}
144
145/**
146 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
147 * @port: PCIe port information
148 */
149static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
150{
abc596b9 151 unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
8961def5
ST		 152
153 if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
abc596b9 154 dev_dbg(port->dev, "Requester ID %lu\n",
8961def5
ST		 155 val & XILINX_PCIE_RPEFR_REQ_ID);
156 pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
157 XILINX_PCIE_REG_RPEFR);
158 }
159}
160
161/**
162 * xilinx_pcie_valid_device - Check if a valid device is present on bus
163 * @bus: PCI Bus structure
164 * @devfn: device/function
165 *
166 * Return: 'true' on success and 'false' if invalid device is found
167 */
168static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
169{
170 struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
171
172 /* Check if link is up when trying to access downstream ports */
173 if (bus->number != port->root_busno)
174 if (!xilinx_pcie_link_is_up(port))
175 return false;
176
177 /* Only one device down on each root port */
178 if (bus->number == port->root_busno && devfn > 0)
179 return false;
180
181 /*
182 * Do not read more than one device on the bus directly attached
183 * to RC.
184 */
185 if (bus->primary == port->root_busno && devfn > 0)
186 return false;
187
188 return true;
189}
190
191/**
029e2151 192 * xilinx_pcie_map_bus - Get configuration base
8961def5
ST		 193 * @bus: PCI Bus structure
194 * @devfn: Device/function
195 * @where: Offset from base
196 *
197 * Return: Base address of the configuration space needed to be
198 * accessed.
199 */
029e2151
RH		 200static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
201 unsigned int devfn, int where)
8961def5
ST		 202{
203 struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
204 int relbus;
205
029e2151
RH		 206 if (!xilinx_pcie_valid_device(bus, devfn))
207 return NULL;
208
8961def5
ST		 209 relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
210 (devfn << ECAM_DEV_NUM_SHIFT);
211
212 return port->reg_base + relbus + where;
213}
214
8961def5
ST		 215/* PCIe operations */
216static struct pci_ops xilinx_pcie_ops = {
029e2151
RH		 217 .map_bus = xilinx_pcie_map_bus,
218 .read = pci_generic_config_read,
219 .write = pci_generic_config_write,
8961def5
ST		 220};
221
222/* MSI functions */
223
224/**
225 * xilinx_pcie_destroy_msi - Free MSI number
226 * @irq: IRQ to be freed
227 */
228static void xilinx_pcie_destroy_msi(unsigned int irq)
229{
8961def5
ST		 230 struct msi_desc *msi;
231 struct xilinx_pcie_port *port;
232
e39758e0
JL		 233 if (!test_bit(irq, msi_irq_in_use)) {
234 msi = irq_get_msi_desc(irq);
649953b5 235 port = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
8961def5 236 dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
e39758e0 237 } else {
8961def5 238 clear_bit(irq, msi_irq_in_use);
e39758e0 239 }
8961def5
ST		 240}
241
242/**
243 * xilinx_pcie_assign_msi - Allocate MSI number
244 * @port: PCIe port structure
245 *
246 * Return: A valid IRQ on success and error value on failure.
247 */
248static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
249{
250 int pos;
251
252 pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
253 if (pos < XILINX_NUM_MSI_IRQS)
254 set_bit(pos, msi_irq_in_use);
255 else
256 return -ENOSPC;
257
258 return pos;
259}
260
261/**
262 * xilinx_msi_teardown_irq - Destroy the MSI
263 * @chip: MSI Chip descriptor
264 * @irq: MSI IRQ to destroy
265 */
c2791b80
YW		 266static void xilinx_msi_teardown_irq(struct msi_controller *chip,
267 unsigned int irq)
8961def5
ST		 268{
269 xilinx_pcie_destroy_msi(irq);
270}
271
272/**
273 * xilinx_pcie_msi_setup_irq - Setup MSI request
274 * @chip: MSI chip pointer
275 * @pdev: PCIe device pointer
276 * @desc: MSI descriptor pointer
277 *
278 * Return: '0' on success and error value on failure
279 */
c2791b80 280static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
8961def5
ST		 281 struct pci_dev *pdev,
282 struct msi_desc *desc)
283{
284 struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
285 unsigned int irq;
286 int hwirq;
287 struct msi_msg msg;
288 phys_addr_t msg_addr;
289
290 hwirq = xilinx_pcie_assign_msi(port);
f9dd0ce6
DC		 291 if (hwirq < 0)
292 return hwirq;
8961def5
ST		 293
294 irq = irq_create_mapping(port->irq_domain, hwirq);
295 if (!irq)
296 return -EINVAL;
297
298 irq_set_msi_desc(irq, desc);
299
300 msg_addr = virt_to_phys((void *)port->msi_pages);
301
302 msg.address_hi = 0;
303 msg.address_lo = msg_addr;
304 msg.data = irq;
305
83a18912 306 pci_write_msi_msg(irq, &msg);
8961def5
ST		 307
308 return 0;
309}
310
311/* MSI Chip Descriptor */
c2791b80 312static struct msi_controller xilinx_pcie_msi_chip = {
8961def5
ST		 313 .setup_irq = xilinx_pcie_msi_setup_irq,
314 .teardown_irq = xilinx_msi_teardown_irq,
315};
316
317/* HW Interrupt Chip Descriptor */
318static struct irq_chip xilinx_msi_irq_chip = {
319 .name = "Xilinx PCIe MSI",
280510f1
TG		 320 .irq_enable = pci_msi_unmask_irq,
321 .irq_disable = pci_msi_mask_irq,
322 .irq_mask = pci_msi_mask_irq,
323 .irq_unmask = pci_msi_unmask_irq,
8961def5
ST		 324};
325
326/**
327 * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
328 * @domain: IRQ domain
329 * @irq: Virtual IRQ number
330 * @hwirq: HW interrupt number
331 *
332 * Return: Always returns 0.
333 */
334static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
335 irq_hw_number_t hwirq)
336{
337 irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
338 irq_set_chip_data(irq, domain->host_data);
8961def5
ST		 339
340 return 0;
341}
342
343/* IRQ Domain operations */
344static const struct irq_domain_ops msi_domain_ops = {
345 .map = xilinx_pcie_msi_map,
346};
347
348/**
349 * xilinx_pcie_enable_msi - Enable MSI support
350 * @port: PCIe port information
351 */
352static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
353{
354 phys_addr_t msg_addr;
355
356 port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
357 msg_addr = virt_to_phys((void *)port->msi_pages);
358 pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
359 pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
360}
361
8961def5
ST		 362/* INTx Functions */
363
364/**
365 * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
366 * @domain: IRQ domain
367 * @irq: Virtual IRQ number
368 * @hwirq: HW interrupt number
369 *
370 * Return: Always returns 0.
371 */
372static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
373 irq_hw_number_t hwirq)
374{
375 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
376 irq_set_chip_data(irq, domain->host_data);
8961def5
ST		 377
378 return 0;
379}
380
381/* INTx IRQ Domain operations */
382static const struct irq_domain_ops intx_domain_ops = {
383 .map = xilinx_pcie_intx_map,
384};
385
386/* PCIe HW Functions */
387
388/**
389 * xilinx_pcie_intr_handler - Interrupt Service Handler
390 * @irq: IRQ number
391 * @data: PCIe port information
392 *
393 * Return: IRQ_HANDLED on success and IRQ_NONE on failure
394 */
395static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
396{
397 struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
398 u32 val, mask, status, msi_data;
399
400 /* Read interrupt decode and mask registers */
401 val = pcie_read(port, XILINX_PCIE_REG_IDR);
402 mask = pcie_read(port, XILINX_PCIE_REG_IMR);
403
404 status = val & mask;
405 if (!status)
406 return IRQ_NONE;
407
408 if (status & XILINX_PCIE_INTR_LINK_DOWN)
409 dev_warn(port->dev, "Link Down\n");
410
411 if (status & XILINX_PCIE_INTR_ECRC_ERR)
412 dev_warn(port->dev, "ECRC failed\n");
413
414 if (status & XILINX_PCIE_INTR_STR_ERR)
415 dev_warn(port->dev, "Streaming error\n");
416
417 if (status & XILINX_PCIE_INTR_HOT_RESET)
418 dev_info(port->dev, "Hot reset\n");
419
420 if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
421 dev_warn(port->dev, "ECAM access timeout\n");
422
423 if (status & XILINX_PCIE_INTR_CORRECTABLE) {
424 dev_warn(port->dev, "Correctable error message\n");
425 xilinx_pcie_clear_err_interrupts(port);
426 }
427
428 if (status & XILINX_PCIE_INTR_NONFATAL) {
429 dev_warn(port->dev, "Non fatal error message\n");
430 xilinx_pcie_clear_err_interrupts(port);
431 }
432
433 if (status & XILINX_PCIE_INTR_FATAL) {
434 dev_warn(port->dev, "Fatal error message\n");
435 xilinx_pcie_clear_err_interrupts(port);
436 }
437
438 if (status & XILINX_PCIE_INTR_INTX) {
439 /* INTx interrupt received */
440 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
441
442 /* Check whether interrupt valid */
443 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
444 dev_warn(port->dev, "RP Intr FIFO1 read error\n");
445 return IRQ_HANDLED;
446 }
447
e4a8f8ee
RJ		 448 if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
449 /* Clear interrupt FIFO register 1 */
450 pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
451 XILINX_PCIE_REG_RPIFR1);
452
453 /* Handle INTx Interrupt */
454 val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
455 XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
456 generic_handle_irq(irq_find_mapping(port->irq_domain,
457 val));
458 }
8961def5
ST		 459 }
460
461 if (status & XILINX_PCIE_INTR_MSI) {
462 /* MSI Interrupt */
463 val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
464
465 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
466 dev_warn(port->dev, "RP Intr FIFO1 read error\n");
467 return IRQ_HANDLED;
468 }
469
470 if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
471 msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
472 XILINX_PCIE_RPIFR2_MSG_DATA;
473
474 /* Clear interrupt FIFO register 1 */
475 pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
476 XILINX_PCIE_REG_RPIFR1);
477
478 if (IS_ENABLED(CONFIG_PCI_MSI)) {
479 /* Handle MSI Interrupt */
480 generic_handle_irq(msi_data);
481 }
482 }
483 }
484
485 if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
486 dev_warn(port->dev, "Slave unsupported request\n");
487
488 if (status & XILINX_PCIE_INTR_SLV_UNEXP)
489 dev_warn(port->dev, "Slave unexpected completion\n");
490
491 if (status & XILINX_PCIE_INTR_SLV_COMPL)
492 dev_warn(port->dev, "Slave completion timeout\n");
493
494 if (status & XILINX_PCIE_INTR_SLV_ERRP)
495 dev_warn(port->dev, "Slave Error Poison\n");
496
497 if (status & XILINX_PCIE_INTR_SLV_CMPABT)
498 dev_warn(port->dev, "Slave Completer Abort\n");
499
500 if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
501 dev_warn(port->dev, "Slave Illegal Burst\n");
502
503 if (status & XILINX_PCIE_INTR_MST_DECERR)
504 dev_warn(port->dev, "Master decode error\n");
505
506 if (status & XILINX_PCIE_INTR_MST_SLVERR)
507 dev_warn(port->dev, "Master slave error\n");
508
509 if (status & XILINX_PCIE_INTR_MST_ERRP)
510 dev_warn(port->dev, "Master error poison\n");
511
512 /* Clear the Interrupt Decode register */
513 pcie_write(port, status, XILINX_PCIE_REG_IDR);
514
515 return IRQ_HANDLED;
516}
517
518/**
519 * xilinx_pcie_free_irq_domain - Free IRQ domain
520 * @port: PCIe port information
521 */
522static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
523{
524 int i;
525 u32 irq, num_irqs;
526
527 /* Free IRQ Domain */
528 if (IS_ENABLED(CONFIG_PCI_MSI)) {
529
530 free_pages(port->msi_pages, 0);
531
532 num_irqs = XILINX_NUM_MSI_IRQS;
533 } else {
534 /* INTx */
535 num_irqs = 4;
536 }
537
538 for (i = 0; i < num_irqs; i++) {
539 irq = irq_find_mapping(port->irq_domain, i);
540 if (irq > 0)
541 irq_dispose_mapping(irq);
542 }
543
544 irq_domain_remove(port->irq_domain);
545}
546
547/**
548 * xilinx_pcie_init_irq_domain - Initialize IRQ domain
549 * @port: PCIe port information
550 *
551 * Return: '0' on success and error value on failure
552 */
553static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
554{
555 struct device *dev = port->dev;
556 struct device_node *node = dev->of_node;
557 struct device_node *pcie_intc_node;
558
559 /* Setup INTx */
560 pcie_intc_node = of_get_next_child(node, NULL);
561 if (!pcie_intc_node) {
562 dev_err(dev, "No PCIe Intc node found\n");
563 return PTR_ERR(pcie_intc_node);
564 }
565
566 port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
567 &intx_domain_ops,
568 port);
569 if (!port->irq_domain) {
570 dev_err(dev, "Failed to get a INTx IRQ domain\n");
571 return PTR_ERR(port->irq_domain);
572 }
573
574 /* Setup MSI */
575 if (IS_ENABLED(CONFIG_PCI_MSI)) {
576 port->irq_domain = irq_domain_add_linear(node,
577 XILINX_NUM_MSI_IRQS,
578 &msi_domain_ops,
579 &xilinx_pcie_msi_chip);
580 if (!port->irq_domain) {
581 dev_err(dev, "Failed to get a MSI IRQ domain\n");
582 return PTR_ERR(port->irq_domain);
583 }
584
585 xilinx_pcie_enable_msi(port);
586 }
587
588 return 0;
589}
590
591/**
592 * xilinx_pcie_init_port - Initialize hardware
593 * @port: PCIe port information
594 */
595static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
596{
597 if (xilinx_pcie_link_is_up(port))
598 dev_info(port->dev, "PCIe Link is UP\n");
599 else
600 dev_info(port->dev, "PCIe Link is DOWN\n");
601
602 /* Disable all interrupts */
603 pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
604 XILINX_PCIE_REG_IMR);
605
606 /* Clear pending interrupts */
607 pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
608 XILINX_PCIE_IMR_ALL_MASK,
609 XILINX_PCIE_REG_IDR);
610
611 /* Enable all interrupts */
612 pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
613
614 /* Enable the Bridge enable bit */
615 pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
616 XILINX_PCIE_REG_RPSC_BEN,
617 XILINX_PCIE_REG_RPSC);
618}
619
620/**
621 * xilinx_pcie_setup - Setup memory resources
622 * @nr: Bus number
623 * @sys: Per controller structure
624 *
625 * Return: '1' on success and error value on failure
626 */
627static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
628{
629 struct xilinx_pcie_port *port = sys_to_pcie(sys);
630
631 list_splice_init(&port->resources, &sys->resources);
632
633 return 1;
634}
635
636/**
637 * xilinx_pcie_scan_bus - Scan PCIe bus for devices
638 * @nr: Bus number
639 * @sys: Per controller structure
640 *
641 * Return: Valid Bus pointer on success and NULL on failure
642 */
643static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
644{
645 struct xilinx_pcie_port *port = sys_to_pcie(sys);
646 struct pci_bus *bus;
647
648 port->root_busno = sys->busnr;
8961def5 649
8953aab1
LP		 650 if (IS_ENABLED(CONFIG_PCI_MSI))
651 bus = pci_scan_root_bus_msi(port->dev, sys->busnr,
652 &xilinx_pcie_ops, sys,
653 &sys->resources,
654 &xilinx_pcie_msi_chip);
655 else
656 bus = pci_scan_root_bus(port->dev, sys->busnr,
657 &xilinx_pcie_ops, sys, &sys->resources);
8961def5
ST		 658 return bus;
659}
660
661/**
662 * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
663 * @port: PCIe port information
664 *
665 * Return: '0' on success and error value on failure
666 */
667static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
668{
669 struct device *dev = port->dev;
670 struct device_node *node = dev->of_node;
671 struct resource *mem;
672 resource_size_t offset;
673 struct of_pci_range_parser parser;
674 struct of_pci_range range;
14d76b68 675 struct resource_entry *win;
8961def5
ST		 676 int err = 0, mem_resno = 0;
677
678 /* Get the ranges */
679 if (of_pci_range_parser_init(&parser, node)) {
680 dev_err(dev, "missing \"ranges\" property\n");
681 return -EINVAL;
682 }
683
684 /* Parse the ranges and add the resources found to the list */
685 for_each_of_pci_range(&parser, &range) {
686
687 if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
688 dev_err(dev, "Maximum memory resources exceeded\n");
689 return -EINVAL;
690 }
691
692 mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
693 if (!mem) {
694 err = -ENOMEM;
695 goto free_resources;
696 }
697
698 of_pci_range_to_resource(&range, node, mem);
699
700 switch (mem->flags & IORESOURCE_TYPE_BITS) {
701 case IORESOURCE_MEM:
702 offset = range.cpu_addr - range.pci_addr;
703 mem_resno++;
704 break;
705 default:
706 err = -EINVAL;
707 break;
708 }
709
710 if (err < 0) {
711 dev_warn(dev, "Invalid resource found %pR\n", mem);
712 continue;
713 }
714
715 err = request_resource(&iomem_resource, mem);
716 if (err)
717 goto free_resources;
718
719 pci_add_resource_offset(&port->resources, mem, offset);
720 }
721
722 /* Get the bus range */
723 if (of_pci_parse_bus_range(node, &port->bus_range)) {
724 u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
725 u8 last;
726
727 last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
728 XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
729
730 port->bus_range = (struct resource) {
731 .name = node->name,
732 .start = 0,
733 .end = last,
734 .flags = IORESOURCE_BUS,
735 };
736 }
737
738 /* Register bus resource */
739 pci_add_resource(&port->resources, &port->bus_range);
740
741 return 0;
742
743free_resources:
744 release_child_resources(&iomem_resource);
14d76b68 745 resource_list_for_each_entry(win, &port->resources)
8961def5
ST		 746 devm_kfree(dev, win->res);
747 pci_free_resource_list(&port->resources);
748
749 return err;
750}
751
752/**
753 * xilinx_pcie_parse_dt - Parse Device tree
754 * @port: PCIe port information
755 *
756 * Return: '0' on success and error value on failure
757 */
758static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
759{
760 struct device *dev = port->dev;
761 struct device_node *node = dev->of_node;
762 struct resource regs;
763 const char *type;
764 int err;
765
766 type = of_get_property(node, "device_type", NULL);
767 if (!type || strcmp(type, "pci")) {
768 dev_err(dev, "invalid \"device_type\" %s\n", type);
769 return -EINVAL;
770 }
771
772 err = of_address_to_resource(node, 0, &regs);
773 if (err) {
774 dev_err(dev, "missing \"reg\" property\n");
775 return err;
776 }
777
778 port->reg_base = devm_ioremap_resource(dev, &regs);
779 if (IS_ERR(port->reg_base))
780 return PTR_ERR(port->reg_base);
781
782 port->irq = irq_of_parse_and_map(node, 0);
783 err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
784 IRQF_SHARED, "xilinx-pcie", port);
785 if (err) {
786 dev_err(dev, "unable to request irq %d\n", port->irq);
787 return err;
788 }
789
790 return 0;
791}
792
793/**
794 * xilinx_pcie_probe - Probe function
795 * @pdev: Platform device pointer
796 *
797 * Return: '0' on success and error value on failure
798 */
799static int xilinx_pcie_probe(struct platform_device *pdev)
800{
801 struct xilinx_pcie_port *port;
802 struct hw_pci hw;
803 struct device *dev = &pdev->dev;
804 int err;
805
806 if (!dev->of_node)
807 return -ENODEV;
808
809 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
810 if (!port)
811 return -ENOMEM;
812
813 port->dev = dev;
814
815 err = xilinx_pcie_parse_dt(port);
816 if (err) {
817 dev_err(dev, "Parsing DT failed\n");
818 return err;
819 }
820
821 xilinx_pcie_init_port(port);
822
823 err = xilinx_pcie_init_irq_domain(port);
824 if (err) {
825 dev_err(dev, "Failed creating IRQ Domain\n");
826 return err;
827 }
828
829 /*
830 * Parse PCI ranges, configuration bus range and
831 * request their resources
832 */
833 INIT_LIST_HEAD(&port->resources);
834 err = xilinx_pcie_parse_and_add_res(port);
835 if (err) {
836 dev_err(dev, "Failed adding resources\n");
837 return err;
838 }
839
840 platform_set_drvdata(pdev, port);
841
842 /* Register the device */
843 memset(&hw, 0, sizeof(hw));
844 hw = (struct hw_pci) {
845 .nr_controllers = 1,
846 .private_data = (void **)&port,
847 .setup = xilinx_pcie_setup,
848 .map_irq = of_irq_parse_and_map_pci,
8961def5
ST		 849 .scan = xilinx_pcie_scan_bus,
850 .ops = &xilinx_pcie_ops,
851 };
8dd26dc8
YW		 852
853#ifdef CONFIG_PCI_MSI
854 xilinx_pcie_msi_chip.dev = port->dev;
8dd26dc8 855#endif
8961def5
ST		 856 pci_common_init_dev(dev, &hw);
857
858 return 0;
859}
860
861/**
862 * xilinx_pcie_remove - Remove function
863 * @pdev: Platform device pointer
864 *
865 * Return: '0' always
866 */
867static int xilinx_pcie_remove(struct platform_device *pdev)
868{
869 struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
870
871 xilinx_pcie_free_irq_domain(port);
872
873 return 0;
874}
875
876static struct of_device_id xilinx_pcie_of_match[] = {
877 { .compatible = "xlnx,axi-pcie-host-1.00.a", },
878 {}
879};
880
881static struct platform_driver xilinx_pcie_driver = {
882 .driver = {
883 .name = "xilinx-pcie",
8961def5
ST		 884 .of_match_table = xilinx_pcie_of_match,
885 .suppress_bind_attrs = true,
886 },
887 .probe = xilinx_pcie_probe,
888 .remove = xilinx_pcie_remove,
889};
890module_platform_driver(xilinx_pcie_driver);
891
892MODULE_AUTHOR("Xilinx Inc");
893MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
894MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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