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8961def5 ST |
1 | /* |
2 | * PCIe host controller driver for Xilinx AXI PCIe Bridge | |
3 | * | |
4 | * Copyright (c) 2012 - 2014 Xilinx, Inc. | |
5 | * | |
6 | * Based on the Tegra PCIe driver | |
7 | * | |
8 | * Bits taken from Synopsys Designware Host controller driver and | |
9 | * ARM PCI Host generic driver. | |
10 | * | |
11 | * This program is free software: you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #include <linux/interrupt.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/irqdomain.h> | |
20 | #include <linux/kernel.h> | |
da4eafca | 21 | #include <linux/init.h> |
8961def5 ST |
22 | #include <linux/msi.h> |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_pci.h> | |
25 | #include <linux/of_platform.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/platform_device.h> | |
29 | ||
30 | /* Register definitions */ | |
31 | #define XILINX_PCIE_REG_BIR 0x00000130 | |
32 | #define XILINX_PCIE_REG_IDR 0x00000138 | |
33 | #define XILINX_PCIE_REG_IMR 0x0000013c | |
34 | #define XILINX_PCIE_REG_PSCR 0x00000144 | |
35 | #define XILINX_PCIE_REG_RPSC 0x00000148 | |
36 | #define XILINX_PCIE_REG_MSIBASE1 0x0000014c | |
37 | #define XILINX_PCIE_REG_MSIBASE2 0x00000150 | |
38 | #define XILINX_PCIE_REG_RPEFR 0x00000154 | |
39 | #define XILINX_PCIE_REG_RPIFR1 0x00000158 | |
40 | #define XILINX_PCIE_REG_RPIFR2 0x0000015c | |
41 | ||
42 | /* Interrupt registers definitions */ | |
43 | #define XILINX_PCIE_INTR_LINK_DOWN BIT(0) | |
44 | #define XILINX_PCIE_INTR_ECRC_ERR BIT(1) | |
45 | #define XILINX_PCIE_INTR_STR_ERR BIT(2) | |
46 | #define XILINX_PCIE_INTR_HOT_RESET BIT(3) | |
47 | #define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8) | |
48 | #define XILINX_PCIE_INTR_CORRECTABLE BIT(9) | |
49 | #define XILINX_PCIE_INTR_NONFATAL BIT(10) | |
50 | #define XILINX_PCIE_INTR_FATAL BIT(11) | |
51 | #define XILINX_PCIE_INTR_INTX BIT(16) | |
52 | #define XILINX_PCIE_INTR_MSI BIT(17) | |
53 | #define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20) | |
54 | #define XILINX_PCIE_INTR_SLV_UNEXP BIT(21) | |
55 | #define XILINX_PCIE_INTR_SLV_COMPL BIT(22) | |
56 | #define XILINX_PCIE_INTR_SLV_ERRP BIT(23) | |
57 | #define XILINX_PCIE_INTR_SLV_CMPABT BIT(24) | |
58 | #define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25) | |
59 | #define XILINX_PCIE_INTR_MST_DECERR BIT(26) | |
60 | #define XILINX_PCIE_INTR_MST_SLVERR BIT(27) | |
61 | #define XILINX_PCIE_INTR_MST_ERRP BIT(28) | |
62 | #define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED | |
63 | #define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF | |
64 | ||
65 | /* Root Port Error FIFO Read Register definitions */ | |
66 | #define XILINX_PCIE_RPEFR_ERR_VALID BIT(18) | |
67 | #define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0) | |
68 | #define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF | |
69 | ||
70 | /* Root Port Interrupt FIFO Read Register 1 definitions */ | |
71 | #define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31) | |
72 | #define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30) | |
73 | #define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27) | |
74 | #define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF | |
75 | #define XILINX_PCIE_RPIFR1_INTR_SHIFT 27 | |
76 | ||
77 | /* Bridge Info Register definitions */ | |
78 | #define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16) | |
79 | #define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16 | |
80 | ||
81 | /* Root Port Interrupt FIFO Read Register 2 definitions */ | |
82 | #define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0) | |
83 | ||
84 | /* Root Port Status/control Register definitions */ | |
85 | #define XILINX_PCIE_REG_RPSC_BEN BIT(0) | |
86 | ||
87 | /* Phy Status/Control Register definitions */ | |
88 | #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) | |
89 | ||
90 | /* ECAM definitions */ | |
91 | #define ECAM_BUS_NUM_SHIFT 20 | |
92 | #define ECAM_DEV_NUM_SHIFT 12 | |
93 | ||
94 | /* Number of MSI IRQs */ | |
95 | #define XILINX_NUM_MSI_IRQS 128 | |
96 | ||
8961def5 ST |
97 | /** |
98 | * struct xilinx_pcie_port - PCIe port information | |
99 | * @reg_base: IO Mapped Register Base | |
100 | * @irq: Interrupt number | |
101 | * @msi_pages: MSI pages | |
102 | * @root_busno: Root Bus number | |
103 | * @dev: Device pointer | |
104 | * @irq_domain: IRQ domain pointer | |
8961def5 ST |
105 | * @resources: Bus Resources |
106 | */ | |
107 | struct xilinx_pcie_port { | |
108 | void __iomem *reg_base; | |
109 | u32 irq; | |
110 | unsigned long msi_pages; | |
111 | u8 root_busno; | |
112 | struct device *dev; | |
113 | struct irq_domain *irq_domain; | |
8961def5 ST |
114 | struct list_head resources; |
115 | }; | |
116 | ||
117 | static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS); | |
118 | ||
8961def5 ST |
119 | static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg) |
120 | { | |
121 | return readl(port->reg_base + reg); | |
122 | } | |
123 | ||
124 | static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg) | |
125 | { | |
126 | writel(val, port->reg_base + reg); | |
127 | } | |
128 | ||
129 | static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port) | |
130 | { | |
131 | return (pcie_read(port, XILINX_PCIE_REG_PSCR) & | |
132 | XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0; | |
133 | } | |
134 | ||
135 | /** | |
136 | * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts | |
137 | * @port: PCIe port information | |
138 | */ | |
139 | static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) | |
140 | { | |
abc596b9 | 141 | unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR); |
8961def5 ST |
142 | |
143 | if (val & XILINX_PCIE_RPEFR_ERR_VALID) { | |
abc596b9 | 144 | dev_dbg(port->dev, "Requester ID %lu\n", |
8961def5 ST |
145 | val & XILINX_PCIE_RPEFR_REQ_ID); |
146 | pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK, | |
147 | XILINX_PCIE_REG_RPEFR); | |
148 | } | |
149 | } | |
150 | ||
151 | /** | |
152 | * xilinx_pcie_valid_device - Check if a valid device is present on bus | |
153 | * @bus: PCI Bus structure | |
154 | * @devfn: device/function | |
155 | * | |
156 | * Return: 'true' on success and 'false' if invalid device is found | |
157 | */ | |
158 | static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) | |
159 | { | |
4c01f3b0 | 160 | struct xilinx_pcie_port *port = bus->sysdata; |
8961def5 ST |
161 | |
162 | /* Check if link is up when trying to access downstream ports */ | |
163 | if (bus->number != port->root_busno) | |
164 | if (!xilinx_pcie_link_is_up(port)) | |
165 | return false; | |
166 | ||
167 | /* Only one device down on each root port */ | |
168 | if (bus->number == port->root_busno && devfn > 0) | |
169 | return false; | |
170 | ||
171 | /* | |
172 | * Do not read more than one device on the bus directly attached | |
173 | * to RC. | |
174 | */ | |
175 | if (bus->primary == port->root_busno && devfn > 0) | |
176 | return false; | |
177 | ||
178 | return true; | |
179 | } | |
180 | ||
181 | /** | |
029e2151 | 182 | * xilinx_pcie_map_bus - Get configuration base |
8961def5 ST |
183 | * @bus: PCI Bus structure |
184 | * @devfn: Device/function | |
185 | * @where: Offset from base | |
186 | * | |
187 | * Return: Base address of the configuration space needed to be | |
188 | * accessed. | |
189 | */ | |
029e2151 RH |
190 | static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, |
191 | unsigned int devfn, int where) | |
8961def5 | 192 | { |
4c01f3b0 | 193 | struct xilinx_pcie_port *port = bus->sysdata; |
8961def5 ST |
194 | int relbus; |
195 | ||
029e2151 RH |
196 | if (!xilinx_pcie_valid_device(bus, devfn)) |
197 | return NULL; | |
198 | ||
8961def5 ST |
199 | relbus = (bus->number << ECAM_BUS_NUM_SHIFT) | |
200 | (devfn << ECAM_DEV_NUM_SHIFT); | |
201 | ||
202 | return port->reg_base + relbus + where; | |
203 | } | |
204 | ||
8961def5 ST |
205 | /* PCIe operations */ |
206 | static struct pci_ops xilinx_pcie_ops = { | |
029e2151 RH |
207 | .map_bus = xilinx_pcie_map_bus, |
208 | .read = pci_generic_config_read, | |
209 | .write = pci_generic_config_write, | |
8961def5 ST |
210 | }; |
211 | ||
212 | /* MSI functions */ | |
213 | ||
214 | /** | |
215 | * xilinx_pcie_destroy_msi - Free MSI number | |
216 | * @irq: IRQ to be freed | |
217 | */ | |
218 | static void xilinx_pcie_destroy_msi(unsigned int irq) | |
219 | { | |
8961def5 ST |
220 | struct msi_desc *msi; |
221 | struct xilinx_pcie_port *port; | |
222 | ||
e39758e0 JL |
223 | if (!test_bit(irq, msi_irq_in_use)) { |
224 | msi = irq_get_msi_desc(irq); | |
4c01f3b0 | 225 | port = msi_desc_to_pci_sysdata(msi); |
8961def5 | 226 | dev_err(port->dev, "Trying to free unused MSI#%d\n", irq); |
e39758e0 | 227 | } else { |
8961def5 | 228 | clear_bit(irq, msi_irq_in_use); |
e39758e0 | 229 | } |
8961def5 ST |
230 | } |
231 | ||
232 | /** | |
233 | * xilinx_pcie_assign_msi - Allocate MSI number | |
234 | * @port: PCIe port structure | |
235 | * | |
236 | * Return: A valid IRQ on success and error value on failure. | |
237 | */ | |
238 | static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) | |
239 | { | |
240 | int pos; | |
241 | ||
242 | pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); | |
243 | if (pos < XILINX_NUM_MSI_IRQS) | |
244 | set_bit(pos, msi_irq_in_use); | |
245 | else | |
246 | return -ENOSPC; | |
247 | ||
248 | return pos; | |
249 | } | |
250 | ||
251 | /** | |
252 | * xilinx_msi_teardown_irq - Destroy the MSI | |
253 | * @chip: MSI Chip descriptor | |
254 | * @irq: MSI IRQ to destroy | |
255 | */ | |
c2791b80 YW |
256 | static void xilinx_msi_teardown_irq(struct msi_controller *chip, |
257 | unsigned int irq) | |
8961def5 ST |
258 | { |
259 | xilinx_pcie_destroy_msi(irq); | |
260 | } | |
261 | ||
262 | /** | |
263 | * xilinx_pcie_msi_setup_irq - Setup MSI request | |
264 | * @chip: MSI chip pointer | |
265 | * @pdev: PCIe device pointer | |
266 | * @desc: MSI descriptor pointer | |
267 | * | |
268 | * Return: '0' on success and error value on failure | |
269 | */ | |
c2791b80 | 270 | static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip, |
8961def5 ST |
271 | struct pci_dev *pdev, |
272 | struct msi_desc *desc) | |
273 | { | |
4c01f3b0 | 274 | struct xilinx_pcie_port *port = pdev->bus->sysdata; |
8961def5 ST |
275 | unsigned int irq; |
276 | int hwirq; | |
277 | struct msi_msg msg; | |
278 | phys_addr_t msg_addr; | |
279 | ||
280 | hwirq = xilinx_pcie_assign_msi(port); | |
f9dd0ce6 DC |
281 | if (hwirq < 0) |
282 | return hwirq; | |
8961def5 ST |
283 | |
284 | irq = irq_create_mapping(port->irq_domain, hwirq); | |
285 | if (!irq) | |
286 | return -EINVAL; | |
287 | ||
288 | irq_set_msi_desc(irq, desc); | |
289 | ||
290 | msg_addr = virt_to_phys((void *)port->msi_pages); | |
291 | ||
292 | msg.address_hi = 0; | |
293 | msg.address_lo = msg_addr; | |
294 | msg.data = irq; | |
295 | ||
83a18912 | 296 | pci_write_msi_msg(irq, &msg); |
8961def5 ST |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
301 | /* MSI Chip Descriptor */ | |
c2791b80 | 302 | static struct msi_controller xilinx_pcie_msi_chip = { |
8961def5 ST |
303 | .setup_irq = xilinx_pcie_msi_setup_irq, |
304 | .teardown_irq = xilinx_msi_teardown_irq, | |
305 | }; | |
306 | ||
307 | /* HW Interrupt Chip Descriptor */ | |
308 | static struct irq_chip xilinx_msi_irq_chip = { | |
309 | .name = "Xilinx PCIe MSI", | |
280510f1 TG |
310 | .irq_enable = pci_msi_unmask_irq, |
311 | .irq_disable = pci_msi_mask_irq, | |
312 | .irq_mask = pci_msi_mask_irq, | |
313 | .irq_unmask = pci_msi_unmask_irq, | |
8961def5 ST |
314 | }; |
315 | ||
316 | /** | |
317 | * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid | |
318 | * @domain: IRQ domain | |
319 | * @irq: Virtual IRQ number | |
320 | * @hwirq: HW interrupt number | |
321 | * | |
322 | * Return: Always returns 0. | |
323 | */ | |
324 | static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq, | |
325 | irq_hw_number_t hwirq) | |
326 | { | |
327 | irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq); | |
328 | irq_set_chip_data(irq, domain->host_data); | |
8961def5 ST |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
333 | /* IRQ Domain operations */ | |
334 | static const struct irq_domain_ops msi_domain_ops = { | |
335 | .map = xilinx_pcie_msi_map, | |
336 | }; | |
337 | ||
338 | /** | |
339 | * xilinx_pcie_enable_msi - Enable MSI support | |
340 | * @port: PCIe port information | |
341 | */ | |
342 | static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port) | |
343 | { | |
344 | phys_addr_t msg_addr; | |
345 | ||
346 | port->msi_pages = __get_free_pages(GFP_KERNEL, 0); | |
347 | msg_addr = virt_to_phys((void *)port->msi_pages); | |
348 | pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1); | |
349 | pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2); | |
350 | } | |
351 | ||
8961def5 ST |
352 | /* INTx Functions */ |
353 | ||
354 | /** | |
355 | * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid | |
356 | * @domain: IRQ domain | |
357 | * @irq: Virtual IRQ number | |
358 | * @hwirq: HW interrupt number | |
359 | * | |
360 | * Return: Always returns 0. | |
361 | */ | |
362 | static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, | |
363 | irq_hw_number_t hwirq) | |
364 | { | |
365 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
366 | irq_set_chip_data(irq, domain->host_data); | |
8961def5 ST |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
371 | /* INTx IRQ Domain operations */ | |
372 | static const struct irq_domain_ops intx_domain_ops = { | |
373 | .map = xilinx_pcie_intx_map, | |
374 | }; | |
375 | ||
376 | /* PCIe HW Functions */ | |
377 | ||
378 | /** | |
379 | * xilinx_pcie_intr_handler - Interrupt Service Handler | |
380 | * @irq: IRQ number | |
381 | * @data: PCIe port information | |
382 | * | |
383 | * Return: IRQ_HANDLED on success and IRQ_NONE on failure | |
384 | */ | |
385 | static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) | |
386 | { | |
387 | struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; | |
388 | u32 val, mask, status, msi_data; | |
389 | ||
390 | /* Read interrupt decode and mask registers */ | |
391 | val = pcie_read(port, XILINX_PCIE_REG_IDR); | |
392 | mask = pcie_read(port, XILINX_PCIE_REG_IMR); | |
393 | ||
394 | status = val & mask; | |
395 | if (!status) | |
396 | return IRQ_NONE; | |
397 | ||
398 | if (status & XILINX_PCIE_INTR_LINK_DOWN) | |
399 | dev_warn(port->dev, "Link Down\n"); | |
400 | ||
401 | if (status & XILINX_PCIE_INTR_ECRC_ERR) | |
402 | dev_warn(port->dev, "ECRC failed\n"); | |
403 | ||
404 | if (status & XILINX_PCIE_INTR_STR_ERR) | |
405 | dev_warn(port->dev, "Streaming error\n"); | |
406 | ||
407 | if (status & XILINX_PCIE_INTR_HOT_RESET) | |
408 | dev_info(port->dev, "Hot reset\n"); | |
409 | ||
410 | if (status & XILINX_PCIE_INTR_CFG_TIMEOUT) | |
411 | dev_warn(port->dev, "ECAM access timeout\n"); | |
412 | ||
413 | if (status & XILINX_PCIE_INTR_CORRECTABLE) { | |
414 | dev_warn(port->dev, "Correctable error message\n"); | |
415 | xilinx_pcie_clear_err_interrupts(port); | |
416 | } | |
417 | ||
418 | if (status & XILINX_PCIE_INTR_NONFATAL) { | |
419 | dev_warn(port->dev, "Non fatal error message\n"); | |
420 | xilinx_pcie_clear_err_interrupts(port); | |
421 | } | |
422 | ||
423 | if (status & XILINX_PCIE_INTR_FATAL) { | |
424 | dev_warn(port->dev, "Fatal error message\n"); | |
425 | xilinx_pcie_clear_err_interrupts(port); | |
426 | } | |
427 | ||
428 | if (status & XILINX_PCIE_INTR_INTX) { | |
429 | /* INTx interrupt received */ | |
430 | val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); | |
431 | ||
432 | /* Check whether interrupt valid */ | |
433 | if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { | |
434 | dev_warn(port->dev, "RP Intr FIFO1 read error\n"); | |
435 | return IRQ_HANDLED; | |
436 | } | |
437 | ||
e4a8f8ee RJ |
438 | if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { |
439 | /* Clear interrupt FIFO register 1 */ | |
440 | pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, | |
441 | XILINX_PCIE_REG_RPIFR1); | |
442 | ||
443 | /* Handle INTx Interrupt */ | |
444 | val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> | |
445 | XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; | |
446 | generic_handle_irq(irq_find_mapping(port->irq_domain, | |
447 | val)); | |
448 | } | |
8961def5 ST |
449 | } |
450 | ||
451 | if (status & XILINX_PCIE_INTR_MSI) { | |
452 | /* MSI Interrupt */ | |
453 | val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); | |
454 | ||
455 | if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { | |
456 | dev_warn(port->dev, "RP Intr FIFO1 read error\n"); | |
457 | return IRQ_HANDLED; | |
458 | } | |
459 | ||
460 | if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { | |
461 | msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & | |
462 | XILINX_PCIE_RPIFR2_MSG_DATA; | |
463 | ||
464 | /* Clear interrupt FIFO register 1 */ | |
465 | pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, | |
466 | XILINX_PCIE_REG_RPIFR1); | |
467 | ||
468 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
469 | /* Handle MSI Interrupt */ | |
470 | generic_handle_irq(msi_data); | |
471 | } | |
472 | } | |
473 | } | |
474 | ||
475 | if (status & XILINX_PCIE_INTR_SLV_UNSUPP) | |
476 | dev_warn(port->dev, "Slave unsupported request\n"); | |
477 | ||
478 | if (status & XILINX_PCIE_INTR_SLV_UNEXP) | |
479 | dev_warn(port->dev, "Slave unexpected completion\n"); | |
480 | ||
481 | if (status & XILINX_PCIE_INTR_SLV_COMPL) | |
482 | dev_warn(port->dev, "Slave completion timeout\n"); | |
483 | ||
484 | if (status & XILINX_PCIE_INTR_SLV_ERRP) | |
485 | dev_warn(port->dev, "Slave Error Poison\n"); | |
486 | ||
487 | if (status & XILINX_PCIE_INTR_SLV_CMPABT) | |
488 | dev_warn(port->dev, "Slave Completer Abort\n"); | |
489 | ||
490 | if (status & XILINX_PCIE_INTR_SLV_ILLBUR) | |
491 | dev_warn(port->dev, "Slave Illegal Burst\n"); | |
492 | ||
493 | if (status & XILINX_PCIE_INTR_MST_DECERR) | |
494 | dev_warn(port->dev, "Master decode error\n"); | |
495 | ||
496 | if (status & XILINX_PCIE_INTR_MST_SLVERR) | |
497 | dev_warn(port->dev, "Master slave error\n"); | |
498 | ||
499 | if (status & XILINX_PCIE_INTR_MST_ERRP) | |
500 | dev_warn(port->dev, "Master error poison\n"); | |
501 | ||
502 | /* Clear the Interrupt Decode register */ | |
503 | pcie_write(port, status, XILINX_PCIE_REG_IDR); | |
504 | ||
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
8961def5 ST |
508 | /** |
509 | * xilinx_pcie_init_irq_domain - Initialize IRQ domain | |
510 | * @port: PCIe port information | |
511 | * | |
512 | * Return: '0' on success and error value on failure | |
513 | */ | |
514 | static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) | |
515 | { | |
516 | struct device *dev = port->dev; | |
517 | struct device_node *node = dev->of_node; | |
518 | struct device_node *pcie_intc_node; | |
519 | ||
520 | /* Setup INTx */ | |
521 | pcie_intc_node = of_get_next_child(node, NULL); | |
522 | if (!pcie_intc_node) { | |
523 | dev_err(dev, "No PCIe Intc node found\n"); | |
cec6dba2 | 524 | return -ENODEV; |
8961def5 ST |
525 | } |
526 | ||
527 | port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4, | |
528 | &intx_domain_ops, | |
529 | port); | |
530 | if (!port->irq_domain) { | |
531 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
cec6dba2 | 532 | return -ENODEV; |
8961def5 ST |
533 | } |
534 | ||
535 | /* Setup MSI */ | |
536 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
537 | port->irq_domain = irq_domain_add_linear(node, | |
538 | XILINX_NUM_MSI_IRQS, | |
539 | &msi_domain_ops, | |
540 | &xilinx_pcie_msi_chip); | |
541 | if (!port->irq_domain) { | |
542 | dev_err(dev, "Failed to get a MSI IRQ domain\n"); | |
cec6dba2 | 543 | return -ENODEV; |
8961def5 ST |
544 | } |
545 | ||
546 | xilinx_pcie_enable_msi(port); | |
547 | } | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | /** | |
553 | * xilinx_pcie_init_port - Initialize hardware | |
554 | * @port: PCIe port information | |
555 | */ | |
556 | static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) | |
557 | { | |
558 | if (xilinx_pcie_link_is_up(port)) | |
559 | dev_info(port->dev, "PCIe Link is UP\n"); | |
560 | else | |
561 | dev_info(port->dev, "PCIe Link is DOWN\n"); | |
562 | ||
563 | /* Disable all interrupts */ | |
564 | pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK, | |
565 | XILINX_PCIE_REG_IMR); | |
566 | ||
567 | /* Clear pending interrupts */ | |
568 | pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) & | |
569 | XILINX_PCIE_IMR_ALL_MASK, | |
570 | XILINX_PCIE_REG_IDR); | |
571 | ||
572 | /* Enable all interrupts */ | |
573 | pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR); | |
574 | ||
575 | /* Enable the Bridge enable bit */ | |
576 | pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) | | |
577 | XILINX_PCIE_REG_RPSC_BEN, | |
578 | XILINX_PCIE_REG_RPSC); | |
579 | } | |
580 | ||
8961def5 ST |
581 | /** |
582 | * xilinx_pcie_parse_dt - Parse Device tree | |
583 | * @port: PCIe port information | |
584 | * | |
585 | * Return: '0' on success and error value on failure | |
586 | */ | |
587 | static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port) | |
588 | { | |
589 | struct device *dev = port->dev; | |
590 | struct device_node *node = dev->of_node; | |
591 | struct resource regs; | |
592 | const char *type; | |
593 | int err; | |
594 | ||
595 | type = of_get_property(node, "device_type", NULL); | |
596 | if (!type || strcmp(type, "pci")) { | |
597 | dev_err(dev, "invalid \"device_type\" %s\n", type); | |
598 | return -EINVAL; | |
599 | } | |
600 | ||
601 | err = of_address_to_resource(node, 0, ®s); | |
602 | if (err) { | |
603 | dev_err(dev, "missing \"reg\" property\n"); | |
604 | return err; | |
605 | } | |
606 | ||
607 | port->reg_base = devm_ioremap_resource(dev, ®s); | |
608 | if (IS_ERR(port->reg_base)) | |
609 | return PTR_ERR(port->reg_base); | |
610 | ||
611 | port->irq = irq_of_parse_and_map(node, 0); | |
612 | err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler, | |
8ff0ef99 GS |
613 | IRQF_SHARED | IRQF_NO_THREAD, |
614 | "xilinx-pcie", port); | |
8961def5 ST |
615 | if (err) { |
616 | dev_err(dev, "unable to request irq %d\n", port->irq); | |
617 | return err; | |
618 | } | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | /** | |
624 | * xilinx_pcie_probe - Probe function | |
625 | * @pdev: Platform device pointer | |
626 | * | |
627 | * Return: '0' on success and error value on failure | |
628 | */ | |
629 | static int xilinx_pcie_probe(struct platform_device *pdev) | |
630 | { | |
631 | struct xilinx_pcie_port *port; | |
8961def5 | 632 | struct device *dev = &pdev->dev; |
4c01f3b0 | 633 | struct pci_bus *bus; |
8961def5 | 634 | int err; |
0259882e BKG |
635 | resource_size_t iobase = 0; |
636 | LIST_HEAD(res); | |
8961def5 ST |
637 | |
638 | if (!dev->of_node) | |
639 | return -ENODEV; | |
640 | ||
641 | port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); | |
642 | if (!port) | |
643 | return -ENOMEM; | |
644 | ||
645 | port->dev = dev; | |
646 | ||
647 | err = xilinx_pcie_parse_dt(port); | |
648 | if (err) { | |
649 | dev_err(dev, "Parsing DT failed\n"); | |
650 | return err; | |
651 | } | |
652 | ||
653 | xilinx_pcie_init_port(port); | |
654 | ||
655 | err = xilinx_pcie_init_irq_domain(port); | |
656 | if (err) { | |
657 | dev_err(dev, "Failed creating IRQ Domain\n"); | |
658 | return err; | |
659 | } | |
660 | ||
0259882e BKG |
661 | err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res, |
662 | &iobase); | |
8961def5 | 663 | if (err) { |
0259882e | 664 | dev_err(dev, "Getting bridge resources failed\n"); |
8961def5 ST |
665 | return err; |
666 | } | |
93a5b5e5 BH |
667 | |
668 | err = devm_request_pci_bus_resources(dev, &res); | |
669 | if (err) | |
670 | goto error; | |
671 | ||
4c01f3b0 BKG |
672 | bus = pci_create_root_bus(&pdev->dev, 0, |
673 | &xilinx_pcie_ops, port, &res); | |
c41be7a6 BH |
674 | if (!bus) { |
675 | err = -ENOMEM; | |
676 | goto error; | |
677 | } | |
8dd26dc8 YW |
678 | |
679 | #ifdef CONFIG_PCI_MSI | |
680 | xilinx_pcie_msi_chip.dev = port->dev; | |
4c01f3b0 | 681 | bus->msi = &xilinx_pcie_msi_chip; |
8dd26dc8 | 682 | #endif |
4c01f3b0 BKG |
683 | pci_scan_child_bus(bus); |
684 | pci_assign_unassigned_bus_resources(bus); | |
2c51391d | 685 | #ifndef CONFIG_MICROBLAZE |
4c01f3b0 | 686 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); |
2c51391d | 687 | #endif |
4c01f3b0 BKG |
688 | pci_bus_add_devices(bus); |
689 | platform_set_drvdata(pdev, port); | |
8961def5 ST |
690 | |
691 | return 0; | |
c41be7a6 BH |
692 | |
693 | error: | |
694 | pci_free_resource_list(&res); | |
695 | return err; | |
8961def5 ST |
696 | } |
697 | ||
8961def5 ST |
698 | static struct of_device_id xilinx_pcie_of_match[] = { |
699 | { .compatible = "xlnx,axi-pcie-host-1.00.a", }, | |
700 | {} | |
701 | }; | |
702 | ||
703 | static struct platform_driver xilinx_pcie_driver = { | |
704 | .driver = { | |
705 | .name = "xilinx-pcie", | |
8961def5 ST |
706 | .of_match_table = xilinx_pcie_of_match, |
707 | .suppress_bind_attrs = true, | |
708 | }, | |
709 | .probe = xilinx_pcie_probe, | |
8961def5 | 710 | }; |
da4eafca | 711 | builtin_platform_driver(xilinx_pcie_driver); |