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1 | /* |
2 | * cpcihp_zt5550.h | |
3 | * | |
4 | * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions | |
5 | * | |
6 | * Copyright 2002 SOMA Networks, Inc. | |
7 | * Copyright 2001 Intel San Luis Obispo | |
8 | * Copyright 2000,2001 MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
f7625980 BH |
16 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
18 | * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
19 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
20 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
21 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
22 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
23 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
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24 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
25 | * | |
26 | * You should have received a copy of the GNU General Public License along | |
27 | * with this program; if not, write to the Free Software Foundation, Inc., | |
28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
29 | * | |
30 | * Send feedback to <scottm@somanetworks.com> | |
31 | */ | |
32 | ||
33 | #ifndef _CPCIHP_ZT5550_H | |
34 | #define _CPCIHP_ZT5550_H | |
35 | ||
36 | /* Direct registers */ | |
37 | #define CSR_HCINDEX 0x00 | |
38 | #define CSR_HCDATA 0x04 | |
39 | #define CSR_INTSTAT 0x08 | |
40 | #define CSR_INTMASK 0x09 | |
41 | #define CSR_CNT0CMD 0x0C | |
42 | #define CSR_CNT1CMD 0x0E | |
43 | #define CSR_CNT0 0x10 | |
44 | #define CSR_CNT1 0x14 | |
45 | ||
46 | /* Masks for interrupt bits in CSR_INTMASK direct register */ | |
47 | #define CNT0_INT_MASK 0x01 | |
48 | #define CNT1_INT_MASK 0x02 | |
49 | #define ENUM_INT_MASK 0x04 | |
50 | #define ALL_DIRECT_INTS_MASK 0x07 | |
51 | ||
52 | /* Indexed registers (through CSR_INDEX, CSR_DATA) */ | |
53 | #define HC_INT_MASK_REG 0x04 | |
54 | #define HC_STATUS_REG 0x08 | |
55 | #define HC_CMD_REG 0x0C | |
56 | #define ARB_CONFIG_GNT_REG 0x10 | |
57 | #define ARB_CONFIG_CFG_REG 0x12 | |
f7625980 | 58 | #define ARB_CONFIG_REG 0x10 |
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59 | #define ISOL_CONFIG_REG 0x18 |
60 | #define FAULT_STATUS_REG 0x20 | |
61 | #define FAULT_CONFIG_REG 0x24 | |
62 | #define WD_CONFIG_REG 0x2C | |
63 | #define HC_DIAG_REG 0x30 | |
64 | #define SERIAL_COMM_REG 0x34 | |
65 | #define SERIAL_OUT_REG 0x38 | |
66 | #define SERIAL_IN_REG 0x3C | |
67 | ||
68 | /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ | |
69 | #define SERIAL_INT_MASK 0x01 | |
70 | #define FAULT_INT_MASK 0x02 | |
71 | #define HCF_INT_MASK 0x04 | |
72 | #define ALL_INDEXED_INTS_MASK 0x07 | |
73 | ||
74 | /* Digital I/O port storing ENUM# */ | |
75 | #define ENUM_PORT 0xE1 | |
76 | /* Mask to get to the ENUM# bit on the bus */ | |
77 | #define ENUM_MASK 0x40 | |
78 | ||
79 | #endif /* _CPCIHP_ZT5550_H */ |