Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
48fe3915 KK |
49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
50 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
51 | |
52 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 53 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 54 | { |
48fe3915 | 55 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 56 | |
1da177e4 | 57 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 58 | pcie_isr(0, ctrl); |
1da177e4 | 59 | |
48fe3915 | 60 | init_timer(&ctrl->poll_timer); |
1da177e4 | 61 | if (!pciehp_poll_time) |
40730d10 | 62 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 63 | |
48fe3915 | 64 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
65 | } |
66 | ||
67 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 68 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 69 | { |
48fe3915 KK |
70 | /* Clamp to sane value */ |
71 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 72 | sec = 2; |
48fe3915 KK |
73 | |
74 | ctrl->poll_timer.function = &int_poll_timeout; | |
75 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
76 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
77 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
78 | } |
79 | ||
2aeeef11 KK |
80 | static inline int pciehp_request_irq(struct controller *ctrl) |
81 | { | |
f7a10e32 | 82 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
83 | |
84 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
85 | if (pciehp_poll_mode) { | |
86 | init_timer(&ctrl->poll_timer); | |
87 | start_int_poll_timer(ctrl, 10); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* Installs the interrupt handler */ | |
92 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
93 | if (retval) | |
7f2feec1 TI |
94 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
95 | irq); | |
2aeeef11 KK |
96 | return retval; |
97 | } | |
98 | ||
99 | static inline void pciehp_free_irq(struct controller *ctrl) | |
100 | { | |
101 | if (pciehp_poll_mode) | |
102 | del_timer_sync(&ctrl->poll_timer); | |
103 | else | |
f7a10e32 | 104 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
105 | } |
106 | ||
40b96083 | 107 | static int pcie_poll_cmd(struct controller *ctrl, int timeout) |
6592e02a | 108 | { |
cd84d340 | 109 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 110 | u16 slot_status; |
6592e02a | 111 | |
1a84b99c BH |
112 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
113 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
114 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
115 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 116 | return 1; |
820943b6 | 117 | } |
a5827f40 | 118 | while (timeout > 0) { |
66618bad KK |
119 | msleep(10); |
120 | timeout -= 10; | |
1a84b99c BH |
121 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
122 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
123 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
124 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 125 | return 1; |
820943b6 | 126 | } |
6592e02a KK |
127 | } |
128 | return 0; /* timeout */ | |
6592e02a KK |
129 | } |
130 | ||
4283c70e | 131 | static void pcie_wait_cmd(struct controller *ctrl) |
44ef4cef | 132 | { |
262303fe | 133 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
40b96083 BH |
134 | unsigned long duration = msecs_to_jiffies(msecs); |
135 | unsigned long cmd_timeout = ctrl->cmd_started + duration; | |
136 | unsigned long now, timeout; | |
262303fe KK |
137 | int rc; |
138 | ||
4283c70e BH |
139 | /* |
140 | * If the controller does not generate notifications for command | |
141 | * completions, we never need to wait between writes. | |
142 | */ | |
6c1a32e0 | 143 | if (NO_CMD_CMPL(ctrl)) |
4283c70e BH |
144 | return; |
145 | ||
146 | if (!ctrl->cmd_busy) | |
147 | return; | |
148 | ||
40b96083 BH |
149 | /* |
150 | * Even if the command has already timed out, we want to call | |
151 | * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. | |
152 | */ | |
153 | now = jiffies; | |
154 | if (time_before_eq(cmd_timeout, now)) | |
155 | timeout = 1; | |
156 | else | |
157 | timeout = cmd_timeout - now; | |
158 | ||
4283c70e BH |
159 | if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && |
160 | ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
4283c70e | 162 | else |
7cbeb9f9 | 163 | rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); |
40b96083 BH |
164 | |
165 | /* | |
166 | * Controllers with errata like Intel CF118 don't generate | |
167 | * completion notifications unless the power/indicator/interlock | |
168 | * control bits are changed. On such controllers, we'll emit this | |
169 | * timeout message when we wait for completion of commands that | |
170 | * don't change those bits, e.g., commands that merely enable | |
171 | * interrupts. | |
172 | */ | |
262303fe | 173 | if (!rc) |
d537a3ab | 174 | ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", |
40b96083 | 175 | ctrl->slot_ctrl, |
d433889c | 176 | jiffies_to_msecs(jiffies - ctrl->cmd_started)); |
44ef4cef KK |
177 | } |
178 | ||
f4778364 KK |
179 | /** |
180 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 181 | * @ctrl: controller to which the command is issued |
f4778364 KK |
182 | * @cmd: command value written to slot control register |
183 | * @mask: bitmask of slot control register to be modified | |
184 | */ | |
6dae6202 | 185 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 186 | { |
cd84d340 | 187 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 188 | u16 slot_ctrl; |
1da177e4 | 189 | |
44ef4cef KK |
190 | mutex_lock(&ctrl->ctrl_lock); |
191 | ||
3461a068 BH |
192 | /* Wait for any previous command that might still be in progress */ |
193 | pcie_wait_cmd(ctrl); | |
194 | ||
1a84b99c | 195 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
f4778364 | 196 | slot_ctrl &= ~mask; |
b7aa1f16 | 197 | slot_ctrl |= (cmd & mask); |
f4778364 | 198 | ctrl->cmd_busy = 1; |
2d32a9ae | 199 | smp_mb(); |
1a84b99c | 200 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
40b96083 | 201 | ctrl->cmd_started = jiffies; |
4283c70e | 202 | ctrl->slot_ctrl = slot_ctrl; |
f4778364 | 203 | |
44ef4cef | 204 | mutex_unlock(&ctrl->ctrl_lock); |
1da177e4 LT |
205 | } |
206 | ||
4703389f | 207 | bool pciehp_check_link_active(struct controller *ctrl) |
f18e9625 | 208 | { |
cd84d340 | 209 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 210 | u16 lnk_status; |
1a84b99c | 211 | bool ret; |
f18e9625 | 212 | |
1a84b99c | 213 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
214 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
215 | ||
216 | if (ret) | |
217 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
218 | ||
219 | return ret; | |
f18e9625 KK |
220 | } |
221 | ||
bffe4f72 | 222 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
223 | { |
224 | int timeout = 1000; | |
225 | ||
4703389f | 226 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
227 | return; |
228 | while (timeout > 0) { | |
229 | msleep(10); | |
230 | timeout -= 10; | |
4703389f | 231 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
232 | return; |
233 | } | |
bffe4f72 YL |
234 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
235 | active ? "set" : "cleared"); | |
236 | } | |
237 | ||
238 | static void pcie_wait_link_active(struct controller *ctrl) | |
239 | { | |
240 | __pcie_wait_link_active(ctrl, true); | |
241 | } | |
242 | ||
2f5d8e4f YL |
243 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
244 | { | |
245 | u32 l; | |
246 | int count = 0; | |
247 | int delay = 1000, step = 20; | |
248 | bool found = false; | |
249 | ||
250 | do { | |
251 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
252 | count++; | |
253 | ||
254 | if (found) | |
255 | break; | |
256 | ||
257 | msleep(step); | |
258 | delay -= step; | |
259 | } while (delay > 0); | |
260 | ||
261 | if (count > 1 && pciehp_debug) | |
262 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
263 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
264 | PCI_FUNC(devfn), count, step, l); | |
265 | ||
266 | return found; | |
267 | } | |
268 | ||
82a9e79e | 269 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 270 | { |
cd84d340 | 271 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 272 | bool found; |
1da177e4 | 273 | u16 lnk_status; |
1da177e4 | 274 | |
3c78bc61 RD |
275 | /* |
276 | * Data Link Layer Link Active Reporting must be capable for | |
277 | * hot-plug capable downstream port. But old controller might | |
278 | * not implement it. In this case, we wait for 1000 ms. | |
279 | */ | |
280 | if (ctrl->link_active_reporting) | |
281 | pcie_wait_link_active(ctrl); | |
282 | else | |
283 | msleep(1000); | |
f18e9625 | 284 | |
2f5d8e4f YL |
285 | /* wait 100ms before read pci conf, and try in 1s */ |
286 | msleep(100); | |
287 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
288 | PCI_DEVFN(0, 0)); | |
0027cb3e | 289 | |
1a84b99c | 290 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 291 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
292 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
293 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
3c78bc61 | 294 | ctrl_err(ctrl, "Link Training Error occurs\n"); |
1a84b99c | 295 | return -1; |
1da177e4 LT |
296 | } |
297 | ||
fdbd3ce9 YL |
298 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
299 | ||
1a84b99c BH |
300 | if (!found) |
301 | return -1; | |
2f5d8e4f | 302 | |
1a84b99c | 303 | return 0; |
1da177e4 LT |
304 | } |
305 | ||
7f822999 YL |
306 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
307 | { | |
cd84d340 | 308 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 309 | u16 lnk_ctrl; |
7f822999 | 310 | |
1a84b99c | 311 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
312 | |
313 | if (enable) | |
314 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
315 | else | |
316 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
317 | ||
1a84b99c | 318 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 319 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 320 | return 0; |
7f822999 YL |
321 | } |
322 | ||
323 | static int pciehp_link_enable(struct controller *ctrl) | |
324 | { | |
325 | return __pciehp_link_set(ctrl, true); | |
326 | } | |
327 | ||
6dae6202 | 328 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 329 | { |
48fe3915 | 330 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 331 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 332 | u16 slot_ctrl; |
1da177e4 | 333 | |
1a84b99c | 334 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
335 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
336 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 337 | |
e7b4f0d7 BH |
338 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
339 | case PCI_EXP_SLTCTL_ATTN_IND_ON: | |
1da177e4 LT |
340 | *status = 1; /* On */ |
341 | break; | |
e7b4f0d7 | 342 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
1da177e4 LT |
343 | *status = 2; /* Blink */ |
344 | break; | |
e7b4f0d7 | 345 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
1da177e4 LT |
346 | *status = 0; /* Off */ |
347 | break; | |
348 | default: | |
349 | *status = 0xFF; | |
350 | break; | |
351 | } | |
1da177e4 LT |
352 | } |
353 | ||
6dae6202 | 354 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 355 | { |
48fe3915 | 356 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 357 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 358 | u16 slot_ctrl; |
1da177e4 | 359 | |
1a84b99c | 360 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
361 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
362 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 363 | |
e7b4f0d7 BH |
364 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
365 | case PCI_EXP_SLTCTL_PWR_ON: | |
366 | *status = 1; /* On */ | |
1da177e4 | 367 | break; |
e7b4f0d7 BH |
368 | case PCI_EXP_SLTCTL_PWR_OFF: |
369 | *status = 0; /* Off */ | |
1da177e4 LT |
370 | break; |
371 | default: | |
372 | *status = 0xFF; | |
373 | break; | |
374 | } | |
1da177e4 LT |
375 | } |
376 | ||
6dae6202 | 377 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 378 | { |
1a84b99c | 379 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 380 | u16 slot_status; |
1da177e4 | 381 | |
1a84b99c | 382 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 383 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
384 | } |
385 | ||
6dae6202 | 386 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 387 | { |
1a84b99c | 388 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 389 | u16 slot_status; |
1da177e4 | 390 | |
1a84b99c | 391 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 392 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
393 | } |
394 | ||
82a9e79e | 395 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 396 | { |
1a84b99c | 397 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 398 | u16 slot_status; |
1da177e4 | 399 | |
1a84b99c | 400 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 401 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
402 | } |
403 | ||
6dae6202 | 404 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 405 | { |
48fe3915 | 406 | struct controller *ctrl = slot->ctrl; |
f4778364 | 407 | u16 slot_cmd; |
1da177e4 | 408 | |
af9ab791 BH |
409 | if (!ATTN_LED(ctrl)) |
410 | return; | |
411 | ||
1da177e4 | 412 | switch (value) { |
3c78bc61 | 413 | case 0: /* turn off */ |
e7b4f0d7 | 414 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
445f7985 KK |
415 | break; |
416 | case 1: /* turn on */ | |
e7b4f0d7 | 417 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
445f7985 KK |
418 | break; |
419 | case 2: /* turn blink */ | |
e7b4f0d7 | 420 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
445f7985 KK |
421 | break; |
422 | default: | |
6dae6202 | 423 | return; |
1da177e4 | 424 | } |
cf8d7b58 | 425 | pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
1518c17a KK |
426 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
427 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
428 | } |
429 | ||
82a9e79e | 430 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 431 | { |
48fe3915 | 432 | struct controller *ctrl = slot->ctrl; |
71ad556d | 433 | |
af9ab791 BH |
434 | if (!PWR_LED(ctrl)) |
435 | return; | |
436 | ||
e7b4f0d7 | 437 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC); |
1518c17a | 438 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
439 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
440 | PCI_EXP_SLTCTL_PWR_IND_ON); | |
1da177e4 LT |
441 | } |
442 | ||
82a9e79e | 443 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 444 | { |
48fe3915 | 445 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 446 | |
af9ab791 BH |
447 | if (!PWR_LED(ctrl)) |
448 | return; | |
449 | ||
e7b4f0d7 | 450 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC); |
1518c17a | 451 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
452 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
453 | PCI_EXP_SLTCTL_PWR_IND_OFF); | |
1da177e4 LT |
454 | } |
455 | ||
82a9e79e | 456 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 457 | { |
48fe3915 | 458 | struct controller *ctrl = slot->ctrl; |
71ad556d | 459 | |
af9ab791 BH |
460 | if (!PWR_LED(ctrl)) |
461 | return; | |
462 | ||
e7b4f0d7 | 463 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC); |
1518c17a | 464 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
465 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
466 | PCI_EXP_SLTCTL_PWR_IND_BLINK); | |
1da177e4 LT |
467 | } |
468 | ||
3c78bc61 | 469 | int pciehp_power_on_slot(struct slot *slot) |
1da177e4 | 470 | { |
48fe3915 | 471 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 472 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 473 | u16 slot_status; |
1a84b99c | 474 | int retval; |
1da177e4 | 475 | |
5a49f203 | 476 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 477 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
2f2ed41c BH |
478 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
479 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
480 | PCI_EXP_SLTSTA_PFD); | |
5651c48c | 481 | ctrl->power_fault_detected = 0; |
1da177e4 | 482 | |
e7b4f0d7 | 483 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
1518c17a | 484 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
485 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
486 | PCI_EXP_SLTCTL_PWR_ON); | |
1da177e4 | 487 | |
2debd928 YL |
488 | retval = pciehp_link_enable(ctrl); |
489 | if (retval) | |
490 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
491 | ||
1da177e4 LT |
492 | return retval; |
493 | } | |
494 | ||
3c78bc61 | 495 | void pciehp_power_off_slot(struct slot *slot) |
1da177e4 | 496 | { |
48fe3915 | 497 | struct controller *ctrl = slot->ctrl; |
f1050a35 | 498 | |
e7b4f0d7 | 499 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
1518c17a | 500 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
501 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
502 | PCI_EXP_SLTCTL_PWR_OFF); | |
1da177e4 LT |
503 | } |
504 | ||
48fe3915 | 505 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 506 | { |
48fe3915 | 507 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 508 | struct pci_dev *pdev = ctrl_dev(ctrl); |
b440bde7 BH |
509 | struct pci_bus *subordinate = pdev->subordinate; |
510 | struct pci_dev *dev; | |
8720d27d | 511 | struct slot *slot = ctrl->slot; |
c6b069e9 | 512 | u16 detected, intr_loc; |
1da177e4 | 513 | |
c6b069e9 KK |
514 | /* |
515 | * In order to guarantee that all interrupt events are | |
516 | * serviced, we need to re-inspect Slot Status register after | |
517 | * clearing what is presumed to be the last pending interrupt. | |
518 | */ | |
519 | intr_loc = 0; | |
520 | do { | |
1a84b99c | 521 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
1da177e4 | 522 | |
322162a7 KK |
523 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
524 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
e48f1b67 | 525 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
81b840cd | 526 | detected &= ~intr_loc; |
c6b069e9 KK |
527 | intr_loc |= detected; |
528 | if (!intr_loc) | |
1da177e4 | 529 | return IRQ_NONE; |
1a84b99c BH |
530 | if (detected) |
531 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
532 | intr_loc); | |
c6b069e9 | 533 | } while (detected); |
71ad556d | 534 | |
7f2feec1 | 535 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 536 | |
c6b069e9 | 537 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 538 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 539 | ctrl->cmd_busy = 0; |
2d32a9ae | 540 | smp_mb(); |
d737bdc1 | 541 | wake_up(&ctrl->queue); |
1da177e4 LT |
542 | } |
543 | ||
b440bde7 BH |
544 | if (subordinate) { |
545 | list_for_each_entry(dev, &subordinate->devices, bus_list) { | |
546 | if (dev->ignore_hotplug) { | |
547 | ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", | |
548 | intr_loc, pci_name(dev)); | |
549 | return IRQ_HANDLED; | |
550 | } | |
551 | } | |
552 | } | |
553 | ||
322162a7 | 554 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
555 | return IRQ_HANDLED; |
556 | ||
c6b069e9 | 557 | /* Check MRL Sensor Changed */ |
322162a7 | 558 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 559 | pciehp_handle_switch_change(slot); |
48fe3915 | 560 | |
c6b069e9 | 561 | /* Check Attention Button Pressed */ |
322162a7 | 562 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 563 | pciehp_handle_attention_button(slot); |
48fe3915 | 564 | |
c6b069e9 | 565 | /* Check Presence Detect Changed */ |
322162a7 | 566 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 567 | pciehp_handle_presence_change(slot); |
48fe3915 | 568 | |
c6b069e9 | 569 | /* Check Power Fault Detected */ |
99f0169c KK |
570 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
571 | ctrl->power_fault_detected = 1; | |
8720d27d | 572 | pciehp_handle_power_fault(slot); |
99f0169c | 573 | } |
e48f1b67 RJ |
574 | |
575 | if (intr_loc & PCI_EXP_SLTSTA_DLLSC) | |
576 | pciehp_handle_linkstate_change(slot); | |
577 | ||
1da177e4 LT |
578 | return IRQ_HANDLED; |
579 | } | |
580 | ||
6dae6202 | 581 | void pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 582 | { |
c27fb883 | 583 | u16 cmd, mask; |
1da177e4 | 584 | |
5651c48c KK |
585 | /* |
586 | * TBD: Power fault detected software notification support. | |
587 | * | |
588 | * Power fault detected software notification is not enabled | |
589 | * now, because it caused power fault detected interrupt storm | |
590 | * on some machines. On those machines, power fault detected | |
591 | * bit in the slot status register was set again immediately | |
592 | * when it is cleared in the interrupt service routine, and | |
593 | * next power fault detected interrupt was notified again. | |
594 | */ | |
4f854f2a RJ |
595 | |
596 | /* | |
597 | * Always enable link events: thus link-up and link-down shall | |
598 | * always be treated as hotplug and unplug respectively. Enable | |
599 | * presence detect only if Attention Button is not present. | |
600 | */ | |
601 | cmd = PCI_EXP_SLTCTL_DLLSCE; | |
ae416e6b | 602 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 603 | cmd |= PCI_EXP_SLTCTL_ABPE; |
4f854f2a RJ |
604 | else |
605 | cmd |= PCI_EXP_SLTCTL_PDCE; | |
ae416e6b | 606 | if (MRL_SENS(ctrl)) |
322162a7 | 607 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 608 | if (!pciehp_poll_mode) |
322162a7 | 609 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 610 | |
322162a7 KK |
611 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
612 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
4f854f2a RJ |
613 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
614 | PCI_EXP_SLTCTL_DLLSCE); | |
c27fb883 | 615 | |
6dae6202 | 616 | pcie_write_cmd(ctrl, cmd, mask); |
cf8d7b58 YL |
617 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
618 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); | |
c4635eb0 KK |
619 | } |
620 | ||
621 | static void pcie_disable_notification(struct controller *ctrl) | |
622 | { | |
623 | u16 mask; | |
6dae6202 | 624 | |
322162a7 KK |
625 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
626 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
627 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
628 | PCI_EXP_SLTCTL_DLLSCE); | |
6dae6202 | 629 | pcie_write_cmd(ctrl, 0, mask); |
cf8d7b58 YL |
630 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
631 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
c4635eb0 KK |
632 | } |
633 | ||
2e35afae AW |
634 | /* |
635 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
2b3940b6 RJ |
636 | * bus reset of the bridge, but at the same time we want to ensure that it is |
637 | * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, | |
638 | * disable link state notification and presence detection change notification | |
639 | * momentarily, if we see that they could interfere. Also, clear any spurious | |
2e35afae AW |
640 | * events after. |
641 | */ | |
642 | int pciehp_reset_slot(struct slot *slot, int probe) | |
643 | { | |
644 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 645 | struct pci_dev *pdev = ctrl_dev(ctrl); |
06a8d89a | 646 | u16 stat_mask = 0, ctrl_mask = 0; |
2e35afae AW |
647 | |
648 | if (probe) | |
649 | return 0; | |
650 | ||
2b3940b6 | 651 | if (!ATTN_BUTTN(ctrl)) { |
06a8d89a RJ |
652 | ctrl_mask |= PCI_EXP_SLTCTL_PDCE; |
653 | stat_mask |= PCI_EXP_SLTSTA_PDC; | |
2e35afae | 654 | } |
06a8d89a RJ |
655 | ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; |
656 | stat_mask |= PCI_EXP_SLTSTA_DLLSC; | |
657 | ||
658 | pcie_write_cmd(ctrl, 0, ctrl_mask); | |
cf8d7b58 YL |
659 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
660 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); | |
06a8d89a RJ |
661 | if (pciehp_poll_mode) |
662 | del_timer_sync(&ctrl->poll_timer); | |
2e35afae AW |
663 | |
664 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
665 | ||
06a8d89a RJ |
666 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); |
667 | pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask); | |
cf8d7b58 YL |
668 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
669 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); | |
06a8d89a RJ |
670 | if (pciehp_poll_mode) |
671 | int_poll_timeout(ctrl->poll_timer.data); | |
2e35afae AW |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
dbc7e1e5 | 676 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
677 | { |
678 | if (pciehp_request_irq(ctrl)) | |
679 | return -1; | |
6dae6202 | 680 | pcie_enable_notification(ctrl); |
dbc7e1e5 | 681 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
682 | return 0; |
683 | } | |
684 | ||
685 | static void pcie_shutdown_notification(struct controller *ctrl) | |
686 | { | |
dbc7e1e5 EB |
687 | if (ctrl->notification_enabled) { |
688 | pcie_disable_notification(ctrl); | |
689 | pciehp_free_irq(ctrl); | |
690 | ctrl->notification_enabled = 0; | |
691 | } | |
c4635eb0 KK |
692 | } |
693 | ||
c4635eb0 KK |
694 | static int pcie_init_slot(struct controller *ctrl) |
695 | { | |
696 | struct slot *slot; | |
697 | ||
698 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
699 | if (!slot) | |
700 | return -ENOMEM; | |
701 | ||
d8537548 | 702 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
703 | if (!slot->wq) |
704 | goto abort; | |
705 | ||
c4635eb0 | 706 | slot->ctrl = ctrl; |
c4635eb0 | 707 | mutex_init(&slot->lock); |
50b52fde | 708 | mutex_init(&slot->hotplug_lock); |
c4635eb0 | 709 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
8720d27d | 710 | ctrl->slot = slot; |
1da177e4 | 711 | return 0; |
c2be6f93 YW |
712 | abort: |
713 | kfree(slot); | |
714 | return -ENOMEM; | |
1da177e4 | 715 | } |
08e7a7d2 | 716 | |
c4635eb0 KK |
717 | static void pcie_cleanup_slot(struct controller *ctrl) |
718 | { | |
8720d27d | 719 | struct slot *slot = ctrl->slot; |
c4635eb0 | 720 | cancel_delayed_work(&slot->work); |
c2be6f93 | 721 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
722 | kfree(slot); |
723 | } | |
724 | ||
2aeeef11 | 725 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 726 | { |
2aeeef11 KK |
727 | int i; |
728 | u16 reg16; | |
385e2491 | 729 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 730 | |
2aeeef11 KK |
731 | if (!pciehp_debug) |
732 | return; | |
08e7a7d2 | 733 | |
7f2feec1 TI |
734 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
735 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
736 | pci_name(pdev), pdev->irq); | |
737 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
738 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
739 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
740 | pdev->subsystem_device); | |
741 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
742 | pdev->subsystem_vendor); | |
1518c17a KK |
743 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
744 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
745 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
746 | if (!pci_resource_len(pdev, i)) | |
747 | continue; | |
e1944c6b BH |
748 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
749 | i, &pdev->resource[i]); | |
08e7a7d2 | 750 | } |
7f2feec1 | 751 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 752 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
753 | ctrl_info(ctrl, " Attention Button : %3s\n", |
754 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
755 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
756 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
757 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
758 | MRL_SENS(ctrl) ? "yes" : "no"); | |
759 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
760 | ATTN_LED(ctrl) ? "yes" : "no"); | |
761 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
762 | PWR_LED(ctrl) ? "yes" : "no"); | |
763 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
764 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
765 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
766 | EMI(ctrl) ? "yes" : "no"); | |
767 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
768 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
cd84d340 | 769 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 770 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 771 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 772 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 773 | } |
08e7a7d2 | 774 | |
3c78bc61 | 775 | #define FLAG(x, y) (((x) & (y)) ? '+' : '-') |
afe2478f | 776 | |
c4635eb0 | 777 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 778 | { |
c4635eb0 | 779 | struct controller *ctrl; |
f18e9625 | 780 | u32 slot_cap, link_cap; |
2aeeef11 | 781 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 782 | |
c4635eb0 KK |
783 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
784 | if (!ctrl) { | |
18b341b7 | 785 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
786 | goto abort; |
787 | } | |
f7a10e32 | 788 | ctrl->pcie = dev; |
1a84b99c | 789 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
2aeeef11 | 790 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 791 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 792 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 793 | dbg_ctrl(ctrl); |
2cc56f30 | 794 | |
3c78bc61 RD |
795 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
796 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); | |
797 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { | |
798 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); | |
799 | ctrl->link_active_reporting = 1; | |
800 | } | |
f18e9625 | 801 | |
c4635eb0 | 802 | /* Clear all remaining event bits in Slot Status register */ |
df72648c BH |
803 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
804 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | | |
805 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
0d25d35c | 806 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
08e7a7d2 | 807 | |
afe2478f BH |
808 | ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", |
809 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, | |
810 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), | |
811 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), | |
812 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), | |
813 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), | |
814 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), | |
815 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), | |
816 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), | |
817 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); | |
c4635eb0 KK |
818 | |
819 | if (pcie_init_slot(ctrl)) | |
820 | goto abort_ctrl; | |
2aeeef11 | 821 | |
c4635eb0 KK |
822 | return ctrl; |
823 | ||
c4635eb0 KK |
824 | abort_ctrl: |
825 | kfree(ctrl); | |
08e7a7d2 | 826 | abort: |
c4635eb0 KK |
827 | return NULL; |
828 | } | |
829 | ||
82a9e79e | 830 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
831 | { |
832 | pcie_shutdown_notification(ctrl); | |
833 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 834 | kfree(ctrl); |
08e7a7d2 | 835 | } |