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PCI: pciehp: remove pci_dev field
[deliverable/linux.git] / drivers / pci / hotplug / pciehp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
de25968c
TS		 33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
1da177e4 36#include <linux/pci.h>
5d1b8c9e 37#include <linux/interrupt.h>
34d03419 38#include <linux/time.h>
5d1b8c9e 39
1da177e4
LT		 40#include "../pci.h"
41#include "pciehp.h"
1da177e4 42
5d386e1a
KK		 43static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
a0f018da
KK		 45static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46{
385e2491 47 struct pci_dev *dev = ctrl->pcie->port;
a0f018da
KK		 48 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
49}
50
51static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52{
385e2491 53 struct pci_dev *dev = ctrl->pcie->port;
a0f018da
KK		 54 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
55}
56
57static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58{
385e2491 59 struct pci_dev *dev = ctrl->pcie->port;
a0f018da
KK		 60 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
61}
62
63static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64{
385e2491 65 struct pci_dev *dev = ctrl->pcie->port;
a0f018da
KK		 66 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
67}
1da177e4 68
1da177e4
LT		 69/* Power Control Command */
70#define POWER_ON 0
322162a7 71#define POWER_OFF PCI_EXP_SLTCTL_PCC
1da177e4 72
48fe3915
KK		 73static irqreturn_t pcie_isr(int irq, void *dev_id);
74static void start_int_poll_timer(struct controller *ctrl, int sec);
1da177e4
LT		 75
76/* This is the interrupt polling timeout function. */
48fe3915 77static void int_poll_timeout(unsigned long data)
1da177e4 78{
48fe3915 79 struct controller *ctrl = (struct controller *)data;
1da177e4 80
1da177e4 81 /* Poll for interrupt events. regs == NULL => polling */
48fe3915 82 pcie_isr(0, ctrl);
1da177e4 83
48fe3915 84 init_timer(&ctrl->poll_timer);
1da177e4 85 if (!pciehp_poll_time)
40730d10 86 pciehp_poll_time = 2; /* default polling interval is 2 sec */
1da177e4 87
48fe3915 88 start_int_poll_timer(ctrl, pciehp_poll_time);
1da177e4
LT		 89}
90
91/* This function starts the interrupt polling timer. */
48fe3915 92static void start_int_poll_timer(struct controller *ctrl, int sec)
1da177e4 93{
48fe3915
KK		 94 /* Clamp to sane value */
95 if ((sec <= 0) || (sec > 60))
96 sec = 2;
97
98 ctrl->poll_timer.function = &int_poll_timeout;
99 ctrl->poll_timer.data = (unsigned long)ctrl;
100 ctrl->poll_timer.expires = jiffies + sec * HZ;
101 add_timer(&ctrl->poll_timer);
1da177e4
LT		 102}
103
2aeeef11
KK		 104static inline int pciehp_request_irq(struct controller *ctrl)
105{
f7a10e32 106 int retval, irq = ctrl->pcie->irq;
2aeeef11
KK		 107
108 /* Install interrupt polling timer. Start with 10 sec delay */
109 if (pciehp_poll_mode) {
110 init_timer(&ctrl->poll_timer);
111 start_int_poll_timer(ctrl, 10);
112 return 0;
113 }
114
115 /* Installs the interrupt handler */
116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 if (retval)
7f2feec1
TI		 118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
119 irq);
2aeeef11
KK		 120 return retval;
121}
122
123static inline void pciehp_free_irq(struct controller *ctrl)
124{
125 if (pciehp_poll_mode)
126 del_timer_sync(&ctrl->poll_timer);
127 else
f7a10e32 128 free_irq(ctrl->pcie->irq, ctrl);
2aeeef11
KK		 129}
130
563f1190 131static int pcie_poll_cmd(struct controller *ctrl)
6592e02a
KK		 132{
133 u16 slot_status;
322162a7 134 int err, timeout = 1000;
6592e02a 135
322162a7
KK		 136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
139 return 1;
820943b6 140 }
a5827f40 141 while (timeout > 0) {
66618bad
KK		 142 msleep(10);
143 timeout -= 10;
322162a7
KK		 144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
147 return 1;
820943b6 148 }
6592e02a
KK		 149 }
150 return 0; /* timeout */
6592e02a
KK		 151}
152
563f1190 153static void pcie_wait_cmd(struct controller *ctrl, int poll)
44ef4cef 154{
262303fe
KK		 155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
156 unsigned long timeout = msecs_to_jiffies(msecs);
157 int rc;
158
6592e02a
KK		 159 if (poll)
160 rc = pcie_poll_cmd(ctrl);
161 else
d737bdc1 162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
262303fe 163 if (!rc)
7f2feec1 164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
44ef4cef
KK		 165}
166
f4778364
KK		 167/**
168 * pcie_write_cmd - Issue controller command
c27fb883 169 * @ctrl: controller to which the command is issued
f4778364
KK		 170 * @cmd: command value written to slot control register
171 * @mask: bitmask of slot control register to be modified
172 */
c27fb883 173static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
1da177e4 174{
1da177e4
LT		 175 int retval = 0;
176 u16 slot_status;
f4778364 177 u16 slot_ctrl;
1da177e4 178
44ef4cef
KK		 179 mutex_lock(&ctrl->ctrl_lock);
180
322162a7 181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 182 if (retval) {
7f2feec1
TI		 183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
184 __func__);
44ef4cef 185 goto out;
a0f018da
KK		 186 }
187
322162a7 188 if (slot_status & PCI_EXP_SLTSTA_CC) {
5808639b
KK		 189 if (!ctrl->no_cmd_complete) {
190 /*
191 * After 1 sec and CMD_COMPLETED still not set, just
192 * proceed forward to issue the next command according
193 * to spec. Just print out the error message.
194 */
18b341b7 195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
5808639b
KK		 196 } else if (!NO_CMD_CMPL(ctrl)) {
197 /*
198 * This controller semms to notify of command completed
199 * event even though it supports none of power
200 * controller, attention led, power led and EMI.
201 */
18b341b7
TI		 202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 "wait for command completed event.\n");
5808639b
KK		 204 ctrl->no_cmd_complete = 0;
205 } else {
18b341b7
TI		 206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
207 "the controller is broken.\n");
5808639b 208 }
1da177e4
LT		 209 }
210
322162a7 211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 212 if (retval) {
7f2feec1 213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
c6b069e9 214 goto out;
1da177e4 215 }
1da177e4 216
f4778364 217 slot_ctrl &= ~mask;
b7aa1f16 218 slot_ctrl |= (cmd & mask);
f4778364 219 ctrl->cmd_busy = 1;
2d32a9ae 220 smp_mb();
322162a7 221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
f4778364 222 if (retval)
18b341b7 223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
f4778364 224
44ef4cef
KK		 225 /*
226 * Wait for command completion.
227 */
6592e02a
KK		 228 if (!retval && !ctrl->no_cmd_complete) {
229 int poll = 0;
230 /*
231 * if hotplug interrupt is not enabled or command
232 * completed interrupt is not enabled, we need to poll
233 * command completed event.
234 */
322162a7
KK		 235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
6592e02a 237 poll = 1;
d737bdc1 238 pcie_wait_cmd(ctrl, poll);
6592e02a 239 }
44ef4cef
KK		 240 out:
241 mutex_unlock(&ctrl->ctrl_lock);
1da177e4
LT		 242 return retval;
243}
244
f18e9625
KK		 245static inline int check_link_active(struct controller *ctrl)
246{
247 u16 link_status;
248
322162a7 249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
f18e9625 250 return 0;
322162a7 251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
f18e9625
KK		 252}
253
254static void pcie_wait_link_active(struct controller *ctrl)
255{
256 int timeout = 1000;
257
258 if (check_link_active(ctrl))
259 return;
260 while (timeout > 0) {
261 msleep(10);
262 timeout -= 10;
263 if (check_link_active(ctrl))
264 return;
265 }
266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
267}
268
1da177e4
LT		 269static int hpc_check_lnk_status(struct controller *ctrl)
270{
1da177e4
LT		 271 u16 lnk_status;
272 int retval = 0;
273
f18e9625
KK		 274 /*
275 * Data Link Layer Link Active Reporting must be capable for
276 * hot-plug capable downstream port. But old controller might
277 * not implement it. In this case, we wait for 1000 ms.
278 */
279 if (ctrl->link_active_reporting){
280 /* Wait for Data Link Layer Link Active bit to be set */
281 pcie_wait_link_active(ctrl);
282 /*
283 * We must wait for 100 ms after the Data Link Layer
284 * Link Active bit reads 1b before initiating a
285 * configuration access to the hot added device.
286 */
287 msleep(100);
288 } else
289 msleep(1000);
290
322162a7 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 292 if (retval) {
18b341b7 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
1da177e4
LT		 294 return retval;
295 }
296
7f2feec1 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
322162a7
KK		 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
18b341b7 300 ctrl_err(ctrl, "Link Training Error occurs \n");
1da177e4
LT		 301 retval = -1;
302 return retval;
303 }
304
1da177e4
LT		 305 return retval;
306}
307
1da177e4
LT		 308static int hpc_get_attention_status(struct slot *slot, u8 *status)
309{
48fe3915 310 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 311 u16 slot_ctrl;
312 u8 atten_led_state;
313 int retval = 0;
1da177e4 314
322162a7 315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 316 if (retval) {
7f2feec1 317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 318 return retval;
319 }
320
7f2feec1 321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
322162a7 322 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
1da177e4 323
322162a7 324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
1da177e4
LT		 325
326 switch (atten_led_state) {
327 case 0:
328 *status = 0xFF; /* Reserved */
329 break;
330 case 1:
331 *status = 1; /* On */
332 break;
333 case 2:
334 *status = 2; /* Blink */
335 break;
336 case 3:
337 *status = 0; /* Off */
338 break;
339 default:
340 *status = 0xFF;
341 break;
342 }
343
1da177e4
LT		 344 return 0;
345}
346
48fe3915 347static int hpc_get_power_status(struct slot *slot, u8 *status)
1da177e4 348{
48fe3915 349 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 350 u16 slot_ctrl;
351 u8 pwr_state;
352 int retval = 0;
1da177e4 353
322162a7 354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 355 if (retval) {
7f2feec1 356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 357 return retval;
358 }
7f2feec1 359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
322162a7 360 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
1da177e4 361
322162a7 362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
1da177e4
LT		 363
364 switch (pwr_state) {
365 case 0:
366 *status = 1;
367 break;
368 case 1:
71ad556d 369 *status = 0;
1da177e4
LT		 370 break;
371 default:
372 *status = 0xFF;
373 break;
374 }
375
1da177e4
LT		 376 return retval;
377}
378
1da177e4
LT		 379static int hpc_get_latch_status(struct slot *slot, u8 *status)
380{
48fe3915 381 struct controller *ctrl = slot->ctrl;
1da177e4 382 u16 slot_status;
322162a7 383 int retval;
1da177e4 384
322162a7 385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 386 if (retval) {
7f2feec1
TI		 387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
388 __func__);
1da177e4
LT		 389 return retval;
390 }
322162a7 391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
1da177e4
LT		 392 return 0;
393}
394
395static int hpc_get_adapter_status(struct slot *slot, u8 *status)
396{
48fe3915 397 struct controller *ctrl = slot->ctrl;
1da177e4 398 u16 slot_status;
322162a7 399 int retval;
1da177e4 400
322162a7 401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 402 if (retval) {
7f2feec1
TI		 403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
404 __func__);
1da177e4
LT		 405 return retval;
406 }
322162a7 407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
1da177e4
LT		 408 return 0;
409}
410
48fe3915 411static int hpc_query_power_fault(struct slot *slot)
1da177e4 412{
48fe3915 413 struct controller *ctrl = slot->ctrl;
1da177e4 414 u16 slot_status;
322162a7 415 int retval;
1da177e4 416
322162a7 417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 418 if (retval) {
18b341b7 419 ctrl_err(ctrl, "Cannot check for power fault\n");
1da177e4
LT		 420 return retval;
421 }
322162a7 422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
1da177e4
LT		 423}
424
425static int hpc_set_attention_status(struct slot *slot, u8 value)
426{
48fe3915 427 struct controller *ctrl = slot->ctrl;
f4778364
KK		 428 u16 slot_cmd;
429 u16 cmd_mask;
430 int rc;
1da177e4 431
322162a7 432 cmd_mask = PCI_EXP_SLTCTL_AIC;
1da177e4
LT		 433 switch (value) {
434 case 0 : /* turn off */
f4778364 435 slot_cmd = 0x00C0;
1da177e4
LT		 436 break;
437 case 1: /* turn on */
f4778364 438 slot_cmd = 0x0040;
1da177e4
LT		 439 break;
440 case 2: /* turn blink */
f4778364 441 slot_cmd = 0x0080;
1da177e4
LT		 442 break;
443 default:
444 return -1;
445 }
c27fb883 446 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 448 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
71ad556d 449
1da177e4
LT		 450 return rc;
451}
452
1da177e4
LT		 453static void hpc_set_green_led_on(struct slot *slot)
454{
48fe3915 455 struct controller *ctrl = slot->ctrl;
1da177e4 456 u16 slot_cmd;
f4778364 457 u16 cmd_mask;
71ad556d 458
f4778364 459 slot_cmd = 0x0100;
322162a7 460 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 461 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 462 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 463 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 464}
465
466static void hpc_set_green_led_off(struct slot *slot)
467{
48fe3915 468 struct controller *ctrl = slot->ctrl;
1da177e4 469 u16 slot_cmd;
f4778364 470 u16 cmd_mask;
1da177e4 471
f4778364 472 slot_cmd = 0x0300;
322162a7 473 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 474 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 475 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 476 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 477}
478
479static void hpc_set_green_led_blink(struct slot *slot)
480{
48fe3915 481 struct controller *ctrl = slot->ctrl;
1da177e4 482 u16 slot_cmd;
f4778364 483 u16 cmd_mask;
71ad556d 484
f4778364 485 slot_cmd = 0x0200;
322162a7 486 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 487 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 489 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 490}
491
1da177e4
LT		 492static int hpc_power_on_slot(struct slot * slot)
493{
48fe3915 494 struct controller *ctrl = slot->ctrl;
1da177e4 495 u16 slot_cmd;
f4778364
KK		 496 u16 cmd_mask;
497 u16 slot_status;
1da177e4
LT		 498 int retval = 0;
499
5a49f203 500 /* Clear sticky power-fault bit from previous power failures */
322162a7 501 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
a0f018da 502 if (retval) {
7f2feec1
TI		 503 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
504 __func__);
a0f018da
KK		 505 return retval;
506 }
322162a7 507 slot_status &= PCI_EXP_SLTSTA_PFD;
a0f018da 508 if (slot_status) {
322162a7 509 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
a0f018da 510 if (retval) {
7f2feec1
TI		 511 ctrl_err(ctrl,
512 "%s: Cannot write to SLOTSTATUS register\n",
513 __func__);
a0f018da
KK		 514 return retval;
515 }
516 }
1da177e4 517
f4778364 518 slot_cmd = POWER_ON;
322162a7 519 cmd_mask = PCI_EXP_SLTCTL_PCC;
f4778364 520 if (!pciehp_poll_mode) {
99f0169c
KK		 521 /* Enable power fault detection turned off at power off time */
522 slot_cmd |= PCI_EXP_SLTCTL_PFDE;
523 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
f4778364 524 }
1da177e4 525
c27fb883 526 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4 527 if (retval) {
18b341b7 528 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
99f0169c 529 return retval;
1da177e4 530 }
7f2feec1 531 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 532 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4 533
99f0169c 534 ctrl->power_fault_detected = 0;
1da177e4
LT		 535 return retval;
536}
537
f1050a35
KK		 538static inline int pcie_mask_bad_dllp(struct controller *ctrl)
539{
385e2491 540 struct pci_dev *dev = ctrl->pcie->port;
f1050a35
KK		 541 int pos;
542 u32 reg;
543
544 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
545 if (!pos)
546 return 0;
547 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
548 if (reg & PCI_ERR_COR_BAD_DLLP)
549 return 0;
550 reg |= PCI_ERR_COR_BAD_DLLP;
551 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
552 return 1;
553}
554
555static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
556{
385e2491 557 struct pci_dev *dev = ctrl->pcie->port;
f1050a35
KK		 558 u32 reg;
559 int pos;
560
561 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
562 if (!pos)
563 return;
564 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
565 if (!(reg & PCI_ERR_COR_BAD_DLLP))
566 return;
567 reg &= ~PCI_ERR_COR_BAD_DLLP;
568 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
569}
570
1da177e4
LT		 571static int hpc_power_off_slot(struct slot * slot)
572{
48fe3915 573 struct controller *ctrl = slot->ctrl;
1da177e4 574 u16 slot_cmd;
f4778364 575 u16 cmd_mask;
1da177e4 576 int retval = 0;
f1050a35 577 int changed;
1da177e4 578
f1050a35
KK		 579 /*
580 * Set Bad DLLP Mask bit in Correctable Error Mask
581 * Register. This is the workaround against Bad DLLP error
582 * that sometimes happens during turning power off the slot
583 * which conforms to PCI Express 1.0a spec.
584 */
585 changed = pcie_mask_bad_dllp(ctrl);
586
f4778364 587 slot_cmd = POWER_OFF;
322162a7 588 cmd_mask = PCI_EXP_SLTCTL_PCC;
f4778364 589 if (!pciehp_poll_mode) {
99f0169c
KK		 590 /* Disable power fault detection */
591 slot_cmd &= ~PCI_EXP_SLTCTL_PFDE;
592 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
f4778364 593 }
1da177e4 594
c27fb883 595 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4 596 if (retval) {
18b341b7 597 ctrl_err(ctrl, "Write command failed!\n");
c1ef5cbd
KK		 598 retval = -1;
599 goto out;
1da177e4 600 }
7f2feec1 601 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 602 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
c1ef5cbd 603 out:
f1050a35
KK		 604 if (changed)
605 pcie_unmask_bad_dllp(ctrl);
606
1da177e4
LT		 607 return retval;
608}
609
48fe3915 610static irqreturn_t pcie_isr(int irq, void *dev_id)
1da177e4 611{
48fe3915 612 struct controller *ctrl = (struct controller *)dev_id;
8720d27d 613 struct slot *slot = ctrl->slot;
c6b069e9 614 u16 detected, intr_loc;
1da177e4 615
c6b069e9
KK		 616 /*
617 * In order to guarantee that all interrupt events are
618 * serviced, we need to re-inspect Slot Status register after
619 * clearing what is presumed to be the last pending interrupt.
620 */
621 intr_loc = 0;
622 do {
322162a7 623 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
7f2feec1
TI		 624 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
625 __func__);
1da177e4
LT		 626 return IRQ_NONE;
627 }
628
322162a7
KK		 629 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
630 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
631 PCI_EXP_SLTSTA_CC);
81b840cd 632 detected &= ~intr_loc;
c6b069e9
KK		 633 intr_loc |= detected;
634 if (!intr_loc)
1da177e4 635 return IRQ_NONE;
81b840cd 636 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
7f2feec1
TI		 637 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
638 __func__);
1da177e4
LT		 639 return IRQ_NONE;
640 }
c6b069e9 641 } while (detected);
71ad556d 642
7f2feec1 643 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
71ad556d 644
c6b069e9 645 /* Check Command Complete Interrupt Pending */
322162a7 646 if (intr_loc & PCI_EXP_SLTSTA_CC) {
262303fe 647 ctrl->cmd_busy = 0;
2d32a9ae 648 smp_mb();
d737bdc1 649 wake_up(&ctrl->queue);
1da177e4
LT		 650 }
651
322162a7 652 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
dbd79aed
KK		 653 return IRQ_HANDLED;
654
c6b069e9 655 /* Check MRL Sensor Changed */
322162a7 656 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
8720d27d 657 pciehp_handle_switch_change(slot);
48fe3915 658
c6b069e9 659 /* Check Attention Button Pressed */
322162a7 660 if (intr_loc & PCI_EXP_SLTSTA_ABP)
8720d27d 661 pciehp_handle_attention_button(slot);
48fe3915 662
c6b069e9 663 /* Check Presence Detect Changed */
322162a7 664 if (intr_loc & PCI_EXP_SLTSTA_PDC)
8720d27d 665 pciehp_handle_presence_change(slot);
48fe3915 666
c6b069e9 667 /* Check Power Fault Detected */
99f0169c
KK		 668 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
669 ctrl->power_fault_detected = 1;
8720d27d 670 pciehp_handle_power_fault(slot);
99f0169c 671 }
1da177e4
LT		 672 return IRQ_HANDLED;
673}
674
40730d10 675static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 676{
48fe3915 677 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 678 enum pcie_link_speed lnk_speed;
679 u32 lnk_cap;
680 int retval = 0;
681
322162a7 682 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
1da177e4 683 if (retval) {
7f2feec1 684 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 685 return retval;
686 }
687
688 switch (lnk_cap & 0x000F) {
689 case 1:
825c423a
KK		 690 lnk_speed = PCIE_2_5GB;
691 break;
692 case 2:
693 lnk_speed = PCIE_5_0GB;
1da177e4
LT		 694 break;
695 default:
696 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
697 break;
698 }
699
700 *value = lnk_speed;
7f2feec1 701 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
c8426483 702
1da177e4
LT		 703 return retval;
704}
705
40730d10
KK		 706static int hpc_get_max_lnk_width(struct slot *slot,
707 enum pcie_link_width *value)
1da177e4 708{
48fe3915 709 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 710 enum pcie_link_width lnk_wdth;
711 u32 lnk_cap;
712 int retval = 0;
713
322162a7 714 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
1da177e4 715 if (retval) {
7f2feec1 716 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 717 return retval;
718 }
719
322162a7 720 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
1da177e4
LT		 721 case 0:
722 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
723 break;
724 case 1:
725 lnk_wdth = PCIE_LNK_X1;
726 break;
727 case 2:
728 lnk_wdth = PCIE_LNK_X2;
729 break;
730 case 4:
731 lnk_wdth = PCIE_LNK_X4;
732 break;
733 case 8:
734 lnk_wdth = PCIE_LNK_X8;
735 break;
736 case 12:
737 lnk_wdth = PCIE_LNK_X12;
738 break;
739 case 16:
740 lnk_wdth = PCIE_LNK_X16;
741 break;
742 case 32:
743 lnk_wdth = PCIE_LNK_X32;
744 break;
745 default:
746 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
747 break;
748 }
749
750 *value = lnk_wdth;
7f2feec1 751 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
c8426483 752
1da177e4
LT		 753 return retval;
754}
755
40730d10 756static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 757{
48fe3915 758 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 759 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
760 int retval = 0;
761 u16 lnk_status;
762
322162a7 763 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 764 if (retval) {
7f2feec1
TI		 765 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
766 __func__);
1da177e4
LT		 767 return retval;
768 }
769
322162a7 770 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
1da177e4 771 case 1:
825c423a
KK		 772 lnk_speed = PCIE_2_5GB;
773 break;
774 case 2:
775 lnk_speed = PCIE_5_0GB;
1da177e4
LT		 776 break;
777 default:
778 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
779 break;
780 }
781
782 *value = lnk_speed;
7f2feec1 783 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
c8426483 784
1da177e4
LT		 785 return retval;
786}
787
40730d10
KK		 788static int hpc_get_cur_lnk_width(struct slot *slot,
789 enum pcie_link_width *value)
1da177e4 790{
48fe3915 791 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 792 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
793 int retval = 0;
794 u16 lnk_status;
795
322162a7 796 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 797 if (retval) {
7f2feec1
TI		 798 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
799 __func__);
1da177e4
LT		 800 return retval;
801 }
71ad556d 802
322162a7 803 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
1da177e4
LT		 804 case 0:
805 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
806 break;
807 case 1:
808 lnk_wdth = PCIE_LNK_X1;
809 break;
810 case 2:
811 lnk_wdth = PCIE_LNK_X2;
812 break;
813 case 4:
814 lnk_wdth = PCIE_LNK_X4;
815 break;
816 case 8:
817 lnk_wdth = PCIE_LNK_X8;
818 break;
819 case 12:
820 lnk_wdth = PCIE_LNK_X12;
821 break;
822 case 16:
823 lnk_wdth = PCIE_LNK_X16;
824 break;
825 case 32:
826 lnk_wdth = PCIE_LNK_X32;
827 break;
828 default:
829 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
830 break;
831 }
832
833 *value = lnk_wdth;
7f2feec1 834 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
c8426483 835
1da177e4
LT		 836 return retval;
837}
838
c4635eb0 839static void pcie_release_ctrl(struct controller *ctrl);
1da177e4
LT		 840static struct hpc_ops pciehp_hpc_ops = {
841 .power_on_slot = hpc_power_on_slot,
842 .power_off_slot = hpc_power_off_slot,
843 .set_attention_status = hpc_set_attention_status,
844 .get_power_status = hpc_get_power_status,
845 .get_attention_status = hpc_get_attention_status,
846 .get_latch_status = hpc_get_latch_status,
847 .get_adapter_status = hpc_get_adapter_status,
848
849 .get_max_bus_speed = hpc_get_max_lnk_speed,
850 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
851 .get_max_lnk_width = hpc_get_max_lnk_width,
852 .get_cur_lnk_width = hpc_get_cur_lnk_width,
71ad556d 853
1da177e4
LT		 854 .query_power_fault = hpc_query_power_fault,
855 .green_led_on = hpc_set_green_led_on,
856 .green_led_off = hpc_set_green_led_off,
857 .green_led_blink = hpc_set_green_led_blink,
71ad556d 858
c4635eb0 859 .release_ctlr = pcie_release_ctrl,
1da177e4
LT		 860 .check_lnk_status = hpc_check_lnk_status,
861};
862
c4635eb0 863int pcie_enable_notification(struct controller *ctrl)
ecdde939 864{
c27fb883 865 u16 cmd, mask;
1da177e4 866
322162a7 867 cmd = PCI_EXP_SLTCTL_PDCE;
ae416e6b 868 if (ATTN_BUTTN(ctrl))
322162a7 869 cmd |= PCI_EXP_SLTCTL_ABPE;
ae416e6b 870 if (POWER_CTRL(ctrl))
322162a7 871 cmd |= PCI_EXP_SLTCTL_PFDE;
ae416e6b 872 if (MRL_SENS(ctrl))
322162a7 873 cmd |= PCI_EXP_SLTCTL_MRLSCE;
c27fb883 874 if (!pciehp_poll_mode)
322162a7 875 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
c27fb883 876
322162a7
KK		 877 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
878 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
879 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
c27fb883
KK		 880
881 if (pcie_write_cmd(ctrl, cmd, mask)) {
18b341b7 882 ctrl_err(ctrl, "Cannot enable software notification\n");
125c39f7 883 return -1;
1da177e4 884 }
c4635eb0
KK		 885 return 0;
886}
887
888static void pcie_disable_notification(struct controller *ctrl)
889{
890 u16 mask;
322162a7
KK		 891 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
892 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
893 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
c4635eb0 894 if (pcie_write_cmd(ctrl, 0, mask))
18b341b7 895 ctrl_warn(ctrl, "Cannot disable software notification\n");
c4635eb0
KK		 896}
897
dbc7e1e5 898int pcie_init_notification(struct controller *ctrl)
c4635eb0
KK		 899{
900 if (pciehp_request_irq(ctrl))
901 return -1;
902 if (pcie_enable_notification(ctrl)) {
903 pciehp_free_irq(ctrl);
904 return -1;
905 }
dbc7e1e5 906 ctrl->notification_enabled = 1;
c4635eb0
KK		 907 return 0;
908}
909
910static void pcie_shutdown_notification(struct controller *ctrl)
911{
dbc7e1e5
EB		 912 if (ctrl->notification_enabled) {
913 pcie_disable_notification(ctrl);
914 pciehp_free_irq(ctrl);
915 ctrl->notification_enabled = 0;
916 }
c4635eb0
KK		 917}
918
c4635eb0
KK		 919static int pcie_init_slot(struct controller *ctrl)
920{
921 struct slot *slot;
922
923 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
924 if (!slot)
925 return -ENOMEM;
926
c4635eb0 927 slot->ctrl = ctrl;
c4635eb0 928 slot->hpc_ops = ctrl->hpc_ops;
d54798f0 929 slot->number = PSN(ctrl);
c4635eb0
KK		 930 mutex_init(&slot->lock);
931 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
8720d27d 932 ctrl->slot = slot;
1da177e4 933 return 0;
1da177e4 934}
08e7a7d2 935
c4635eb0
KK		 936static void pcie_cleanup_slot(struct controller *ctrl)
937{
8720d27d 938 struct slot *slot = ctrl->slot;
c4635eb0
KK		 939 cancel_delayed_work(&slot->work);
940 flush_scheduled_work();
941 flush_workqueue(pciehp_wq);
942 kfree(slot);
943}
944
2aeeef11 945static inline void dbg_ctrl(struct controller *ctrl)
08e7a7d2 946{
2aeeef11
KK		 947 int i;
948 u16 reg16;
385e2491 949 struct pci_dev *pdev = ctrl->pcie->port;
08e7a7d2 950
2aeeef11
KK		 951 if (!pciehp_debug)
952 return;
08e7a7d2 953
7f2feec1
TI		 954 ctrl_info(ctrl, "Hotplug Controller:\n");
955 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
956 pci_name(pdev), pdev->irq);
957 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
958 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
959 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
960 pdev->subsystem_device);
961 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
962 pdev->subsystem_vendor);
963 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
2aeeef11
KK		 964 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
965 if (!pci_resource_len(pdev, i))
966 continue;
7f2feec1
TI		 967 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
968 i, (unsigned long long)pci_resource_len(pdev, i),
969 (unsigned long long)pci_resource_start(pdev, i));
08e7a7d2 970 }
7f2feec1 971 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
d54798f0 972 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
7f2feec1
TI		 973 ctrl_info(ctrl, " Attention Button : %3s\n",
974 ATTN_BUTTN(ctrl) ? "yes" : "no");
975 ctrl_info(ctrl, " Power Controller : %3s\n",
976 POWER_CTRL(ctrl) ? "yes" : "no");
977 ctrl_info(ctrl, " MRL Sensor : %3s\n",
978 MRL_SENS(ctrl) ? "yes" : "no");
979 ctrl_info(ctrl, " Attention Indicator : %3s\n",
980 ATTN_LED(ctrl) ? "yes" : "no");
981 ctrl_info(ctrl, " Power Indicator : %3s\n",
982 PWR_LED(ctrl) ? "yes" : "no");
983 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
984 HP_SUPR_RM(ctrl) ? "yes" : "no");
985 ctrl_info(ctrl, " EMI Present : %3s\n",
986 EMI(ctrl) ? "yes" : "no");
987 ctrl_info(ctrl, " Command Completed : %3s\n",
988 NO_CMD_CMPL(ctrl) ? "no" : "yes");
322162a7 989 pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
7f2feec1 990 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
322162a7 991 pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
7f2feec1 992 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
2aeeef11 993}
08e7a7d2 994
c4635eb0 995struct controller *pcie_init(struct pcie_device *dev)
2aeeef11 996{
c4635eb0 997 struct controller *ctrl;
f18e9625 998 u32 slot_cap, link_cap;
2aeeef11 999 struct pci_dev *pdev = dev->port;
08e7a7d2 1000
c4635eb0
KK		 1001 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1002 if (!ctrl) {
18b341b7 1003 dev_err(&dev->device, "%s: Out of memory\n", __func__);
c4635eb0
KK		 1004 goto abort;
1005 }
f7a10e32 1006 ctrl->pcie = dev;
2aeeef11
KK		 1007 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1008 if (!ctrl->cap_base) {
18b341b7 1009 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
b84346ef 1010 goto abort_ctrl;
08e7a7d2 1011 }
322162a7 1012 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
18b341b7 1013 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
b84346ef 1014 goto abort_ctrl;
08e7a7d2 1015 }
08e7a7d2 1016
2aeeef11 1017 ctrl->slot_cap = slot_cap;
2aeeef11 1018 ctrl->hpc_ops = &pciehp_hpc_ops;
08e7a7d2 1019 mutex_init(&ctrl->ctrl_lock);
08e7a7d2 1020 init_waitqueue_head(&ctrl->queue);
2aeeef11 1021 dbg_ctrl(ctrl);
5808639b
KK		 1022 /*
1023 * Controller doesn't notify of command completion if the "No
1024 * Command Completed Support" bit is set in Slot Capability
1025 * register or the controller supports none of power
1026 * controller, attention led, power led and EMI.
1027 */
1028 if (NO_CMD_CMPL(ctrl) ||
1029 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1030 ctrl->no_cmd_complete = 1;
08e7a7d2 1031
f18e9625 1032 /* Check if Data Link Layer Link Active Reporting is implemented */
322162a7 1033 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
f18e9625
KK		 1034 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1035 goto abort_ctrl;
1036 }
322162a7 1037 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
f18e9625
KK		 1038 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1039 ctrl->link_active_reporting = 1;
1040 }
1041
c4635eb0 1042 /* Clear all remaining event bits in Slot Status register */
322162a7 1043 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
c4635eb0 1044 goto abort_ctrl;
08e7a7d2 1045
c4635eb0
KK		 1046 /* Disable sotfware notification */
1047 pcie_disable_notification(ctrl);
ecdde939
ML		 1048
1049 /*
1050 * If this is the first controller to be initialized,
1051 * initialize the pciehp work queue
1052 */
1053 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1054 pciehp_wq = create_singlethread_workqueue("pciehpd");
c4635eb0
KK		 1055 if (!pciehp_wq)
1056 goto abort_ctrl;
ecdde939
ML		 1057 }
1058
7f2feec1
TI		 1059 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1060 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1061 pdev->subsystem_device);
c4635eb0
KK		 1062
1063 if (pcie_init_slot(ctrl))
1064 goto abort_ctrl;
2aeeef11 1065
c4635eb0
KK		 1066 return ctrl;
1067
c4635eb0
KK		 1068abort_ctrl:
1069 kfree(ctrl);
08e7a7d2 1070abort:
c4635eb0
KK		 1071 return NULL;
1072}
1073
1074void pcie_release_ctrl(struct controller *ctrl)
1075{
1076 pcie_shutdown_notification(ctrl);
1077 pcie_cleanup_slot(ctrl);
1078 /*
1079 * If this is the last controller to be released, destroy the
1080 * pciehp work queue
1081 */
1082 if (atomic_dec_and_test(&pciehp_num_controllers))
1083 destroy_workqueue(pciehp_wq);
1084 kfree(ctrl);
08e7a7d2 1085}
Linux kernel - Deliverables
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