Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
a0f018da KK |
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
45 | { | |
385e2491 | 46 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 47 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
48 | } |
49 | ||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
51 | { | |
385e2491 | 52 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 53 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
54 | } |
55 | ||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
57 | { | |
385e2491 | 58 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 59 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
60 | } |
61 | ||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
63 | { | |
385e2491 | 64 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 65 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 66 | } |
1da177e4 | 67 | |
1da177e4 LT |
68 | /* Power Control Command */ |
69 | #define POWER_ON 0 | |
322162a7 | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 71 | |
48fe3915 KK |
72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
73 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
74 | |
75 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 76 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 77 | { |
48fe3915 | 78 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 79 | |
1da177e4 | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 81 | pcie_isr(0, ctrl); |
1da177e4 | 82 | |
48fe3915 | 83 | init_timer(&ctrl->poll_timer); |
1da177e4 | 84 | if (!pciehp_poll_time) |
40730d10 | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 86 | |
48fe3915 | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
88 | } |
89 | ||
90 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 92 | { |
48fe3915 KK |
93 | /* Clamp to sane value */ |
94 | if ((sec <= 0) || (sec > 60)) | |
95 | sec = 2; | |
96 | ||
97 | ctrl->poll_timer.function = &int_poll_timeout; | |
98 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
99 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
100 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
101 | } |
102 | ||
2aeeef11 KK |
103 | static inline int pciehp_request_irq(struct controller *ctrl) |
104 | { | |
f7a10e32 | 105 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
106 | |
107 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
108 | if (pciehp_poll_mode) { | |
109 | init_timer(&ctrl->poll_timer); | |
110 | start_int_poll_timer(ctrl, 10); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | /* Installs the interrupt handler */ | |
115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
116 | if (retval) | |
7f2feec1 TI |
117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
118 | irq); | |
2aeeef11 KK |
119 | return retval; |
120 | } | |
121 | ||
122 | static inline void pciehp_free_irq(struct controller *ctrl) | |
123 | { | |
124 | if (pciehp_poll_mode) | |
125 | del_timer_sync(&ctrl->poll_timer); | |
126 | else | |
f7a10e32 | 127 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
128 | } |
129 | ||
563f1190 | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
131 | { |
132 | u16 slot_status; | |
322162a7 | 133 | int err, timeout = 1000; |
6592e02a | 134 | |
322162a7 KK |
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
138 | return 1; | |
820943b6 | 139 | } |
a5827f40 | 140 | while (timeout > 0) { |
66618bad KK |
141 | msleep(10); |
142 | timeout -= 10; | |
322162a7 KK |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
146 | return 1; | |
820943b6 | 147 | } |
6592e02a KK |
148 | } |
149 | return 0; /* timeout */ | |
6592e02a KK |
150 | } |
151 | ||
563f1190 | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 153 | { |
262303fe KK |
154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
155 | unsigned long timeout = msecs_to_jiffies(msecs); | |
156 | int rc; | |
157 | ||
6592e02a KK |
158 | if (poll) |
159 | rc = pcie_poll_cmd(ctrl); | |
160 | else | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 162 | if (!rc) |
7f2feec1 | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
164 | } |
165 | ||
f4778364 KK |
166 | /** |
167 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 168 | * @ctrl: controller to which the command is issued |
f4778364 KK |
169 | * @cmd: command value written to slot control register |
170 | * @mask: bitmask of slot control register to be modified | |
171 | */ | |
c27fb883 | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 173 | { |
1da177e4 LT |
174 | int retval = 0; |
175 | u16 slot_status; | |
f4778364 | 176 | u16 slot_ctrl; |
1da177e4 | 177 | |
44ef4cef KK |
178 | mutex_lock(&ctrl->ctrl_lock); |
179 | ||
322162a7 | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 181 | if (retval) { |
7f2feec1 TI |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | |
44ef4cef | 184 | goto out; |
a0f018da KK |
185 | } |
186 | ||
322162a7 | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
188 | if (!ctrl->no_cmd_complete) { |
189 | /* | |
190 | * After 1 sec and CMD_COMPLETED still not set, just | |
191 | * proceed forward to issue the next command according | |
192 | * to spec. Just print out the error message. | |
193 | */ | |
18b341b7 | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
195 | } else if (!NO_CMD_CMPL(ctrl)) { |
196 | /* | |
197 | * This controller semms to notify of command completed | |
198 | * event even though it supports none of power | |
199 | * controller, attention led, power led and EMI. | |
200 | */ | |
18b341b7 TI |
201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
202 | "wait for command completed event.\n"); | |
5808639b KK |
203 | ctrl->no_cmd_complete = 0; |
204 | } else { | |
18b341b7 TI |
205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
206 | "the controller is broken.\n"); | |
5808639b | 207 | } |
1da177e4 LT |
208 | } |
209 | ||
322162a7 | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 211 | if (retval) { |
7f2feec1 | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 213 | goto out; |
1da177e4 | 214 | } |
1da177e4 | 215 | |
f4778364 | 216 | slot_ctrl &= ~mask; |
b7aa1f16 | 217 | slot_ctrl |= (cmd & mask); |
f4778364 | 218 | ctrl->cmd_busy = 1; |
2d32a9ae | 219 | smp_mb(); |
322162a7 | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 221 | if (retval) |
18b341b7 | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 223 | |
44ef4cef KK |
224 | /* |
225 | * Wait for command completion. | |
226 | */ | |
6592e02a KK |
227 | if (!retval && !ctrl->no_cmd_complete) { |
228 | int poll = 0; | |
229 | /* | |
230 | * if hotplug interrupt is not enabled or command | |
231 | * completed interrupt is not enabled, we need to poll | |
232 | * command completed event. | |
233 | */ | |
322162a7 KK |
234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 236 | poll = 1; |
d737bdc1 | 237 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 238 | } |
44ef4cef KK |
239 | out: |
240 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
241 | return retval; |
242 | } | |
243 | ||
4e2ce405 | 244 | static bool check_link_active(struct controller *ctrl) |
f18e9625 | 245 | { |
4e2ce405 YL |
246 | bool ret = false; |
247 | u16 lnk_status; | |
f18e9625 | 248 | |
4e2ce405 YL |
249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status)) |
250 | return ret; | |
251 | ||
252 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
253 | ||
254 | if (ret) | |
255 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
256 | ||
257 | return ret; | |
f18e9625 KK |
258 | } |
259 | ||
260 | static void pcie_wait_link_active(struct controller *ctrl) | |
261 | { | |
262 | int timeout = 1000; | |
263 | ||
264 | if (check_link_active(ctrl)) | |
265 | return; | |
266 | while (timeout > 0) { | |
267 | msleep(10); | |
268 | timeout -= 10; | |
269 | if (check_link_active(ctrl)) | |
270 | return; | |
271 | } | |
272 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
273 | } | |
274 | ||
2f5d8e4f YL |
275 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
276 | { | |
277 | u32 l; | |
278 | int count = 0; | |
279 | int delay = 1000, step = 20; | |
280 | bool found = false; | |
281 | ||
282 | do { | |
283 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
284 | count++; | |
285 | ||
286 | if (found) | |
287 | break; | |
288 | ||
289 | msleep(step); | |
290 | delay -= step; | |
291 | } while (delay > 0); | |
292 | ||
293 | if (count > 1 && pciehp_debug) | |
294 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
295 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
296 | PCI_FUNC(devfn), count, step, l); | |
297 | ||
298 | return found; | |
299 | } | |
300 | ||
82a9e79e | 301 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 302 | { |
1da177e4 LT |
303 | u16 lnk_status; |
304 | int retval = 0; | |
2f5d8e4f | 305 | bool found = false; |
1da177e4 | 306 | |
f18e9625 KK |
307 | /* |
308 | * Data Link Layer Link Active Reporting must be capable for | |
309 | * hot-plug capable downstream port. But old controller might | |
310 | * not implement it. In this case, we wait for 1000 ms. | |
311 | */ | |
0cab0841 | 312 | if (ctrl->link_active_reporting) |
f18e9625 | 313 | pcie_wait_link_active(ctrl); |
0cab0841 | 314 | else |
f18e9625 KK |
315 | msleep(1000); |
316 | ||
2f5d8e4f YL |
317 | /* wait 100ms before read pci conf, and try in 1s */ |
318 | msleep(100); | |
319 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
320 | PCI_DEVFN(0, 0)); | |
0027cb3e | 321 | |
322162a7 | 322 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 323 | if (retval) { |
18b341b7 | 324 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
325 | return retval; |
326 | } | |
327 | ||
7f2feec1 | 328 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
329 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
330 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 331 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
332 | retval = -1; |
333 | return retval; | |
334 | } | |
335 | ||
fdbd3ce9 YL |
336 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
337 | ||
2f5d8e4f YL |
338 | if (!found && !retval) |
339 | retval = -1; | |
340 | ||
1da177e4 LT |
341 | return retval; |
342 | } | |
343 | ||
82a9e79e | 344 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 345 | { |
48fe3915 | 346 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
347 | u16 slot_ctrl; |
348 | u8 atten_led_state; | |
349 | int retval = 0; | |
1da177e4 | 350 | |
322162a7 | 351 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 352 | if (retval) { |
7f2feec1 | 353 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
354 | return retval; |
355 | } | |
356 | ||
1518c17a KK |
357 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
358 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 359 | |
322162a7 | 360 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
361 | |
362 | switch (atten_led_state) { | |
363 | case 0: | |
364 | *status = 0xFF; /* Reserved */ | |
365 | break; | |
366 | case 1: | |
367 | *status = 1; /* On */ | |
368 | break; | |
369 | case 2: | |
370 | *status = 2; /* Blink */ | |
371 | break; | |
372 | case 3: | |
373 | *status = 0; /* Off */ | |
374 | break; | |
375 | default: | |
376 | *status = 0xFF; | |
377 | break; | |
378 | } | |
379 | ||
1da177e4 LT |
380 | return 0; |
381 | } | |
382 | ||
82a9e79e | 383 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 384 | { |
48fe3915 | 385 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
386 | u16 slot_ctrl; |
387 | u8 pwr_state; | |
388 | int retval = 0; | |
1da177e4 | 389 | |
322162a7 | 390 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 391 | if (retval) { |
7f2feec1 | 392 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
393 | return retval; |
394 | } | |
1518c17a KK |
395 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
396 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 397 | |
322162a7 | 398 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
399 | |
400 | switch (pwr_state) { | |
401 | case 0: | |
402 | *status = 1; | |
403 | break; | |
404 | case 1: | |
71ad556d | 405 | *status = 0; |
1da177e4 LT |
406 | break; |
407 | default: | |
408 | *status = 0xFF; | |
409 | break; | |
410 | } | |
411 | ||
1da177e4 LT |
412 | return retval; |
413 | } | |
414 | ||
82a9e79e | 415 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 416 | { |
48fe3915 | 417 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 418 | u16 slot_status; |
322162a7 | 419 | int retval; |
1da177e4 | 420 | |
322162a7 | 421 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 422 | if (retval) { |
7f2feec1 TI |
423 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
424 | __func__); | |
1da177e4 LT |
425 | return retval; |
426 | } | |
322162a7 | 427 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
428 | return 0; |
429 | } | |
430 | ||
82a9e79e | 431 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 432 | { |
48fe3915 | 433 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 434 | u16 slot_status; |
322162a7 | 435 | int retval; |
1da177e4 | 436 | |
322162a7 | 437 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 438 | if (retval) { |
7f2feec1 TI |
439 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
440 | __func__); | |
1da177e4 LT |
441 | return retval; |
442 | } | |
322162a7 | 443 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
444 | return 0; |
445 | } | |
446 | ||
82a9e79e | 447 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 448 | { |
48fe3915 | 449 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 450 | u16 slot_status; |
322162a7 | 451 | int retval; |
1da177e4 | 452 | |
322162a7 | 453 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 454 | if (retval) { |
18b341b7 | 455 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
456 | return retval; |
457 | } | |
322162a7 | 458 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
459 | } |
460 | ||
82a9e79e | 461 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 462 | { |
48fe3915 | 463 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
464 | u16 slot_cmd; |
465 | u16 cmd_mask; | |
1da177e4 | 466 | |
322162a7 | 467 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 468 | switch (value) { |
445f7985 KK |
469 | case 0 : /* turn off */ |
470 | slot_cmd = 0x00C0; | |
471 | break; | |
472 | case 1: /* turn on */ | |
473 | slot_cmd = 0x0040; | |
474 | break; | |
475 | case 2: /* turn blink */ | |
476 | slot_cmd = 0x0080; | |
477 | break; | |
478 | default: | |
479 | return -EINVAL; | |
1da177e4 | 480 | } |
1518c17a KK |
481 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
482 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 483 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
484 | } |
485 | ||
82a9e79e | 486 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 487 | { |
48fe3915 | 488 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 489 | u16 slot_cmd; |
f4778364 | 490 | u16 cmd_mask; |
71ad556d | 491 | |
f4778364 | 492 | slot_cmd = 0x0100; |
322162a7 | 493 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 494 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
495 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
496 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
497 | } |
498 | ||
82a9e79e | 499 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 500 | { |
48fe3915 | 501 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 502 | u16 slot_cmd; |
f4778364 | 503 | u16 cmd_mask; |
1da177e4 | 504 | |
f4778364 | 505 | slot_cmd = 0x0300; |
322162a7 | 506 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 507 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
508 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
509 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
510 | } |
511 | ||
82a9e79e | 512 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 513 | { |
48fe3915 | 514 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 515 | u16 slot_cmd; |
f4778364 | 516 | u16 cmd_mask; |
71ad556d | 517 | |
f4778364 | 518 | slot_cmd = 0x0200; |
322162a7 | 519 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 520 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
521 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
522 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
523 | } |
524 | ||
82a9e79e | 525 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 526 | { |
48fe3915 | 527 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 528 | u16 slot_cmd; |
f4778364 KK |
529 | u16 cmd_mask; |
530 | u16 slot_status; | |
1da177e4 LT |
531 | int retval = 0; |
532 | ||
5a49f203 | 533 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 534 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 535 | if (retval) { |
7f2feec1 TI |
536 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
537 | __func__); | |
a0f018da KK |
538 | return retval; |
539 | } | |
322162a7 | 540 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 541 | if (slot_status) { |
322162a7 | 542 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 543 | if (retval) { |
7f2feec1 TI |
544 | ctrl_err(ctrl, |
545 | "%s: Cannot write to SLOTSTATUS register\n", | |
546 | __func__); | |
a0f018da KK |
547 | return retval; |
548 | } | |
549 | } | |
5651c48c | 550 | ctrl->power_fault_detected = 0; |
1da177e4 | 551 | |
f4778364 | 552 | slot_cmd = POWER_ON; |
322162a7 | 553 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 554 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 555 | if (retval) { |
18b341b7 | 556 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 557 | return retval; |
1da177e4 | 558 | } |
1518c17a KK |
559 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
560 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 561 | |
1da177e4 LT |
562 | return retval; |
563 | } | |
564 | ||
82a9e79e | 565 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 566 | { |
48fe3915 | 567 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 568 | u16 slot_cmd; |
f4778364 | 569 | u16 cmd_mask; |
3c3a1b17 | 570 | int retval; |
f1050a35 | 571 | |
f4778364 | 572 | slot_cmd = POWER_OFF; |
322162a7 | 573 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 574 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 575 | if (retval) { |
18b341b7 | 576 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 577 | return retval; |
1da177e4 | 578 | } |
1518c17a KK |
579 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
580 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 581 | return 0; |
1da177e4 LT |
582 | } |
583 | ||
48fe3915 | 584 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 585 | { |
48fe3915 | 586 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 587 | struct slot *slot = ctrl->slot; |
c6b069e9 | 588 | u16 detected, intr_loc; |
1da177e4 | 589 | |
c6b069e9 KK |
590 | /* |
591 | * In order to guarantee that all interrupt events are | |
592 | * serviced, we need to re-inspect Slot Status register after | |
593 | * clearing what is presumed to be the last pending interrupt. | |
594 | */ | |
595 | intr_loc = 0; | |
596 | do { | |
322162a7 | 597 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
598 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
599 | __func__); | |
1da177e4 LT |
600 | return IRQ_NONE; |
601 | } | |
602 | ||
322162a7 KK |
603 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
604 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
605 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 606 | detected &= ~intr_loc; |
c6b069e9 KK |
607 | intr_loc |= detected; |
608 | if (!intr_loc) | |
1da177e4 | 609 | return IRQ_NONE; |
81b840cd | 610 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
611 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
612 | __func__); | |
1da177e4 LT |
613 | return IRQ_NONE; |
614 | } | |
c6b069e9 | 615 | } while (detected); |
71ad556d | 616 | |
7f2feec1 | 617 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 618 | |
c6b069e9 | 619 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 620 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 621 | ctrl->cmd_busy = 0; |
2d32a9ae | 622 | smp_mb(); |
d737bdc1 | 623 | wake_up(&ctrl->queue); |
1da177e4 LT |
624 | } |
625 | ||
322162a7 | 626 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
627 | return IRQ_HANDLED; |
628 | ||
c6b069e9 | 629 | /* Check MRL Sensor Changed */ |
322162a7 | 630 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 631 | pciehp_handle_switch_change(slot); |
48fe3915 | 632 | |
c6b069e9 | 633 | /* Check Attention Button Pressed */ |
322162a7 | 634 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 635 | pciehp_handle_attention_button(slot); |
48fe3915 | 636 | |
c6b069e9 | 637 | /* Check Presence Detect Changed */ |
322162a7 | 638 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 639 | pciehp_handle_presence_change(slot); |
48fe3915 | 640 | |
c6b069e9 | 641 | /* Check Power Fault Detected */ |
99f0169c KK |
642 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
643 | ctrl->power_fault_detected = 1; | |
8720d27d | 644 | pciehp_handle_power_fault(slot); |
99f0169c | 645 | } |
1da177e4 LT |
646 | return IRQ_HANDLED; |
647 | } | |
648 | ||
82a9e79e | 649 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 650 | enum pcie_link_width *value) |
1da177e4 | 651 | { |
48fe3915 | 652 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
653 | enum pcie_link_width lnk_wdth; |
654 | u32 lnk_cap; | |
655 | int retval = 0; | |
656 | ||
322162a7 | 657 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 658 | if (retval) { |
7f2feec1 | 659 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
660 | return retval; |
661 | } | |
662 | ||
322162a7 | 663 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
664 | case 0: |
665 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
666 | break; | |
667 | case 1: | |
668 | lnk_wdth = PCIE_LNK_X1; | |
669 | break; | |
670 | case 2: | |
671 | lnk_wdth = PCIE_LNK_X2; | |
672 | break; | |
673 | case 4: | |
674 | lnk_wdth = PCIE_LNK_X4; | |
675 | break; | |
676 | case 8: | |
677 | lnk_wdth = PCIE_LNK_X8; | |
678 | break; | |
679 | case 12: | |
680 | lnk_wdth = PCIE_LNK_X12; | |
681 | break; | |
682 | case 16: | |
683 | lnk_wdth = PCIE_LNK_X16; | |
684 | break; | |
685 | case 32: | |
686 | lnk_wdth = PCIE_LNK_X32; | |
687 | break; | |
688 | default: | |
689 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
690 | break; | |
691 | } | |
692 | ||
693 | *value = lnk_wdth; | |
7f2feec1 | 694 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 695 | |
1da177e4 LT |
696 | return retval; |
697 | } | |
698 | ||
82a9e79e | 699 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 700 | enum pcie_link_width *value) |
1da177e4 | 701 | { |
48fe3915 | 702 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
703 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
704 | int retval = 0; | |
705 | u16 lnk_status; | |
706 | ||
322162a7 | 707 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 708 | if (retval) { |
7f2feec1 TI |
709 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
710 | __func__); | |
1da177e4 LT |
711 | return retval; |
712 | } | |
71ad556d | 713 | |
322162a7 | 714 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
715 | case 0: |
716 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
717 | break; | |
718 | case 1: | |
719 | lnk_wdth = PCIE_LNK_X1; | |
720 | break; | |
721 | case 2: | |
722 | lnk_wdth = PCIE_LNK_X2; | |
723 | break; | |
724 | case 4: | |
725 | lnk_wdth = PCIE_LNK_X4; | |
726 | break; | |
727 | case 8: | |
728 | lnk_wdth = PCIE_LNK_X8; | |
729 | break; | |
730 | case 12: | |
731 | lnk_wdth = PCIE_LNK_X12; | |
732 | break; | |
733 | case 16: | |
734 | lnk_wdth = PCIE_LNK_X16; | |
735 | break; | |
736 | case 32: | |
737 | lnk_wdth = PCIE_LNK_X32; | |
738 | break; | |
739 | default: | |
740 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
741 | break; | |
742 | } | |
743 | ||
744 | *value = lnk_wdth; | |
7f2feec1 | 745 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 746 | |
1da177e4 LT |
747 | return retval; |
748 | } | |
749 | ||
c4635eb0 | 750 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 751 | { |
c27fb883 | 752 | u16 cmd, mask; |
1da177e4 | 753 | |
5651c48c KK |
754 | /* |
755 | * TBD: Power fault detected software notification support. | |
756 | * | |
757 | * Power fault detected software notification is not enabled | |
758 | * now, because it caused power fault detected interrupt storm | |
759 | * on some machines. On those machines, power fault detected | |
760 | * bit in the slot status register was set again immediately | |
761 | * when it is cleared in the interrupt service routine, and | |
762 | * next power fault detected interrupt was notified again. | |
763 | */ | |
322162a7 | 764 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 765 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 766 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 767 | if (MRL_SENS(ctrl)) |
322162a7 | 768 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 769 | if (!pciehp_poll_mode) |
322162a7 | 770 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 771 | |
322162a7 KK |
772 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
773 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
774 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
775 | |
776 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 777 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 778 | return -1; |
1da177e4 | 779 | } |
c4635eb0 KK |
780 | return 0; |
781 | } | |
782 | ||
783 | static void pcie_disable_notification(struct controller *ctrl) | |
784 | { | |
785 | u16 mask; | |
322162a7 KK |
786 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
787 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
788 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
789 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 790 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 791 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
792 | } |
793 | ||
dbc7e1e5 | 794 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
795 | { |
796 | if (pciehp_request_irq(ctrl)) | |
797 | return -1; | |
798 | if (pcie_enable_notification(ctrl)) { | |
799 | pciehp_free_irq(ctrl); | |
800 | return -1; | |
801 | } | |
dbc7e1e5 | 802 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
803 | return 0; |
804 | } | |
805 | ||
806 | static void pcie_shutdown_notification(struct controller *ctrl) | |
807 | { | |
dbc7e1e5 EB |
808 | if (ctrl->notification_enabled) { |
809 | pcie_disable_notification(ctrl); | |
810 | pciehp_free_irq(ctrl); | |
811 | ctrl->notification_enabled = 0; | |
812 | } | |
c4635eb0 KK |
813 | } |
814 | ||
c4635eb0 KK |
815 | static int pcie_init_slot(struct controller *ctrl) |
816 | { | |
817 | struct slot *slot; | |
818 | ||
819 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
820 | if (!slot) | |
821 | return -ENOMEM; | |
822 | ||
c4635eb0 | 823 | slot->ctrl = ctrl; |
c4635eb0 KK |
824 | mutex_init(&slot->lock); |
825 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 826 | ctrl->slot = slot; |
1da177e4 | 827 | return 0; |
1da177e4 | 828 | } |
08e7a7d2 | 829 | |
c4635eb0 KK |
830 | static void pcie_cleanup_slot(struct controller *ctrl) |
831 | { | |
8720d27d | 832 | struct slot *slot = ctrl->slot; |
c4635eb0 | 833 | cancel_delayed_work(&slot->work); |
c4635eb0 KK |
834 | flush_workqueue(pciehp_wq); |
835 | kfree(slot); | |
836 | } | |
837 | ||
2aeeef11 | 838 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 839 | { |
2aeeef11 KK |
840 | int i; |
841 | u16 reg16; | |
385e2491 | 842 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 843 | |
2aeeef11 KK |
844 | if (!pciehp_debug) |
845 | return; | |
08e7a7d2 | 846 | |
7f2feec1 TI |
847 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
848 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
849 | pci_name(pdev), pdev->irq); | |
850 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
851 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
852 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
853 | pdev->subsystem_device); | |
854 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
855 | pdev->subsystem_vendor); | |
1518c17a KK |
856 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
857 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
858 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
859 | if (!pci_resource_len(pdev, i)) | |
860 | continue; | |
e1944c6b BH |
861 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
862 | i, &pdev->resource[i]); | |
08e7a7d2 | 863 | } |
7f2feec1 | 864 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 865 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
866 | ctrl_info(ctrl, " Attention Button : %3s\n", |
867 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
868 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
869 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
870 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
871 | MRL_SENS(ctrl) ? "yes" : "no"); | |
872 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
873 | ATTN_LED(ctrl) ? "yes" : "no"); | |
874 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
875 | PWR_LED(ctrl) ? "yes" : "no"); | |
876 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
877 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
878 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
879 | EMI(ctrl) ? "yes" : "no"); | |
880 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
881 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 882 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 883 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 884 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 885 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 886 | } |
08e7a7d2 | 887 | |
c4635eb0 | 888 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 889 | { |
c4635eb0 | 890 | struct controller *ctrl; |
f18e9625 | 891 | u32 slot_cap, link_cap; |
2aeeef11 | 892 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 893 | |
c4635eb0 KK |
894 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
895 | if (!ctrl) { | |
18b341b7 | 896 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
897 | goto abort; |
898 | } | |
f7a10e32 | 899 | ctrl->pcie = dev; |
1518c17a | 900 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 901 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 902 | goto abort_ctrl; |
08e7a7d2 | 903 | } |
322162a7 | 904 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 905 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 906 | goto abort_ctrl; |
08e7a7d2 | 907 | } |
08e7a7d2 | 908 | |
2aeeef11 | 909 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 910 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 911 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 912 | dbg_ctrl(ctrl); |
5808639b KK |
913 | /* |
914 | * Controller doesn't notify of command completion if the "No | |
915 | * Command Completed Support" bit is set in Slot Capability | |
916 | * register or the controller supports none of power | |
917 | * controller, attention led, power led and EMI. | |
918 | */ | |
919 | if (NO_CMD_CMPL(ctrl) || | |
920 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
921 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 922 | |
f18e9625 | 923 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 924 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
925 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
926 | goto abort_ctrl; | |
927 | } | |
322162a7 | 928 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
929 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
930 | ctrl->link_active_reporting = 1; | |
931 | } | |
932 | ||
c4635eb0 | 933 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 934 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 935 | goto abort_ctrl; |
08e7a7d2 | 936 | |
c4635eb0 KK |
937 | /* Disable sotfware notification */ |
938 | pcie_disable_notification(ctrl); | |
ecdde939 | 939 | |
7f2feec1 TI |
940 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
941 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
942 | pdev->subsystem_device); | |
c4635eb0 KK |
943 | |
944 | if (pcie_init_slot(ctrl)) | |
945 | goto abort_ctrl; | |
2aeeef11 | 946 | |
c4635eb0 KK |
947 | return ctrl; |
948 | ||
c4635eb0 KK |
949 | abort_ctrl: |
950 | kfree(ctrl); | |
08e7a7d2 | 951 | abort: |
c4635eb0 KK |
952 | return NULL; |
953 | } | |
954 | ||
82a9e79e | 955 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
956 | { |
957 | pcie_shutdown_notification(ctrl); | |
958 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 959 | kfree(ctrl); |
08e7a7d2 | 960 | } |