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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
2aeeef11 KK |
224 | static inline int pciehp_request_irq(struct controller *ctrl) |
225 | { | |
226 | int retval, irq = ctrl->pci_dev->irq; | |
227 | ||
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
229 | if (pciehp_poll_mode) { | |
230 | init_timer(&ctrl->poll_timer); | |
231 | start_int_poll_timer(ctrl, 10); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /* Installs the interrupt handler */ | |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
237 | if (retval) | |
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | |
239 | return retval; | |
240 | } | |
241 | ||
242 | static inline void pciehp_free_irq(struct controller *ctrl) | |
243 | { | |
244 | if (pciehp_poll_mode) | |
245 | del_timer_sync(&ctrl->poll_timer); | |
246 | else | |
247 | free_irq(ctrl->pci_dev->irq, ctrl); | |
248 | } | |
249 | ||
6592e02a KK |
250 | static inline int pcie_poll_cmd(struct controller *ctrl) |
251 | { | |
252 | u16 slot_status; | |
253 | int timeout = 1000; | |
254 | ||
820943b6 KK |
255 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { |
256 | if (slot_status & CMD_COMPLETED) { | |
257 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
258 | return 1; | |
259 | } | |
260 | } | |
261 | while (timeout > 1000) { | |
66618bad KK |
262 | msleep(10); |
263 | timeout -= 10; | |
820943b6 KK |
264 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { |
265 | if (slot_status & CMD_COMPLETED) { | |
266 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
267 | return 1; | |
268 | } | |
269 | } | |
6592e02a KK |
270 | } |
271 | return 0; /* timeout */ | |
6592e02a KK |
272 | } |
273 | ||
d737bdc1 | 274 | static inline void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 275 | { |
262303fe KK |
276 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
277 | unsigned long timeout = msecs_to_jiffies(msecs); | |
278 | int rc; | |
279 | ||
6592e02a KK |
280 | if (poll) |
281 | rc = pcie_poll_cmd(ctrl); | |
282 | else | |
d737bdc1 | 283 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe KK |
284 | if (!rc) |
285 | dbg("Command not completed in 1000 msec\n"); | |
44ef4cef KK |
286 | } |
287 | ||
f4778364 KK |
288 | /** |
289 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 290 | * @ctrl: controller to which the command is issued |
f4778364 KK |
291 | * @cmd: command value written to slot control register |
292 | * @mask: bitmask of slot control register to be modified | |
293 | */ | |
c27fb883 | 294 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 295 | { |
1da177e4 LT |
296 | int retval = 0; |
297 | u16 slot_status; | |
f4778364 | 298 | u16 slot_ctrl; |
1da177e4 | 299 | |
44ef4cef KK |
300 | mutex_lock(&ctrl->ctrl_lock); |
301 | ||
a0f018da | 302 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 303 | if (retval) { |
66bef8c0 | 304 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
44ef4cef | 305 | goto out; |
a0f018da KK |
306 | } |
307 | ||
5808639b KK |
308 | if (slot_status & CMD_COMPLETED) { |
309 | if (!ctrl->no_cmd_complete) { | |
310 | /* | |
311 | * After 1 sec and CMD_COMPLETED still not set, just | |
312 | * proceed forward to issue the next command according | |
313 | * to spec. Just print out the error message. | |
314 | */ | |
315 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
316 | __func__); | |
317 | } else if (!NO_CMD_CMPL(ctrl)) { | |
318 | /* | |
319 | * This controller semms to notify of command completed | |
320 | * event even though it supports none of power | |
321 | * controller, attention led, power led and EMI. | |
322 | */ | |
323 | dbg("%s: Unexpected CMD_COMPLETED. Need to wait for " | |
324 | "command completed event.\n", __func__); | |
325 | ctrl->no_cmd_complete = 0; | |
326 | } else { | |
327 | dbg("%s: Unexpected CMD_COMPLETED. Maybe the " | |
328 | "controller is broken.\n", __func__); | |
329 | } | |
1da177e4 LT |
330 | } |
331 | ||
f4778364 | 332 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 333 | if (retval) { |
66bef8c0 | 334 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 335 | goto out; |
1da177e4 | 336 | } |
1da177e4 | 337 | |
f4778364 | 338 | slot_ctrl &= ~mask; |
b7aa1f16 KK |
339 | slot_ctrl |= (cmd & mask); |
340 | /* Don't enable command completed if caller is changing it. */ | |
341 | if (!(mask & CMD_CMPL_INTR_ENABLE)) | |
342 | slot_ctrl |= CMD_CMPL_INTR_ENABLE; | |
f4778364 KK |
343 | |
344 | ctrl->cmd_busy = 1; | |
2d32a9ae | 345 | smp_mb(); |
f4778364 KK |
346 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
347 | if (retval) | |
66bef8c0 | 348 | err("%s: Cannot write to SLOTCTRL register\n", __func__); |
f4778364 | 349 | |
44ef4cef KK |
350 | /* |
351 | * Wait for command completion. | |
352 | */ | |
6592e02a KK |
353 | if (!retval && !ctrl->no_cmd_complete) { |
354 | int poll = 0; | |
355 | /* | |
356 | * if hotplug interrupt is not enabled or command | |
357 | * completed interrupt is not enabled, we need to poll | |
358 | * command completed event. | |
359 | */ | |
360 | if (!(slot_ctrl & HP_INTR_ENABLE) || | |
361 | !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) | |
362 | poll = 1; | |
d737bdc1 | 363 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 364 | } |
44ef4cef KK |
365 | out: |
366 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
367 | return retval; |
368 | } | |
369 | ||
370 | static int hpc_check_lnk_status(struct controller *ctrl) | |
371 | { | |
1da177e4 LT |
372 | u16 lnk_status; |
373 | int retval = 0; | |
374 | ||
a0f018da | 375 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 376 | if (retval) { |
66bef8c0 | 377 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
378 | return retval; |
379 | } | |
380 | ||
66bef8c0 | 381 | dbg("%s: lnk_status = %x\n", __func__, lnk_status); |
71ad556d | 382 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 | 383 | !(lnk_status & NEG_LINK_WD)) { |
66bef8c0 | 384 | err("%s : Link Training Error occurs \n", __func__); |
1da177e4 LT |
385 | retval = -1; |
386 | return retval; | |
387 | } | |
388 | ||
1da177e4 LT |
389 | return retval; |
390 | } | |
391 | ||
1da177e4 LT |
392 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
393 | { | |
48fe3915 | 394 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
395 | u16 slot_ctrl; |
396 | u8 atten_led_state; | |
397 | int retval = 0; | |
1da177e4 | 398 | |
a0f018da | 399 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 400 | if (retval) { |
66bef8c0 | 401 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
402 | return retval; |
403 | } | |
404 | ||
a0f018da | 405 | dbg("%s: SLOTCTRL %x, value read %x\n", |
66bef8c0 | 406 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
407 | |
408 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
409 | ||
410 | switch (atten_led_state) { | |
411 | case 0: | |
412 | *status = 0xFF; /* Reserved */ | |
413 | break; | |
414 | case 1: | |
415 | *status = 1; /* On */ | |
416 | break; | |
417 | case 2: | |
418 | *status = 2; /* Blink */ | |
419 | break; | |
420 | case 3: | |
421 | *status = 0; /* Off */ | |
422 | break; | |
423 | default: | |
424 | *status = 0xFF; | |
425 | break; | |
426 | } | |
427 | ||
1da177e4 LT |
428 | return 0; |
429 | } | |
430 | ||
48fe3915 | 431 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 432 | { |
48fe3915 | 433 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
434 | u16 slot_ctrl; |
435 | u8 pwr_state; | |
436 | int retval = 0; | |
1da177e4 | 437 | |
a0f018da | 438 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 439 | if (retval) { |
66bef8c0 | 440 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
441 | return retval; |
442 | } | |
a0f018da | 443 | dbg("%s: SLOTCTRL %x value read %x\n", |
66bef8c0 | 444 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
445 | |
446 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
447 | ||
448 | switch (pwr_state) { | |
449 | case 0: | |
450 | *status = 1; | |
451 | break; | |
452 | case 1: | |
71ad556d | 453 | *status = 0; |
1da177e4 LT |
454 | break; |
455 | default: | |
456 | *status = 0xFF; | |
457 | break; | |
458 | } | |
459 | ||
1da177e4 LT |
460 | return retval; |
461 | } | |
462 | ||
1da177e4 LT |
463 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
464 | { | |
48fe3915 | 465 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
466 | u16 slot_status; |
467 | int retval = 0; | |
468 | ||
a0f018da | 469 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 470 | if (retval) { |
66bef8c0 | 471 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
472 | return retval; |
473 | } | |
474 | ||
71ad556d | 475 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 476 | |
1da177e4 LT |
477 | return 0; |
478 | } | |
479 | ||
480 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
481 | { | |
48fe3915 | 482 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
483 | u16 slot_status; |
484 | u8 card_state; | |
485 | int retval = 0; | |
486 | ||
a0f018da | 487 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 488 | if (retval) { |
66bef8c0 | 489 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
490 | return retval; |
491 | } | |
492 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
493 | *status = (card_state == 1) ? 1 : 0; | |
494 | ||
1da177e4 LT |
495 | return 0; |
496 | } | |
497 | ||
48fe3915 | 498 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 499 | { |
48fe3915 | 500 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
501 | u16 slot_status; |
502 | u8 pwr_fault; | |
503 | int retval = 0; | |
1da177e4 | 504 | |
a0f018da | 505 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 506 | if (retval) { |
66bef8c0 | 507 | err("%s: Cannot check for power fault\n", __func__); |
1da177e4 LT |
508 | return retval; |
509 | } | |
510 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 511 | |
8239def1 | 512 | return pwr_fault; |
1da177e4 LT |
513 | } |
514 | ||
34d03419 KCA |
515 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
516 | { | |
517 | struct controller *ctrl = slot->ctrl; | |
518 | u16 slot_status; | |
519 | int retval = 0; | |
520 | ||
34d03419 KCA |
521 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
522 | if (retval) { | |
66bef8c0 | 523 | err("%s : Cannot check EMI status\n", __func__); |
34d03419 KCA |
524 | return retval; |
525 | } | |
526 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
527 | ||
34d03419 KCA |
528 | return retval; |
529 | } | |
530 | ||
531 | static int hpc_toggle_emi(struct slot *slot) | |
532 | { | |
f4778364 KK |
533 | u16 slot_cmd; |
534 | u16 cmd_mask; | |
535 | int rc; | |
34d03419 | 536 | |
f4778364 KK |
537 | slot_cmd = EMI_CTRL; |
538 | cmd_mask = EMI_CTRL; | |
c27fb883 | 539 | rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); |
34d03419 | 540 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 541 | |
34d03419 KCA |
542 | return rc; |
543 | } | |
544 | ||
1da177e4 LT |
545 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
546 | { | |
48fe3915 | 547 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
548 | u16 slot_cmd; |
549 | u16 cmd_mask; | |
550 | int rc; | |
1da177e4 | 551 | |
f4778364 | 552 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
553 | switch (value) { |
554 | case 0 : /* turn off */ | |
f4778364 | 555 | slot_cmd = 0x00C0; |
1da177e4 LT |
556 | break; |
557 | case 1: /* turn on */ | |
f4778364 | 558 | slot_cmd = 0x0040; |
1da177e4 LT |
559 | break; |
560 | case 2: /* turn blink */ | |
f4778364 | 561 | slot_cmd = 0x0080; |
1da177e4 LT |
562 | break; |
563 | default: | |
564 | return -1; | |
565 | } | |
c27fb883 | 566 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 567 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 568 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
71ad556d | 569 | |
1da177e4 LT |
570 | return rc; |
571 | } | |
572 | ||
1da177e4 LT |
573 | static void hpc_set_green_led_on(struct slot *slot) |
574 | { | |
48fe3915 | 575 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 576 | u16 slot_cmd; |
f4778364 | 577 | u16 cmd_mask; |
71ad556d | 578 | |
f4778364 KK |
579 | slot_cmd = 0x0100; |
580 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 581 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 582 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 583 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
584 | } |
585 | ||
586 | static void hpc_set_green_led_off(struct slot *slot) | |
587 | { | |
48fe3915 | 588 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 589 | u16 slot_cmd; |
f4778364 | 590 | u16 cmd_mask; |
1da177e4 | 591 | |
f4778364 KK |
592 | slot_cmd = 0x0300; |
593 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 594 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 595 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 596 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
597 | } |
598 | ||
599 | static void hpc_set_green_led_blink(struct slot *slot) | |
600 | { | |
48fe3915 | 601 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 602 | u16 slot_cmd; |
f4778364 | 603 | u16 cmd_mask; |
71ad556d | 604 | |
f4778364 KK |
605 | slot_cmd = 0x0200; |
606 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 607 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 608 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 609 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
610 | } |
611 | ||
1da177e4 LT |
612 | static void hpc_release_ctlr(struct controller *ctrl) |
613 | { | |
d84be093 KK |
614 | /* Mask Hot-plug Interrupt Enable */ |
615 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) | |
b30dd56d | 616 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); |
d84be093 | 617 | |
2aeeef11 KK |
618 | /* Free interrupt handler or interrupt polling timer */ |
619 | pciehp_free_irq(ctrl); | |
1da177e4 | 620 | |
5d386e1a KK |
621 | /* |
622 | * If this is the last controller to be released, destroy the | |
623 | * pciehp work queue | |
624 | */ | |
625 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
626 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
627 | } |
628 | ||
629 | static int hpc_power_on_slot(struct slot * slot) | |
630 | { | |
48fe3915 | 631 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 632 | u16 slot_cmd; |
f4778364 KK |
633 | u16 cmd_mask; |
634 | u16 slot_status; | |
1da177e4 LT |
635 | int retval = 0; |
636 | ||
66bef8c0 | 637 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 638 | |
5a49f203 | 639 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
640 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
641 | if (retval) { | |
66bef8c0 | 642 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
a0f018da KK |
643 | return retval; |
644 | } | |
5a49f203 | 645 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
646 | if (slot_status) { |
647 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
648 | if (retval) { | |
649 | err("%s: Cannot write to SLOTSTATUS register\n", | |
66bef8c0 | 650 | __func__); |
a0f018da KK |
651 | return retval; |
652 | } | |
653 | } | |
1da177e4 | 654 | |
f4778364 KK |
655 | slot_cmd = POWER_ON; |
656 | cmd_mask = PWR_CTRL; | |
c7ab337f | 657 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 658 | if (!pciehp_poll_mode) { |
cff00654 KK |
659 | slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
660 | PRSN_DETECT_ENABLE); | |
661 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
662 | PRSN_DETECT_ENABLE); | |
f4778364 | 663 | } |
1da177e4 | 664 | |
c27fb883 | 665 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
666 | |
667 | if (retval) { | |
66bef8c0 | 668 | err("%s: Write %x command failed!\n", __func__, slot_cmd); |
1da177e4 LT |
669 | return -1; |
670 | } | |
a0f018da | 671 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 672 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 | 673 | |
1da177e4 LT |
674 | return retval; |
675 | } | |
676 | ||
f1050a35 KK |
677 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
678 | { | |
679 | struct pci_dev *dev = ctrl->pci_dev; | |
680 | int pos; | |
681 | u32 reg; | |
682 | ||
683 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
684 | if (!pos) | |
685 | return 0; | |
686 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
687 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
688 | return 0; | |
689 | reg |= PCI_ERR_COR_BAD_DLLP; | |
690 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
691 | return 1; | |
692 | } | |
693 | ||
694 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
695 | { | |
696 | struct pci_dev *dev = ctrl->pci_dev; | |
697 | u32 reg; | |
698 | int pos; | |
699 | ||
700 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
701 | if (!pos) | |
702 | return; | |
703 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
704 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
705 | return; | |
706 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
707 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
708 | } | |
709 | ||
1da177e4 LT |
710 | static int hpc_power_off_slot(struct slot * slot) |
711 | { | |
48fe3915 | 712 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 713 | u16 slot_cmd; |
f4778364 | 714 | u16 cmd_mask; |
1da177e4 | 715 | int retval = 0; |
f1050a35 | 716 | int changed; |
1da177e4 | 717 | |
66bef8c0 | 718 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 719 | |
f1050a35 KK |
720 | /* |
721 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
722 | * Register. This is the workaround against Bad DLLP error | |
723 | * that sometimes happens during turning power off the slot | |
724 | * which conforms to PCI Express 1.0a spec. | |
725 | */ | |
726 | changed = pcie_mask_bad_dllp(ctrl); | |
727 | ||
f4778364 KK |
728 | slot_cmd = POWER_OFF; |
729 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
730 | /* |
731 | * If we get MRL or presence detect interrupts now, the isr | |
732 | * will notice the sticky power-fault bit too and issue power | |
733 | * indicator change commands. This will lead to an endless loop | |
734 | * of command completions, since the power-fault bit remains on | |
735 | * till the slot is powered on again. | |
736 | */ | |
f4778364 | 737 | if (!pciehp_poll_mode) { |
cff00654 KK |
738 | slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
739 | PRSN_DETECT_ENABLE); | |
740 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
741 | PRSN_DETECT_ENABLE); | |
f4778364 | 742 | } |
1da177e4 | 743 | |
c27fb883 | 744 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 745 | if (retval) { |
66bef8c0 | 746 | err("%s: Write command failed!\n", __func__); |
c1ef5cbd KK |
747 | retval = -1; |
748 | goto out; | |
1da177e4 | 749 | } |
a0f018da | 750 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 751 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
c1ef5cbd | 752 | out: |
f1050a35 KK |
753 | if (changed) |
754 | pcie_unmask_bad_dllp(ctrl); | |
755 | ||
1da177e4 LT |
756 | return retval; |
757 | } | |
758 | ||
48fe3915 | 759 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 760 | { |
48fe3915 | 761 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 762 | u16 detected, intr_loc; |
dbd79aed | 763 | struct slot *p_slot; |
1da177e4 | 764 | |
c6b069e9 KK |
765 | /* |
766 | * In order to guarantee that all interrupt events are | |
767 | * serviced, we need to re-inspect Slot Status register after | |
768 | * clearing what is presumed to be the last pending interrupt. | |
769 | */ | |
770 | intr_loc = 0; | |
771 | do { | |
772 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | |
773 | err("%s: Cannot read SLOTSTATUS\n", __func__); | |
1da177e4 LT |
774 | return IRQ_NONE; |
775 | } | |
776 | ||
c6b069e9 KK |
777 | detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
778 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | | |
779 | CMD_COMPLETED); | |
780 | intr_loc |= detected; | |
781 | if (!intr_loc) | |
1da177e4 | 782 | return IRQ_NONE; |
6a3f0849 | 783 | if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
c6b069e9 | 784 | err("%s: Cannot write to SLOTSTATUS\n", __func__); |
1da177e4 LT |
785 | return IRQ_NONE; |
786 | } | |
c6b069e9 | 787 | } while (detected); |
71ad556d | 788 | |
c6b069e9 | 789 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); |
71ad556d | 790 | |
c6b069e9 | 791 | /* Check Command Complete Interrupt Pending */ |
1da177e4 | 792 | if (intr_loc & CMD_COMPLETED) { |
262303fe | 793 | ctrl->cmd_busy = 0; |
2d32a9ae | 794 | smp_mb(); |
d737bdc1 | 795 | wake_up(&ctrl->queue); |
1da177e4 LT |
796 | } |
797 | ||
dbd79aed KK |
798 | if (!(intr_loc & ~CMD_COMPLETED)) |
799 | return IRQ_HANDLED; | |
800 | ||
801 | /* | |
802 | * Return without handling events if this handler routine is | |
803 | * called before controller initialization is done. This may | |
804 | * happen if hotplug event or another interrupt that shares | |
805 | * the IRQ with pciehp arrives before slot initialization is | |
806 | * done after interrupt handler is registered. | |
807 | * | |
808 | * FIXME - Need more structural fixes. We need to be ready to | |
809 | * handle the event before installing interrupt handler. | |
810 | */ | |
811 | p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); | |
812 | if (!p_slot || !p_slot->hpc_ops) | |
813 | return IRQ_HANDLED; | |
814 | ||
c6b069e9 | 815 | /* Check MRL Sensor Changed */ |
48fe3915 | 816 | if (intr_loc & MRL_SENS_CHANGED) |
dbd79aed | 817 | pciehp_handle_switch_change(p_slot); |
48fe3915 | 818 | |
c6b069e9 | 819 | /* Check Attention Button Pressed */ |
48fe3915 | 820 | if (intr_loc & ATTN_BUTTN_PRESSED) |
dbd79aed | 821 | pciehp_handle_attention_button(p_slot); |
48fe3915 | 822 | |
c6b069e9 | 823 | /* Check Presence Detect Changed */ |
48fe3915 | 824 | if (intr_loc & PRSN_DETECT_CHANGED) |
dbd79aed | 825 | pciehp_handle_presence_change(p_slot); |
48fe3915 | 826 | |
c6b069e9 | 827 | /* Check Power Fault Detected */ |
48fe3915 | 828 | if (intr_loc & PWR_FAULT_DETECTED) |
dbd79aed | 829 | pciehp_handle_power_fault(p_slot); |
71ad556d | 830 | |
1da177e4 LT |
831 | return IRQ_HANDLED; |
832 | } | |
833 | ||
40730d10 | 834 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 835 | { |
48fe3915 | 836 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
837 | enum pcie_link_speed lnk_speed; |
838 | u32 lnk_cap; | |
839 | int retval = 0; | |
840 | ||
a0f018da | 841 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 842 | if (retval) { |
66bef8c0 | 843 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
844 | return retval; |
845 | } | |
846 | ||
847 | switch (lnk_cap & 0x000F) { | |
848 | case 1: | |
849 | lnk_speed = PCIE_2PT5GB; | |
850 | break; | |
851 | default: | |
852 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
853 | break; | |
854 | } | |
855 | ||
856 | *value = lnk_speed; | |
857 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 858 | |
1da177e4 LT |
859 | return retval; |
860 | } | |
861 | ||
40730d10 KK |
862 | static int hpc_get_max_lnk_width(struct slot *slot, |
863 | enum pcie_link_width *value) | |
1da177e4 | 864 | { |
48fe3915 | 865 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
866 | enum pcie_link_width lnk_wdth; |
867 | u32 lnk_cap; | |
868 | int retval = 0; | |
869 | ||
a0f018da | 870 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 871 | if (retval) { |
66bef8c0 | 872 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
873 | return retval; |
874 | } | |
875 | ||
876 | switch ((lnk_cap & 0x03F0) >> 4){ | |
877 | case 0: | |
878 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
879 | break; | |
880 | case 1: | |
881 | lnk_wdth = PCIE_LNK_X1; | |
882 | break; | |
883 | case 2: | |
884 | lnk_wdth = PCIE_LNK_X2; | |
885 | break; | |
886 | case 4: | |
887 | lnk_wdth = PCIE_LNK_X4; | |
888 | break; | |
889 | case 8: | |
890 | lnk_wdth = PCIE_LNK_X8; | |
891 | break; | |
892 | case 12: | |
893 | lnk_wdth = PCIE_LNK_X12; | |
894 | break; | |
895 | case 16: | |
896 | lnk_wdth = PCIE_LNK_X16; | |
897 | break; | |
898 | case 32: | |
899 | lnk_wdth = PCIE_LNK_X32; | |
900 | break; | |
901 | default: | |
902 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
903 | break; | |
904 | } | |
905 | ||
906 | *value = lnk_wdth; | |
907 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 908 | |
1da177e4 LT |
909 | return retval; |
910 | } | |
911 | ||
40730d10 | 912 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 913 | { |
48fe3915 | 914 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
915 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
916 | int retval = 0; | |
917 | u16 lnk_status; | |
918 | ||
a0f018da | 919 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 920 | if (retval) { |
66bef8c0 | 921 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
922 | return retval; |
923 | } | |
924 | ||
925 | switch (lnk_status & 0x0F) { | |
926 | case 1: | |
927 | lnk_speed = PCIE_2PT5GB; | |
928 | break; | |
929 | default: | |
930 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
931 | break; | |
932 | } | |
933 | ||
934 | *value = lnk_speed; | |
935 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 936 | |
1da177e4 LT |
937 | return retval; |
938 | } | |
939 | ||
40730d10 KK |
940 | static int hpc_get_cur_lnk_width(struct slot *slot, |
941 | enum pcie_link_width *value) | |
1da177e4 | 942 | { |
48fe3915 | 943 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
944 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
945 | int retval = 0; | |
946 | u16 lnk_status; | |
947 | ||
a0f018da | 948 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 949 | if (retval) { |
66bef8c0 | 950 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
951 | return retval; |
952 | } | |
71ad556d | 953 | |
1da177e4 LT |
954 | switch ((lnk_status & 0x03F0) >> 4){ |
955 | case 0: | |
956 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
957 | break; | |
958 | case 1: | |
959 | lnk_wdth = PCIE_LNK_X1; | |
960 | break; | |
961 | case 2: | |
962 | lnk_wdth = PCIE_LNK_X2; | |
963 | break; | |
964 | case 4: | |
965 | lnk_wdth = PCIE_LNK_X4; | |
966 | break; | |
967 | case 8: | |
968 | lnk_wdth = PCIE_LNK_X8; | |
969 | break; | |
970 | case 12: | |
971 | lnk_wdth = PCIE_LNK_X12; | |
972 | break; | |
973 | case 16: | |
974 | lnk_wdth = PCIE_LNK_X16; | |
975 | break; | |
976 | case 32: | |
977 | lnk_wdth = PCIE_LNK_X32; | |
978 | break; | |
979 | default: | |
980 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
981 | break; | |
982 | } | |
983 | ||
984 | *value = lnk_wdth; | |
985 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 986 | |
1da177e4 LT |
987 | return retval; |
988 | } | |
989 | ||
990 | static struct hpc_ops pciehp_hpc_ops = { | |
991 | .power_on_slot = hpc_power_on_slot, | |
992 | .power_off_slot = hpc_power_off_slot, | |
993 | .set_attention_status = hpc_set_attention_status, | |
994 | .get_power_status = hpc_get_power_status, | |
995 | .get_attention_status = hpc_get_attention_status, | |
996 | .get_latch_status = hpc_get_latch_status, | |
997 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
998 | .get_emi_status = hpc_get_emi_status, |
999 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
1000 | |
1001 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
1002 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
1003 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
1004 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 1005 | |
1da177e4 LT |
1006 | .query_power_fault = hpc_query_power_fault, |
1007 | .green_led_on = hpc_set_green_led_on, | |
1008 | .green_led_off = hpc_set_green_led_off, | |
1009 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 1010 | |
1da177e4 LT |
1011 | .release_ctlr = hpc_release_ctlr, |
1012 | .check_lnk_status = hpc_check_lnk_status, | |
1013 | }; | |
1014 | ||
ecdde939 ML |
1015 | static int pcie_init_hardware_part1(struct controller *ctrl, |
1016 | struct pcie_device *dev) | |
1da177e4 | 1017 | { |
dbd79aed KK |
1018 | /* Clear all remaining event bits in Slot Status register */ |
1019 | if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) { | |
1020 | err("%s: Cannot write to SLOTSTATUS register\n", __func__); | |
1021 | return -1; | |
1022 | } | |
1023 | ||
1da177e4 | 1024 | /* Mask Hot-plug Interrupt Enable */ |
c27fb883 KK |
1025 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) { |
1026 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); | |
ecdde939 | 1027 | return -1; |
1da177e4 | 1028 | } |
ecdde939 ML |
1029 | return 0; |
1030 | } | |
1a9ed1bf | 1031 | |
ecdde939 ML |
1032 | int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev) |
1033 | { | |
c27fb883 | 1034 | u16 cmd, mask; |
1da177e4 | 1035 | |
c27fb883 | 1036 | cmd = PRSN_DETECT_ENABLE; |
ae416e6b | 1037 | if (ATTN_BUTTN(ctrl)) |
c27fb883 | 1038 | cmd |= ATTN_BUTTN_ENABLE; |
ae416e6b | 1039 | if (POWER_CTRL(ctrl)) |
c27fb883 | 1040 | cmd |= PWR_FAULT_DETECT_ENABLE; |
ae416e6b | 1041 | if (MRL_SENS(ctrl)) |
c27fb883 KK |
1042 | cmd |= MRL_DETECT_ENABLE; |
1043 | if (!pciehp_poll_mode) | |
1044 | cmd |= HP_INTR_ENABLE; | |
1045 | ||
1046 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | | |
1047 | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE; | |
1048 | ||
1049 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
1050 | err("%s: Cannot enable software notification\n", __func__); | |
125c39f7 | 1051 | return -1; |
1da177e4 | 1052 | } |
71ad556d | 1053 | |
1da177e4 | 1054 | return 0; |
1da177e4 | 1055 | } |
08e7a7d2 | 1056 | |
2aeeef11 | 1057 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 1058 | { |
2aeeef11 KK |
1059 | int i; |
1060 | u16 reg16; | |
1061 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 1062 | |
2aeeef11 KK |
1063 | if (!pciehp_debug) |
1064 | return; | |
08e7a7d2 | 1065 | |
2aeeef11 KK |
1066 | dbg("Hotplug Controller:\n"); |
1067 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); | |
1068 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); | |
1069 | dbg(" Device ID : 0x%04x\n", pdev->device); | |
1070 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | |
1071 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | |
1072 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
1073 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1074 | if (!pci_resource_len(pdev, i)) | |
1075 | continue; | |
1076 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | |
1077 | (unsigned long long)pci_resource_len(pdev, i), | |
1078 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 1079 | } |
2aeeef11 KK |
1080 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1081 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | |
1082 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
1083 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | |
1084 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | |
1085 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | |
1086 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | |
1087 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
1088 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | |
5808639b | 1089 | dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); |
2aeeef11 KK |
1090 | pciehp_readw(ctrl, SLOTSTATUS, ®16); |
1091 | dbg("Slot Status : 0x%04x\n", reg16); | |
d8b23e8f | 1092 | pciehp_readw(ctrl, SLOTCTRL, ®16); |
2aeeef11 KK |
1093 | dbg("Slot Control : 0x%04x\n", reg16); |
1094 | } | |
08e7a7d2 | 1095 | |
2aeeef11 KK |
1096 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) |
1097 | { | |
1098 | u32 slot_cap; | |
1099 | struct pci_dev *pdev = dev->port; | |
08e7a7d2 | 1100 | |
2aeeef11 KK |
1101 | ctrl->pci_dev = pdev; |
1102 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1103 | if (!ctrl->cap_base) { | |
1104 | err("%s: Cannot find PCI Express capability\n", __func__); | |
08e7a7d2 ML |
1105 | goto abort; |
1106 | } | |
2aeeef11 | 1107 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
66bef8c0 | 1108 | err("%s: Cannot read SLOTCAP register\n", __func__); |
08e7a7d2 ML |
1109 | goto abort; |
1110 | } | |
08e7a7d2 | 1111 | |
2aeeef11 KK |
1112 | ctrl->slot_cap = slot_cap; |
1113 | ctrl->first_slot = slot_cap >> 19; | |
1114 | ctrl->slot_device_offset = 0; | |
1115 | ctrl->num_slots = 1; | |
1116 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1117 | mutex_init(&ctrl->crit_sect); |
1118 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1119 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1120 | dbg_ctrl(ctrl); |
5808639b KK |
1121 | /* |
1122 | * Controller doesn't notify of command completion if the "No | |
1123 | * Command Completed Support" bit is set in Slot Capability | |
1124 | * register or the controller supports none of power | |
1125 | * controller, attention led, power led and EMI. | |
1126 | */ | |
1127 | if (NO_CMD_CMPL(ctrl) || | |
1128 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
1129 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 1130 | |
2aeeef11 KK |
1131 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1132 | pdev->vendor, pdev->device, | |
1133 | pdev->subsystem_vendor, pdev->subsystem_device); | |
08e7a7d2 | 1134 | |
2aeeef11 | 1135 | if (pcie_init_hardware_part1(ctrl, dev)) |
ecdde939 ML |
1136 | goto abort; |
1137 | ||
2aeeef11 KK |
1138 | if (pciehp_request_irq(ctrl)) |
1139 | goto abort; | |
ecdde939 ML |
1140 | |
1141 | /* | |
1142 | * If this is the first controller to be initialized, | |
1143 | * initialize the pciehp work queue | |
1144 | */ | |
1145 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1146 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1147 | if (!pciehp_wq) { | |
ecdde939 ML |
1148 | goto abort_free_irq; |
1149 | } | |
1150 | } | |
1151 | ||
2aeeef11 KK |
1152 | if (pcie_init_hardware_part2(ctrl, dev)) |
1153 | goto abort_free_irq; | |
1154 | ||
1155 | return 0; | |
1156 | ||
ecdde939 | 1157 | abort_free_irq: |
2aeeef11 | 1158 | pciehp_free_irq(ctrl); |
08e7a7d2 ML |
1159 | abort: |
1160 | return -1; | |
1161 | } |