Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
a0f018da KK |
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
45 | { | |
385e2491 | 46 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 47 | return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
48 | } |
49 | ||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
51 | { | |
385e2491 | 52 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 53 | return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
54 | } |
55 | ||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
57 | { | |
385e2491 | 58 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 59 | return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da KK |
60 | } |
61 | ||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
63 | { | |
385e2491 | 64 | struct pci_dev *dev = ctrl->pcie->port; |
1518c17a | 65 | return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); |
a0f018da | 66 | } |
1da177e4 | 67 | |
1da177e4 LT |
68 | /* Power Control Command */ |
69 | #define POWER_ON 0 | |
322162a7 | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 71 | |
48fe3915 KK |
72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
73 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
74 | |
75 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 76 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 77 | { |
48fe3915 | 78 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 79 | |
1da177e4 | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 81 | pcie_isr(0, ctrl); |
1da177e4 | 82 | |
48fe3915 | 83 | init_timer(&ctrl->poll_timer); |
1da177e4 | 84 | if (!pciehp_poll_time) |
40730d10 | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 86 | |
48fe3915 | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
88 | } |
89 | ||
90 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 92 | { |
48fe3915 KK |
93 | /* Clamp to sane value */ |
94 | if ((sec <= 0) || (sec > 60)) | |
95 | sec = 2; | |
96 | ||
97 | ctrl->poll_timer.function = &int_poll_timeout; | |
98 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
99 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
100 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
101 | } |
102 | ||
2aeeef11 KK |
103 | static inline int pciehp_request_irq(struct controller *ctrl) |
104 | { | |
f7a10e32 | 105 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
106 | |
107 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
108 | if (pciehp_poll_mode) { | |
109 | init_timer(&ctrl->poll_timer); | |
110 | start_int_poll_timer(ctrl, 10); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | /* Installs the interrupt handler */ | |
115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
116 | if (retval) | |
7f2feec1 TI |
117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
118 | irq); | |
2aeeef11 KK |
119 | return retval; |
120 | } | |
121 | ||
122 | static inline void pciehp_free_irq(struct controller *ctrl) | |
123 | { | |
124 | if (pciehp_poll_mode) | |
125 | del_timer_sync(&ctrl->poll_timer); | |
126 | else | |
f7a10e32 | 127 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
128 | } |
129 | ||
563f1190 | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
131 | { |
132 | u16 slot_status; | |
322162a7 | 133 | int err, timeout = 1000; |
6592e02a | 134 | |
322162a7 KK |
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
138 | return 1; | |
820943b6 | 139 | } |
a5827f40 | 140 | while (timeout > 0) { |
66618bad KK |
141 | msleep(10); |
142 | timeout -= 10; | |
322162a7 KK |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
146 | return 1; | |
820943b6 | 147 | } |
6592e02a KK |
148 | } |
149 | return 0; /* timeout */ | |
6592e02a KK |
150 | } |
151 | ||
563f1190 | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 153 | { |
262303fe KK |
154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
155 | unsigned long timeout = msecs_to_jiffies(msecs); | |
156 | int rc; | |
157 | ||
6592e02a KK |
158 | if (poll) |
159 | rc = pcie_poll_cmd(ctrl); | |
160 | else | |
d737bdc1 | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 162 | if (!rc) |
7f2feec1 | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
164 | } |
165 | ||
f4778364 KK |
166 | /** |
167 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 168 | * @ctrl: controller to which the command is issued |
f4778364 KK |
169 | * @cmd: command value written to slot control register |
170 | * @mask: bitmask of slot control register to be modified | |
171 | */ | |
c27fb883 | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 173 | { |
1da177e4 LT |
174 | int retval = 0; |
175 | u16 slot_status; | |
f4778364 | 176 | u16 slot_ctrl; |
1da177e4 | 177 | |
44ef4cef KK |
178 | mutex_lock(&ctrl->ctrl_lock); |
179 | ||
322162a7 | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 181 | if (retval) { |
7f2feec1 TI |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | |
44ef4cef | 184 | goto out; |
a0f018da KK |
185 | } |
186 | ||
322162a7 | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
188 | if (!ctrl->no_cmd_complete) { |
189 | /* | |
190 | * After 1 sec and CMD_COMPLETED still not set, just | |
191 | * proceed forward to issue the next command according | |
192 | * to spec. Just print out the error message. | |
193 | */ | |
18b341b7 | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
195 | } else if (!NO_CMD_CMPL(ctrl)) { |
196 | /* | |
197 | * This controller semms to notify of command completed | |
198 | * event even though it supports none of power | |
199 | * controller, attention led, power led and EMI. | |
200 | */ | |
18b341b7 TI |
201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
202 | "wait for command completed event.\n"); | |
5808639b KK |
203 | ctrl->no_cmd_complete = 0; |
204 | } else { | |
18b341b7 TI |
205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
206 | "the controller is broken.\n"); | |
5808639b | 207 | } |
1da177e4 LT |
208 | } |
209 | ||
322162a7 | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 211 | if (retval) { |
7f2feec1 | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 213 | goto out; |
1da177e4 | 214 | } |
1da177e4 | 215 | |
f4778364 | 216 | slot_ctrl &= ~mask; |
b7aa1f16 | 217 | slot_ctrl |= (cmd & mask); |
f4778364 | 218 | ctrl->cmd_busy = 1; |
2d32a9ae | 219 | smp_mb(); |
322162a7 | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 221 | if (retval) |
18b341b7 | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 223 | |
44ef4cef KK |
224 | /* |
225 | * Wait for command completion. | |
226 | */ | |
6592e02a KK |
227 | if (!retval && !ctrl->no_cmd_complete) { |
228 | int poll = 0; | |
229 | /* | |
230 | * if hotplug interrupt is not enabled or command | |
231 | * completed interrupt is not enabled, we need to poll | |
232 | * command completed event. | |
233 | */ | |
322162a7 KK |
234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 236 | poll = 1; |
d737bdc1 | 237 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 238 | } |
44ef4cef KK |
239 | out: |
240 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
241 | return retval; |
242 | } | |
243 | ||
f18e9625 KK |
244 | static inline int check_link_active(struct controller *ctrl) |
245 | { | |
246 | u16 link_status; | |
247 | ||
322162a7 | 248 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 249 | return 0; |
322162a7 | 250 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
251 | } |
252 | ||
253 | static void pcie_wait_link_active(struct controller *ctrl) | |
254 | { | |
255 | int timeout = 1000; | |
256 | ||
257 | if (check_link_active(ctrl)) | |
258 | return; | |
259 | while (timeout > 0) { | |
260 | msleep(10); | |
261 | timeout -= 10; | |
262 | if (check_link_active(ctrl)) | |
263 | return; | |
264 | } | |
265 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
266 | } | |
267 | ||
82a9e79e | 268 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 269 | { |
1da177e4 LT |
270 | u16 lnk_status; |
271 | int retval = 0; | |
272 | ||
f18e9625 KK |
273 | /* |
274 | * Data Link Layer Link Active Reporting must be capable for | |
275 | * hot-plug capable downstream port. But old controller might | |
276 | * not implement it. In this case, we wait for 1000 ms. | |
277 | */ | |
0cab0841 | 278 | if (ctrl->link_active_reporting) |
f18e9625 | 279 | pcie_wait_link_active(ctrl); |
0cab0841 | 280 | else |
f18e9625 KK |
281 | msleep(1000); |
282 | ||
0027cb3e KK |
283 | /* |
284 | * Need to wait for 1000 ms after Data Link Layer Link Active | |
285 | * (DLLLA) bit reads 1b before sending configuration request. | |
286 | * We need it before checking Link Training (LT) bit becuase | |
287 | * LT is still set even after DLLLA bit is set on some platform. | |
288 | */ | |
289 | msleep(1000); | |
290 | ||
322162a7 | 291 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 292 | if (retval) { |
18b341b7 | 293 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
294 | return retval; |
295 | } | |
296 | ||
7f2feec1 | 297 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
298 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
299 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 300 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
301 | retval = -1; |
302 | return retval; | |
303 | } | |
304 | ||
b3c00454 KK |
305 | /* |
306 | * If the port supports Link speeds greater than 5.0 GT/s, we | |
307 | * must wait for 100 ms after Link training completes before | |
308 | * sending configuration request. | |
309 | */ | |
310 | if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT) | |
311 | msleep(100); | |
312 | ||
fdbd3ce9 YL |
313 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
314 | ||
1da177e4 LT |
315 | return retval; |
316 | } | |
317 | ||
82a9e79e | 318 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 319 | { |
48fe3915 | 320 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
321 | u16 slot_ctrl; |
322 | u8 atten_led_state; | |
323 | int retval = 0; | |
1da177e4 | 324 | |
322162a7 | 325 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 326 | if (retval) { |
7f2feec1 | 327 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
328 | return retval; |
329 | } | |
330 | ||
1518c17a KK |
331 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
332 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 333 | |
322162a7 | 334 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
335 | |
336 | switch (atten_led_state) { | |
337 | case 0: | |
338 | *status = 0xFF; /* Reserved */ | |
339 | break; | |
340 | case 1: | |
341 | *status = 1; /* On */ | |
342 | break; | |
343 | case 2: | |
344 | *status = 2; /* Blink */ | |
345 | break; | |
346 | case 3: | |
347 | *status = 0; /* Off */ | |
348 | break; | |
349 | default: | |
350 | *status = 0xFF; | |
351 | break; | |
352 | } | |
353 | ||
1da177e4 LT |
354 | return 0; |
355 | } | |
356 | ||
82a9e79e | 357 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 358 | { |
48fe3915 | 359 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
360 | u16 slot_ctrl; |
361 | u8 pwr_state; | |
362 | int retval = 0; | |
1da177e4 | 363 | |
322162a7 | 364 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 365 | if (retval) { |
7f2feec1 | 366 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
367 | return retval; |
368 | } | |
1518c17a KK |
369 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
370 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 371 | |
322162a7 | 372 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
373 | |
374 | switch (pwr_state) { | |
375 | case 0: | |
376 | *status = 1; | |
377 | break; | |
378 | case 1: | |
71ad556d | 379 | *status = 0; |
1da177e4 LT |
380 | break; |
381 | default: | |
382 | *status = 0xFF; | |
383 | break; | |
384 | } | |
385 | ||
1da177e4 LT |
386 | return retval; |
387 | } | |
388 | ||
82a9e79e | 389 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 390 | { |
48fe3915 | 391 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 392 | u16 slot_status; |
322162a7 | 393 | int retval; |
1da177e4 | 394 | |
322162a7 | 395 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 396 | if (retval) { |
7f2feec1 TI |
397 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
398 | __func__); | |
1da177e4 LT |
399 | return retval; |
400 | } | |
322162a7 | 401 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
402 | return 0; |
403 | } | |
404 | ||
82a9e79e | 405 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 406 | { |
48fe3915 | 407 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 408 | u16 slot_status; |
322162a7 | 409 | int retval; |
1da177e4 | 410 | |
322162a7 | 411 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 412 | if (retval) { |
7f2feec1 TI |
413 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
414 | __func__); | |
1da177e4 LT |
415 | return retval; |
416 | } | |
322162a7 | 417 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
418 | return 0; |
419 | } | |
420 | ||
82a9e79e | 421 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 422 | { |
48fe3915 | 423 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 424 | u16 slot_status; |
322162a7 | 425 | int retval; |
1da177e4 | 426 | |
322162a7 | 427 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 428 | if (retval) { |
18b341b7 | 429 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
430 | return retval; |
431 | } | |
322162a7 | 432 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
433 | } |
434 | ||
82a9e79e | 435 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 436 | { |
48fe3915 | 437 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
438 | u16 slot_cmd; |
439 | u16 cmd_mask; | |
1da177e4 | 440 | |
322162a7 | 441 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 | 442 | switch (value) { |
445f7985 KK |
443 | case 0 : /* turn off */ |
444 | slot_cmd = 0x00C0; | |
445 | break; | |
446 | case 1: /* turn on */ | |
447 | slot_cmd = 0x0040; | |
448 | break; | |
449 | case 2: /* turn blink */ | |
450 | slot_cmd = 0x0080; | |
451 | break; | |
452 | default: | |
453 | return -EINVAL; | |
1da177e4 | 454 | } |
1518c17a KK |
455 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
456 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
445f7985 | 457 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
458 | } |
459 | ||
82a9e79e | 460 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 461 | { |
48fe3915 | 462 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 463 | u16 slot_cmd; |
f4778364 | 464 | u16 cmd_mask; |
71ad556d | 465 | |
f4778364 | 466 | slot_cmd = 0x0100; |
322162a7 | 467 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 468 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
469 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
470 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
471 | } |
472 | ||
82a9e79e | 473 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 474 | { |
48fe3915 | 475 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 476 | u16 slot_cmd; |
f4778364 | 477 | u16 cmd_mask; |
1da177e4 | 478 | |
f4778364 | 479 | slot_cmd = 0x0300; |
322162a7 | 480 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 481 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
482 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
483 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
484 | } |
485 | ||
82a9e79e | 486 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 487 | { |
48fe3915 | 488 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 489 | u16 slot_cmd; |
f4778364 | 490 | u16 cmd_mask; |
71ad556d | 491 | |
f4778364 | 492 | slot_cmd = 0x0200; |
322162a7 | 493 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 494 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1518c17a KK |
495 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
496 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 LT |
497 | } |
498 | ||
82a9e79e | 499 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 500 | { |
48fe3915 | 501 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 502 | u16 slot_cmd; |
f4778364 KK |
503 | u16 cmd_mask; |
504 | u16 slot_status; | |
1da177e4 LT |
505 | int retval = 0; |
506 | ||
5a49f203 | 507 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 508 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 509 | if (retval) { |
7f2feec1 TI |
510 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
511 | __func__); | |
a0f018da KK |
512 | return retval; |
513 | } | |
322162a7 | 514 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 515 | if (slot_status) { |
322162a7 | 516 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 517 | if (retval) { |
7f2feec1 TI |
518 | ctrl_err(ctrl, |
519 | "%s: Cannot write to SLOTSTATUS register\n", | |
520 | __func__); | |
a0f018da KK |
521 | return retval; |
522 | } | |
523 | } | |
5651c48c | 524 | ctrl->power_fault_detected = 0; |
1da177e4 | 525 | |
f4778364 | 526 | slot_cmd = POWER_ON; |
322162a7 | 527 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 528 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 529 | if (retval) { |
18b341b7 | 530 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 531 | return retval; |
1da177e4 | 532 | } |
1518c17a KK |
533 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
534 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
1da177e4 | 535 | |
1da177e4 LT |
536 | return retval; |
537 | } | |
538 | ||
82a9e79e | 539 | int pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 540 | { |
48fe3915 | 541 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 542 | u16 slot_cmd; |
f4778364 | 543 | u16 cmd_mask; |
3c3a1b17 | 544 | int retval; |
f1050a35 | 545 | |
f4778364 | 546 | slot_cmd = POWER_OFF; |
322162a7 | 547 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
c27fb883 | 548 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 549 | if (retval) { |
18b341b7 | 550 | ctrl_err(ctrl, "Write command failed!\n"); |
3c3a1b17 | 551 | return retval; |
1da177e4 | 552 | } |
1518c17a KK |
553 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
554 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
3c3a1b17 | 555 | return 0; |
1da177e4 LT |
556 | } |
557 | ||
48fe3915 | 558 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 559 | { |
48fe3915 | 560 | struct controller *ctrl = (struct controller *)dev_id; |
8720d27d | 561 | struct slot *slot = ctrl->slot; |
c6b069e9 | 562 | u16 detected, intr_loc; |
1da177e4 | 563 | |
c6b069e9 KK |
564 | /* |
565 | * In order to guarantee that all interrupt events are | |
566 | * serviced, we need to re-inspect Slot Status register after | |
567 | * clearing what is presumed to be the last pending interrupt. | |
568 | */ | |
569 | intr_loc = 0; | |
570 | do { | |
322162a7 | 571 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
572 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
573 | __func__); | |
1da177e4 LT |
574 | return IRQ_NONE; |
575 | } | |
576 | ||
322162a7 KK |
577 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
578 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
579 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 580 | detected &= ~intr_loc; |
c6b069e9 KK |
581 | intr_loc |= detected; |
582 | if (!intr_loc) | |
1da177e4 | 583 | return IRQ_NONE; |
81b840cd | 584 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
585 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
586 | __func__); | |
1da177e4 LT |
587 | return IRQ_NONE; |
588 | } | |
c6b069e9 | 589 | } while (detected); |
71ad556d | 590 | |
7f2feec1 | 591 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 592 | |
c6b069e9 | 593 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 594 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 595 | ctrl->cmd_busy = 0; |
2d32a9ae | 596 | smp_mb(); |
d737bdc1 | 597 | wake_up(&ctrl->queue); |
1da177e4 LT |
598 | } |
599 | ||
322162a7 | 600 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
601 | return IRQ_HANDLED; |
602 | ||
c6b069e9 | 603 | /* Check MRL Sensor Changed */ |
322162a7 | 604 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 605 | pciehp_handle_switch_change(slot); |
48fe3915 | 606 | |
c6b069e9 | 607 | /* Check Attention Button Pressed */ |
322162a7 | 608 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 609 | pciehp_handle_attention_button(slot); |
48fe3915 | 610 | |
c6b069e9 | 611 | /* Check Presence Detect Changed */ |
322162a7 | 612 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 613 | pciehp_handle_presence_change(slot); |
48fe3915 | 614 | |
c6b069e9 | 615 | /* Check Power Fault Detected */ |
99f0169c KK |
616 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
617 | ctrl->power_fault_detected = 1; | |
8720d27d | 618 | pciehp_handle_power_fault(slot); |
99f0169c | 619 | } |
1da177e4 LT |
620 | return IRQ_HANDLED; |
621 | } | |
622 | ||
82a9e79e | 623 | int pciehp_get_max_lnk_width(struct slot *slot, |
40730d10 | 624 | enum pcie_link_width *value) |
1da177e4 | 625 | { |
48fe3915 | 626 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
627 | enum pcie_link_width lnk_wdth; |
628 | u32 lnk_cap; | |
629 | int retval = 0; | |
630 | ||
322162a7 | 631 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 632 | if (retval) { |
7f2feec1 | 633 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
634 | return retval; |
635 | } | |
636 | ||
322162a7 | 637 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
638 | case 0: |
639 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
640 | break; | |
641 | case 1: | |
642 | lnk_wdth = PCIE_LNK_X1; | |
643 | break; | |
644 | case 2: | |
645 | lnk_wdth = PCIE_LNK_X2; | |
646 | break; | |
647 | case 4: | |
648 | lnk_wdth = PCIE_LNK_X4; | |
649 | break; | |
650 | case 8: | |
651 | lnk_wdth = PCIE_LNK_X8; | |
652 | break; | |
653 | case 12: | |
654 | lnk_wdth = PCIE_LNK_X12; | |
655 | break; | |
656 | case 16: | |
657 | lnk_wdth = PCIE_LNK_X16; | |
658 | break; | |
659 | case 32: | |
660 | lnk_wdth = PCIE_LNK_X32; | |
661 | break; | |
662 | default: | |
663 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
664 | break; | |
665 | } | |
666 | ||
667 | *value = lnk_wdth; | |
7f2feec1 | 668 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 669 | |
1da177e4 LT |
670 | return retval; |
671 | } | |
672 | ||
82a9e79e | 673 | int pciehp_get_cur_lnk_width(struct slot *slot, |
40730d10 | 674 | enum pcie_link_width *value) |
1da177e4 | 675 | { |
48fe3915 | 676 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
677 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
678 | int retval = 0; | |
679 | u16 lnk_status; | |
680 | ||
322162a7 | 681 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 682 | if (retval) { |
7f2feec1 TI |
683 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
684 | __func__); | |
1da177e4 LT |
685 | return retval; |
686 | } | |
71ad556d | 687 | |
322162a7 | 688 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
689 | case 0: |
690 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
691 | break; | |
692 | case 1: | |
693 | lnk_wdth = PCIE_LNK_X1; | |
694 | break; | |
695 | case 2: | |
696 | lnk_wdth = PCIE_LNK_X2; | |
697 | break; | |
698 | case 4: | |
699 | lnk_wdth = PCIE_LNK_X4; | |
700 | break; | |
701 | case 8: | |
702 | lnk_wdth = PCIE_LNK_X8; | |
703 | break; | |
704 | case 12: | |
705 | lnk_wdth = PCIE_LNK_X12; | |
706 | break; | |
707 | case 16: | |
708 | lnk_wdth = PCIE_LNK_X16; | |
709 | break; | |
710 | case 32: | |
711 | lnk_wdth = PCIE_LNK_X32; | |
712 | break; | |
713 | default: | |
714 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
715 | break; | |
716 | } | |
717 | ||
718 | *value = lnk_wdth; | |
7f2feec1 | 719 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 720 | |
1da177e4 LT |
721 | return retval; |
722 | } | |
723 | ||
c4635eb0 | 724 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 725 | { |
c27fb883 | 726 | u16 cmd, mask; |
1da177e4 | 727 | |
5651c48c KK |
728 | /* |
729 | * TBD: Power fault detected software notification support. | |
730 | * | |
731 | * Power fault detected software notification is not enabled | |
732 | * now, because it caused power fault detected interrupt storm | |
733 | * on some machines. On those machines, power fault detected | |
734 | * bit in the slot status register was set again immediately | |
735 | * when it is cleared in the interrupt service routine, and | |
736 | * next power fault detected interrupt was notified again. | |
737 | */ | |
322162a7 | 738 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 739 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 740 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 741 | if (MRL_SENS(ctrl)) |
322162a7 | 742 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 743 | if (!pciehp_poll_mode) |
322162a7 | 744 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 745 | |
322162a7 KK |
746 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
747 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
748 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
749 | |
750 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 751 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 752 | return -1; |
1da177e4 | 753 | } |
c4635eb0 KK |
754 | return 0; |
755 | } | |
756 | ||
757 | static void pcie_disable_notification(struct controller *ctrl) | |
758 | { | |
759 | u16 mask; | |
322162a7 KK |
760 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
761 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
762 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
763 | PCI_EXP_SLTCTL_DLLSCE); | |
c4635eb0 | 764 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 765 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
766 | } |
767 | ||
dbc7e1e5 | 768 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
769 | { |
770 | if (pciehp_request_irq(ctrl)) | |
771 | return -1; | |
772 | if (pcie_enable_notification(ctrl)) { | |
773 | pciehp_free_irq(ctrl); | |
774 | return -1; | |
775 | } | |
dbc7e1e5 | 776 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
777 | return 0; |
778 | } | |
779 | ||
780 | static void pcie_shutdown_notification(struct controller *ctrl) | |
781 | { | |
dbc7e1e5 EB |
782 | if (ctrl->notification_enabled) { |
783 | pcie_disable_notification(ctrl); | |
784 | pciehp_free_irq(ctrl); | |
785 | ctrl->notification_enabled = 0; | |
786 | } | |
c4635eb0 KK |
787 | } |
788 | ||
c4635eb0 KK |
789 | static int pcie_init_slot(struct controller *ctrl) |
790 | { | |
791 | struct slot *slot; | |
792 | ||
793 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
794 | if (!slot) | |
795 | return -ENOMEM; | |
796 | ||
c4635eb0 | 797 | slot->ctrl = ctrl; |
c4635eb0 KK |
798 | mutex_init(&slot->lock); |
799 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 800 | ctrl->slot = slot; |
1da177e4 | 801 | return 0; |
1da177e4 | 802 | } |
08e7a7d2 | 803 | |
c4635eb0 KK |
804 | static void pcie_cleanup_slot(struct controller *ctrl) |
805 | { | |
8720d27d | 806 | struct slot *slot = ctrl->slot; |
c4635eb0 | 807 | cancel_delayed_work(&slot->work); |
c4635eb0 | 808 | flush_workqueue(pciehp_wq); |
a827ea30 | 809 | flush_workqueue(pciehp_ordered_wq); |
c4635eb0 KK |
810 | kfree(slot); |
811 | } | |
812 | ||
2aeeef11 | 813 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 814 | { |
2aeeef11 KK |
815 | int i; |
816 | u16 reg16; | |
385e2491 | 817 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 818 | |
2aeeef11 KK |
819 | if (!pciehp_debug) |
820 | return; | |
08e7a7d2 | 821 | |
7f2feec1 TI |
822 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
823 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
824 | pci_name(pdev), pdev->irq); | |
825 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
826 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
827 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
828 | pdev->subsystem_device); | |
829 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
830 | pdev->subsystem_vendor); | |
1518c17a KK |
831 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
832 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
833 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
834 | if (!pci_resource_len(pdev, i)) | |
835 | continue; | |
e1944c6b BH |
836 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
837 | i, &pdev->resource[i]); | |
08e7a7d2 | 838 | } |
7f2feec1 | 839 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 840 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
841 | ctrl_info(ctrl, " Attention Button : %3s\n", |
842 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
843 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
844 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
845 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
846 | MRL_SENS(ctrl) ? "yes" : "no"); | |
847 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
848 | ATTN_LED(ctrl) ? "yes" : "no"); | |
849 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
850 | PWR_LED(ctrl) ? "yes" : "no"); | |
851 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
852 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
853 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
854 | EMI(ctrl) ? "yes" : "no"); | |
855 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
856 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 857 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 858 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 859 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 860 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 861 | } |
08e7a7d2 | 862 | |
c4635eb0 | 863 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 864 | { |
c4635eb0 | 865 | struct controller *ctrl; |
f18e9625 | 866 | u32 slot_cap, link_cap; |
2aeeef11 | 867 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 868 | |
c4635eb0 KK |
869 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
870 | if (!ctrl) { | |
18b341b7 | 871 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
872 | goto abort; |
873 | } | |
f7a10e32 | 874 | ctrl->pcie = dev; |
1518c17a | 875 | if (!pci_pcie_cap(pdev)) { |
18b341b7 | 876 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 877 | goto abort_ctrl; |
08e7a7d2 | 878 | } |
322162a7 | 879 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 880 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 881 | goto abort_ctrl; |
08e7a7d2 | 882 | } |
08e7a7d2 | 883 | |
2aeeef11 | 884 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 885 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 886 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 887 | dbg_ctrl(ctrl); |
5808639b KK |
888 | /* |
889 | * Controller doesn't notify of command completion if the "No | |
890 | * Command Completed Support" bit is set in Slot Capability | |
891 | * register or the controller supports none of power | |
892 | * controller, attention led, power led and EMI. | |
893 | */ | |
894 | if (NO_CMD_CMPL(ctrl) || | |
895 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
896 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 897 | |
f18e9625 | 898 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 899 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
900 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
901 | goto abort_ctrl; | |
902 | } | |
322162a7 | 903 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
904 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
905 | ctrl->link_active_reporting = 1; | |
906 | } | |
907 | ||
c4635eb0 | 908 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 909 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 910 | goto abort_ctrl; |
08e7a7d2 | 911 | |
c4635eb0 KK |
912 | /* Disable sotfware notification */ |
913 | pcie_disable_notification(ctrl); | |
ecdde939 | 914 | |
7f2feec1 TI |
915 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
916 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
917 | pdev->subsystem_device); | |
c4635eb0 KK |
918 | |
919 | if (pcie_init_slot(ctrl)) | |
920 | goto abort_ctrl; | |
2aeeef11 | 921 | |
c4635eb0 KK |
922 | return ctrl; |
923 | ||
c4635eb0 KK |
924 | abort_ctrl: |
925 | kfree(ctrl); | |
08e7a7d2 | 926 | abort: |
c4635eb0 KK |
927 | return NULL; |
928 | } | |
929 | ||
82a9e79e | 930 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
931 | { |
932 | pcie_shutdown_notification(ctrl); | |
933 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 934 | kfree(ctrl); |
08e7a7d2 | 935 | } |