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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
[deliverable/linux.git] / drivers / pci / hotplug / pciehp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
de25968c
TS		 33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
1da177e4 36#include <linux/pci.h>
5d1b8c9e 37#include <linux/interrupt.h>
34d03419 38#include <linux/time.h>
5d1b8c9e 39
1da177e4
LT		 40#include "../pci.h"
41#include "pciehp.h"
1da177e4 42
5d386e1a
KK		 43static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
a0f018da
KK		 45static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46{
47 struct pci_dev *dev = ctrl->pci_dev;
48 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
49}
50
51static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52{
53 struct pci_dev *dev = ctrl->pci_dev;
54 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
55}
56
57static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58{
59 struct pci_dev *dev = ctrl->pci_dev;
60 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
61}
62
63static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64{
65 struct pci_dev *dev = ctrl->pci_dev;
66 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
67}
1da177e4 68
1da177e4
LT		 69/* Power Control Command */
70#define POWER_ON 0
322162a7 71#define POWER_OFF PCI_EXP_SLTCTL_PCC
1da177e4 72
48fe3915
KK		 73static irqreturn_t pcie_isr(int irq, void *dev_id);
74static void start_int_poll_timer(struct controller *ctrl, int sec);
1da177e4
LT		 75
76/* This is the interrupt polling timeout function. */
48fe3915 77static void int_poll_timeout(unsigned long data)
1da177e4 78{
48fe3915 79 struct controller *ctrl = (struct controller *)data;
1da177e4 80
1da177e4 81 /* Poll for interrupt events. regs == NULL => polling */
48fe3915 82 pcie_isr(0, ctrl);
1da177e4 83
48fe3915 84 init_timer(&ctrl->poll_timer);
1da177e4 85 if (!pciehp_poll_time)
40730d10 86 pciehp_poll_time = 2; /* default polling interval is 2 sec */
1da177e4 87
48fe3915 88 start_int_poll_timer(ctrl, pciehp_poll_time);
1da177e4
LT		 89}
90
91/* This function starts the interrupt polling timer. */
48fe3915 92static void start_int_poll_timer(struct controller *ctrl, int sec)
1da177e4 93{
48fe3915
KK		 94 /* Clamp to sane value */
95 if ((sec <= 0) || (sec > 60))
96 sec = 2;
97
98 ctrl->poll_timer.function = &int_poll_timeout;
99 ctrl->poll_timer.data = (unsigned long)ctrl;
100 ctrl->poll_timer.expires = jiffies + sec * HZ;
101 add_timer(&ctrl->poll_timer);
1da177e4
LT		 102}
103
2aeeef11
KK		 104static inline int pciehp_request_irq(struct controller *ctrl)
105{
f7a10e32 106 int retval, irq = ctrl->pcie->irq;
2aeeef11
KK		 107
108 /* Install interrupt polling timer. Start with 10 sec delay */
109 if (pciehp_poll_mode) {
110 init_timer(&ctrl->poll_timer);
111 start_int_poll_timer(ctrl, 10);
112 return 0;
113 }
114
115 /* Installs the interrupt handler */
116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 if (retval)
7f2feec1
TI		 118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
119 irq);
2aeeef11
KK		 120 return retval;
121}
122
123static inline void pciehp_free_irq(struct controller *ctrl)
124{
125 if (pciehp_poll_mode)
126 del_timer_sync(&ctrl->poll_timer);
127 else
f7a10e32 128 free_irq(ctrl->pcie->irq, ctrl);
2aeeef11
KK		 129}
130
563f1190 131static int pcie_poll_cmd(struct controller *ctrl)
6592e02a
KK		 132{
133 u16 slot_status;
322162a7 134 int err, timeout = 1000;
6592e02a 135
322162a7
KK		 136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
139 return 1;
820943b6 140 }
a5827f40 141 while (timeout > 0) {
66618bad
KK		 142 msleep(10);
143 timeout -= 10;
322162a7
KK		 144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
147 return 1;
820943b6 148 }
6592e02a
KK		 149 }
150 return 0; /* timeout */
6592e02a
KK		 151}
152
563f1190 153static void pcie_wait_cmd(struct controller *ctrl, int poll)
44ef4cef 154{
262303fe
KK		 155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
156 unsigned long timeout = msecs_to_jiffies(msecs);
157 int rc;
158
6592e02a
KK		 159 if (poll)
160 rc = pcie_poll_cmd(ctrl);
161 else
d737bdc1 162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
262303fe 163 if (!rc)
7f2feec1 164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
44ef4cef
KK		 165}
166
f4778364
KK		 167/**
168 * pcie_write_cmd - Issue controller command
c27fb883 169 * @ctrl: controller to which the command is issued
f4778364
KK		 170 * @cmd: command value written to slot control register
171 * @mask: bitmask of slot control register to be modified
172 */
c27fb883 173static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
1da177e4 174{
1da177e4
LT		 175 int retval = 0;
176 u16 slot_status;
f4778364 177 u16 slot_ctrl;
1da177e4 178
44ef4cef
KK		 179 mutex_lock(&ctrl->ctrl_lock);
180
322162a7 181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 182 if (retval) {
7f2feec1
TI		 183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
184 __func__);
44ef4cef 185 goto out;
a0f018da
KK		 186 }
187
322162a7 188 if (slot_status & PCI_EXP_SLTSTA_CC) {
5808639b
KK		 189 if (!ctrl->no_cmd_complete) {
190 /*
191 * After 1 sec and CMD_COMPLETED still not set, just
192 * proceed forward to issue the next command according
193 * to spec. Just print out the error message.
194 */
18b341b7 195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
5808639b
KK		 196 } else if (!NO_CMD_CMPL(ctrl)) {
197 /*
198 * This controller semms to notify of command completed
199 * event even though it supports none of power
200 * controller, attention led, power led and EMI.
201 */
18b341b7
TI		 202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 "wait for command completed event.\n");
5808639b
KK		 204 ctrl->no_cmd_complete = 0;
205 } else {
18b341b7
TI		 206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
207 "the controller is broken.\n");
5808639b 208 }
1da177e4
LT		 209 }
210
322162a7 211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 212 if (retval) {
7f2feec1 213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
c6b069e9 214 goto out;
1da177e4 215 }
1da177e4 216
f4778364 217 slot_ctrl &= ~mask;
b7aa1f16 218 slot_ctrl |= (cmd & mask);
f4778364 219 ctrl->cmd_busy = 1;
2d32a9ae 220 smp_mb();
322162a7 221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
f4778364 222 if (retval)
18b341b7 223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
f4778364 224
44ef4cef
KK		 225 /*
226 * Wait for command completion.
227 */
6592e02a
KK		 228 if (!retval && !ctrl->no_cmd_complete) {
229 int poll = 0;
230 /*
231 * if hotplug interrupt is not enabled or command
232 * completed interrupt is not enabled, we need to poll
233 * command completed event.
234 */
322162a7
KK		 235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
6592e02a 237 poll = 1;
d737bdc1 238 pcie_wait_cmd(ctrl, poll);
6592e02a 239 }
44ef4cef
KK		 240 out:
241 mutex_unlock(&ctrl->ctrl_lock);
1da177e4
LT		 242 return retval;
243}
244
f18e9625
KK		 245static inline int check_link_active(struct controller *ctrl)
246{
247 u16 link_status;
248
322162a7 249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
f18e9625 250 return 0;
322162a7 251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
f18e9625
KK		 252}
253
254static void pcie_wait_link_active(struct controller *ctrl)
255{
256 int timeout = 1000;
257
258 if (check_link_active(ctrl))
259 return;
260 while (timeout > 0) {
261 msleep(10);
262 timeout -= 10;
263 if (check_link_active(ctrl))
264 return;
265 }
266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
267}
268
1da177e4
LT		 269static int hpc_check_lnk_status(struct controller *ctrl)
270{
1da177e4
LT		 271 u16 lnk_status;
272 int retval = 0;
273
f18e9625
KK		 274 /*
275 * Data Link Layer Link Active Reporting must be capable for
276 * hot-plug capable downstream port. But old controller might
277 * not implement it. In this case, we wait for 1000 ms.
278 */
279 if (ctrl->link_active_reporting){
280 /* Wait for Data Link Layer Link Active bit to be set */
281 pcie_wait_link_active(ctrl);
282 /*
283 * We must wait for 100 ms after the Data Link Layer
284 * Link Active bit reads 1b before initiating a
285 * configuration access to the hot added device.
286 */
287 msleep(100);
288 } else
289 msleep(1000);
290
322162a7 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 292 if (retval) {
18b341b7 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
1da177e4
LT		 294 return retval;
295 }
296
7f2feec1 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
322162a7
KK		 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
18b341b7 300 ctrl_err(ctrl, "Link Training Error occurs \n");
1da177e4
LT		 301 retval = -1;
302 return retval;
303 }
304
1da177e4
LT		 305 return retval;
306}
307
1da177e4
LT		 308static int hpc_get_attention_status(struct slot *slot, u8 *status)
309{
48fe3915 310 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 311 u16 slot_ctrl;
312 u8 atten_led_state;
313 int retval = 0;
1da177e4 314
322162a7 315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 316 if (retval) {
7f2feec1 317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 318 return retval;
319 }
320
7f2feec1 321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
322162a7 322 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
1da177e4 323
322162a7 324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
1da177e4
LT		 325
326 switch (atten_led_state) {
327 case 0:
328 *status = 0xFF; /* Reserved */
329 break;
330 case 1:
331 *status = 1; /* On */
332 break;
333 case 2:
334 *status = 2; /* Blink */
335 break;
336 case 3:
337 *status = 0; /* Off */
338 break;
339 default:
340 *status = 0xFF;
341 break;
342 }
343
1da177e4
LT		 344 return 0;
345}
346
48fe3915 347static int hpc_get_power_status(struct slot *slot, u8 *status)
1da177e4 348{
48fe3915 349 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 350 u16 slot_ctrl;
351 u8 pwr_state;
352 int retval = 0;
1da177e4 353
322162a7 354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
1da177e4 355 if (retval) {
7f2feec1 356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
1da177e4
LT		 357 return retval;
358 }
7f2feec1 359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
322162a7 360 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
1da177e4 361
322162a7 362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
1da177e4
LT		 363
364 switch (pwr_state) {
365 case 0:
366 *status = 1;
367 break;
368 case 1:
71ad556d 369 *status = 0;
1da177e4
LT		 370 break;
371 default:
372 *status = 0xFF;
373 break;
374 }
375
1da177e4
LT		 376 return retval;
377}
378
1da177e4
LT		 379static int hpc_get_latch_status(struct slot *slot, u8 *status)
380{
48fe3915 381 struct controller *ctrl = slot->ctrl;
1da177e4 382 u16 slot_status;
322162a7 383 int retval;
1da177e4 384
322162a7 385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 386 if (retval) {
7f2feec1
TI		 387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
388 __func__);
1da177e4
LT		 389 return retval;
390 }
322162a7 391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
1da177e4
LT		 392 return 0;
393}
394
395static int hpc_get_adapter_status(struct slot *slot, u8 *status)
396{
48fe3915 397 struct controller *ctrl = slot->ctrl;
1da177e4 398 u16 slot_status;
322162a7 399 int retval;
1da177e4 400
322162a7 401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 402 if (retval) {
7f2feec1
TI		 403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
404 __func__);
1da177e4
LT		 405 return retval;
406 }
322162a7 407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
1da177e4
LT		 408 return 0;
409}
410
48fe3915 411static int hpc_query_power_fault(struct slot *slot)
1da177e4 412{
48fe3915 413 struct controller *ctrl = slot->ctrl;
1da177e4 414 u16 slot_status;
322162a7 415 int retval;
1da177e4 416
322162a7 417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
1da177e4 418 if (retval) {
18b341b7 419 ctrl_err(ctrl, "Cannot check for power fault\n");
1da177e4
LT		 420 return retval;
421 }
322162a7 422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
1da177e4
LT		 423}
424
34d03419
KCA		 425static int hpc_get_emi_status(struct slot *slot, u8 *status)
426{
427 struct controller *ctrl = slot->ctrl;
428 u16 slot_status;
322162a7 429 int retval;
34d03419 430
322162a7 431 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
34d03419 432 if (retval) {
18b341b7 433 ctrl_err(ctrl, "Cannot check EMI status\n");
34d03419
KCA		 434 return retval;
435 }
322162a7 436 *status = !!(slot_status & PCI_EXP_SLTSTA_EIS);
34d03419
KCA		 437 return retval;
438}
439
440static int hpc_toggle_emi(struct slot *slot)
441{
f4778364
KK		 442 u16 slot_cmd;
443 u16 cmd_mask;
444 int rc;
34d03419 445
322162a7
KK		 446 slot_cmd = PCI_EXP_SLTCTL_EIC;
447 cmd_mask = PCI_EXP_SLTCTL_EIC;
c27fb883 448 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
34d03419 449 slot->last_emi_toggle = get_seconds();
c8426483 450
34d03419
KCA		 451 return rc;
452}
453
1da177e4
LT		 454static int hpc_set_attention_status(struct slot *slot, u8 value)
455{
48fe3915 456 struct controller *ctrl = slot->ctrl;
f4778364
KK		 457 u16 slot_cmd;
458 u16 cmd_mask;
459 int rc;
1da177e4 460
322162a7 461 cmd_mask = PCI_EXP_SLTCTL_AIC;
1da177e4
LT		 462 switch (value) {
463 case 0 : /* turn off */
f4778364 464 slot_cmd = 0x00C0;
1da177e4
LT		 465 break;
466 case 1: /* turn on */
f4778364 467 slot_cmd = 0x0040;
1da177e4
LT		 468 break;
469 case 2: /* turn blink */
f4778364 470 slot_cmd = 0x0080;
1da177e4
LT		 471 break;
472 default:
473 return -1;
474 }
c27fb883 475 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 476 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 477 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
71ad556d 478
1da177e4
LT		 479 return rc;
480}
481
1da177e4
LT		 482static void hpc_set_green_led_on(struct slot *slot)
483{
48fe3915 484 struct controller *ctrl = slot->ctrl;
1da177e4 485 u16 slot_cmd;
f4778364 486 u16 cmd_mask;
71ad556d 487
f4778364 488 slot_cmd = 0x0100;
322162a7 489 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 490 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 491 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 492 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 493}
494
495static void hpc_set_green_led_off(struct slot *slot)
496{
48fe3915 497 struct controller *ctrl = slot->ctrl;
1da177e4 498 u16 slot_cmd;
f4778364 499 u16 cmd_mask;
1da177e4 500
f4778364 501 slot_cmd = 0x0300;
322162a7 502 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 503 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 504 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 505 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 506}
507
508static void hpc_set_green_led_blink(struct slot *slot)
509{
48fe3915 510 struct controller *ctrl = slot->ctrl;
1da177e4 511 u16 slot_cmd;
f4778364 512 u16 cmd_mask;
71ad556d 513
f4778364 514 slot_cmd = 0x0200;
322162a7 515 cmd_mask = PCI_EXP_SLTCTL_PIC;
c27fb883 516 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
7f2feec1 517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 518 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4
LT		 519}
520
1da177e4
LT		 521static int hpc_power_on_slot(struct slot * slot)
522{
48fe3915 523 struct controller *ctrl = slot->ctrl;
1da177e4 524 u16 slot_cmd;
f4778364
KK		 525 u16 cmd_mask;
526 u16 slot_status;
1da177e4
LT		 527 int retval = 0;
528
7f2feec1 529 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
1da177e4 530
5a49f203 531 /* Clear sticky power-fault bit from previous power failures */
322162a7 532 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
a0f018da 533 if (retval) {
7f2feec1
TI		 534 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
535 __func__);
a0f018da
KK		 536 return retval;
537 }
322162a7 538 slot_status &= PCI_EXP_SLTSTA_PFD;
a0f018da 539 if (slot_status) {
322162a7 540 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
a0f018da 541 if (retval) {
7f2feec1
TI		 542 ctrl_err(ctrl,
543 "%s: Cannot write to SLOTSTATUS register\n",
544 __func__);
a0f018da
KK		 545 return retval;
546 }
547 }
1da177e4 548
f4778364 549 slot_cmd = POWER_ON;
322162a7 550 cmd_mask = PCI_EXP_SLTCTL_PCC;
f4778364 551 if (!pciehp_poll_mode) {
99f0169c
KK		 552 /* Enable power fault detection turned off at power off time */
553 slot_cmd |= PCI_EXP_SLTCTL_PFDE;
554 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
f4778364 555 }
1da177e4 556
c27fb883 557 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4 558 if (retval) {
18b341b7 559 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
99f0169c 560 return retval;
1da177e4 561 }
7f2feec1 562 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 563 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
1da177e4 564
99f0169c 565 ctrl->power_fault_detected = 0;
1da177e4
LT		 566 return retval;
567}
568
f1050a35
KK		 569static inline int pcie_mask_bad_dllp(struct controller *ctrl)
570{
571 struct pci_dev *dev = ctrl->pci_dev;
572 int pos;
573 u32 reg;
574
575 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
576 if (!pos)
577 return 0;
578 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
579 if (reg & PCI_ERR_COR_BAD_DLLP)
580 return 0;
581 reg |= PCI_ERR_COR_BAD_DLLP;
582 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
583 return 1;
584}
585
586static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
587{
588 struct pci_dev *dev = ctrl->pci_dev;
589 u32 reg;
590 int pos;
591
592 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
593 if (!pos)
594 return;
595 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
596 if (!(reg & PCI_ERR_COR_BAD_DLLP))
597 return;
598 reg &= ~PCI_ERR_COR_BAD_DLLP;
599 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
600}
601
1da177e4
LT		 602static int hpc_power_off_slot(struct slot * slot)
603{
48fe3915 604 struct controller *ctrl = slot->ctrl;
1da177e4 605 u16 slot_cmd;
f4778364 606 u16 cmd_mask;
1da177e4 607 int retval = 0;
f1050a35 608 int changed;
1da177e4 609
7f2feec1 610 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
1da177e4 611
f1050a35
KK		 612 /*
613 * Set Bad DLLP Mask bit in Correctable Error Mask
614 * Register. This is the workaround against Bad DLLP error
615 * that sometimes happens during turning power off the slot
616 * which conforms to PCI Express 1.0a spec.
617 */
618 changed = pcie_mask_bad_dllp(ctrl);
619
f4778364 620 slot_cmd = POWER_OFF;
322162a7 621 cmd_mask = PCI_EXP_SLTCTL_PCC;
f4778364 622 if (!pciehp_poll_mode) {
99f0169c
KK		 623 /* Disable power fault detection */
624 slot_cmd &= ~PCI_EXP_SLTCTL_PFDE;
625 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
f4778364 626 }
1da177e4 627
c27fb883 628 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
1da177e4 629 if (retval) {
18b341b7 630 ctrl_err(ctrl, "Write command failed!\n");
c1ef5cbd
KK		 631 retval = -1;
632 goto out;
1da177e4 633 }
7f2feec1 634 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
322162a7 635 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
c1ef5cbd 636 out:
f1050a35
KK		 637 if (changed)
638 pcie_unmask_bad_dllp(ctrl);
639
1da177e4
LT		 640 return retval;
641}
642
48fe3915 643static irqreturn_t pcie_isr(int irq, void *dev_id)
1da177e4 644{
48fe3915 645 struct controller *ctrl = (struct controller *)dev_id;
c6b069e9 646 u16 detected, intr_loc;
dbd79aed 647 struct slot *p_slot;
1da177e4 648
c6b069e9
KK		 649 /*
650 * In order to guarantee that all interrupt events are
651 * serviced, we need to re-inspect Slot Status register after
652 * clearing what is presumed to be the last pending interrupt.
653 */
654 intr_loc = 0;
655 do {
322162a7 656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
7f2feec1
TI		 657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658 __func__);
1da177e4
LT		 659 return IRQ_NONE;
660 }
661
322162a7
KK		 662 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
663 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
664 PCI_EXP_SLTSTA_CC);
81b840cd 665 detected &= ~intr_loc;
c6b069e9
KK		 666 intr_loc |= detected;
667 if (!intr_loc)
1da177e4 668 return IRQ_NONE;
81b840cd 669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
7f2feec1
TI		 670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
671 __func__);
1da177e4
LT		 672 return IRQ_NONE;
673 }
c6b069e9 674 } while (detected);
71ad556d 675
7f2feec1 676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
71ad556d 677
c6b069e9 678 /* Check Command Complete Interrupt Pending */
322162a7 679 if (intr_loc & PCI_EXP_SLTSTA_CC) {
262303fe 680 ctrl->cmd_busy = 0;
2d32a9ae 681 smp_mb();
d737bdc1 682 wake_up(&ctrl->queue);
1da177e4
LT		 683 }
684
322162a7 685 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
dbd79aed
KK		 686 return IRQ_HANDLED;
687
dbd79aed 688 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
dbd79aed 689
c6b069e9 690 /* Check MRL Sensor Changed */
322162a7 691 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
dbd79aed 692 pciehp_handle_switch_change(p_slot);
48fe3915 693
c6b069e9 694 /* Check Attention Button Pressed */
322162a7 695 if (intr_loc & PCI_EXP_SLTSTA_ABP)
dbd79aed 696 pciehp_handle_attention_button(p_slot);
48fe3915 697
c6b069e9 698 /* Check Presence Detect Changed */
322162a7 699 if (intr_loc & PCI_EXP_SLTSTA_PDC)
dbd79aed 700 pciehp_handle_presence_change(p_slot);
48fe3915 701
c6b069e9 702 /* Check Power Fault Detected */
99f0169c
KK		 703 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
704 ctrl->power_fault_detected = 1;
dbd79aed 705 pciehp_handle_power_fault(p_slot);
99f0169c 706 }
1da177e4
LT		 707 return IRQ_HANDLED;
708}
709
40730d10 710static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 711{
48fe3915 712 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 713 enum pcie_link_speed lnk_speed;
714 u32 lnk_cap;
715 int retval = 0;
716
322162a7 717 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
1da177e4 718 if (retval) {
7f2feec1 719 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 720 return retval;
721 }
722
723 switch (lnk_cap & 0x000F) {
724 case 1:
725 lnk_speed = PCIE_2PT5GB;
726 break;
727 default:
728 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
729 break;
730 }
731
732 *value = lnk_speed;
7f2feec1 733 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
c8426483 734
1da177e4
LT		 735 return retval;
736}
737
40730d10
KK		 738static int hpc_get_max_lnk_width(struct slot *slot,
739 enum pcie_link_width *value)
1da177e4 740{
48fe3915 741 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 742 enum pcie_link_width lnk_wdth;
743 u32 lnk_cap;
744 int retval = 0;
745
322162a7 746 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
1da177e4 747 if (retval) {
7f2feec1 748 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1da177e4
LT		 749 return retval;
750 }
751
322162a7 752 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
1da177e4
LT		 753 case 0:
754 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
755 break;
756 case 1:
757 lnk_wdth = PCIE_LNK_X1;
758 break;
759 case 2:
760 lnk_wdth = PCIE_LNK_X2;
761 break;
762 case 4:
763 lnk_wdth = PCIE_LNK_X4;
764 break;
765 case 8:
766 lnk_wdth = PCIE_LNK_X8;
767 break;
768 case 12:
769 lnk_wdth = PCIE_LNK_X12;
770 break;
771 case 16:
772 lnk_wdth = PCIE_LNK_X16;
773 break;
774 case 32:
775 lnk_wdth = PCIE_LNK_X32;
776 break;
777 default:
778 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
779 break;
780 }
781
782 *value = lnk_wdth;
7f2feec1 783 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
c8426483 784
1da177e4
LT		 785 return retval;
786}
787
40730d10 788static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
1da177e4 789{
48fe3915 790 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 791 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
792 int retval = 0;
793 u16 lnk_status;
794
322162a7 795 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 796 if (retval) {
7f2feec1
TI		 797 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
798 __func__);
1da177e4
LT		 799 return retval;
800 }
801
322162a7 802 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
1da177e4
LT		 803 case 1:
804 lnk_speed = PCIE_2PT5GB;
805 break;
806 default:
807 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
808 break;
809 }
810
811 *value = lnk_speed;
7f2feec1 812 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
c8426483 813
1da177e4
LT		 814 return retval;
815}
816
40730d10
KK		 817static int hpc_get_cur_lnk_width(struct slot *slot,
818 enum pcie_link_width *value)
1da177e4 819{
48fe3915 820 struct controller *ctrl = slot->ctrl;
1da177e4
LT		 821 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
822 int retval = 0;
823 u16 lnk_status;
824
322162a7 825 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
1da177e4 826 if (retval) {
7f2feec1
TI		 827 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
828 __func__);
1da177e4
LT		 829 return retval;
830 }
71ad556d 831
322162a7 832 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
1da177e4
LT		 833 case 0:
834 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
835 break;
836 case 1:
837 lnk_wdth = PCIE_LNK_X1;
838 break;
839 case 2:
840 lnk_wdth = PCIE_LNK_X2;
841 break;
842 case 4:
843 lnk_wdth = PCIE_LNK_X4;
844 break;
845 case 8:
846 lnk_wdth = PCIE_LNK_X8;
847 break;
848 case 12:
849 lnk_wdth = PCIE_LNK_X12;
850 break;
851 case 16:
852 lnk_wdth = PCIE_LNK_X16;
853 break;
854 case 32:
855 lnk_wdth = PCIE_LNK_X32;
856 break;
857 default:
858 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
859 break;
860 }
861
862 *value = lnk_wdth;
7f2feec1 863 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
c8426483 864
1da177e4
LT		 865 return retval;
866}
867
c4635eb0 868static void pcie_release_ctrl(struct controller *ctrl);
1da177e4
LT		 869static struct hpc_ops pciehp_hpc_ops = {
870 .power_on_slot = hpc_power_on_slot,
871 .power_off_slot = hpc_power_off_slot,
872 .set_attention_status = hpc_set_attention_status,
873 .get_power_status = hpc_get_power_status,
874 .get_attention_status = hpc_get_attention_status,
875 .get_latch_status = hpc_get_latch_status,
876 .get_adapter_status = hpc_get_adapter_status,
34d03419
KCA		 877 .get_emi_status = hpc_get_emi_status,
878 .toggle_emi = hpc_toggle_emi,
1da177e4
LT		 879
880 .get_max_bus_speed = hpc_get_max_lnk_speed,
881 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
882 .get_max_lnk_width = hpc_get_max_lnk_width,
883 .get_cur_lnk_width = hpc_get_cur_lnk_width,
71ad556d 884
1da177e4
LT		 885 .query_power_fault = hpc_query_power_fault,
886 .green_led_on = hpc_set_green_led_on,
887 .green_led_off = hpc_set_green_led_off,
888 .green_led_blink = hpc_set_green_led_blink,
71ad556d 889
c4635eb0 890 .release_ctlr = pcie_release_ctrl,
1da177e4
LT		 891 .check_lnk_status = hpc_check_lnk_status,
892};
893
c4635eb0 894int pcie_enable_notification(struct controller *ctrl)
ecdde939 895{
c27fb883 896 u16 cmd, mask;
1da177e4 897
322162a7 898 cmd = PCI_EXP_SLTCTL_PDCE;
ae416e6b 899 if (ATTN_BUTTN(ctrl))
322162a7 900 cmd |= PCI_EXP_SLTCTL_ABPE;
ae416e6b 901 if (POWER_CTRL(ctrl))
322162a7 902 cmd |= PCI_EXP_SLTCTL_PFDE;
ae416e6b 903 if (MRL_SENS(ctrl))
322162a7 904 cmd |= PCI_EXP_SLTCTL_MRLSCE;
c27fb883 905 if (!pciehp_poll_mode)
322162a7 906 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
c27fb883 907
322162a7
KK		 908 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
909 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
910 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
c27fb883
KK		 911
912 if (pcie_write_cmd(ctrl, cmd, mask)) {
18b341b7 913 ctrl_err(ctrl, "Cannot enable software notification\n");
125c39f7 914 return -1;
1da177e4 915 }
c4635eb0
KK		 916 return 0;
917}
918
919static void pcie_disable_notification(struct controller *ctrl)
920{
921 u16 mask;
322162a7
KK		 922 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
923 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
924 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
c4635eb0 925 if (pcie_write_cmd(ctrl, 0, mask))
18b341b7 926 ctrl_warn(ctrl, "Cannot disable software notification\n");
c4635eb0
KK		 927}
928
dbc7e1e5 929int pcie_init_notification(struct controller *ctrl)
c4635eb0
KK		 930{
931 if (pciehp_request_irq(ctrl))
932 return -1;
933 if (pcie_enable_notification(ctrl)) {
934 pciehp_free_irq(ctrl);
935 return -1;
936 }
dbc7e1e5 937 ctrl->notification_enabled = 1;
c4635eb0
KK		 938 return 0;
939}
940
941static void pcie_shutdown_notification(struct controller *ctrl)
942{
dbc7e1e5
EB		 943 if (ctrl->notification_enabled) {
944 pcie_disable_notification(ctrl);
945 pciehp_free_irq(ctrl);
946 ctrl->notification_enabled = 0;
947 }
c4635eb0
KK		 948}
949
c4635eb0
KK		 950static int pcie_init_slot(struct controller *ctrl)
951{
952 struct slot *slot;
953
954 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
955 if (!slot)
956 return -ENOMEM;
957
958 slot->hp_slot = 0;
959 slot->ctrl = ctrl;
960 slot->bus = ctrl->pci_dev->subordinate->number;
961 slot->device = ctrl->slot_device_offset + slot->hp_slot;
962 slot->hpc_ops = ctrl->hpc_ops;
963 slot->number = ctrl->first_slot;
c4635eb0
KK		 964 mutex_init(&slot->lock);
965 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
966 list_add(&slot->slot_list, &ctrl->slot_list);
1da177e4 967 return 0;
1da177e4 968}
08e7a7d2 969
c4635eb0
KK		 970static void pcie_cleanup_slot(struct controller *ctrl)
971{
972 struct slot *slot;
973 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
974 list_del(&slot->slot_list);
975 cancel_delayed_work(&slot->work);
976 flush_scheduled_work();
977 flush_workqueue(pciehp_wq);
978 kfree(slot);
979}
980
2aeeef11 981static inline void dbg_ctrl(struct controller *ctrl)
08e7a7d2 982{
2aeeef11
KK		 983 int i;
984 u16 reg16;
985 struct pci_dev *pdev = ctrl->pci_dev;
08e7a7d2 986
2aeeef11
KK		 987 if (!pciehp_debug)
988 return;
08e7a7d2 989
7f2feec1
TI		 990 ctrl_info(ctrl, "Hotplug Controller:\n");
991 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
992 pci_name(pdev), pdev->irq);
993 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
994 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
995 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
996 pdev->subsystem_device);
997 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
998 pdev->subsystem_vendor);
999 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
2aeeef11
KK		 1000 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1001 if (!pci_resource_len(pdev, i))
1002 continue;
7f2feec1
TI		 1003 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
1004 i, (unsigned long long)pci_resource_len(pdev, i),
1005 (unsigned long long)pci_resource_start(pdev, i));
08e7a7d2 1006 }
7f2feec1
TI		 1007 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1008 ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot);
1009 ctrl_info(ctrl, " Attention Button : %3s\n",
1010 ATTN_BUTTN(ctrl) ? "yes" : "no");
1011 ctrl_info(ctrl, " Power Controller : %3s\n",
1012 POWER_CTRL(ctrl) ? "yes" : "no");
1013 ctrl_info(ctrl, " MRL Sensor : %3s\n",
1014 MRL_SENS(ctrl) ? "yes" : "no");
1015 ctrl_info(ctrl, " Attention Indicator : %3s\n",
1016 ATTN_LED(ctrl) ? "yes" : "no");
1017 ctrl_info(ctrl, " Power Indicator : %3s\n",
1018 PWR_LED(ctrl) ? "yes" : "no");
1019 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
1020 HP_SUPR_RM(ctrl) ? "yes" : "no");
1021 ctrl_info(ctrl, " EMI Present : %3s\n",
1022 EMI(ctrl) ? "yes" : "no");
1023 ctrl_info(ctrl, " Command Completed : %3s\n",
1024 NO_CMD_CMPL(ctrl) ? "no" : "yes");
322162a7 1025 pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
7f2feec1 1026 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
322162a7 1027 pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
7f2feec1 1028 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
2aeeef11 1029}
08e7a7d2 1030
c4635eb0 1031struct controller *pcie_init(struct pcie_device *dev)
2aeeef11 1032{
c4635eb0 1033 struct controller *ctrl;
f18e9625 1034 u32 slot_cap, link_cap;
2aeeef11 1035 struct pci_dev *pdev = dev->port;
08e7a7d2 1036
c4635eb0
KK		 1037 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1038 if (!ctrl) {
18b341b7 1039 dev_err(&dev->device, "%s: Out of memory\n", __func__);
c4635eb0
KK		 1040 goto abort;
1041 }
1042 INIT_LIST_HEAD(&ctrl->slot_list);
1043
f7a10e32 1044 ctrl->pcie = dev;
2aeeef11
KK		 1045 ctrl->pci_dev = pdev;
1046 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1047 if (!ctrl->cap_base) {
18b341b7 1048 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
b84346ef 1049 goto abort_ctrl;
08e7a7d2 1050 }
322162a7 1051 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
18b341b7 1052 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
b84346ef 1053 goto abort_ctrl;
08e7a7d2 1054 }
08e7a7d2 1055
2aeeef11
KK		 1056 ctrl->slot_cap = slot_cap;
1057 ctrl->first_slot = slot_cap >> 19;
1058 ctrl->slot_device_offset = 0;
1059 ctrl->num_slots = 1;
1060 ctrl->hpc_ops = &pciehp_hpc_ops;
08e7a7d2
ML		 1061 mutex_init(&ctrl->crit_sect);
1062 mutex_init(&ctrl->ctrl_lock);
08e7a7d2 1063 init_waitqueue_head(&ctrl->queue);
2aeeef11 1064 dbg_ctrl(ctrl);
5808639b
KK		 1065 /*
1066 * Controller doesn't notify of command completion if the "No
1067 * Command Completed Support" bit is set in Slot Capability
1068 * register or the controller supports none of power
1069 * controller, attention led, power led and EMI.
1070 */
1071 if (NO_CMD_CMPL(ctrl) ||
1072 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1073 ctrl->no_cmd_complete = 1;
08e7a7d2 1074
f18e9625 1075 /* Check if Data Link Layer Link Active Reporting is implemented */
322162a7 1076 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
f18e9625
KK		 1077 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1078 goto abort_ctrl;
1079 }
322162a7 1080 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
f18e9625
KK		 1081 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1082 ctrl->link_active_reporting = 1;
1083 }
1084
c4635eb0 1085 /* Clear all remaining event bits in Slot Status register */
322162a7 1086 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
c4635eb0 1087 goto abort_ctrl;
08e7a7d2 1088
c4635eb0
KK		 1089 /* Disable sotfware notification */
1090 pcie_disable_notification(ctrl);
ecdde939
ML		 1091
1092 /*
1093 * If this is the first controller to be initialized,
1094 * initialize the pciehp work queue
1095 */
1096 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1097 pciehp_wq = create_singlethread_workqueue("pciehpd");
c4635eb0
KK		 1098 if (!pciehp_wq)
1099 goto abort_ctrl;
ecdde939
ML		 1100 }
1101
7f2feec1
TI		 1102 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1103 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1104 pdev->subsystem_device);
c4635eb0
KK		 1105
1106 if (pcie_init_slot(ctrl))
1107 goto abort_ctrl;
2aeeef11 1108
c4635eb0
KK		 1109 return ctrl;
1110
c4635eb0
KK		 1111abort_ctrl:
1112 kfree(ctrl);
08e7a7d2 1113abort:
c4635eb0
KK		 1114 return NULL;
1115}
1116
1117void pcie_release_ctrl(struct controller *ctrl)
1118{
1119 pcie_shutdown_notification(ctrl);
1120 pcie_cleanup_slot(ctrl);
1121 /*
1122 * If this is the last controller to be released, destroy the
1123 * pciehp work queue
1124 */
1125 if (atomic_dec_and_test(&pciehp_num_controllers))
1126 destroy_workqueue(pciehp_wq);
1127 kfree(ctrl);
08e7a7d2 1128}
Linux kernel - Deliverables
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