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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
2aeeef11 KK |
224 | static inline int pciehp_request_irq(struct controller *ctrl) |
225 | { | |
226 | int retval, irq = ctrl->pci_dev->irq; | |
227 | ||
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
229 | if (pciehp_poll_mode) { | |
230 | init_timer(&ctrl->poll_timer); | |
231 | start_int_poll_timer(ctrl, 10); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /* Installs the interrupt handler */ | |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
237 | if (retval) | |
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | |
239 | return retval; | |
240 | } | |
241 | ||
242 | static inline void pciehp_free_irq(struct controller *ctrl) | |
243 | { | |
244 | if (pciehp_poll_mode) | |
245 | del_timer_sync(&ctrl->poll_timer); | |
246 | else | |
247 | free_irq(ctrl->pci_dev->irq, ctrl); | |
248 | } | |
249 | ||
6592e02a KK |
250 | static inline int pcie_poll_cmd(struct controller *ctrl) |
251 | { | |
252 | u16 slot_status; | |
253 | int timeout = 1000; | |
254 | ||
255 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) | |
256 | if (slot_status & CMD_COMPLETED) | |
257 | goto completed; | |
258 | for (timeout = 1000; timeout > 0; timeout -= 100) { | |
259 | msleep(100); | |
260 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) | |
261 | if (slot_status & CMD_COMPLETED) | |
262 | goto completed; | |
263 | } | |
264 | return 0; /* timeout */ | |
265 | ||
266 | completed: | |
267 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
268 | return timeout; | |
269 | } | |
270 | ||
271 | static inline int pcie_wait_cmd(struct controller *ctrl, int poll) | |
44ef4cef | 272 | { |
262303fe KK |
273 | int retval = 0; |
274 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; | |
275 | unsigned long timeout = msecs_to_jiffies(msecs); | |
276 | int rc; | |
277 | ||
6592e02a KK |
278 | if (poll) |
279 | rc = pcie_poll_cmd(ctrl); | |
280 | else | |
281 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
262303fe KK |
282 | !ctrl->cmd_busy, timeout); |
283 | if (!rc) | |
284 | dbg("Command not completed in 1000 msec\n"); | |
285 | else if (rc < 0) { | |
286 | retval = -EINTR; | |
287 | info("Command was interrupted by a signal\n"); | |
288 | } | |
44ef4cef | 289 | |
262303fe | 290 | return retval; |
44ef4cef KK |
291 | } |
292 | ||
f4778364 KK |
293 | /** |
294 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 295 | * @ctrl: controller to which the command is issued |
f4778364 KK |
296 | * @cmd: command value written to slot control register |
297 | * @mask: bitmask of slot control register to be modified | |
298 | */ | |
c27fb883 | 299 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 300 | { |
1da177e4 LT |
301 | int retval = 0; |
302 | u16 slot_status; | |
f4778364 | 303 | u16 slot_ctrl; |
1da177e4 | 304 | |
44ef4cef KK |
305 | mutex_lock(&ctrl->ctrl_lock); |
306 | ||
a0f018da | 307 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 308 | if (retval) { |
66bef8c0 | 309 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
44ef4cef | 310 | goto out; |
a0f018da KK |
311 | } |
312 | ||
5808639b KK |
313 | if (slot_status & CMD_COMPLETED) { |
314 | if (!ctrl->no_cmd_complete) { | |
315 | /* | |
316 | * After 1 sec and CMD_COMPLETED still not set, just | |
317 | * proceed forward to issue the next command according | |
318 | * to spec. Just print out the error message. | |
319 | */ | |
320 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
321 | __func__); | |
322 | } else if (!NO_CMD_CMPL(ctrl)) { | |
323 | /* | |
324 | * This controller semms to notify of command completed | |
325 | * event even though it supports none of power | |
326 | * controller, attention led, power led and EMI. | |
327 | */ | |
328 | dbg("%s: Unexpected CMD_COMPLETED. Need to wait for " | |
329 | "command completed event.\n", __func__); | |
330 | ctrl->no_cmd_complete = 0; | |
331 | } else { | |
332 | dbg("%s: Unexpected CMD_COMPLETED. Maybe the " | |
333 | "controller is broken.\n", __func__); | |
334 | } | |
1da177e4 LT |
335 | } |
336 | ||
f4778364 | 337 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 338 | if (retval) { |
66bef8c0 | 339 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 340 | goto out; |
1da177e4 | 341 | } |
1da177e4 | 342 | |
f4778364 | 343 | slot_ctrl &= ~mask; |
b7aa1f16 KK |
344 | slot_ctrl |= (cmd & mask); |
345 | /* Don't enable command completed if caller is changing it. */ | |
346 | if (!(mask & CMD_CMPL_INTR_ENABLE)) | |
347 | slot_ctrl |= CMD_CMPL_INTR_ENABLE; | |
f4778364 KK |
348 | |
349 | ctrl->cmd_busy = 1; | |
2d32a9ae | 350 | smp_mb(); |
f4778364 KK |
351 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
352 | if (retval) | |
66bef8c0 | 353 | err("%s: Cannot write to SLOTCTRL register\n", __func__); |
f4778364 | 354 | |
44ef4cef KK |
355 | /* |
356 | * Wait for command completion. | |
357 | */ | |
6592e02a KK |
358 | if (!retval && !ctrl->no_cmd_complete) { |
359 | int poll = 0; | |
360 | /* | |
361 | * if hotplug interrupt is not enabled or command | |
362 | * completed interrupt is not enabled, we need to poll | |
363 | * command completed event. | |
364 | */ | |
365 | if (!(slot_ctrl & HP_INTR_ENABLE) || | |
366 | !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) | |
367 | poll = 1; | |
368 | retval = pcie_wait_cmd(ctrl, poll); | |
369 | } | |
44ef4cef KK |
370 | out: |
371 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
372 | return retval; |
373 | } | |
374 | ||
375 | static int hpc_check_lnk_status(struct controller *ctrl) | |
376 | { | |
1da177e4 LT |
377 | u16 lnk_status; |
378 | int retval = 0; | |
379 | ||
a0f018da | 380 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 381 | if (retval) { |
66bef8c0 | 382 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
383 | return retval; |
384 | } | |
385 | ||
66bef8c0 | 386 | dbg("%s: lnk_status = %x\n", __func__, lnk_status); |
71ad556d | 387 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 | 388 | !(lnk_status & NEG_LINK_WD)) { |
66bef8c0 | 389 | err("%s : Link Training Error occurs \n", __func__); |
1da177e4 LT |
390 | retval = -1; |
391 | return retval; | |
392 | } | |
393 | ||
1da177e4 LT |
394 | return retval; |
395 | } | |
396 | ||
1da177e4 LT |
397 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
398 | { | |
48fe3915 | 399 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
400 | u16 slot_ctrl; |
401 | u8 atten_led_state; | |
402 | int retval = 0; | |
1da177e4 | 403 | |
a0f018da | 404 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 405 | if (retval) { |
66bef8c0 | 406 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
407 | return retval; |
408 | } | |
409 | ||
a0f018da | 410 | dbg("%s: SLOTCTRL %x, value read %x\n", |
66bef8c0 | 411 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
412 | |
413 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
414 | ||
415 | switch (atten_led_state) { | |
416 | case 0: | |
417 | *status = 0xFF; /* Reserved */ | |
418 | break; | |
419 | case 1: | |
420 | *status = 1; /* On */ | |
421 | break; | |
422 | case 2: | |
423 | *status = 2; /* Blink */ | |
424 | break; | |
425 | case 3: | |
426 | *status = 0; /* Off */ | |
427 | break; | |
428 | default: | |
429 | *status = 0xFF; | |
430 | break; | |
431 | } | |
432 | ||
1da177e4 LT |
433 | return 0; |
434 | } | |
435 | ||
48fe3915 | 436 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 437 | { |
48fe3915 | 438 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
439 | u16 slot_ctrl; |
440 | u8 pwr_state; | |
441 | int retval = 0; | |
1da177e4 | 442 | |
a0f018da | 443 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 444 | if (retval) { |
66bef8c0 | 445 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
446 | return retval; |
447 | } | |
a0f018da | 448 | dbg("%s: SLOTCTRL %x value read %x\n", |
66bef8c0 | 449 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
450 | |
451 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
452 | ||
453 | switch (pwr_state) { | |
454 | case 0: | |
455 | *status = 1; | |
456 | break; | |
457 | case 1: | |
71ad556d | 458 | *status = 0; |
1da177e4 LT |
459 | break; |
460 | default: | |
461 | *status = 0xFF; | |
462 | break; | |
463 | } | |
464 | ||
1da177e4 LT |
465 | return retval; |
466 | } | |
467 | ||
1da177e4 LT |
468 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
469 | { | |
48fe3915 | 470 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
471 | u16 slot_status; |
472 | int retval = 0; | |
473 | ||
a0f018da | 474 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 475 | if (retval) { |
66bef8c0 | 476 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
477 | return retval; |
478 | } | |
479 | ||
71ad556d | 480 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 481 | |
1da177e4 LT |
482 | return 0; |
483 | } | |
484 | ||
485 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
486 | { | |
48fe3915 | 487 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
488 | u16 slot_status; |
489 | u8 card_state; | |
490 | int retval = 0; | |
491 | ||
a0f018da | 492 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 493 | if (retval) { |
66bef8c0 | 494 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
495 | return retval; |
496 | } | |
497 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
498 | *status = (card_state == 1) ? 1 : 0; | |
499 | ||
1da177e4 LT |
500 | return 0; |
501 | } | |
502 | ||
48fe3915 | 503 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 504 | { |
48fe3915 | 505 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
506 | u16 slot_status; |
507 | u8 pwr_fault; | |
508 | int retval = 0; | |
1da177e4 | 509 | |
a0f018da | 510 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 511 | if (retval) { |
66bef8c0 | 512 | err("%s: Cannot check for power fault\n", __func__); |
1da177e4 LT |
513 | return retval; |
514 | } | |
515 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 516 | |
8239def1 | 517 | return pwr_fault; |
1da177e4 LT |
518 | } |
519 | ||
34d03419 KCA |
520 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
521 | { | |
522 | struct controller *ctrl = slot->ctrl; | |
523 | u16 slot_status; | |
524 | int retval = 0; | |
525 | ||
34d03419 KCA |
526 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
527 | if (retval) { | |
66bef8c0 | 528 | err("%s : Cannot check EMI status\n", __func__); |
34d03419 KCA |
529 | return retval; |
530 | } | |
531 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
532 | ||
34d03419 KCA |
533 | return retval; |
534 | } | |
535 | ||
536 | static int hpc_toggle_emi(struct slot *slot) | |
537 | { | |
f4778364 KK |
538 | u16 slot_cmd; |
539 | u16 cmd_mask; | |
540 | int rc; | |
34d03419 | 541 | |
f4778364 KK |
542 | slot_cmd = EMI_CTRL; |
543 | cmd_mask = EMI_CTRL; | |
c27fb883 | 544 | rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); |
34d03419 | 545 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 546 | |
34d03419 KCA |
547 | return rc; |
548 | } | |
549 | ||
1da177e4 LT |
550 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
551 | { | |
48fe3915 | 552 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
553 | u16 slot_cmd; |
554 | u16 cmd_mask; | |
555 | int rc; | |
1da177e4 | 556 | |
f4778364 | 557 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
558 | switch (value) { |
559 | case 0 : /* turn off */ | |
f4778364 | 560 | slot_cmd = 0x00C0; |
1da177e4 LT |
561 | break; |
562 | case 1: /* turn on */ | |
f4778364 | 563 | slot_cmd = 0x0040; |
1da177e4 LT |
564 | break; |
565 | case 2: /* turn blink */ | |
f4778364 | 566 | slot_cmd = 0x0080; |
1da177e4 LT |
567 | break; |
568 | default: | |
569 | return -1; | |
570 | } | |
c27fb883 | 571 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 572 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 573 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
71ad556d | 574 | |
1da177e4 LT |
575 | return rc; |
576 | } | |
577 | ||
1da177e4 LT |
578 | static void hpc_set_green_led_on(struct slot *slot) |
579 | { | |
48fe3915 | 580 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 581 | u16 slot_cmd; |
f4778364 | 582 | u16 cmd_mask; |
71ad556d | 583 | |
f4778364 KK |
584 | slot_cmd = 0x0100; |
585 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 586 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 587 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 588 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
589 | } |
590 | ||
591 | static void hpc_set_green_led_off(struct slot *slot) | |
592 | { | |
48fe3915 | 593 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 594 | u16 slot_cmd; |
f4778364 | 595 | u16 cmd_mask; |
1da177e4 | 596 | |
f4778364 KK |
597 | slot_cmd = 0x0300; |
598 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 599 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 600 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 601 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
602 | } |
603 | ||
604 | static void hpc_set_green_led_blink(struct slot *slot) | |
605 | { | |
48fe3915 | 606 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 607 | u16 slot_cmd; |
f4778364 | 608 | u16 cmd_mask; |
71ad556d | 609 | |
f4778364 KK |
610 | slot_cmd = 0x0200; |
611 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 612 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 613 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 614 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
615 | } |
616 | ||
1da177e4 LT |
617 | static void hpc_release_ctlr(struct controller *ctrl) |
618 | { | |
d84be093 KK |
619 | /* Mask Hot-plug Interrupt Enable */ |
620 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) | |
621 | err("%s: Cannot mask hotplut interrupt enable\n", __func__); | |
622 | ||
2aeeef11 KK |
623 | /* Free interrupt handler or interrupt polling timer */ |
624 | pciehp_free_irq(ctrl); | |
1da177e4 | 625 | |
5d386e1a KK |
626 | /* |
627 | * If this is the last controller to be released, destroy the | |
628 | * pciehp work queue | |
629 | */ | |
630 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
631 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
632 | } |
633 | ||
634 | static int hpc_power_on_slot(struct slot * slot) | |
635 | { | |
48fe3915 | 636 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 637 | u16 slot_cmd; |
f4778364 KK |
638 | u16 cmd_mask; |
639 | u16 slot_status; | |
1da177e4 LT |
640 | int retval = 0; |
641 | ||
66bef8c0 | 642 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 643 | |
5a49f203 | 644 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
645 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
646 | if (retval) { | |
66bef8c0 | 647 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
a0f018da KK |
648 | return retval; |
649 | } | |
5a49f203 | 650 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
651 | if (slot_status) { |
652 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
653 | if (retval) { | |
654 | err("%s: Cannot write to SLOTSTATUS register\n", | |
66bef8c0 | 655 | __func__); |
a0f018da KK |
656 | return retval; |
657 | } | |
658 | } | |
1da177e4 | 659 | |
f4778364 KK |
660 | slot_cmd = POWER_ON; |
661 | cmd_mask = PWR_CTRL; | |
c7ab337f | 662 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 663 | if (!pciehp_poll_mode) { |
cff00654 KK |
664 | slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
665 | PRSN_DETECT_ENABLE); | |
666 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
667 | PRSN_DETECT_ENABLE); | |
f4778364 | 668 | } |
1da177e4 | 669 | |
c27fb883 | 670 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
671 | |
672 | if (retval) { | |
66bef8c0 | 673 | err("%s: Write %x command failed!\n", __func__, slot_cmd); |
1da177e4 LT |
674 | return -1; |
675 | } | |
a0f018da | 676 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 677 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 | 678 | |
1da177e4 LT |
679 | return retval; |
680 | } | |
681 | ||
f1050a35 KK |
682 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
683 | { | |
684 | struct pci_dev *dev = ctrl->pci_dev; | |
685 | int pos; | |
686 | u32 reg; | |
687 | ||
688 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
689 | if (!pos) | |
690 | return 0; | |
691 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
692 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
693 | return 0; | |
694 | reg |= PCI_ERR_COR_BAD_DLLP; | |
695 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
696 | return 1; | |
697 | } | |
698 | ||
699 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
700 | { | |
701 | struct pci_dev *dev = ctrl->pci_dev; | |
702 | u32 reg; | |
703 | int pos; | |
704 | ||
705 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
706 | if (!pos) | |
707 | return; | |
708 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
709 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
710 | return; | |
711 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
712 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
713 | } | |
714 | ||
1da177e4 LT |
715 | static int hpc_power_off_slot(struct slot * slot) |
716 | { | |
48fe3915 | 717 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 718 | u16 slot_cmd; |
f4778364 | 719 | u16 cmd_mask; |
1da177e4 | 720 | int retval = 0; |
f1050a35 | 721 | int changed; |
1da177e4 | 722 | |
66bef8c0 | 723 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 724 | |
f1050a35 KK |
725 | /* |
726 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
727 | * Register. This is the workaround against Bad DLLP error | |
728 | * that sometimes happens during turning power off the slot | |
729 | * which conforms to PCI Express 1.0a spec. | |
730 | */ | |
731 | changed = pcie_mask_bad_dllp(ctrl); | |
732 | ||
f4778364 KK |
733 | slot_cmd = POWER_OFF; |
734 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
735 | /* |
736 | * If we get MRL or presence detect interrupts now, the isr | |
737 | * will notice the sticky power-fault bit too and issue power | |
738 | * indicator change commands. This will lead to an endless loop | |
739 | * of command completions, since the power-fault bit remains on | |
740 | * till the slot is powered on again. | |
741 | */ | |
f4778364 | 742 | if (!pciehp_poll_mode) { |
cff00654 KK |
743 | slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
744 | PRSN_DETECT_ENABLE); | |
745 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
746 | PRSN_DETECT_ENABLE); | |
f4778364 | 747 | } |
1da177e4 | 748 | |
c27fb883 | 749 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 750 | if (retval) { |
66bef8c0 | 751 | err("%s: Write command failed!\n", __func__); |
c1ef5cbd KK |
752 | retval = -1; |
753 | goto out; | |
1da177e4 | 754 | } |
a0f018da | 755 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 756 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
c1ef5cbd | 757 | out: |
f1050a35 KK |
758 | if (changed) |
759 | pcie_unmask_bad_dllp(ctrl); | |
760 | ||
1da177e4 LT |
761 | return retval; |
762 | } | |
763 | ||
48fe3915 | 764 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 765 | { |
48fe3915 | 766 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 767 | u16 detected, intr_loc; |
dbd79aed | 768 | struct slot *p_slot; |
1da177e4 | 769 | |
c6b069e9 KK |
770 | /* |
771 | * In order to guarantee that all interrupt events are | |
772 | * serviced, we need to re-inspect Slot Status register after | |
773 | * clearing what is presumed to be the last pending interrupt. | |
774 | */ | |
775 | intr_loc = 0; | |
776 | do { | |
777 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | |
778 | err("%s: Cannot read SLOTSTATUS\n", __func__); | |
1da177e4 LT |
779 | return IRQ_NONE; |
780 | } | |
781 | ||
c6b069e9 KK |
782 | detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
783 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | | |
784 | CMD_COMPLETED); | |
785 | intr_loc |= detected; | |
786 | if (!intr_loc) | |
1da177e4 | 787 | return IRQ_NONE; |
c6b069e9 KK |
788 | if (pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
789 | err("%s: Cannot write to SLOTSTATUS\n", __func__); | |
1da177e4 LT |
790 | return IRQ_NONE; |
791 | } | |
c6b069e9 | 792 | } while (detected); |
71ad556d | 793 | |
c6b069e9 | 794 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); |
71ad556d | 795 | |
c6b069e9 | 796 | /* Check Command Complete Interrupt Pending */ |
1da177e4 | 797 | if (intr_loc & CMD_COMPLETED) { |
262303fe | 798 | ctrl->cmd_busy = 0; |
2d32a9ae | 799 | smp_mb(); |
1da177e4 LT |
800 | wake_up_interruptible(&ctrl->queue); |
801 | } | |
802 | ||
dbd79aed KK |
803 | if (!(intr_loc & ~CMD_COMPLETED)) |
804 | return IRQ_HANDLED; | |
805 | ||
806 | /* | |
807 | * Return without handling events if this handler routine is | |
808 | * called before controller initialization is done. This may | |
809 | * happen if hotplug event or another interrupt that shares | |
810 | * the IRQ with pciehp arrives before slot initialization is | |
811 | * done after interrupt handler is registered. | |
812 | * | |
813 | * FIXME - Need more structural fixes. We need to be ready to | |
814 | * handle the event before installing interrupt handler. | |
815 | */ | |
816 | p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); | |
817 | if (!p_slot || !p_slot->hpc_ops) | |
818 | return IRQ_HANDLED; | |
819 | ||
c6b069e9 | 820 | /* Check MRL Sensor Changed */ |
48fe3915 | 821 | if (intr_loc & MRL_SENS_CHANGED) |
dbd79aed | 822 | pciehp_handle_switch_change(p_slot); |
48fe3915 | 823 | |
c6b069e9 | 824 | /* Check Attention Button Pressed */ |
48fe3915 | 825 | if (intr_loc & ATTN_BUTTN_PRESSED) |
dbd79aed | 826 | pciehp_handle_attention_button(p_slot); |
48fe3915 | 827 | |
c6b069e9 | 828 | /* Check Presence Detect Changed */ |
48fe3915 | 829 | if (intr_loc & PRSN_DETECT_CHANGED) |
dbd79aed | 830 | pciehp_handle_presence_change(p_slot); |
48fe3915 | 831 | |
c6b069e9 | 832 | /* Check Power Fault Detected */ |
48fe3915 | 833 | if (intr_loc & PWR_FAULT_DETECTED) |
dbd79aed | 834 | pciehp_handle_power_fault(p_slot); |
71ad556d | 835 | |
1da177e4 LT |
836 | return IRQ_HANDLED; |
837 | } | |
838 | ||
40730d10 | 839 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 840 | { |
48fe3915 | 841 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
842 | enum pcie_link_speed lnk_speed; |
843 | u32 lnk_cap; | |
844 | int retval = 0; | |
845 | ||
a0f018da | 846 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 847 | if (retval) { |
66bef8c0 | 848 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
849 | return retval; |
850 | } | |
851 | ||
852 | switch (lnk_cap & 0x000F) { | |
853 | case 1: | |
854 | lnk_speed = PCIE_2PT5GB; | |
855 | break; | |
856 | default: | |
857 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
858 | break; | |
859 | } | |
860 | ||
861 | *value = lnk_speed; | |
862 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 863 | |
1da177e4 LT |
864 | return retval; |
865 | } | |
866 | ||
40730d10 KK |
867 | static int hpc_get_max_lnk_width(struct slot *slot, |
868 | enum pcie_link_width *value) | |
1da177e4 | 869 | { |
48fe3915 | 870 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
871 | enum pcie_link_width lnk_wdth; |
872 | u32 lnk_cap; | |
873 | int retval = 0; | |
874 | ||
a0f018da | 875 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 876 | if (retval) { |
66bef8c0 | 877 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
878 | return retval; |
879 | } | |
880 | ||
881 | switch ((lnk_cap & 0x03F0) >> 4){ | |
882 | case 0: | |
883 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
884 | break; | |
885 | case 1: | |
886 | lnk_wdth = PCIE_LNK_X1; | |
887 | break; | |
888 | case 2: | |
889 | lnk_wdth = PCIE_LNK_X2; | |
890 | break; | |
891 | case 4: | |
892 | lnk_wdth = PCIE_LNK_X4; | |
893 | break; | |
894 | case 8: | |
895 | lnk_wdth = PCIE_LNK_X8; | |
896 | break; | |
897 | case 12: | |
898 | lnk_wdth = PCIE_LNK_X12; | |
899 | break; | |
900 | case 16: | |
901 | lnk_wdth = PCIE_LNK_X16; | |
902 | break; | |
903 | case 32: | |
904 | lnk_wdth = PCIE_LNK_X32; | |
905 | break; | |
906 | default: | |
907 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
908 | break; | |
909 | } | |
910 | ||
911 | *value = lnk_wdth; | |
912 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 913 | |
1da177e4 LT |
914 | return retval; |
915 | } | |
916 | ||
40730d10 | 917 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 918 | { |
48fe3915 | 919 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
920 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
921 | int retval = 0; | |
922 | u16 lnk_status; | |
923 | ||
a0f018da | 924 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 925 | if (retval) { |
66bef8c0 | 926 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
927 | return retval; |
928 | } | |
929 | ||
930 | switch (lnk_status & 0x0F) { | |
931 | case 1: | |
932 | lnk_speed = PCIE_2PT5GB; | |
933 | break; | |
934 | default: | |
935 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
936 | break; | |
937 | } | |
938 | ||
939 | *value = lnk_speed; | |
940 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 941 | |
1da177e4 LT |
942 | return retval; |
943 | } | |
944 | ||
40730d10 KK |
945 | static int hpc_get_cur_lnk_width(struct slot *slot, |
946 | enum pcie_link_width *value) | |
1da177e4 | 947 | { |
48fe3915 | 948 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
949 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
950 | int retval = 0; | |
951 | u16 lnk_status; | |
952 | ||
a0f018da | 953 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 954 | if (retval) { |
66bef8c0 | 955 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
956 | return retval; |
957 | } | |
71ad556d | 958 | |
1da177e4 LT |
959 | switch ((lnk_status & 0x03F0) >> 4){ |
960 | case 0: | |
961 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
962 | break; | |
963 | case 1: | |
964 | lnk_wdth = PCIE_LNK_X1; | |
965 | break; | |
966 | case 2: | |
967 | lnk_wdth = PCIE_LNK_X2; | |
968 | break; | |
969 | case 4: | |
970 | lnk_wdth = PCIE_LNK_X4; | |
971 | break; | |
972 | case 8: | |
973 | lnk_wdth = PCIE_LNK_X8; | |
974 | break; | |
975 | case 12: | |
976 | lnk_wdth = PCIE_LNK_X12; | |
977 | break; | |
978 | case 16: | |
979 | lnk_wdth = PCIE_LNK_X16; | |
980 | break; | |
981 | case 32: | |
982 | lnk_wdth = PCIE_LNK_X32; | |
983 | break; | |
984 | default: | |
985 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
986 | break; | |
987 | } | |
988 | ||
989 | *value = lnk_wdth; | |
990 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 991 | |
1da177e4 LT |
992 | return retval; |
993 | } | |
994 | ||
995 | static struct hpc_ops pciehp_hpc_ops = { | |
996 | .power_on_slot = hpc_power_on_slot, | |
997 | .power_off_slot = hpc_power_off_slot, | |
998 | .set_attention_status = hpc_set_attention_status, | |
999 | .get_power_status = hpc_get_power_status, | |
1000 | .get_attention_status = hpc_get_attention_status, | |
1001 | .get_latch_status = hpc_get_latch_status, | |
1002 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
1003 | .get_emi_status = hpc_get_emi_status, |
1004 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
1005 | |
1006 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
1007 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
1008 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
1009 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 1010 | |
1da177e4 LT |
1011 | .query_power_fault = hpc_query_power_fault, |
1012 | .green_led_on = hpc_set_green_led_on, | |
1013 | .green_led_off = hpc_set_green_led_off, | |
1014 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 1015 | |
1da177e4 LT |
1016 | .release_ctlr = hpc_release_ctlr, |
1017 | .check_lnk_status = hpc_check_lnk_status, | |
1018 | }; | |
1019 | ||
783c49fc | 1020 | #ifdef CONFIG_ACPI |
4ea3e58b | 1021 | static int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) |
783c49fc KA |
1022 | { |
1023 | acpi_status status; | |
1024 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); | |
1025 | struct pci_dev *pdev = dev; | |
1026 | struct pci_bus *parent; | |
b2e6e3ba | 1027 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
783c49fc KA |
1028 | |
1029 | /* | |
1030 | * Per PCI firmware specification, we should run the ACPI _OSC | |
1031 | * method to get control of hotplug hardware before using it. | |
1032 | * If an _OSC is missing, we look for an OSHP to do the same thing. | |
1033 | * To handle different BIOS behavior, we look for _OSC and OSHP | |
1034 | * within the scope of the hotplug controller and its parents, upto | |
1035 | * the host bridge under which this controller exists. | |
1036 | */ | |
1037 | while (!handle) { | |
1038 | /* | |
1039 | * This hotplug controller was not listed in the ACPI name | |
1040 | * space at all. Try to get acpi handle of parent pci bus. | |
1041 | */ | |
1042 | if (!pdev || !pdev->bus->parent) | |
1043 | break; | |
1044 | parent = pdev->bus->parent; | |
1045 | dbg("Could not find %s in acpi namespace, trying parent\n", | |
1046 | pci_name(pdev)); | |
1047 | if (!parent->self) | |
1048 | /* Parent must be a host bridge */ | |
1049 | handle = acpi_get_pci_rootbridge_handle( | |
1050 | pci_domain_nr(parent), | |
1051 | parent->number); | |
1052 | else | |
1053 | handle = DEVICE_ACPI_HANDLE( | |
1054 | &(parent->self->dev)); | |
1055 | pdev = parent->self; | |
1056 | } | |
1057 | ||
1058 | while (handle) { | |
b2e6e3ba MT |
1059 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
1060 | dbg("Trying to get hotplug control for %s \n", | |
1061 | (char *)string.pointer); | |
783c49fc | 1062 | status = pci_osc_control_set(handle, |
57d90c02 | 1063 | OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | |
783c49fc KA |
1064 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); |
1065 | if (status == AE_NOT_FOUND) | |
1066 | status = acpi_run_oshp(handle); | |
1067 | if (ACPI_SUCCESS(status)) { | |
1068 | dbg("Gained control for hotplug HW for pci %s (%s)\n", | |
b2e6e3ba | 1069 | pci_name(dev), (char *)string.pointer); |
81b26bca | 1070 | kfree(string.pointer); |
783c49fc KA |
1071 | return 0; |
1072 | } | |
1073 | if (acpi_root_bridge(handle)) | |
1074 | break; | |
1075 | chandle = handle; | |
1076 | status = acpi_get_parent(chandle, &handle); | |
1077 | if (ACPI_FAILURE(status)) | |
1078 | break; | |
1079 | } | |
1080 | ||
a53edac1 | 1081 | dbg("Cannot get control of hotplug hardware for pci %s\n", |
783c49fc | 1082 | pci_name(dev)); |
b2e6e3ba | 1083 | |
81b26bca | 1084 | kfree(string.pointer); |
783c49fc KA |
1085 | return -1; |
1086 | } | |
1087 | #endif | |
1088 | ||
ecdde939 ML |
1089 | static int pcie_init_hardware_part1(struct controller *ctrl, |
1090 | struct pcie_device *dev) | |
1da177e4 | 1091 | { |
dbd79aed KK |
1092 | /* Clear all remaining event bits in Slot Status register */ |
1093 | if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) { | |
1094 | err("%s: Cannot write to SLOTSTATUS register\n", __func__); | |
1095 | return -1; | |
1096 | } | |
1097 | ||
1da177e4 | 1098 | /* Mask Hot-plug Interrupt Enable */ |
c27fb883 KK |
1099 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) { |
1100 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); | |
ecdde939 | 1101 | return -1; |
1da177e4 | 1102 | } |
ecdde939 ML |
1103 | return 0; |
1104 | } | |
1a9ed1bf | 1105 | |
ecdde939 ML |
1106 | int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev) |
1107 | { | |
c27fb883 | 1108 | u16 cmd, mask; |
1da177e4 | 1109 | |
c27fb883 | 1110 | cmd = PRSN_DETECT_ENABLE; |
ae416e6b | 1111 | if (ATTN_BUTTN(ctrl)) |
c27fb883 | 1112 | cmd |= ATTN_BUTTN_ENABLE; |
ae416e6b | 1113 | if (POWER_CTRL(ctrl)) |
c27fb883 | 1114 | cmd |= PWR_FAULT_DETECT_ENABLE; |
ae416e6b | 1115 | if (MRL_SENS(ctrl)) |
c27fb883 KK |
1116 | cmd |= MRL_DETECT_ENABLE; |
1117 | if (!pciehp_poll_mode) | |
1118 | cmd |= HP_INTR_ENABLE; | |
1119 | ||
1120 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | | |
1121 | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE; | |
1122 | ||
1123 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
1124 | err("%s: Cannot enable software notification\n", __func__); | |
1125 | goto abort; | |
1da177e4 | 1126 | } |
71ad556d | 1127 | |
c27fb883 | 1128 | if (pciehp_force) |
a3a45ec8 | 1129 | dbg("Bypassing BIOS check for pciehp use on %s\n", |
1130 | pci_name(ctrl->pci_dev)); | |
c27fb883 KK |
1131 | else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev)) |
1132 | goto abort_disable_intr; | |
a8a2be94 | 1133 | |
1da177e4 LT |
1134 | return 0; |
1135 | ||
40730d10 | 1136 | /* We end up here for the many possible ways to fail this API. */ |
9c64f977 | 1137 | abort_disable_intr: |
c27fb883 | 1138 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE)) |
66bef8c0 | 1139 | err("%s : disabling interrupts failed\n", __func__); |
ecdde939 | 1140 | abort: |
1da177e4 LT |
1141 | return -1; |
1142 | } | |
08e7a7d2 | 1143 | |
2aeeef11 | 1144 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 1145 | { |
2aeeef11 KK |
1146 | int i; |
1147 | u16 reg16; | |
1148 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 1149 | |
2aeeef11 KK |
1150 | if (!pciehp_debug) |
1151 | return; | |
08e7a7d2 | 1152 | |
2aeeef11 KK |
1153 | dbg("Hotplug Controller:\n"); |
1154 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); | |
1155 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); | |
1156 | dbg(" Device ID : 0x%04x\n", pdev->device); | |
1157 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | |
1158 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | |
1159 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
1160 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1161 | if (!pci_resource_len(pdev, i)) | |
1162 | continue; | |
1163 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | |
1164 | (unsigned long long)pci_resource_len(pdev, i), | |
1165 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 1166 | } |
2aeeef11 KK |
1167 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1168 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | |
1169 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
1170 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | |
1171 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | |
1172 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | |
1173 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | |
1174 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
1175 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | |
5808639b | 1176 | dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); |
2aeeef11 KK |
1177 | pciehp_readw(ctrl, SLOTSTATUS, ®16); |
1178 | dbg("Slot Status : 0x%04x\n", reg16); | |
1179 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | |
1180 | dbg("Slot Control : 0x%04x\n", reg16); | |
1181 | } | |
08e7a7d2 | 1182 | |
2aeeef11 KK |
1183 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) |
1184 | { | |
1185 | u32 slot_cap; | |
1186 | struct pci_dev *pdev = dev->port; | |
08e7a7d2 | 1187 | |
2aeeef11 KK |
1188 | ctrl->pci_dev = pdev; |
1189 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1190 | if (!ctrl->cap_base) { | |
1191 | err("%s: Cannot find PCI Express capability\n", __func__); | |
08e7a7d2 ML |
1192 | goto abort; |
1193 | } | |
2aeeef11 | 1194 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
66bef8c0 | 1195 | err("%s: Cannot read SLOTCAP register\n", __func__); |
08e7a7d2 ML |
1196 | goto abort; |
1197 | } | |
08e7a7d2 | 1198 | |
2aeeef11 KK |
1199 | ctrl->slot_cap = slot_cap; |
1200 | ctrl->first_slot = slot_cap >> 19; | |
1201 | ctrl->slot_device_offset = 0; | |
1202 | ctrl->num_slots = 1; | |
1203 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1204 | mutex_init(&ctrl->crit_sect); |
1205 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1206 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1207 | dbg_ctrl(ctrl); |
5808639b KK |
1208 | /* |
1209 | * Controller doesn't notify of command completion if the "No | |
1210 | * Command Completed Support" bit is set in Slot Capability | |
1211 | * register or the controller supports none of power | |
1212 | * controller, attention led, power led and EMI. | |
1213 | */ | |
1214 | if (NO_CMD_CMPL(ctrl) || | |
1215 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
1216 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 1217 | |
2aeeef11 KK |
1218 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1219 | pdev->vendor, pdev->device, | |
1220 | pdev->subsystem_vendor, pdev->subsystem_device); | |
08e7a7d2 | 1221 | |
2aeeef11 | 1222 | if (pcie_init_hardware_part1(ctrl, dev)) |
ecdde939 ML |
1223 | goto abort; |
1224 | ||
2aeeef11 KK |
1225 | if (pciehp_request_irq(ctrl)) |
1226 | goto abort; | |
ecdde939 ML |
1227 | |
1228 | /* | |
1229 | * If this is the first controller to be initialized, | |
1230 | * initialize the pciehp work queue | |
1231 | */ | |
1232 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1233 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1234 | if (!pciehp_wq) { | |
ecdde939 ML |
1235 | goto abort_free_irq; |
1236 | } | |
1237 | } | |
1238 | ||
2aeeef11 KK |
1239 | if (pcie_init_hardware_part2(ctrl, dev)) |
1240 | goto abort_free_irq; | |
1241 | ||
1242 | return 0; | |
1243 | ||
ecdde939 | 1244 | abort_free_irq: |
2aeeef11 | 1245 | pciehp_free_irq(ctrl); |
08e7a7d2 ML |
1246 | abort: |
1247 | return -1; | |
1248 | } |