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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
2aeeef11 KK |
224 | static inline int pciehp_request_irq(struct controller *ctrl) |
225 | { | |
226 | int retval, irq = ctrl->pci_dev->irq; | |
227 | ||
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
229 | if (pciehp_poll_mode) { | |
230 | init_timer(&ctrl->poll_timer); | |
231 | start_int_poll_timer(ctrl, 10); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /* Installs the interrupt handler */ | |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
237 | if (retval) | |
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | |
239 | return retval; | |
240 | } | |
241 | ||
242 | static inline void pciehp_free_irq(struct controller *ctrl) | |
243 | { | |
244 | if (pciehp_poll_mode) | |
245 | del_timer_sync(&ctrl->poll_timer); | |
246 | else | |
247 | free_irq(ctrl->pci_dev->irq, ctrl); | |
248 | } | |
249 | ||
6592e02a KK |
250 | static inline int pcie_poll_cmd(struct controller *ctrl) |
251 | { | |
252 | u16 slot_status; | |
253 | int timeout = 1000; | |
254 | ||
255 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) | |
256 | if (slot_status & CMD_COMPLETED) | |
257 | goto completed; | |
258 | for (timeout = 1000; timeout > 0; timeout -= 100) { | |
259 | msleep(100); | |
260 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) | |
261 | if (slot_status & CMD_COMPLETED) | |
262 | goto completed; | |
263 | } | |
264 | return 0; /* timeout */ | |
265 | ||
266 | completed: | |
267 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
268 | return timeout; | |
269 | } | |
270 | ||
d737bdc1 | 271 | static inline void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 272 | { |
262303fe KK |
273 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
274 | unsigned long timeout = msecs_to_jiffies(msecs); | |
275 | int rc; | |
276 | ||
6592e02a KK |
277 | if (poll) |
278 | rc = pcie_poll_cmd(ctrl); | |
279 | else | |
d737bdc1 | 280 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe KK |
281 | if (!rc) |
282 | dbg("Command not completed in 1000 msec\n"); | |
44ef4cef KK |
283 | } |
284 | ||
f4778364 KK |
285 | /** |
286 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 287 | * @ctrl: controller to which the command is issued |
f4778364 KK |
288 | * @cmd: command value written to slot control register |
289 | * @mask: bitmask of slot control register to be modified | |
290 | */ | |
c27fb883 | 291 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 292 | { |
1da177e4 LT |
293 | int retval = 0; |
294 | u16 slot_status; | |
f4778364 | 295 | u16 slot_ctrl; |
1da177e4 | 296 | |
44ef4cef KK |
297 | mutex_lock(&ctrl->ctrl_lock); |
298 | ||
a0f018da | 299 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 300 | if (retval) { |
66bef8c0 | 301 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
44ef4cef | 302 | goto out; |
a0f018da KK |
303 | } |
304 | ||
5808639b KK |
305 | if (slot_status & CMD_COMPLETED) { |
306 | if (!ctrl->no_cmd_complete) { | |
307 | /* | |
308 | * After 1 sec and CMD_COMPLETED still not set, just | |
309 | * proceed forward to issue the next command according | |
310 | * to spec. Just print out the error message. | |
311 | */ | |
312 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
313 | __func__); | |
314 | } else if (!NO_CMD_CMPL(ctrl)) { | |
315 | /* | |
316 | * This controller semms to notify of command completed | |
317 | * event even though it supports none of power | |
318 | * controller, attention led, power led and EMI. | |
319 | */ | |
320 | dbg("%s: Unexpected CMD_COMPLETED. Need to wait for " | |
321 | "command completed event.\n", __func__); | |
322 | ctrl->no_cmd_complete = 0; | |
323 | } else { | |
324 | dbg("%s: Unexpected CMD_COMPLETED. Maybe the " | |
325 | "controller is broken.\n", __func__); | |
326 | } | |
1da177e4 LT |
327 | } |
328 | ||
f4778364 | 329 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 330 | if (retval) { |
66bef8c0 | 331 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 332 | goto out; |
1da177e4 | 333 | } |
1da177e4 | 334 | |
f4778364 | 335 | slot_ctrl &= ~mask; |
b7aa1f16 KK |
336 | slot_ctrl |= (cmd & mask); |
337 | /* Don't enable command completed if caller is changing it. */ | |
338 | if (!(mask & CMD_CMPL_INTR_ENABLE)) | |
339 | slot_ctrl |= CMD_CMPL_INTR_ENABLE; | |
f4778364 KK |
340 | |
341 | ctrl->cmd_busy = 1; | |
2d32a9ae | 342 | smp_mb(); |
f4778364 KK |
343 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
344 | if (retval) | |
66bef8c0 | 345 | err("%s: Cannot write to SLOTCTRL register\n", __func__); |
f4778364 | 346 | |
44ef4cef KK |
347 | /* |
348 | * Wait for command completion. | |
349 | */ | |
6592e02a KK |
350 | if (!retval && !ctrl->no_cmd_complete) { |
351 | int poll = 0; | |
352 | /* | |
353 | * if hotplug interrupt is not enabled or command | |
354 | * completed interrupt is not enabled, we need to poll | |
355 | * command completed event. | |
356 | */ | |
357 | if (!(slot_ctrl & HP_INTR_ENABLE) || | |
358 | !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) | |
359 | poll = 1; | |
d737bdc1 | 360 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 361 | } |
44ef4cef KK |
362 | out: |
363 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
364 | return retval; |
365 | } | |
366 | ||
367 | static int hpc_check_lnk_status(struct controller *ctrl) | |
368 | { | |
1da177e4 LT |
369 | u16 lnk_status; |
370 | int retval = 0; | |
371 | ||
a0f018da | 372 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 373 | if (retval) { |
66bef8c0 | 374 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
375 | return retval; |
376 | } | |
377 | ||
66bef8c0 | 378 | dbg("%s: lnk_status = %x\n", __func__, lnk_status); |
71ad556d | 379 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 | 380 | !(lnk_status & NEG_LINK_WD)) { |
66bef8c0 | 381 | err("%s : Link Training Error occurs \n", __func__); |
1da177e4 LT |
382 | retval = -1; |
383 | return retval; | |
384 | } | |
385 | ||
1da177e4 LT |
386 | return retval; |
387 | } | |
388 | ||
1da177e4 LT |
389 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
390 | { | |
48fe3915 | 391 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
392 | u16 slot_ctrl; |
393 | u8 atten_led_state; | |
394 | int retval = 0; | |
1da177e4 | 395 | |
a0f018da | 396 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 397 | if (retval) { |
66bef8c0 | 398 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
399 | return retval; |
400 | } | |
401 | ||
a0f018da | 402 | dbg("%s: SLOTCTRL %x, value read %x\n", |
66bef8c0 | 403 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
404 | |
405 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
406 | ||
407 | switch (atten_led_state) { | |
408 | case 0: | |
409 | *status = 0xFF; /* Reserved */ | |
410 | break; | |
411 | case 1: | |
412 | *status = 1; /* On */ | |
413 | break; | |
414 | case 2: | |
415 | *status = 2; /* Blink */ | |
416 | break; | |
417 | case 3: | |
418 | *status = 0; /* Off */ | |
419 | break; | |
420 | default: | |
421 | *status = 0xFF; | |
422 | break; | |
423 | } | |
424 | ||
1da177e4 LT |
425 | return 0; |
426 | } | |
427 | ||
48fe3915 | 428 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 429 | { |
48fe3915 | 430 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
431 | u16 slot_ctrl; |
432 | u8 pwr_state; | |
433 | int retval = 0; | |
1da177e4 | 434 | |
a0f018da | 435 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 436 | if (retval) { |
66bef8c0 | 437 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
438 | return retval; |
439 | } | |
a0f018da | 440 | dbg("%s: SLOTCTRL %x value read %x\n", |
66bef8c0 | 441 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
442 | |
443 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
444 | ||
445 | switch (pwr_state) { | |
446 | case 0: | |
447 | *status = 1; | |
448 | break; | |
449 | case 1: | |
71ad556d | 450 | *status = 0; |
1da177e4 LT |
451 | break; |
452 | default: | |
453 | *status = 0xFF; | |
454 | break; | |
455 | } | |
456 | ||
1da177e4 LT |
457 | return retval; |
458 | } | |
459 | ||
1da177e4 LT |
460 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
461 | { | |
48fe3915 | 462 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
463 | u16 slot_status; |
464 | int retval = 0; | |
465 | ||
a0f018da | 466 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 467 | if (retval) { |
66bef8c0 | 468 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
469 | return retval; |
470 | } | |
471 | ||
71ad556d | 472 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 473 | |
1da177e4 LT |
474 | return 0; |
475 | } | |
476 | ||
477 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
478 | { | |
48fe3915 | 479 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
480 | u16 slot_status; |
481 | u8 card_state; | |
482 | int retval = 0; | |
483 | ||
a0f018da | 484 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 485 | if (retval) { |
66bef8c0 | 486 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
487 | return retval; |
488 | } | |
489 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
490 | *status = (card_state == 1) ? 1 : 0; | |
491 | ||
1da177e4 LT |
492 | return 0; |
493 | } | |
494 | ||
48fe3915 | 495 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 496 | { |
48fe3915 | 497 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
498 | u16 slot_status; |
499 | u8 pwr_fault; | |
500 | int retval = 0; | |
1da177e4 | 501 | |
a0f018da | 502 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 503 | if (retval) { |
66bef8c0 | 504 | err("%s: Cannot check for power fault\n", __func__); |
1da177e4 LT |
505 | return retval; |
506 | } | |
507 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 508 | |
8239def1 | 509 | return pwr_fault; |
1da177e4 LT |
510 | } |
511 | ||
34d03419 KCA |
512 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
513 | { | |
514 | struct controller *ctrl = slot->ctrl; | |
515 | u16 slot_status; | |
516 | int retval = 0; | |
517 | ||
34d03419 KCA |
518 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
519 | if (retval) { | |
66bef8c0 | 520 | err("%s : Cannot check EMI status\n", __func__); |
34d03419 KCA |
521 | return retval; |
522 | } | |
523 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
524 | ||
34d03419 KCA |
525 | return retval; |
526 | } | |
527 | ||
528 | static int hpc_toggle_emi(struct slot *slot) | |
529 | { | |
f4778364 KK |
530 | u16 slot_cmd; |
531 | u16 cmd_mask; | |
532 | int rc; | |
34d03419 | 533 | |
f4778364 KK |
534 | slot_cmd = EMI_CTRL; |
535 | cmd_mask = EMI_CTRL; | |
c27fb883 | 536 | rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); |
34d03419 | 537 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 538 | |
34d03419 KCA |
539 | return rc; |
540 | } | |
541 | ||
1da177e4 LT |
542 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
543 | { | |
48fe3915 | 544 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
545 | u16 slot_cmd; |
546 | u16 cmd_mask; | |
547 | int rc; | |
1da177e4 | 548 | |
f4778364 | 549 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
550 | switch (value) { |
551 | case 0 : /* turn off */ | |
f4778364 | 552 | slot_cmd = 0x00C0; |
1da177e4 LT |
553 | break; |
554 | case 1: /* turn on */ | |
f4778364 | 555 | slot_cmd = 0x0040; |
1da177e4 LT |
556 | break; |
557 | case 2: /* turn blink */ | |
f4778364 | 558 | slot_cmd = 0x0080; |
1da177e4 LT |
559 | break; |
560 | default: | |
561 | return -1; | |
562 | } | |
c27fb883 | 563 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 564 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 565 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
71ad556d | 566 | |
1da177e4 LT |
567 | return rc; |
568 | } | |
569 | ||
1da177e4 LT |
570 | static void hpc_set_green_led_on(struct slot *slot) |
571 | { | |
48fe3915 | 572 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 573 | u16 slot_cmd; |
f4778364 | 574 | u16 cmd_mask; |
71ad556d | 575 | |
f4778364 KK |
576 | slot_cmd = 0x0100; |
577 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 578 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 579 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 580 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
581 | } |
582 | ||
583 | static void hpc_set_green_led_off(struct slot *slot) | |
584 | { | |
48fe3915 | 585 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 586 | u16 slot_cmd; |
f4778364 | 587 | u16 cmd_mask; |
1da177e4 | 588 | |
f4778364 KK |
589 | slot_cmd = 0x0300; |
590 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 591 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 592 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 593 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
594 | } |
595 | ||
596 | static void hpc_set_green_led_blink(struct slot *slot) | |
597 | { | |
48fe3915 | 598 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 599 | u16 slot_cmd; |
f4778364 | 600 | u16 cmd_mask; |
71ad556d | 601 | |
f4778364 KK |
602 | slot_cmd = 0x0200; |
603 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 604 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 605 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 606 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
607 | } |
608 | ||
1da177e4 LT |
609 | static void hpc_release_ctlr(struct controller *ctrl) |
610 | { | |
d84be093 KK |
611 | /* Mask Hot-plug Interrupt Enable */ |
612 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) | |
b30dd56d | 613 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); |
d84be093 | 614 | |
2aeeef11 KK |
615 | /* Free interrupt handler or interrupt polling timer */ |
616 | pciehp_free_irq(ctrl); | |
1da177e4 | 617 | |
5d386e1a KK |
618 | /* |
619 | * If this is the last controller to be released, destroy the | |
620 | * pciehp work queue | |
621 | */ | |
622 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
623 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
624 | } |
625 | ||
626 | static int hpc_power_on_slot(struct slot * slot) | |
627 | { | |
48fe3915 | 628 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 629 | u16 slot_cmd; |
f4778364 KK |
630 | u16 cmd_mask; |
631 | u16 slot_status; | |
1da177e4 LT |
632 | int retval = 0; |
633 | ||
66bef8c0 | 634 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 635 | |
5a49f203 | 636 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
637 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
638 | if (retval) { | |
66bef8c0 | 639 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
a0f018da KK |
640 | return retval; |
641 | } | |
5a49f203 | 642 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
643 | if (slot_status) { |
644 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
645 | if (retval) { | |
646 | err("%s: Cannot write to SLOTSTATUS register\n", | |
66bef8c0 | 647 | __func__); |
a0f018da KK |
648 | return retval; |
649 | } | |
650 | } | |
1da177e4 | 651 | |
f4778364 KK |
652 | slot_cmd = POWER_ON; |
653 | cmd_mask = PWR_CTRL; | |
c7ab337f | 654 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 655 | if (!pciehp_poll_mode) { |
cff00654 KK |
656 | slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
657 | PRSN_DETECT_ENABLE); | |
658 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
659 | PRSN_DETECT_ENABLE); | |
f4778364 | 660 | } |
1da177e4 | 661 | |
c27fb883 | 662 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
663 | |
664 | if (retval) { | |
66bef8c0 | 665 | err("%s: Write %x command failed!\n", __func__, slot_cmd); |
1da177e4 LT |
666 | return -1; |
667 | } | |
a0f018da | 668 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 669 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 | 670 | |
1da177e4 LT |
671 | return retval; |
672 | } | |
673 | ||
f1050a35 KK |
674 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
675 | { | |
676 | struct pci_dev *dev = ctrl->pci_dev; | |
677 | int pos; | |
678 | u32 reg; | |
679 | ||
680 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
681 | if (!pos) | |
682 | return 0; | |
683 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
684 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
685 | return 0; | |
686 | reg |= PCI_ERR_COR_BAD_DLLP; | |
687 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
688 | return 1; | |
689 | } | |
690 | ||
691 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
692 | { | |
693 | struct pci_dev *dev = ctrl->pci_dev; | |
694 | u32 reg; | |
695 | int pos; | |
696 | ||
697 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
698 | if (!pos) | |
699 | return; | |
700 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
701 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
702 | return; | |
703 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
704 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
705 | } | |
706 | ||
1da177e4 LT |
707 | static int hpc_power_off_slot(struct slot * slot) |
708 | { | |
48fe3915 | 709 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 710 | u16 slot_cmd; |
f4778364 | 711 | u16 cmd_mask; |
1da177e4 | 712 | int retval = 0; |
f1050a35 | 713 | int changed; |
1da177e4 | 714 | |
66bef8c0 | 715 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 716 | |
f1050a35 KK |
717 | /* |
718 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
719 | * Register. This is the workaround against Bad DLLP error | |
720 | * that sometimes happens during turning power off the slot | |
721 | * which conforms to PCI Express 1.0a spec. | |
722 | */ | |
723 | changed = pcie_mask_bad_dllp(ctrl); | |
724 | ||
f4778364 KK |
725 | slot_cmd = POWER_OFF; |
726 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
727 | /* |
728 | * If we get MRL or presence detect interrupts now, the isr | |
729 | * will notice the sticky power-fault bit too and issue power | |
730 | * indicator change commands. This will lead to an endless loop | |
731 | * of command completions, since the power-fault bit remains on | |
732 | * till the slot is powered on again. | |
733 | */ | |
f4778364 | 734 | if (!pciehp_poll_mode) { |
cff00654 KK |
735 | slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
736 | PRSN_DETECT_ENABLE); | |
737 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
738 | PRSN_DETECT_ENABLE); | |
f4778364 | 739 | } |
1da177e4 | 740 | |
c27fb883 | 741 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 742 | if (retval) { |
66bef8c0 | 743 | err("%s: Write command failed!\n", __func__); |
c1ef5cbd KK |
744 | retval = -1; |
745 | goto out; | |
1da177e4 | 746 | } |
a0f018da | 747 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 748 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
c1ef5cbd | 749 | out: |
f1050a35 KK |
750 | if (changed) |
751 | pcie_unmask_bad_dllp(ctrl); | |
752 | ||
1da177e4 LT |
753 | return retval; |
754 | } | |
755 | ||
48fe3915 | 756 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 757 | { |
48fe3915 | 758 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 759 | u16 detected, intr_loc; |
dbd79aed | 760 | struct slot *p_slot; |
1da177e4 | 761 | |
c6b069e9 KK |
762 | /* |
763 | * In order to guarantee that all interrupt events are | |
764 | * serviced, we need to re-inspect Slot Status register after | |
765 | * clearing what is presumed to be the last pending interrupt. | |
766 | */ | |
767 | intr_loc = 0; | |
768 | do { | |
769 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | |
770 | err("%s: Cannot read SLOTSTATUS\n", __func__); | |
1da177e4 LT |
771 | return IRQ_NONE; |
772 | } | |
773 | ||
c6b069e9 KK |
774 | detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
775 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | | |
776 | CMD_COMPLETED); | |
777 | intr_loc |= detected; | |
778 | if (!intr_loc) | |
1da177e4 | 779 | return IRQ_NONE; |
6a3f0849 | 780 | if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
c6b069e9 | 781 | err("%s: Cannot write to SLOTSTATUS\n", __func__); |
1da177e4 LT |
782 | return IRQ_NONE; |
783 | } | |
c6b069e9 | 784 | } while (detected); |
71ad556d | 785 | |
c6b069e9 | 786 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); |
71ad556d | 787 | |
c6b069e9 | 788 | /* Check Command Complete Interrupt Pending */ |
1da177e4 | 789 | if (intr_loc & CMD_COMPLETED) { |
262303fe | 790 | ctrl->cmd_busy = 0; |
2d32a9ae | 791 | smp_mb(); |
d737bdc1 | 792 | wake_up(&ctrl->queue); |
1da177e4 LT |
793 | } |
794 | ||
dbd79aed KK |
795 | if (!(intr_loc & ~CMD_COMPLETED)) |
796 | return IRQ_HANDLED; | |
797 | ||
798 | /* | |
799 | * Return without handling events if this handler routine is | |
800 | * called before controller initialization is done. This may | |
801 | * happen if hotplug event or another interrupt that shares | |
802 | * the IRQ with pciehp arrives before slot initialization is | |
803 | * done after interrupt handler is registered. | |
804 | * | |
805 | * FIXME - Need more structural fixes. We need to be ready to | |
806 | * handle the event before installing interrupt handler. | |
807 | */ | |
808 | p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); | |
809 | if (!p_slot || !p_slot->hpc_ops) | |
810 | return IRQ_HANDLED; | |
811 | ||
c6b069e9 | 812 | /* Check MRL Sensor Changed */ |
48fe3915 | 813 | if (intr_loc & MRL_SENS_CHANGED) |
dbd79aed | 814 | pciehp_handle_switch_change(p_slot); |
48fe3915 | 815 | |
c6b069e9 | 816 | /* Check Attention Button Pressed */ |
48fe3915 | 817 | if (intr_loc & ATTN_BUTTN_PRESSED) |
dbd79aed | 818 | pciehp_handle_attention_button(p_slot); |
48fe3915 | 819 | |
c6b069e9 | 820 | /* Check Presence Detect Changed */ |
48fe3915 | 821 | if (intr_loc & PRSN_DETECT_CHANGED) |
dbd79aed | 822 | pciehp_handle_presence_change(p_slot); |
48fe3915 | 823 | |
c6b069e9 | 824 | /* Check Power Fault Detected */ |
48fe3915 | 825 | if (intr_loc & PWR_FAULT_DETECTED) |
dbd79aed | 826 | pciehp_handle_power_fault(p_slot); |
71ad556d | 827 | |
1da177e4 LT |
828 | return IRQ_HANDLED; |
829 | } | |
830 | ||
40730d10 | 831 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 832 | { |
48fe3915 | 833 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
834 | enum pcie_link_speed lnk_speed; |
835 | u32 lnk_cap; | |
836 | int retval = 0; | |
837 | ||
a0f018da | 838 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 839 | if (retval) { |
66bef8c0 | 840 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
841 | return retval; |
842 | } | |
843 | ||
844 | switch (lnk_cap & 0x000F) { | |
845 | case 1: | |
846 | lnk_speed = PCIE_2PT5GB; | |
847 | break; | |
848 | default: | |
849 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
850 | break; | |
851 | } | |
852 | ||
853 | *value = lnk_speed; | |
854 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 855 | |
1da177e4 LT |
856 | return retval; |
857 | } | |
858 | ||
40730d10 KK |
859 | static int hpc_get_max_lnk_width(struct slot *slot, |
860 | enum pcie_link_width *value) | |
1da177e4 | 861 | { |
48fe3915 | 862 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
863 | enum pcie_link_width lnk_wdth; |
864 | u32 lnk_cap; | |
865 | int retval = 0; | |
866 | ||
a0f018da | 867 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 868 | if (retval) { |
66bef8c0 | 869 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
870 | return retval; |
871 | } | |
872 | ||
873 | switch ((lnk_cap & 0x03F0) >> 4){ | |
874 | case 0: | |
875 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
876 | break; | |
877 | case 1: | |
878 | lnk_wdth = PCIE_LNK_X1; | |
879 | break; | |
880 | case 2: | |
881 | lnk_wdth = PCIE_LNK_X2; | |
882 | break; | |
883 | case 4: | |
884 | lnk_wdth = PCIE_LNK_X4; | |
885 | break; | |
886 | case 8: | |
887 | lnk_wdth = PCIE_LNK_X8; | |
888 | break; | |
889 | case 12: | |
890 | lnk_wdth = PCIE_LNK_X12; | |
891 | break; | |
892 | case 16: | |
893 | lnk_wdth = PCIE_LNK_X16; | |
894 | break; | |
895 | case 32: | |
896 | lnk_wdth = PCIE_LNK_X32; | |
897 | break; | |
898 | default: | |
899 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
900 | break; | |
901 | } | |
902 | ||
903 | *value = lnk_wdth; | |
904 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 905 | |
1da177e4 LT |
906 | return retval; |
907 | } | |
908 | ||
40730d10 | 909 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 910 | { |
48fe3915 | 911 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
912 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
913 | int retval = 0; | |
914 | u16 lnk_status; | |
915 | ||
a0f018da | 916 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 917 | if (retval) { |
66bef8c0 | 918 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
919 | return retval; |
920 | } | |
921 | ||
922 | switch (lnk_status & 0x0F) { | |
923 | case 1: | |
924 | lnk_speed = PCIE_2PT5GB; | |
925 | break; | |
926 | default: | |
927 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
928 | break; | |
929 | } | |
930 | ||
931 | *value = lnk_speed; | |
932 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 933 | |
1da177e4 LT |
934 | return retval; |
935 | } | |
936 | ||
40730d10 KK |
937 | static int hpc_get_cur_lnk_width(struct slot *slot, |
938 | enum pcie_link_width *value) | |
1da177e4 | 939 | { |
48fe3915 | 940 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
941 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
942 | int retval = 0; | |
943 | u16 lnk_status; | |
944 | ||
a0f018da | 945 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 946 | if (retval) { |
66bef8c0 | 947 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
948 | return retval; |
949 | } | |
71ad556d | 950 | |
1da177e4 LT |
951 | switch ((lnk_status & 0x03F0) >> 4){ |
952 | case 0: | |
953 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
954 | break; | |
955 | case 1: | |
956 | lnk_wdth = PCIE_LNK_X1; | |
957 | break; | |
958 | case 2: | |
959 | lnk_wdth = PCIE_LNK_X2; | |
960 | break; | |
961 | case 4: | |
962 | lnk_wdth = PCIE_LNK_X4; | |
963 | break; | |
964 | case 8: | |
965 | lnk_wdth = PCIE_LNK_X8; | |
966 | break; | |
967 | case 12: | |
968 | lnk_wdth = PCIE_LNK_X12; | |
969 | break; | |
970 | case 16: | |
971 | lnk_wdth = PCIE_LNK_X16; | |
972 | break; | |
973 | case 32: | |
974 | lnk_wdth = PCIE_LNK_X32; | |
975 | break; | |
976 | default: | |
977 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
978 | break; | |
979 | } | |
980 | ||
981 | *value = lnk_wdth; | |
982 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 983 | |
1da177e4 LT |
984 | return retval; |
985 | } | |
986 | ||
987 | static struct hpc_ops pciehp_hpc_ops = { | |
988 | .power_on_slot = hpc_power_on_slot, | |
989 | .power_off_slot = hpc_power_off_slot, | |
990 | .set_attention_status = hpc_set_attention_status, | |
991 | .get_power_status = hpc_get_power_status, | |
992 | .get_attention_status = hpc_get_attention_status, | |
993 | .get_latch_status = hpc_get_latch_status, | |
994 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
995 | .get_emi_status = hpc_get_emi_status, |
996 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
997 | |
998 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
999 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
1000 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
1001 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 1002 | |
1da177e4 LT |
1003 | .query_power_fault = hpc_query_power_fault, |
1004 | .green_led_on = hpc_set_green_led_on, | |
1005 | .green_led_off = hpc_set_green_led_off, | |
1006 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 1007 | |
1da177e4 LT |
1008 | .release_ctlr = hpc_release_ctlr, |
1009 | .check_lnk_status = hpc_check_lnk_status, | |
1010 | }; | |
1011 | ||
ecdde939 ML |
1012 | static int pcie_init_hardware_part1(struct controller *ctrl, |
1013 | struct pcie_device *dev) | |
1da177e4 | 1014 | { |
dbd79aed KK |
1015 | /* Clear all remaining event bits in Slot Status register */ |
1016 | if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) { | |
1017 | err("%s: Cannot write to SLOTSTATUS register\n", __func__); | |
1018 | return -1; | |
1019 | } | |
1020 | ||
1da177e4 | 1021 | /* Mask Hot-plug Interrupt Enable */ |
c27fb883 KK |
1022 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) { |
1023 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); | |
ecdde939 | 1024 | return -1; |
1da177e4 | 1025 | } |
ecdde939 ML |
1026 | return 0; |
1027 | } | |
1a9ed1bf | 1028 | |
ecdde939 ML |
1029 | int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev) |
1030 | { | |
c27fb883 | 1031 | u16 cmd, mask; |
1da177e4 | 1032 | |
c27fb883 | 1033 | cmd = PRSN_DETECT_ENABLE; |
ae416e6b | 1034 | if (ATTN_BUTTN(ctrl)) |
c27fb883 | 1035 | cmd |= ATTN_BUTTN_ENABLE; |
ae416e6b | 1036 | if (POWER_CTRL(ctrl)) |
c27fb883 | 1037 | cmd |= PWR_FAULT_DETECT_ENABLE; |
ae416e6b | 1038 | if (MRL_SENS(ctrl)) |
c27fb883 KK |
1039 | cmd |= MRL_DETECT_ENABLE; |
1040 | if (!pciehp_poll_mode) | |
1041 | cmd |= HP_INTR_ENABLE; | |
1042 | ||
1043 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | | |
1044 | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE; | |
1045 | ||
1046 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
1047 | err("%s: Cannot enable software notification\n", __func__); | |
125c39f7 | 1048 | return -1; |
1da177e4 | 1049 | } |
71ad556d | 1050 | |
1da177e4 | 1051 | return 0; |
1da177e4 | 1052 | } |
08e7a7d2 | 1053 | |
2aeeef11 | 1054 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 1055 | { |
2aeeef11 KK |
1056 | int i; |
1057 | u16 reg16; | |
1058 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 1059 | |
2aeeef11 KK |
1060 | if (!pciehp_debug) |
1061 | return; | |
08e7a7d2 | 1062 | |
2aeeef11 KK |
1063 | dbg("Hotplug Controller:\n"); |
1064 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); | |
1065 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); | |
1066 | dbg(" Device ID : 0x%04x\n", pdev->device); | |
1067 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | |
1068 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | |
1069 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
1070 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1071 | if (!pci_resource_len(pdev, i)) | |
1072 | continue; | |
1073 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | |
1074 | (unsigned long long)pci_resource_len(pdev, i), | |
1075 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 1076 | } |
2aeeef11 KK |
1077 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1078 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | |
1079 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
1080 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | |
1081 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | |
1082 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | |
1083 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | |
1084 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
1085 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | |
5808639b | 1086 | dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); |
2aeeef11 KK |
1087 | pciehp_readw(ctrl, SLOTSTATUS, ®16); |
1088 | dbg("Slot Status : 0x%04x\n", reg16); | |
d8b23e8f | 1089 | pciehp_readw(ctrl, SLOTCTRL, ®16); |
2aeeef11 KK |
1090 | dbg("Slot Control : 0x%04x\n", reg16); |
1091 | } | |
08e7a7d2 | 1092 | |
2aeeef11 KK |
1093 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) |
1094 | { | |
1095 | u32 slot_cap; | |
1096 | struct pci_dev *pdev = dev->port; | |
08e7a7d2 | 1097 | |
2aeeef11 KK |
1098 | ctrl->pci_dev = pdev; |
1099 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1100 | if (!ctrl->cap_base) { | |
1101 | err("%s: Cannot find PCI Express capability\n", __func__); | |
08e7a7d2 ML |
1102 | goto abort; |
1103 | } | |
2aeeef11 | 1104 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
66bef8c0 | 1105 | err("%s: Cannot read SLOTCAP register\n", __func__); |
08e7a7d2 ML |
1106 | goto abort; |
1107 | } | |
08e7a7d2 | 1108 | |
2aeeef11 KK |
1109 | ctrl->slot_cap = slot_cap; |
1110 | ctrl->first_slot = slot_cap >> 19; | |
1111 | ctrl->slot_device_offset = 0; | |
1112 | ctrl->num_slots = 1; | |
1113 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1114 | mutex_init(&ctrl->crit_sect); |
1115 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1116 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1117 | dbg_ctrl(ctrl); |
5808639b KK |
1118 | /* |
1119 | * Controller doesn't notify of command completion if the "No | |
1120 | * Command Completed Support" bit is set in Slot Capability | |
1121 | * register or the controller supports none of power | |
1122 | * controller, attention led, power led and EMI. | |
1123 | */ | |
1124 | if (NO_CMD_CMPL(ctrl) || | |
1125 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
1126 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 1127 | |
2aeeef11 KK |
1128 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1129 | pdev->vendor, pdev->device, | |
1130 | pdev->subsystem_vendor, pdev->subsystem_device); | |
08e7a7d2 | 1131 | |
2aeeef11 | 1132 | if (pcie_init_hardware_part1(ctrl, dev)) |
ecdde939 ML |
1133 | goto abort; |
1134 | ||
2aeeef11 KK |
1135 | if (pciehp_request_irq(ctrl)) |
1136 | goto abort; | |
ecdde939 ML |
1137 | |
1138 | /* | |
1139 | * If this is the first controller to be initialized, | |
1140 | * initialize the pciehp work queue | |
1141 | */ | |
1142 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1143 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1144 | if (!pciehp_wq) { | |
ecdde939 ML |
1145 | goto abort_free_irq; |
1146 | } | |
1147 | } | |
1148 | ||
2aeeef11 KK |
1149 | if (pcie_init_hardware_part2(ctrl, dev)) |
1150 | goto abort_free_irq; | |
1151 | ||
1152 | return 0; | |
1153 | ||
ecdde939 | 1154 | abort_free_irq: |
2aeeef11 | 1155 | pciehp_free_irq(ctrl); |
08e7a7d2 ML |
1156 | abort: |
1157 | return -1; | |
1158 | } |