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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
2aeeef11 KK |
224 | static inline int pciehp_request_irq(struct controller *ctrl) |
225 | { | |
f7a10e32 | 226 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
227 | |
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
229 | if (pciehp_poll_mode) { | |
230 | init_timer(&ctrl->poll_timer); | |
231 | start_int_poll_timer(ctrl, 10); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /* Installs the interrupt handler */ | |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
237 | if (retval) | |
7f2feec1 TI |
238 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
239 | irq); | |
2aeeef11 KK |
240 | return retval; |
241 | } | |
242 | ||
243 | static inline void pciehp_free_irq(struct controller *ctrl) | |
244 | { | |
245 | if (pciehp_poll_mode) | |
246 | del_timer_sync(&ctrl->poll_timer); | |
247 | else | |
f7a10e32 | 248 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
249 | } |
250 | ||
563f1190 | 251 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
252 | { |
253 | u16 slot_status; | |
254 | int timeout = 1000; | |
255 | ||
820943b6 KK |
256 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { |
257 | if (slot_status & CMD_COMPLETED) { | |
258 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
259 | return 1; | |
260 | } | |
261 | } | |
a5827f40 | 262 | while (timeout > 0) { |
66618bad KK |
263 | msleep(10); |
264 | timeout -= 10; | |
820943b6 KK |
265 | if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { |
266 | if (slot_status & CMD_COMPLETED) { | |
267 | pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); | |
268 | return 1; | |
269 | } | |
270 | } | |
6592e02a KK |
271 | } |
272 | return 0; /* timeout */ | |
6592e02a KK |
273 | } |
274 | ||
563f1190 | 275 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 276 | { |
262303fe KK |
277 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
278 | unsigned long timeout = msecs_to_jiffies(msecs); | |
279 | int rc; | |
280 | ||
6592e02a KK |
281 | if (poll) |
282 | rc = pcie_poll_cmd(ctrl); | |
283 | else | |
d737bdc1 | 284 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 285 | if (!rc) |
7f2feec1 | 286 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
287 | } |
288 | ||
f4778364 KK |
289 | /** |
290 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 291 | * @ctrl: controller to which the command is issued |
f4778364 KK |
292 | * @cmd: command value written to slot control register |
293 | * @mask: bitmask of slot control register to be modified | |
294 | */ | |
c27fb883 | 295 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 296 | { |
1da177e4 LT |
297 | int retval = 0; |
298 | u16 slot_status; | |
f4778364 | 299 | u16 slot_ctrl; |
1da177e4 | 300 | |
44ef4cef KK |
301 | mutex_lock(&ctrl->ctrl_lock); |
302 | ||
a0f018da | 303 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 304 | if (retval) { |
7f2feec1 TI |
305 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
306 | __func__); | |
44ef4cef | 307 | goto out; |
a0f018da KK |
308 | } |
309 | ||
5808639b KK |
310 | if (slot_status & CMD_COMPLETED) { |
311 | if (!ctrl->no_cmd_complete) { | |
312 | /* | |
313 | * After 1 sec and CMD_COMPLETED still not set, just | |
314 | * proceed forward to issue the next command according | |
315 | * to spec. Just print out the error message. | |
316 | */ | |
7f2feec1 TI |
317 | ctrl_dbg(ctrl, |
318 | "%s: CMD_COMPLETED not clear after 1 sec.\n", | |
319 | __func__); | |
5808639b KK |
320 | } else if (!NO_CMD_CMPL(ctrl)) { |
321 | /* | |
322 | * This controller semms to notify of command completed | |
323 | * event even though it supports none of power | |
324 | * controller, attention led, power led and EMI. | |
325 | */ | |
7f2feec1 TI |
326 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Need to " |
327 | "wait for command completed event.\n", | |
328 | __func__); | |
5808639b KK |
329 | ctrl->no_cmd_complete = 0; |
330 | } else { | |
7f2feec1 TI |
331 | ctrl_dbg(ctrl, "%s: Unexpected CMD_COMPLETED. Maybe " |
332 | "the controller is broken.\n", __func__); | |
5808639b | 333 | } |
1da177e4 LT |
334 | } |
335 | ||
f4778364 | 336 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 337 | if (retval) { |
7f2feec1 | 338 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 339 | goto out; |
1da177e4 | 340 | } |
1da177e4 | 341 | |
f4778364 | 342 | slot_ctrl &= ~mask; |
b7aa1f16 | 343 | slot_ctrl |= (cmd & mask); |
f4778364 | 344 | ctrl->cmd_busy = 1; |
2d32a9ae | 345 | smp_mb(); |
f4778364 KK |
346 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
347 | if (retval) | |
7f2feec1 TI |
348 | ctrl_err(ctrl, "%s: Cannot write to SLOTCTRL register\n", |
349 | __func__); | |
f4778364 | 350 | |
44ef4cef KK |
351 | /* |
352 | * Wait for command completion. | |
353 | */ | |
6592e02a KK |
354 | if (!retval && !ctrl->no_cmd_complete) { |
355 | int poll = 0; | |
356 | /* | |
357 | * if hotplug interrupt is not enabled or command | |
358 | * completed interrupt is not enabled, we need to poll | |
359 | * command completed event. | |
360 | */ | |
361 | if (!(slot_ctrl & HP_INTR_ENABLE) || | |
362 | !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) | |
363 | poll = 1; | |
d737bdc1 | 364 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 365 | } |
44ef4cef KK |
366 | out: |
367 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
368 | return retval; |
369 | } | |
370 | ||
371 | static int hpc_check_lnk_status(struct controller *ctrl) | |
372 | { | |
1da177e4 LT |
373 | u16 lnk_status; |
374 | int retval = 0; | |
375 | ||
a0f018da | 376 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 377 | if (retval) { |
7f2feec1 TI |
378 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
379 | __func__); | |
1da177e4 LT |
380 | return retval; |
381 | } | |
382 | ||
7f2feec1 | 383 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
71ad556d | 384 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 | 385 | !(lnk_status & NEG_LINK_WD)) { |
7f2feec1 | 386 | ctrl_err(ctrl, "%s : Link Training Error occurs \n", __func__); |
1da177e4 LT |
387 | retval = -1; |
388 | return retval; | |
389 | } | |
390 | ||
1da177e4 LT |
391 | return retval; |
392 | } | |
393 | ||
1da177e4 LT |
394 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
395 | { | |
48fe3915 | 396 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
397 | u16 slot_ctrl; |
398 | u8 atten_led_state; | |
399 | int retval = 0; | |
1da177e4 | 400 | |
a0f018da | 401 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 402 | if (retval) { |
7f2feec1 | 403 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
404 | return retval; |
405 | } | |
406 | ||
7f2feec1 TI |
407 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", |
408 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
409 | |
410 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
411 | ||
412 | switch (atten_led_state) { | |
413 | case 0: | |
414 | *status = 0xFF; /* Reserved */ | |
415 | break; | |
416 | case 1: | |
417 | *status = 1; /* On */ | |
418 | break; | |
419 | case 2: | |
420 | *status = 2; /* Blink */ | |
421 | break; | |
422 | case 3: | |
423 | *status = 0; /* Off */ | |
424 | break; | |
425 | default: | |
426 | *status = 0xFF; | |
427 | break; | |
428 | } | |
429 | ||
1da177e4 LT |
430 | return 0; |
431 | } | |
432 | ||
48fe3915 | 433 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 434 | { |
48fe3915 | 435 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
436 | u16 slot_ctrl; |
437 | u8 pwr_state; | |
438 | int retval = 0; | |
1da177e4 | 439 | |
a0f018da | 440 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 441 | if (retval) { |
7f2feec1 | 442 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
443 | return retval; |
444 | } | |
7f2feec1 TI |
445 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", |
446 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
447 | |
448 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
449 | ||
450 | switch (pwr_state) { | |
451 | case 0: | |
452 | *status = 1; | |
453 | break; | |
454 | case 1: | |
71ad556d | 455 | *status = 0; |
1da177e4 LT |
456 | break; |
457 | default: | |
458 | *status = 0xFF; | |
459 | break; | |
460 | } | |
461 | ||
1da177e4 LT |
462 | return retval; |
463 | } | |
464 | ||
1da177e4 LT |
465 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
466 | { | |
48fe3915 | 467 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
468 | u16 slot_status; |
469 | int retval = 0; | |
470 | ||
a0f018da | 471 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 472 | if (retval) { |
7f2feec1 TI |
473 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
474 | __func__); | |
1da177e4 LT |
475 | return retval; |
476 | } | |
477 | ||
71ad556d | 478 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 479 | |
1da177e4 LT |
480 | return 0; |
481 | } | |
482 | ||
483 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
484 | { | |
48fe3915 | 485 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
486 | u16 slot_status; |
487 | u8 card_state; | |
488 | int retval = 0; | |
489 | ||
a0f018da | 490 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 491 | if (retval) { |
7f2feec1 TI |
492 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
493 | __func__); | |
1da177e4 LT |
494 | return retval; |
495 | } | |
496 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
497 | *status = (card_state == 1) ? 1 : 0; | |
498 | ||
1da177e4 LT |
499 | return 0; |
500 | } | |
501 | ||
48fe3915 | 502 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 503 | { |
48fe3915 | 504 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
505 | u16 slot_status; |
506 | u8 pwr_fault; | |
507 | int retval = 0; | |
1da177e4 | 508 | |
a0f018da | 509 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 510 | if (retval) { |
7f2feec1 | 511 | ctrl_err(ctrl, "%s: Cannot check for power fault\n", __func__); |
1da177e4 LT |
512 | return retval; |
513 | } | |
514 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 515 | |
8239def1 | 516 | return pwr_fault; |
1da177e4 LT |
517 | } |
518 | ||
34d03419 KCA |
519 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
520 | { | |
521 | struct controller *ctrl = slot->ctrl; | |
522 | u16 slot_status; | |
523 | int retval = 0; | |
524 | ||
34d03419 KCA |
525 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
526 | if (retval) { | |
7f2feec1 | 527 | ctrl_err(ctrl, "%s : Cannot check EMI status\n", __func__); |
34d03419 KCA |
528 | return retval; |
529 | } | |
530 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
531 | ||
34d03419 KCA |
532 | return retval; |
533 | } | |
534 | ||
535 | static int hpc_toggle_emi(struct slot *slot) | |
536 | { | |
f4778364 KK |
537 | u16 slot_cmd; |
538 | u16 cmd_mask; | |
539 | int rc; | |
34d03419 | 540 | |
f4778364 KK |
541 | slot_cmd = EMI_CTRL; |
542 | cmd_mask = EMI_CTRL; | |
c27fb883 | 543 | rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); |
34d03419 | 544 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 545 | |
34d03419 KCA |
546 | return rc; |
547 | } | |
548 | ||
1da177e4 LT |
549 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
550 | { | |
48fe3915 | 551 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
552 | u16 slot_cmd; |
553 | u16 cmd_mask; | |
554 | int rc; | |
1da177e4 | 555 | |
f4778364 | 556 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
557 | switch (value) { |
558 | case 0 : /* turn off */ | |
f4778364 | 559 | slot_cmd = 0x00C0; |
1da177e4 LT |
560 | break; |
561 | case 1: /* turn on */ | |
f4778364 | 562 | slot_cmd = 0x0040; |
1da177e4 LT |
563 | break; |
564 | case 2: /* turn blink */ | |
f4778364 | 565 | slot_cmd = 0x0080; |
1da177e4 LT |
566 | break; |
567 | default: | |
568 | return -1; | |
569 | } | |
c27fb883 | 570 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 TI |
571 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
572 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
71ad556d | 573 | |
1da177e4 LT |
574 | return rc; |
575 | } | |
576 | ||
1da177e4 LT |
577 | static void hpc_set_green_led_on(struct slot *slot) |
578 | { | |
48fe3915 | 579 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 580 | u16 slot_cmd; |
f4778364 | 581 | u16 cmd_mask; |
71ad556d | 582 | |
f4778364 KK |
583 | slot_cmd = 0x0100; |
584 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 585 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 TI |
586 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
587 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
588 | } |
589 | ||
590 | static void hpc_set_green_led_off(struct slot *slot) | |
591 | { | |
48fe3915 | 592 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 593 | u16 slot_cmd; |
f4778364 | 594 | u16 cmd_mask; |
1da177e4 | 595 | |
f4778364 KK |
596 | slot_cmd = 0x0300; |
597 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 598 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 TI |
599 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
600 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
601 | } |
602 | ||
603 | static void hpc_set_green_led_blink(struct slot *slot) | |
604 | { | |
48fe3915 | 605 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 606 | u16 slot_cmd; |
f4778364 | 607 | u16 cmd_mask; |
71ad556d | 608 | |
f4778364 KK |
609 | slot_cmd = 0x0200; |
610 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 611 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 TI |
612 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
613 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
614 | } |
615 | ||
1da177e4 LT |
616 | static int hpc_power_on_slot(struct slot * slot) |
617 | { | |
48fe3915 | 618 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 619 | u16 slot_cmd; |
f4778364 KK |
620 | u16 cmd_mask; |
621 | u16 slot_status; | |
1da177e4 LT |
622 | int retval = 0; |
623 | ||
7f2feec1 | 624 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 625 | |
5a49f203 | 626 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
627 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
628 | if (retval) { | |
7f2feec1 TI |
629 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
630 | __func__); | |
a0f018da KK |
631 | return retval; |
632 | } | |
5a49f203 | 633 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
634 | if (slot_status) { |
635 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
636 | if (retval) { | |
7f2feec1 TI |
637 | ctrl_err(ctrl, |
638 | "%s: Cannot write to SLOTSTATUS register\n", | |
639 | __func__); | |
a0f018da KK |
640 | return retval; |
641 | } | |
642 | } | |
1da177e4 | 643 | |
f4778364 KK |
644 | slot_cmd = POWER_ON; |
645 | cmd_mask = PWR_CTRL; | |
c7ab337f | 646 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 647 | if (!pciehp_poll_mode) { |
cff00654 KK |
648 | slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
649 | PRSN_DETECT_ENABLE); | |
650 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
651 | PRSN_DETECT_ENABLE); | |
f4778364 | 652 | } |
1da177e4 | 653 | |
c27fb883 | 654 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
655 | |
656 | if (retval) { | |
7f2feec1 TI |
657 | ctrl_err(ctrl, "%s: Write %x command failed!\n", |
658 | __func__, slot_cmd); | |
1da177e4 LT |
659 | return -1; |
660 | } | |
7f2feec1 TI |
661 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
662 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 | 663 | |
1da177e4 LT |
664 | return retval; |
665 | } | |
666 | ||
f1050a35 KK |
667 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
668 | { | |
669 | struct pci_dev *dev = ctrl->pci_dev; | |
670 | int pos; | |
671 | u32 reg; | |
672 | ||
673 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
674 | if (!pos) | |
675 | return 0; | |
676 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
677 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
678 | return 0; | |
679 | reg |= PCI_ERR_COR_BAD_DLLP; | |
680 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
681 | return 1; | |
682 | } | |
683 | ||
684 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
685 | { | |
686 | struct pci_dev *dev = ctrl->pci_dev; | |
687 | u32 reg; | |
688 | int pos; | |
689 | ||
690 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
691 | if (!pos) | |
692 | return; | |
693 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
694 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
695 | return; | |
696 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
697 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
698 | } | |
699 | ||
1da177e4 LT |
700 | static int hpc_power_off_slot(struct slot * slot) |
701 | { | |
48fe3915 | 702 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 703 | u16 slot_cmd; |
f4778364 | 704 | u16 cmd_mask; |
1da177e4 | 705 | int retval = 0; |
f1050a35 | 706 | int changed; |
1da177e4 | 707 | |
7f2feec1 | 708 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 709 | |
f1050a35 KK |
710 | /* |
711 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
712 | * Register. This is the workaround against Bad DLLP error | |
713 | * that sometimes happens during turning power off the slot | |
714 | * which conforms to PCI Express 1.0a spec. | |
715 | */ | |
716 | changed = pcie_mask_bad_dllp(ctrl); | |
717 | ||
f4778364 KK |
718 | slot_cmd = POWER_OFF; |
719 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
720 | /* |
721 | * If we get MRL or presence detect interrupts now, the isr | |
722 | * will notice the sticky power-fault bit too and issue power | |
723 | * indicator change commands. This will lead to an endless loop | |
724 | * of command completions, since the power-fault bit remains on | |
725 | * till the slot is powered on again. | |
726 | */ | |
f4778364 | 727 | if (!pciehp_poll_mode) { |
cff00654 KK |
728 | slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
729 | PRSN_DETECT_ENABLE); | |
730 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
731 | PRSN_DETECT_ENABLE); | |
f4778364 | 732 | } |
1da177e4 | 733 | |
c27fb883 | 734 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 735 | if (retval) { |
7f2feec1 | 736 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
c1ef5cbd KK |
737 | retval = -1; |
738 | goto out; | |
1da177e4 | 739 | } |
7f2feec1 TI |
740 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
741 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
c1ef5cbd | 742 | out: |
f1050a35 KK |
743 | if (changed) |
744 | pcie_unmask_bad_dllp(ctrl); | |
745 | ||
1da177e4 LT |
746 | return retval; |
747 | } | |
748 | ||
48fe3915 | 749 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 750 | { |
48fe3915 | 751 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 752 | u16 detected, intr_loc; |
dbd79aed | 753 | struct slot *p_slot; |
1da177e4 | 754 | |
c6b069e9 KK |
755 | /* |
756 | * In order to guarantee that all interrupt events are | |
757 | * serviced, we need to re-inspect Slot Status register after | |
758 | * clearing what is presumed to be the last pending interrupt. | |
759 | */ | |
760 | intr_loc = 0; | |
761 | do { | |
762 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | |
7f2feec1 TI |
763 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
764 | __func__); | |
1da177e4 LT |
765 | return IRQ_NONE; |
766 | } | |
767 | ||
c6b069e9 KK |
768 | detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
769 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | | |
770 | CMD_COMPLETED); | |
771 | intr_loc |= detected; | |
772 | if (!intr_loc) | |
1da177e4 | 773 | return IRQ_NONE; |
6a3f0849 | 774 | if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
7f2feec1 TI |
775 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
776 | __func__); | |
1da177e4 LT |
777 | return IRQ_NONE; |
778 | } | |
c6b069e9 | 779 | } while (detected); |
71ad556d | 780 | |
7f2feec1 | 781 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 782 | |
c6b069e9 | 783 | /* Check Command Complete Interrupt Pending */ |
1da177e4 | 784 | if (intr_loc & CMD_COMPLETED) { |
262303fe | 785 | ctrl->cmd_busy = 0; |
2d32a9ae | 786 | smp_mb(); |
d737bdc1 | 787 | wake_up(&ctrl->queue); |
1da177e4 LT |
788 | } |
789 | ||
dbd79aed KK |
790 | if (!(intr_loc & ~CMD_COMPLETED)) |
791 | return IRQ_HANDLED; | |
792 | ||
dbd79aed | 793 | p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); |
dbd79aed | 794 | |
c6b069e9 | 795 | /* Check MRL Sensor Changed */ |
48fe3915 | 796 | if (intr_loc & MRL_SENS_CHANGED) |
dbd79aed | 797 | pciehp_handle_switch_change(p_slot); |
48fe3915 | 798 | |
c6b069e9 | 799 | /* Check Attention Button Pressed */ |
48fe3915 | 800 | if (intr_loc & ATTN_BUTTN_PRESSED) |
dbd79aed | 801 | pciehp_handle_attention_button(p_slot); |
48fe3915 | 802 | |
c6b069e9 | 803 | /* Check Presence Detect Changed */ |
48fe3915 | 804 | if (intr_loc & PRSN_DETECT_CHANGED) |
dbd79aed | 805 | pciehp_handle_presence_change(p_slot); |
48fe3915 | 806 | |
c6b069e9 | 807 | /* Check Power Fault Detected */ |
48fe3915 | 808 | if (intr_loc & PWR_FAULT_DETECTED) |
dbd79aed | 809 | pciehp_handle_power_fault(p_slot); |
71ad556d | 810 | |
1da177e4 LT |
811 | return IRQ_HANDLED; |
812 | } | |
813 | ||
40730d10 | 814 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 815 | { |
48fe3915 | 816 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
817 | enum pcie_link_speed lnk_speed; |
818 | u32 lnk_cap; | |
819 | int retval = 0; | |
820 | ||
a0f018da | 821 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 822 | if (retval) { |
7f2feec1 | 823 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
824 | return retval; |
825 | } | |
826 | ||
827 | switch (lnk_cap & 0x000F) { | |
828 | case 1: | |
829 | lnk_speed = PCIE_2PT5GB; | |
830 | break; | |
831 | default: | |
832 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
833 | break; | |
834 | } | |
835 | ||
836 | *value = lnk_speed; | |
7f2feec1 | 837 | ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed); |
c8426483 | 838 | |
1da177e4 LT |
839 | return retval; |
840 | } | |
841 | ||
40730d10 KK |
842 | static int hpc_get_max_lnk_width(struct slot *slot, |
843 | enum pcie_link_width *value) | |
1da177e4 | 844 | { |
48fe3915 | 845 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
846 | enum pcie_link_width lnk_wdth; |
847 | u32 lnk_cap; | |
848 | int retval = 0; | |
849 | ||
a0f018da | 850 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 851 | if (retval) { |
7f2feec1 | 852 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
853 | return retval; |
854 | } | |
855 | ||
856 | switch ((lnk_cap & 0x03F0) >> 4){ | |
857 | case 0: | |
858 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
859 | break; | |
860 | case 1: | |
861 | lnk_wdth = PCIE_LNK_X1; | |
862 | break; | |
863 | case 2: | |
864 | lnk_wdth = PCIE_LNK_X2; | |
865 | break; | |
866 | case 4: | |
867 | lnk_wdth = PCIE_LNK_X4; | |
868 | break; | |
869 | case 8: | |
870 | lnk_wdth = PCIE_LNK_X8; | |
871 | break; | |
872 | case 12: | |
873 | lnk_wdth = PCIE_LNK_X12; | |
874 | break; | |
875 | case 16: | |
876 | lnk_wdth = PCIE_LNK_X16; | |
877 | break; | |
878 | case 32: | |
879 | lnk_wdth = PCIE_LNK_X32; | |
880 | break; | |
881 | default: | |
882 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
883 | break; | |
884 | } | |
885 | ||
886 | *value = lnk_wdth; | |
7f2feec1 | 887 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 888 | |
1da177e4 LT |
889 | return retval; |
890 | } | |
891 | ||
40730d10 | 892 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 893 | { |
48fe3915 | 894 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
895 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
896 | int retval = 0; | |
897 | u16 lnk_status; | |
898 | ||
a0f018da | 899 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 900 | if (retval) { |
7f2feec1 TI |
901 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
902 | __func__); | |
1da177e4 LT |
903 | return retval; |
904 | } | |
905 | ||
906 | switch (lnk_status & 0x0F) { | |
907 | case 1: | |
908 | lnk_speed = PCIE_2PT5GB; | |
909 | break; | |
910 | default: | |
911 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
912 | break; | |
913 | } | |
914 | ||
915 | *value = lnk_speed; | |
7f2feec1 | 916 | ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed); |
c8426483 | 917 | |
1da177e4 LT |
918 | return retval; |
919 | } | |
920 | ||
40730d10 KK |
921 | static int hpc_get_cur_lnk_width(struct slot *slot, |
922 | enum pcie_link_width *value) | |
1da177e4 | 923 | { |
48fe3915 | 924 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
925 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
926 | int retval = 0; | |
927 | u16 lnk_status; | |
928 | ||
a0f018da | 929 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 930 | if (retval) { |
7f2feec1 TI |
931 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
932 | __func__); | |
1da177e4 LT |
933 | return retval; |
934 | } | |
71ad556d | 935 | |
1da177e4 LT |
936 | switch ((lnk_status & 0x03F0) >> 4){ |
937 | case 0: | |
938 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
939 | break; | |
940 | case 1: | |
941 | lnk_wdth = PCIE_LNK_X1; | |
942 | break; | |
943 | case 2: | |
944 | lnk_wdth = PCIE_LNK_X2; | |
945 | break; | |
946 | case 4: | |
947 | lnk_wdth = PCIE_LNK_X4; | |
948 | break; | |
949 | case 8: | |
950 | lnk_wdth = PCIE_LNK_X8; | |
951 | break; | |
952 | case 12: | |
953 | lnk_wdth = PCIE_LNK_X12; | |
954 | break; | |
955 | case 16: | |
956 | lnk_wdth = PCIE_LNK_X16; | |
957 | break; | |
958 | case 32: | |
959 | lnk_wdth = PCIE_LNK_X32; | |
960 | break; | |
961 | default: | |
962 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
963 | break; | |
964 | } | |
965 | ||
966 | *value = lnk_wdth; | |
7f2feec1 | 967 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 968 | |
1da177e4 LT |
969 | return retval; |
970 | } | |
971 | ||
c4635eb0 | 972 | static void pcie_release_ctrl(struct controller *ctrl); |
1da177e4 LT |
973 | static struct hpc_ops pciehp_hpc_ops = { |
974 | .power_on_slot = hpc_power_on_slot, | |
975 | .power_off_slot = hpc_power_off_slot, | |
976 | .set_attention_status = hpc_set_attention_status, | |
977 | .get_power_status = hpc_get_power_status, | |
978 | .get_attention_status = hpc_get_attention_status, | |
979 | .get_latch_status = hpc_get_latch_status, | |
980 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
981 | .get_emi_status = hpc_get_emi_status, |
982 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
983 | |
984 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
985 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
986 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
987 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 988 | |
1da177e4 LT |
989 | .query_power_fault = hpc_query_power_fault, |
990 | .green_led_on = hpc_set_green_led_on, | |
991 | .green_led_off = hpc_set_green_led_off, | |
992 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 993 | |
c4635eb0 | 994 | .release_ctlr = pcie_release_ctrl, |
1da177e4 LT |
995 | .check_lnk_status = hpc_check_lnk_status, |
996 | }; | |
997 | ||
c4635eb0 | 998 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 999 | { |
c27fb883 | 1000 | u16 cmd, mask; |
1da177e4 | 1001 | |
c27fb883 | 1002 | cmd = PRSN_DETECT_ENABLE; |
ae416e6b | 1003 | if (ATTN_BUTTN(ctrl)) |
c27fb883 | 1004 | cmd |= ATTN_BUTTN_ENABLE; |
ae416e6b | 1005 | if (POWER_CTRL(ctrl)) |
c27fb883 | 1006 | cmd |= PWR_FAULT_DETECT_ENABLE; |
ae416e6b | 1007 | if (MRL_SENS(ctrl)) |
c27fb883 KK |
1008 | cmd |= MRL_DETECT_ENABLE; |
1009 | if (!pciehp_poll_mode) | |
3aa50c44 | 1010 | cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; |
c27fb883 | 1011 | |
3aa50c44 KK |
1012 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | |
1013 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | |
c27fb883 KK |
1014 | |
1015 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
7f2feec1 TI |
1016 | ctrl_err(ctrl, "%s: Cannot enable software notification\n", |
1017 | __func__); | |
125c39f7 | 1018 | return -1; |
1da177e4 | 1019 | } |
c4635eb0 KK |
1020 | return 0; |
1021 | } | |
1022 | ||
1023 | static void pcie_disable_notification(struct controller *ctrl) | |
1024 | { | |
1025 | u16 mask; | |
1026 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | | |
1027 | PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; | |
1028 | if (pcie_write_cmd(ctrl, 0, mask)) | |
7f2feec1 TI |
1029 | ctrl_warn(ctrl, "%s: Cannot disable software notification\n", |
1030 | __func__); | |
c4635eb0 KK |
1031 | } |
1032 | ||
1033 | static int pcie_init_notification(struct controller *ctrl) | |
1034 | { | |
1035 | if (pciehp_request_irq(ctrl)) | |
1036 | return -1; | |
1037 | if (pcie_enable_notification(ctrl)) { | |
1038 | pciehp_free_irq(ctrl); | |
1039 | return -1; | |
1040 | } | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static void pcie_shutdown_notification(struct controller *ctrl) | |
1045 | { | |
1046 | pcie_disable_notification(ctrl); | |
1047 | pciehp_free_irq(ctrl); | |
1048 | } | |
1049 | ||
c4635eb0 KK |
1050 | static int pcie_init_slot(struct controller *ctrl) |
1051 | { | |
1052 | struct slot *slot; | |
1053 | ||
1054 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
1055 | if (!slot) | |
1056 | return -ENOMEM; | |
1057 | ||
1058 | slot->hp_slot = 0; | |
1059 | slot->ctrl = ctrl; | |
1060 | slot->bus = ctrl->pci_dev->subordinate->number; | |
1061 | slot->device = ctrl->slot_device_offset + slot->hp_slot; | |
1062 | slot->hpc_ops = ctrl->hpc_ops; | |
1063 | slot->number = ctrl->first_slot; | |
c4635eb0 KK |
1064 | mutex_init(&slot->lock); |
1065 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
1066 | list_add(&slot->slot_list, &ctrl->slot_list); | |
1da177e4 | 1067 | return 0; |
1da177e4 | 1068 | } |
08e7a7d2 | 1069 | |
c4635eb0 KK |
1070 | static void pcie_cleanup_slot(struct controller *ctrl) |
1071 | { | |
1072 | struct slot *slot; | |
1073 | slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list); | |
1074 | list_del(&slot->slot_list); | |
1075 | cancel_delayed_work(&slot->work); | |
1076 | flush_scheduled_work(); | |
1077 | flush_workqueue(pciehp_wq); | |
1078 | kfree(slot); | |
1079 | } | |
1080 | ||
2aeeef11 | 1081 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 1082 | { |
2aeeef11 KK |
1083 | int i; |
1084 | u16 reg16; | |
1085 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 1086 | |
2aeeef11 KK |
1087 | if (!pciehp_debug) |
1088 | return; | |
08e7a7d2 | 1089 | |
7f2feec1 TI |
1090 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
1091 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
1092 | pci_name(pdev), pdev->irq); | |
1093 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
1094 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
1095 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
1096 | pdev->subsystem_device); | |
1097 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
1098 | pdev->subsystem_vendor); | |
1099 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
2aeeef11 KK |
1100 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
1101 | if (!pci_resource_len(pdev, i)) | |
1102 | continue; | |
7f2feec1 TI |
1103 | ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n", |
1104 | i, (unsigned long long)pci_resource_len(pdev, i), | |
1105 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 1106 | } |
7f2feec1 TI |
1107 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1108 | ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot); | |
1109 | ctrl_info(ctrl, " Attention Button : %3s\n", | |
1110 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
1111 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
1112 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
1113 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
1114 | MRL_SENS(ctrl) ? "yes" : "no"); | |
1115 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
1116 | ATTN_LED(ctrl) ? "yes" : "no"); | |
1117 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
1118 | PWR_LED(ctrl) ? "yes" : "no"); | |
1119 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
1120 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
1121 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
1122 | EMI(ctrl) ? "yes" : "no"); | |
1123 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
1124 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
2aeeef11 | 1125 | pciehp_readw(ctrl, SLOTSTATUS, ®16); |
7f2feec1 | 1126 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
d8b23e8f | 1127 | pciehp_readw(ctrl, SLOTCTRL, ®16); |
7f2feec1 | 1128 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 1129 | } |
08e7a7d2 | 1130 | |
c4635eb0 | 1131 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 1132 | { |
c4635eb0 | 1133 | struct controller *ctrl; |
2aeeef11 KK |
1134 | u32 slot_cap; |
1135 | struct pci_dev *pdev = dev->port; | |
08e7a7d2 | 1136 | |
c4635eb0 KK |
1137 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
1138 | if (!ctrl) { | |
7f2feec1 | 1139 | dev_err(&dev->device, "%s : out of memory\n", __func__); |
c4635eb0 KK |
1140 | goto abort; |
1141 | } | |
1142 | INIT_LIST_HEAD(&ctrl->slot_list); | |
1143 | ||
f7a10e32 | 1144 | ctrl->pcie = dev; |
2aeeef11 KK |
1145 | ctrl->pci_dev = pdev; |
1146 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1147 | if (!ctrl->cap_base) { | |
7f2feec1 TI |
1148 | ctrl_err(ctrl, "%s: Cannot find PCI Express capability\n", |
1149 | __func__); | |
b84346ef | 1150 | goto abort_ctrl; |
08e7a7d2 | 1151 | } |
2aeeef11 | 1152 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
7f2feec1 | 1153 | ctrl_err(ctrl, "%s: Cannot read SLOTCAP register\n", __func__); |
b84346ef | 1154 | goto abort_ctrl; |
08e7a7d2 | 1155 | } |
08e7a7d2 | 1156 | |
2aeeef11 KK |
1157 | ctrl->slot_cap = slot_cap; |
1158 | ctrl->first_slot = slot_cap >> 19; | |
1159 | ctrl->slot_device_offset = 0; | |
1160 | ctrl->num_slots = 1; | |
1161 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1162 | mutex_init(&ctrl->crit_sect); |
1163 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1164 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1165 | dbg_ctrl(ctrl); |
5808639b KK |
1166 | /* |
1167 | * Controller doesn't notify of command completion if the "No | |
1168 | * Command Completed Support" bit is set in Slot Capability | |
1169 | * register or the controller supports none of power | |
1170 | * controller, attention led, power led and EMI. | |
1171 | */ | |
1172 | if (NO_CMD_CMPL(ctrl) || | |
1173 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
1174 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 1175 | |
c4635eb0 KK |
1176 | /* Clear all remaining event bits in Slot Status register */ |
1177 | if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) | |
1178 | goto abort_ctrl; | |
08e7a7d2 | 1179 | |
c4635eb0 KK |
1180 | /* Disable sotfware notification */ |
1181 | pcie_disable_notification(ctrl); | |
ecdde939 ML |
1182 | |
1183 | /* | |
1184 | * If this is the first controller to be initialized, | |
1185 | * initialize the pciehp work queue | |
1186 | */ | |
1187 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1188 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
c4635eb0 KK |
1189 | if (!pciehp_wq) |
1190 | goto abort_ctrl; | |
ecdde939 ML |
1191 | } |
1192 | ||
7f2feec1 TI |
1193 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1194 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
1195 | pdev->subsystem_device); | |
c4635eb0 KK |
1196 | |
1197 | if (pcie_init_slot(ctrl)) | |
1198 | goto abort_ctrl; | |
2aeeef11 | 1199 | |
c4635eb0 KK |
1200 | if (pcie_init_notification(ctrl)) |
1201 | goto abort_slot; | |
2aeeef11 | 1202 | |
c4635eb0 KK |
1203 | return ctrl; |
1204 | ||
1205 | abort_slot: | |
1206 | pcie_cleanup_slot(ctrl); | |
1207 | abort_ctrl: | |
1208 | kfree(ctrl); | |
08e7a7d2 | 1209 | abort: |
c4635eb0 KK |
1210 | return NULL; |
1211 | } | |
1212 | ||
1213 | void pcie_release_ctrl(struct controller *ctrl) | |
1214 | { | |
1215 | pcie_shutdown_notification(ctrl); | |
1216 | pcie_cleanup_slot(ctrl); | |
1217 | /* | |
1218 | * If this is the last controller to be released, destroy the | |
1219 | * pciehp work queue | |
1220 | */ | |
1221 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
1222 | destroy_workqueue(pciehp_wq); | |
1223 | kfree(ctrl); | |
08e7a7d2 | 1224 | } |