projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] shpchp: event handling rework
[deliverable/linux.git] / drivers / pci / hotplug / shpchp.h
CommitLineData
1da177e4
LT		 1/*
2 * Standard Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29#ifndef _SHPCHP_H
30#define _SHPCHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/delay.h>
4e57b681 35#include <linux/sched.h> /* signal_pending(), struct timer_list */
6aa4cdd0 36#include <linux/mutex.h>
4e57b681 37
1da177e4
LT		 38#include "pci_hotplug.h"
39
40#if !defined(MODULE)
41 #define MY_NAME "shpchp"
42#else
43 #define MY_NAME THIS_MODULE->name
44#endif
45
46extern int shpchp_poll_mode;
47extern int shpchp_poll_time;
48extern int shpchp_debug;
f7391f53 49extern struct workqueue_struct *shpchp_wq;
1da177e4
LT		 50
51/*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
52#define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
53#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
54#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
55#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
56
bbe779db 57#define SLOT_NAME_SIZE 10
1da177e4 58struct slot {
1da177e4
LT		 59 u8 bus;
60 u8 device;
2178bfad 61 u16 status;
1da177e4
LT		 62 u32 number;
63 u8 is_a_board;
1da177e4 64 u8 state;
1da177e4 65 u8 presence_save;
2178bfad 66 u8 pwr_save;
1da177e4
LT		 67 struct timer_list task_event;
68 u8 hp_slot;
69 struct controller *ctrl;
70 struct hpc_ops *hpc_ops;
71 struct hotplug_slot *hotplug_slot;
72 struct list_head slot_list;
bbe779db 73 char name[SLOT_NAME_SIZE];
f7391f53 74 struct work_struct work; /* work for button event */
1da177e4
LT		 75};
76
1da177e4
LT		 77struct event_info {
78 u32 event_type;
f7391f53
KK		 79 struct slot *p_slot;
80 struct work_struct work;
1da177e4
LT		 81};
82
83struct controller {
a4534560 84 struct list_head ctrl_list;
6aa4cdd0 85 struct mutex crit_sect; /* critical section mutex */
d29aadda 86 struct mutex cmd_lock; /* command lock */
ee138334 87 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
1da177e4
LT		 88 int num_slots; /* Number of slots on ctlr */
89 int slot_num_inc; /* 1 or -1 */
1da177e4 90 struct pci_dev *pci_dev;
5b1a960d 91 struct list_head slot_list;
1da177e4
LT		 92 struct hpc_ops *hpc_ops;
93 wait_queue_head_t queue; /* sleep & wake process */
1da177e4
LT		 94 u8 bus;
95 u8 device;
96 u8 function;
1da177e4
LT		 97 u8 slot_device_offset;
98 u8 add_support;
53044f35 99 u32 pcix_misc2_reg; /* for amd pogo errata */
1da177e4
LT		 100 enum pci_bus_speed speed;
101 u32 first_slot; /* First physical slot number */
102 u8 slot_bus; /* Bus where the slots handled by this controller sit */
0455986c
KK		 103 u32 cap_offset;
104 unsigned long mmio_base;
105 unsigned long mmio_size;
bd62e271 106 volatile int cmd_busy;
1da177e4
LT		 107};
108
424600f9 109struct hotplug_params {
110 u8 cache_line_size;
111 u8 latency_timer;
112 u8 enable_serr;
113 u8 enable_perr;
114};
115
1da177e4
LT		 116/* Define AMD SHPC ID */
117#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
53044f35
KD		 118#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
119
120/* AMD PCIX bridge registers */
121
122#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
123#define PCIX_MISCII_OFFSET 0x48
124#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
125
126/* AMD PCIX_MISCII masks and offsets */
127#define PERRNONFATALENABLE_MASK 0x00040000
128#define PERRFATALENABLE_MASK 0x00080000
129#define PERRFLOODENABLE_MASK 0x00100000
130#define SERRNONFATALENABLE_MASK 0x00200000
131#define SERRFATALENABLE_MASK 0x00400000
132
133/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
134#define PERR_OBSERVED_MASK 0x00000001
135
136/* AMD PCIX_MEM_BASE_LIMIT masks */
137#define RSE_MASK 0x40000000
1da177e4
LT		 138
139#define INT_BUTTON_IGNORE 0
140#define INT_PRESENCE_ON 1
141#define INT_PRESENCE_OFF 2
142#define INT_SWITCH_CLOSE 3
143#define INT_SWITCH_OPEN 4
144#define INT_POWER_FAULT 5
145#define INT_POWER_FAULT_CLEAR 6
146#define INT_BUTTON_PRESS 7
147#define INT_BUTTON_RELEASE 8
148#define INT_BUTTON_CANCEL 9
149
150#define STATIC_STATE 0
151#define BLINKINGON_STATE 1
152#define BLINKINGOFF_STATE 2
153#define POWERON_STATE 3
154#define POWEROFF_STATE 4
155
156#define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
157
158/* Error messages */
159#define INTERLOCK_OPEN 0x00000002
160#define ADD_NOT_SUPPORTED 0x00000003
161#define CARD_FUNCTIONING 0x00000005
162#define ADAPTER_NOT_SAME 0x00000006
163#define NO_ADAPTER_PRESENT 0x00000009
164#define NOT_ENOUGH_RESOURCES 0x0000000B
165#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
166#define WRONG_BUS_FREQUENCY 0x0000000D
167#define POWER_FAILURE 0x0000000E
168
169#define REMOVE_NOT_SUPPORTED 0x00000003
170
171#define DISABLE_CARD 1
172
173/*
174 * error Messages
175 */
176#define msg_initialization_err "Initialization failure, error=%d\n"
1da177e4
LT		 177#define msg_button_on "PCI slot #%d - powering on due to button press.\n"
178#define msg_button_off "PCI slot #%d - powering off due to button press.\n"
179#define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
1da177e4
LT		 180
181/* sysfs functions for the hotplug controller info */
182extern void shpchp_create_ctrl_files (struct controller *ctrl);
183
1da177e4
LT		 184extern int shpchp_enable_slot(struct slot *slot);
185extern int shpchp_disable_slot(struct slot *slot);
186
187extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
188extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
189extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
190extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
191
1da177e4 192/* pci functions */
1da177e4 193extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
dbd7a788 194extern int shpchp_configure_device(struct slot *p_slot);
2178bfad 195extern int shpchp_unconfigure_device(struct slot *p_slot);
424600f9 196extern void get_hp_hw_control_from_firmware(struct pci_dev *dev);
197extern void get_hp_params_from_firmware(struct pci_dev *dev,
198 struct hotplug_params *hpp);
199extern int shpchprm_get_physical_slot_number(struct controller *ctrl,
200 u32 *sun, u8 busnum, u8 devnum);
c2608a11 201extern void shpchp_remove_ctrl_files(struct controller *ctrl);
f7391f53
KK		 202extern void cleanup_slots(struct controller *ctrl);
203extern void shpchp_pushbutton_thread(void *data);
1da177e4
LT		 204
205/* Global variables */
a4534560 206extern struct list_head shpchp_ctrl_list;
1da177e4 207
1da177e4
LT		 208struct ctrl_reg {
209 volatile u32 base_offset;
210 volatile u32 slot_avail1;
211 volatile u32 slot_avail2;
212 volatile u32 slot_config;
213 volatile u16 sec_bus_config;
214 volatile u8 msi_ctrl;
215 volatile u8 prog_interface;
216 volatile u16 cmd;
217 volatile u16 cmd_status;
218 volatile u32 intr_loc;
219 volatile u32 serr_loc;
220 volatile u32 serr_intr_enable;
221 volatile u32 slot1;
222 volatile u32 slot2;
223 volatile u32 slot3;
224 volatile u32 slot4;
225 volatile u32 slot5;
226 volatile u32 slot6;
227 volatile u32 slot7;
228 volatile u32 slot8;
229 volatile u32 slot9;
230 volatile u32 slot10;
231 volatile u32 slot11;
232 volatile u32 slot12;
233} __attribute__ ((packed));
234
235/* offsets to the controller registers based on the above structure layout */
236enum ctrl_offsets {
237 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
238 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
239 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
240 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
241 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
242 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
243 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
244 CMD = offsetof(struct ctrl_reg, cmd),
245 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
246 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
247 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
248 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
249 SLOT1 = offsetof(struct ctrl_reg, slot1),
250 SLOT2 = offsetof(struct ctrl_reg, slot2),
251 SLOT3 = offsetof(struct ctrl_reg, slot3),
252 SLOT4 = offsetof(struct ctrl_reg, slot4),
253 SLOT5 = offsetof(struct ctrl_reg, slot5),
254 SLOT6 = offsetof(struct ctrl_reg, slot6),
255 SLOT7 = offsetof(struct ctrl_reg, slot7),
256 SLOT8 = offsetof(struct ctrl_reg, slot8),
257 SLOT9 = offsetof(struct ctrl_reg, slot9),
258 SLOT10 = offsetof(struct ctrl_reg, slot10),
259 SLOT11 = offsetof(struct ctrl_reg, slot11),
260 SLOT12 = offsetof(struct ctrl_reg, slot12),
261};
ee138334 262typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
1da177e4
LT		 263struct php_ctlr_state_s {
264 struct php_ctlr_state_s *pnext;
265 struct pci_dev *pci_dev;
266 unsigned int irq;
267 unsigned long flags; /* spinlock's */
268 u32 slot_device_offset;
269 u32 num_slots;
270 struct timer_list int_poll_timer; /* Added for poll event */
271 php_intr_callback_t attention_button_callback;
272 php_intr_callback_t switch_change_callback;
273 php_intr_callback_t presence_change_callback;
274 php_intr_callback_t power_fault_callback;
275 void *callback_instance_id;
276 void __iomem *creg; /* Ptr to controller register space */
277};
278/* Inline functions */
279
280
281/* Inline functions to check the sanity of a pointer that is passed to us */
282static inline int slot_paranoia_check (struct slot *slot, const char *function)
283{
284 if (!slot) {
285 dbg("%s - slot == NULL", function);
286 return -1;
287 }
1da177e4
LT		 288 if (!slot->hotplug_slot) {
289 dbg("%s - slot->hotplug_slot == NULL!", function);
290 return -1;
291 }
292 return 0;
293}
294
295static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
296{
297 struct slot *slot;
298
299 if (!hotplug_slot) {
300 dbg("%s - hotplug_slot == NULL\n", function);
301 return NULL;
302 }
303
304 slot = (struct slot *)hotplug_slot->private;
305 if (slot_paranoia_check (slot, function))
306 return NULL;
307 return slot;
308}
309
310static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
311{
5b1a960d 312 struct slot *slot;
1da177e4
LT		 313
314 if (!ctrl)
315 return NULL;
316
5b1a960d
KK		 317 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
318 if (slot->device == device)
319 return slot;
1da177e4
LT		 320 }
321
5b1a960d
KK		 322 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
323
324 return NULL;
1da177e4
LT		 325}
326
53044f35
KD		 327static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
328{
329 u32 pcix_misc2_temp;
330
331 /* save MiscII register */
332 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
333
334 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
335
336 /* clear SERR/PERR enable bits */
337 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
338 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
339 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
340 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
341 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
342 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
343}
344
345static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
346{
347 u32 pcix_misc2_temp;
348 u32 pcix_bridge_errors_reg;
349 u32 pcix_mem_base_reg;
350 u8 perr_set;
351 u8 rse_set;
352
353 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
354 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
355 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
356 if (perr_set) {
357 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
358
359 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
360 }
361
362 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
363 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
364 rse_set = pcix_mem_base_reg & RSE_MASK;
365 if (rse_set) {
366 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
367
368 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
369 }
370 /* restore MiscII register */
371 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
372
373 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
374 pcix_misc2_temp |= SERRFATALENABLE_MASK;
375 else
376 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
377
378 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
379 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
380 else
381 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
382
383 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
384 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
385 else
386 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
387
388 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
389 pcix_misc2_temp |= PERRFATALENABLE_MASK;
390 else
391 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
392
393 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
394 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
395 else
396 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
397 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
398}
399
1da177e4
LT		 400enum php_ctlr_type {
401 PCI,
402 ISA,
403 ACPI
404};
405
ee138334 406int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
1da177e4
LT		 407
408int shpc_get_ctlr_slot_config( struct controller *ctrl,
409 int *num_ctlr_slots,
410 int *first_device_num,
411 int *physical_slot_num,
412 int *updown,
413 int *flags);
414
415struct hpc_ops {
416 int (*power_on_slot ) (struct slot *slot);
417 int (*slot_enable ) (struct slot *slot);
418 int (*slot_disable ) (struct slot *slot);
1da177e4
LT		 419 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
420 int (*get_power_status) (struct slot *slot, u8 *status);
421 int (*get_attention_status) (struct slot *slot, u8 *status);
422 int (*set_attention_status) (struct slot *slot, u8 status);
423 int (*get_latch_status) (struct slot *slot, u8 *status);
424 int (*get_adapter_status) (struct slot *slot, u8 *status);
425
426 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
427 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
428 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed);
429 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode);
430 int (*get_prog_int) (struct slot *slot, u8 *prog_int);
431
432 int (*query_power_fault) (struct slot *slot);
433 void (*green_led_on) (struct slot *slot);
434 void (*green_led_off) (struct slot *slot);
435 void (*green_led_blink) (struct slot *slot);
436 void (*release_ctlr) (struct controller *ctrl);
437 int (*check_cmd_status) (struct controller *ctrl);
438};
439
440#endif /* _SHPCHP_H */
Linux kernel - Deliverables
This page took 0.130206 seconds and 5 git commands to generate.