Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Standard PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
d4d28dd4 AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "shpchp.h" |
37 | ||
1da177e4 LT |
38 | /* Slot Available Register I field definition */ |
39 | #define SLOT_33MHZ 0x0000001f | |
40 | #define SLOT_66MHZ_PCIX 0x00001f00 | |
41 | #define SLOT_100MHZ_PCIX 0x001f0000 | |
42 | #define SLOT_133MHZ_PCIX 0x1f000000 | |
43 | ||
44 | /* Slot Available Register II field definition */ | |
45 | #define SLOT_66MHZ 0x0000001f | |
46 | #define SLOT_66MHZ_PCIX_266 0x00000f00 | |
47 | #define SLOT_100MHZ_PCIX_266 0x0000f000 | |
48 | #define SLOT_133MHZ_PCIX_266 0x000f0000 | |
49 | #define SLOT_66MHZ_PCIX_533 0x00f00000 | |
50 | #define SLOT_100MHZ_PCIX_533 0x0f000000 | |
51 | #define SLOT_133MHZ_PCIX_533 0xf0000000 | |
52 | ||
1da177e4 LT |
53 | /* Slot Configuration */ |
54 | #define SLOT_NUM 0x0000001F | |
55 | #define FIRST_DEV_NUM 0x00001F00 | |
56 | #define PSN 0x07FF0000 | |
57 | #define UPDOWN 0x20000000 | |
58 | #define MRLSENSOR 0x40000000 | |
59 | #define ATTN_BUTTON 0x80000000 | |
60 | ||
c4cecc19 KK |
61 | /* |
62 | * Interrupt Locator Register definitions | |
63 | */ | |
64 | #define CMD_INTR_PENDING (1 << 0) | |
65 | #define SLOT_INTR_PENDING(i) (1 << (i + 1)) | |
66 | ||
e7138723 KK |
67 | /* |
68 | * Controller SERR-INT Register | |
69 | */ | |
70 | #define GLOBAL_INTR_MASK (1 << 0) | |
71 | #define GLOBAL_SERR_MASK (1 << 1) | |
72 | #define COMMAND_INTR_MASK (1 << 2) | |
73 | #define ARBITER_SERR_MASK (1 << 3) | |
74 | #define COMMAND_DETECTED (1 << 16) | |
75 | #define ARBITER_DETECTED (1 << 17) | |
76 | #define SERR_INTR_RSVDZ_MASK 0xfffc0000 | |
77 | ||
2b34da7e KK |
78 | /* |
79 | * Logical Slot Register definitions | |
80 | */ | |
81 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | |
82 | ||
5858759c KK |
83 | #define SLOT_STATE_SHIFT (0) |
84 | #define SLOT_STATE_MASK (3 << 0) | |
85 | #define SLOT_STATE_PWRONLY (1) | |
86 | #define SLOT_STATE_ENABLED (2) | |
87 | #define SLOT_STATE_DISABLED (3) | |
88 | #define PWR_LED_STATE_SHIFT (2) | |
89 | #define PWR_LED_STATE_MASK (3 << 2) | |
90 | #define ATN_LED_STATE_SHIFT (4) | |
91 | #define ATN_LED_STATE_MASK (3 << 4) | |
92 | #define ATN_LED_STATE_ON (1) | |
93 | #define ATN_LED_STATE_BLINK (2) | |
94 | #define ATN_LED_STATE_OFF (3) | |
95 | #define POWER_FAULT (1 << 6) | |
96 | #define ATN_BUTTON (1 << 7) | |
97 | #define MRL_SENSOR (1 << 8) | |
98 | #define MHZ66_CAP (1 << 9) | |
99 | #define PRSNT_SHIFT (10) | |
100 | #define PRSNT_MASK (3 << 10) | |
101 | #define PCIX_CAP_SHIFT (12) | |
102 | #define PCIX_CAP_MASK_PI1 (3 << 12) | |
103 | #define PCIX_CAP_MASK_PI2 (7 << 12) | |
104 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
105 | #define ISO_PFAULT_DETECTED (1 << 17) | |
106 | #define BUTTON_PRESS_DETECTED (1 << 18) | |
107 | #define MRL_CHANGE_DETECTED (1 << 19) | |
108 | #define CON_PFAULT_DETECTED (1 << 20) | |
109 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) | |
110 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
111 | #define BUTTON_PRESS_INTR_MASK (1 << 26) | |
112 | #define MRL_CHANGE_INTR_MASK (1 << 27) | |
113 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
114 | #define MRL_CHANGE_SERR_MASK (1 << 29) | |
115 | #define CON_PFAULT_SERR_MASK (1 << 30) | |
3b8fdb75 | 116 | #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) |
1da177e4 | 117 | |
4085399d | 118 | /* |
f7625980 | 119 | * SHPC Command Code definitions |
4085399d KK |
120 | * |
121 | * Slot Operation 00h - 3Fh | |
122 | * Set Bus Segment Speed/Mode A 40h - 47h | |
123 | * Power-Only All Slots 48h | |
124 | * Enable All Slots 49h | |
125 | * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh | |
126 | * Reserved Command Codes 60h - BFh | |
127 | * Vendor Specific Commands C0h - FFh | |
128 | */ | |
129 | #define SET_SLOT_PWR 0x01 /* Slot Operation */ | |
130 | #define SET_SLOT_ENABLE 0x02 | |
131 | #define SET_SLOT_DISABLE 0x03 | |
132 | #define SET_PWR_ON 0x04 | |
133 | #define SET_PWR_BLINK 0x08 | |
134 | #define SET_PWR_OFF 0x0c | |
135 | #define SET_ATTN_ON 0x10 | |
136 | #define SET_ATTN_BLINK 0x20 | |
137 | #define SET_ATTN_OFF 0x30 | |
138 | #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ | |
1da177e4 LT |
139 | #define SETA_PCI_66MHZ 0x41 |
140 | #define SETA_PCIX_66MHZ 0x42 | |
141 | #define SETA_PCIX_100MHZ 0x43 | |
142 | #define SETA_PCIX_133MHZ 0x44 | |
4085399d KK |
143 | #define SETA_RESERVED1 0x45 |
144 | #define SETA_RESERVED2 0x46 | |
145 | #define SETA_RESERVED3 0x47 | |
146 | #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ | |
147 | #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ | |
148 | #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ | |
1da177e4 LT |
149 | #define SETB_PCI_66MHZ 0x51 |
150 | #define SETB_PCIX_66MHZ_PM 0x52 | |
151 | #define SETB_PCIX_100MHZ_PM 0x53 | |
152 | #define SETB_PCIX_133MHZ_PM 0x54 | |
153 | #define SETB_PCIX_66MHZ_EM 0x55 | |
154 | #define SETB_PCIX_100MHZ_EM 0x56 | |
155 | #define SETB_PCIX_133MHZ_EM 0x57 | |
156 | #define SETB_PCIX_66MHZ_266 0x58 | |
157 | #define SETB_PCIX_100MHZ_266 0x59 | |
158 | #define SETB_PCIX_133MHZ_266 0x5a | |
159 | #define SETB_PCIX_66MHZ_533 0x5b | |
160 | #define SETB_PCIX_100MHZ_533 0x5c | |
161 | #define SETB_PCIX_133MHZ_533 0x5d | |
4085399d KK |
162 | #define SETB_RESERVED1 0x5e |
163 | #define SETB_RESERVED2 0x5f | |
1da177e4 | 164 | |
4085399d KK |
165 | /* |
166 | * SHPC controller command error code | |
167 | */ | |
1da177e4 LT |
168 | #define SWITCH_OPEN 0x1 |
169 | #define INVALID_CMD 0x2 | |
170 | #define INVALID_SPEED_MODE 0x4 | |
171 | ||
4085399d KK |
172 | /* |
173 | * For accessing SHPC Working Register Set via PCI Configuration Space | |
174 | */ | |
1da177e4 LT |
175 | #define DWORD_SELECT 0x2 |
176 | #define DWORD_DATA 0x4 | |
1da177e4 LT |
177 | |
178 | /* Field Offset in Logical Slot Register - byte boundary */ | |
179 | #define SLOT_EVENT_LATCH 0x2 | |
180 | #define SLOT_SERR_INT_MASK 0x3 | |
181 | ||
7d12e780 | 182 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
0abe68ce | 183 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
d29aadda | 184 | static int hpc_check_cmd_status(struct controller *ctrl); |
1da177e4 | 185 | |
75d97c59 KK |
186 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
187 | { | |
0abe68ce | 188 | return readb(ctrl->creg + reg); |
75d97c59 KK |
189 | } |
190 | ||
191 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | |
192 | { | |
0abe68ce | 193 | writeb(val, ctrl->creg + reg); |
75d97c59 KK |
194 | } |
195 | ||
196 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | |
197 | { | |
0abe68ce | 198 | return readw(ctrl->creg + reg); |
75d97c59 KK |
199 | } |
200 | ||
201 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | |
202 | { | |
0abe68ce | 203 | writew(val, ctrl->creg + reg); |
75d97c59 KK |
204 | } |
205 | ||
206 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | |
207 | { | |
0abe68ce | 208 | return readl(ctrl->creg + reg); |
75d97c59 KK |
209 | } |
210 | ||
211 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | |
212 | { | |
0abe68ce | 213 | writel(val, ctrl->creg + reg); |
75d97c59 KK |
214 | } |
215 | ||
216 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | |
217 | u32 *value) | |
218 | { | |
219 | int rc; | |
220 | u32 cap_offset = ctrl->cap_offset; | |
221 | struct pci_dev *pdev = ctrl->pci_dev; | |
222 | ||
223 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); | |
224 | if (rc) | |
225 | return rc; | |
226 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); | |
227 | } | |
228 | ||
f4263957 KK |
229 | /* |
230 | * This is the interrupt polling timeout function. | |
231 | */ | |
0abe68ce | 232 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 233 | { |
0abe68ce | 234 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 235 | |
f4263957 | 236 | /* Poll for interrupt events. regs == NULL => polling */ |
0abe68ce | 237 | shpc_isr(0, ctrl); |
1da177e4 | 238 | |
0abe68ce | 239 | init_timer(&ctrl->poll_timer); |
1da177e4 | 240 | if (!shpchp_poll_time) |
f4263957 KK |
241 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
242 | ||
0abe68ce | 243 | start_int_poll_timer(ctrl, shpchp_poll_time); |
1da177e4 LT |
244 | } |
245 | ||
f4263957 KK |
246 | /* |
247 | * This function starts the interrupt polling timer. | |
248 | */ | |
0abe68ce | 249 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 250 | { |
f4263957 KK |
251 | /* Clamp to sane value */ |
252 | if ((sec <= 0) || (sec > 60)) | |
253 | sec = 2; | |
254 | ||
0abe68ce KK |
255 | ctrl->poll_timer.function = &int_poll_timeout; |
256 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
257 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
258 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
259 | } |
260 | ||
d1729cce KK |
261 | static inline int is_ctrl_busy(struct controller *ctrl) |
262 | { | |
263 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); | |
264 | return cmd_status & 0x1; | |
265 | } | |
266 | ||
b4a1efff KK |
267 | /* |
268 | * Returns 1 if SHPC finishes executing a command within 1 sec, | |
269 | * otherwise returns 0. | |
270 | */ | |
271 | static inline int shpc_poll_ctrl_busy(struct controller *ctrl) | |
272 | { | |
273 | int i; | |
b4a1efff | 274 | |
d1729cce | 275 | if (!is_ctrl_busy(ctrl)) |
b4a1efff KK |
276 | return 1; |
277 | ||
278 | /* Check every 0.1 sec for a total of 1 sec */ | |
279 | for (i = 0; i < 10; i++) { | |
280 | msleep(100); | |
d1729cce | 281 | if (!is_ctrl_busy(ctrl)) |
b4a1efff KK |
282 | return 1; |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
bd62e271 KK |
288 | static inline int shpc_wait_cmd(struct controller *ctrl) |
289 | { | |
290 | int retval = 0; | |
b4a1efff KK |
291 | unsigned long timeout = msecs_to_jiffies(1000); |
292 | int rc; | |
293 | ||
294 | if (shpchp_poll_mode) | |
295 | rc = shpc_poll_ctrl_busy(ctrl); | |
296 | else | |
297 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
6aa562c2 | 298 | !is_ctrl_busy(ctrl), timeout); |
d1729cce | 299 | if (!rc && is_ctrl_busy(ctrl)) { |
bd62e271 | 300 | retval = -EIO; |
f98ca311 | 301 | ctrl_err(ctrl, "Command not completed in 1000 msec\n"); |
bd62e271 KK |
302 | } else if (rc < 0) { |
303 | retval = -EINTR; | |
f98ca311 | 304 | ctrl_info(ctrl, "Command was interrupted by a signal\n"); |
bd62e271 | 305 | } |
bd62e271 KK |
306 | |
307 | return retval; | |
308 | } | |
309 | ||
1da177e4 LT |
310 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
311 | { | |
75d97c59 | 312 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
313 | u16 cmd_status; |
314 | int retval = 0; | |
315 | u16 temp_word; | |
1da177e4 | 316 | |
d29aadda KK |
317 | mutex_lock(&slot->ctrl->cmd_lock); |
318 | ||
b4a1efff | 319 | if (!shpc_poll_ctrl_busy(ctrl)) { |
1da177e4 | 320 | /* After 1 sec and and the controller is still busy */ |
be7bce25 | 321 | ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); |
d29aadda KK |
322 | retval = -EBUSY; |
323 | goto out; | |
1da177e4 LT |
324 | } |
325 | ||
326 | ++t_slot; | |
327 | temp_word = (t_slot << 8) | (cmd & 0xFF); | |
f98ca311 | 328 | ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); |
9f593e30 | 329 | |
1da177e4 | 330 | /* To make sure the Controller Busy bit is 0 before we send out the |
9f593e30 | 331 | * command. |
1da177e4 | 332 | */ |
75d97c59 | 333 | shpc_writew(ctrl, CMD, temp_word); |
1da177e4 | 334 | |
bd62e271 KK |
335 | /* |
336 | * Wait for command completion. | |
337 | */ | |
338 | retval = shpc_wait_cmd(slot->ctrl); | |
d29aadda KK |
339 | if (retval) |
340 | goto out; | |
341 | ||
342 | cmd_status = hpc_check_cmd_status(slot->ctrl); | |
343 | if (cmd_status) { | |
227f0647 | 344 | ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", |
be7bce25 | 345 | cmd, cmd_status); |
d29aadda KK |
346 | retval = -EIO; |
347 | } | |
348 | out: | |
349 | mutex_unlock(&slot->ctrl->cmd_lock); | |
1da177e4 LT |
350 | return retval; |
351 | } | |
352 | ||
353 | static int hpc_check_cmd_status(struct controller *ctrl) | |
354 | { | |
1da177e4 | 355 | int retval = 0; |
1555b33d | 356 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
9f593e30 | 357 | |
1da177e4 LT |
358 | switch (cmd_status >> 1) { |
359 | case 0: | |
360 | retval = 0; | |
361 | break; | |
362 | case 1: | |
363 | retval = SWITCH_OPEN; | |
be7bce25 | 364 | ctrl_err(ctrl, "Switch opened!\n"); |
1da177e4 LT |
365 | break; |
366 | case 2: | |
367 | retval = INVALID_CMD; | |
be7bce25 | 368 | ctrl_err(ctrl, "Invalid HPC command!\n"); |
1da177e4 LT |
369 | break; |
370 | case 4: | |
371 | retval = INVALID_SPEED_MODE; | |
be7bce25 | 372 | ctrl_err(ctrl, "Invalid bus speed/mode!\n"); |
1da177e4 LT |
373 | break; |
374 | default: | |
375 | retval = cmd_status; | |
376 | } | |
377 | ||
1da177e4 LT |
378 | return retval; |
379 | } | |
380 | ||
381 | ||
382 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
383 | { | |
75d97c59 | 384 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
385 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
386 | u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; | |
1da177e4 | 387 | |
5858759c KK |
388 | switch (state) { |
389 | case ATN_LED_STATE_ON: | |
1da177e4 LT |
390 | *status = 1; /* On */ |
391 | break; | |
5858759c | 392 | case ATN_LED_STATE_BLINK: |
1da177e4 LT |
393 | *status = 2; /* Blink */ |
394 | break; | |
5858759c | 395 | case ATN_LED_STATE_OFF: |
1da177e4 LT |
396 | *status = 0; /* Off */ |
397 | break; | |
398 | default: | |
5858759c | 399 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
400 | break; |
401 | } | |
402 | ||
1da177e4 LT |
403 | return 0; |
404 | } | |
405 | ||
3c78bc61 | 406 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 407 | { |
75d97c59 | 408 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
409 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
410 | u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; | |
1da177e4 | 411 | |
5858759c KK |
412 | switch (state) { |
413 | case SLOT_STATE_PWRONLY: | |
1da177e4 LT |
414 | *status = 2; /* Powered only */ |
415 | break; | |
5858759c | 416 | case SLOT_STATE_ENABLED: |
1da177e4 LT |
417 | *status = 1; /* Enabled */ |
418 | break; | |
5858759c | 419 | case SLOT_STATE_DISABLED: |
1da177e4 LT |
420 | *status = 0; /* Disabled */ |
421 | break; | |
422 | default: | |
5858759c | 423 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
424 | break; |
425 | } | |
426 | ||
5858759c | 427 | return 0; |
1da177e4 LT |
428 | } |
429 | ||
430 | ||
431 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
432 | { | |
75d97c59 | 433 | struct controller *ctrl = slot->ctrl; |
1555b33d | 434 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 | 435 | |
5858759c | 436 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
1da177e4 | 437 | |
1da177e4 LT |
438 | return 0; |
439 | } | |
440 | ||
441 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
442 | { | |
75d97c59 | 443 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
444 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
445 | u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; | |
1da177e4 | 446 | |
5858759c | 447 | *status = (state != 0x3) ? 1 : 0; |
1da177e4 | 448 | |
1da177e4 LT |
449 | return 0; |
450 | } | |
451 | ||
452 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |
453 | { | |
75d97c59 | 454 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 455 | |
75d97c59 | 456 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
1da177e4 | 457 | |
1da177e4 LT |
458 | return 0; |
459 | } | |
460 | ||
461 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |
462 | { | |
1da177e4 | 463 | int retval = 0; |
75d97c59 | 464 | struct controller *ctrl = slot->ctrl; |
2b34da7e | 465 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 466 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
795eb5c4 | 467 | u8 pi, pcix_cap; |
1da177e4 | 468 | |
79e50e72 QL |
469 | retval = hpc_get_prog_int(slot, &pi); |
470 | if (retval) | |
795eb5c4 KK |
471 | return retval; |
472 | ||
473 | switch (pi) { | |
474 | case 1: | |
475 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; | |
476 | break; | |
477 | case 2: | |
478 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; | |
479 | break; | |
480 | default: | |
481 | return -ENODEV; | |
482 | } | |
483 | ||
f98ca311 TI |
484 | ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
485 | __func__, slot_reg, pcix_cap, m66_cap); | |
1da177e4 | 486 | |
0afabe90 KK |
487 | switch (pcix_cap) { |
488 | case 0x0: | |
489 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; | |
490 | break; | |
491 | case 0x1: | |
492 | *value = PCI_SPEED_66MHz_PCIX; | |
493 | break; | |
494 | case 0x3: | |
495 | *value = PCI_SPEED_133MHz_PCIX; | |
496 | break; | |
497 | case 0x4: | |
498 | *value = PCI_SPEED_133MHz_PCIX_266; | |
499 | break; | |
500 | case 0x5: | |
501 | *value = PCI_SPEED_133MHz_PCIX_533; | |
502 | break; | |
503 | case 0x2: | |
504 | default: | |
505 | *value = PCI_SPEED_UNKNOWN; | |
506 | retval = -ENODEV; | |
507 | break; | |
1da177e4 LT |
508 | } |
509 | ||
f98ca311 | 510 | ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); |
1da177e4 LT |
511 | return retval; |
512 | } | |
513 | ||
514 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |
515 | { | |
1da177e4 | 516 | int retval = 0; |
1555b33d KK |
517 | struct controller *ctrl = slot->ctrl; |
518 | u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
519 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
1da177e4 LT |
520 | |
521 | if (pi == 2) { | |
87d6c559 | 522 | *mode = (sec_bus_status & 0x0100) >> 8; |
1da177e4 LT |
523 | } else { |
524 | retval = -1; | |
525 | } | |
526 | ||
f98ca311 | 527 | ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); |
1da177e4 LT |
528 | return retval; |
529 | } | |
530 | ||
3c78bc61 | 531 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 532 | { |
75d97c59 | 533 | struct controller *ctrl = slot->ctrl; |
1555b33d | 534 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 | 535 | |
1da177e4 | 536 | /* Note: Logic 0 => fault */ |
5858759c | 537 | return !(slot_reg & POWER_FAULT); |
1da177e4 LT |
538 | } |
539 | ||
540 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
541 | { | |
1da177e4 | 542 | u8 slot_cmd = 0; |
1da177e4 LT |
543 | |
544 | switch (value) { | |
ff3ce480 | 545 | case 0: |
4085399d | 546 | slot_cmd = SET_ATTN_OFF; /* OFF */ |
1da177e4 LT |
547 | break; |
548 | case 1: | |
4085399d | 549 | slot_cmd = SET_ATTN_ON; /* ON */ |
1da177e4 LT |
550 | break; |
551 | case 2: | |
4085399d | 552 | slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
1da177e4 LT |
553 | break; |
554 | default: | |
555 | return -1; | |
556 | } | |
557 | ||
d4fbf600 | 558 | return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); |
1da177e4 LT |
559 | } |
560 | ||
561 | ||
562 | static void hpc_set_green_led_on(struct slot *slot) | |
563 | { | |
4085399d | 564 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
1da177e4 LT |
565 | } |
566 | ||
567 | static void hpc_set_green_led_off(struct slot *slot) | |
568 | { | |
4085399d | 569 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
1da177e4 LT |
570 | } |
571 | ||
572 | static void hpc_set_green_led_blink(struct slot *slot) | |
573 | { | |
4085399d | 574 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
1da177e4 LT |
575 | } |
576 | ||
1da177e4 LT |
577 | static void hpc_release_ctlr(struct controller *ctrl) |
578 | { | |
f7391f53 | 579 | int i; |
d49f2c49 | 580 | u32 slot_reg, serr_int; |
1da177e4 | 581 | |
f7391f53 | 582 | /* |
795eb5c4 | 583 | * Mask event interrupts and SERRs of all slots |
f7391f53 | 584 | */ |
795eb5c4 KK |
585 | for (i = 0; i < ctrl->num_slots; i++) { |
586 | slot_reg = shpc_readl(ctrl, SLOT_REG(i)); | |
587 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | |
588 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
589 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
590 | CON_PFAULT_SERR_MASK); | |
591 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
592 | shpc_writel(ctrl, SLOT_REG(i), slot_reg); | |
593 | } | |
f7391f53 KK |
594 | |
595 | cleanup_slots(ctrl); | |
596 | ||
d49f2c49 | 597 | /* |
3609801e | 598 | * Mask SERR and System Interrupt generation |
d49f2c49 KK |
599 | */ |
600 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
601 | serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | | |
602 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
603 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
604 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
605 | ||
0abe68ce KK |
606 | if (shpchp_poll_mode) |
607 | del_timer(&ctrl->poll_timer); | |
608 | else { | |
609 | free_irq(ctrl->pci_dev->irq, ctrl); | |
610 | pci_disable_msi(ctrl->pci_dev); | |
1da177e4 | 611 | } |
1da177e4 | 612 | |
0abe68ce KK |
613 | iounmap(ctrl->creg); |
614 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | |
1da177e4 LT |
615 | } |
616 | ||
3c78bc61 | 617 | static int hpc_power_on_slot(struct slot *slot) |
1da177e4 | 618 | { |
d4fbf600 | 619 | int retval; |
1da177e4 | 620 | |
4085399d | 621 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
1555b33d | 622 | if (retval) |
f98ca311 | 623 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 624 | |
1555b33d | 625 | return retval; |
1da177e4 LT |
626 | } |
627 | ||
3c78bc61 | 628 | static int hpc_slot_enable(struct slot *slot) |
1da177e4 | 629 | { |
d4fbf600 | 630 | int retval; |
1da177e4 | 631 | |
4085399d KK |
632 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
633 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
634 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); | |
1555b33d | 635 | if (retval) |
f98ca311 | 636 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 637 | |
1555b33d | 638 | return retval; |
1da177e4 LT |
639 | } |
640 | ||
3c78bc61 | 641 | static int hpc_slot_disable(struct slot *slot) |
1da177e4 | 642 | { |
d4fbf600 | 643 | int retval; |
1da177e4 | 644 | |
4085399d KK |
645 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
646 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
647 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); | |
1555b33d | 648 | if (retval) |
f98ca311 | 649 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 650 | |
1555b33d | 651 | return retval; |
1da177e4 LT |
652 | } |
653 | ||
3749c51a MW |
654 | static int shpc_get_cur_bus_speed(struct controller *ctrl) |
655 | { | |
656 | int retval = 0; | |
657 | struct pci_bus *bus = ctrl->pci_dev->subordinate; | |
658 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; | |
659 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
660 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
661 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); | |
662 | ||
663 | if ((pi == 1) && (speed_mode > 4)) { | |
664 | retval = -ENODEV; | |
665 | goto out; | |
666 | } | |
667 | ||
668 | switch (speed_mode) { | |
669 | case 0x0: | |
670 | bus_speed = PCI_SPEED_33MHz; | |
671 | break; | |
672 | case 0x1: | |
673 | bus_speed = PCI_SPEED_66MHz; | |
674 | break; | |
675 | case 0x2: | |
676 | bus_speed = PCI_SPEED_66MHz_PCIX; | |
677 | break; | |
678 | case 0x3: | |
679 | bus_speed = PCI_SPEED_100MHz_PCIX; | |
680 | break; | |
681 | case 0x4: | |
682 | bus_speed = PCI_SPEED_133MHz_PCIX; | |
683 | break; | |
684 | case 0x5: | |
685 | bus_speed = PCI_SPEED_66MHz_PCIX_ECC; | |
686 | break; | |
687 | case 0x6: | |
688 | bus_speed = PCI_SPEED_100MHz_PCIX_ECC; | |
689 | break; | |
690 | case 0x7: | |
691 | bus_speed = PCI_SPEED_133MHz_PCIX_ECC; | |
692 | break; | |
693 | case 0x8: | |
694 | bus_speed = PCI_SPEED_66MHz_PCIX_266; | |
695 | break; | |
696 | case 0x9: | |
697 | bus_speed = PCI_SPEED_100MHz_PCIX_266; | |
698 | break; | |
699 | case 0xa: | |
700 | bus_speed = PCI_SPEED_133MHz_PCIX_266; | |
701 | break; | |
702 | case 0xb: | |
703 | bus_speed = PCI_SPEED_66MHz_PCIX_533; | |
704 | break; | |
705 | case 0xc: | |
706 | bus_speed = PCI_SPEED_100MHz_PCIX_533; | |
707 | break; | |
708 | case 0xd: | |
709 | bus_speed = PCI_SPEED_133MHz_PCIX_533; | |
710 | break; | |
711 | default: | |
712 | retval = -ENODEV; | |
713 | break; | |
714 | } | |
715 | ||
716 | out: | |
717 | bus->cur_bus_speed = bus_speed; | |
718 | dbg("Current bus speed = %d\n", bus_speed); | |
719 | return retval; | |
720 | } | |
721 | ||
722 | ||
3c78bc61 | 723 | static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) |
1da177e4 | 724 | { |
0afabe90 | 725 | int retval; |
75d97c59 | 726 | struct controller *ctrl = slot->ctrl; |
0afabe90 | 727 | u8 pi, cmd; |
1da177e4 | 728 | |
75d97c59 | 729 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
0afabe90 KK |
730 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
731 | return -EINVAL; | |
1da177e4 | 732 | |
0afabe90 KK |
733 | switch (value) { |
734 | case PCI_SPEED_33MHz: | |
735 | cmd = SETA_PCI_33MHZ; | |
736 | break; | |
737 | case PCI_SPEED_66MHz: | |
738 | cmd = SETA_PCI_66MHZ; | |
739 | break; | |
740 | case PCI_SPEED_66MHz_PCIX: | |
741 | cmd = SETA_PCIX_66MHZ; | |
742 | break; | |
743 | case PCI_SPEED_100MHz_PCIX: | |
744 | cmd = SETA_PCIX_100MHZ; | |
745 | break; | |
746 | case PCI_SPEED_133MHz_PCIX: | |
747 | cmd = SETA_PCIX_133MHZ; | |
748 | break; | |
749 | case PCI_SPEED_66MHz_PCIX_ECC: | |
750 | cmd = SETB_PCIX_66MHZ_EM; | |
751 | break; | |
752 | case PCI_SPEED_100MHz_PCIX_ECC: | |
753 | cmd = SETB_PCIX_100MHZ_EM; | |
754 | break; | |
755 | case PCI_SPEED_133MHz_PCIX_ECC: | |
756 | cmd = SETB_PCIX_133MHZ_EM; | |
757 | break; | |
758 | case PCI_SPEED_66MHz_PCIX_266: | |
759 | cmd = SETB_PCIX_66MHZ_266; | |
760 | break; | |
761 | case PCI_SPEED_100MHz_PCIX_266: | |
762 | cmd = SETB_PCIX_100MHZ_266; | |
763 | break; | |
764 | case PCI_SPEED_133MHz_PCIX_266: | |
765 | cmd = SETB_PCIX_133MHZ_266; | |
766 | break; | |
767 | case PCI_SPEED_66MHz_PCIX_533: | |
768 | cmd = SETB_PCIX_66MHZ_533; | |
769 | break; | |
770 | case PCI_SPEED_100MHz_PCIX_533: | |
771 | cmd = SETB_PCIX_100MHZ_533; | |
772 | break; | |
773 | case PCI_SPEED_133MHz_PCIX_533: | |
774 | cmd = SETB_PCIX_133MHZ_533; | |
775 | break; | |
776 | default: | |
777 | return -EINVAL; | |
1da177e4 | 778 | } |
0afabe90 KK |
779 | |
780 | retval = shpc_write_cmd(slot, 0, cmd); | |
781 | if (retval) | |
f98ca311 | 782 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
3749c51a MW |
783 | else |
784 | shpc_get_cur_bus_speed(ctrl); | |
1da177e4 | 785 | |
1da177e4 LT |
786 | return retval; |
787 | } | |
788 | ||
7d12e780 | 789 | static irqreturn_t shpc_isr(int irq, void *dev_id) |
1da177e4 | 790 | { |
c4cecc19 | 791 | struct controller *ctrl = (struct controller *)dev_id; |
c4cecc19 | 792 | u32 serr_int, slot_reg, intr_loc, intr_loc2; |
1da177e4 LT |
793 | int hp_slot; |
794 | ||
1da177e4 | 795 | /* Check to see if it was our interrupt */ |
75d97c59 | 796 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
797 | if (!intr_loc) |
798 | return IRQ_NONE; | |
c4cecc19 | 799 | |
f98ca311 | 800 | ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); |
1da177e4 | 801 | |
382a9c9a | 802 | if (!shpchp_poll_mode) { |
c4cecc19 KK |
803 | /* |
804 | * Mask Global Interrupt Mask - see implementation | |
805 | * note on p. 139 of SHPC spec rev 1.0 | |
806 | */ | |
807 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
808 | serr_int |= GLOBAL_INTR_MASK; | |
809 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
810 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 | 811 | |
75d97c59 | 812 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
f98ca311 | 813 | ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); |
1da177e4 LT |
814 | } |
815 | ||
c4cecc19 | 816 | if (intr_loc & CMD_INTR_PENDING) { |
9f593e30 KK |
817 | /* |
818 | * Command Complete Interrupt Pending | |
f467f618 | 819 | * RO only - clear by writing 1 to the Command Completion |
1da177e4 LT |
820 | * Detect bit in Controller SERR-INT register |
821 | */ | |
c4cecc19 KK |
822 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
823 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
824 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
825 | ||
1da177e4 LT |
826 | wake_up_interruptible(&ctrl->queue); |
827 | } | |
828 | ||
c4cecc19 | 829 | if (!(intr_loc & ~CMD_INTR_PENDING)) |
e4e73041 | 830 | goto out; |
1da177e4 | 831 | |
9f593e30 | 832 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
c4cecc19 KK |
833 | /* To find out which slot has interrupt pending */ |
834 | if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) | |
835 | continue; | |
836 | ||
837 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | |
be7bce25 TI |
838 | ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", |
839 | hp_slot, slot_reg); | |
c4cecc19 KK |
840 | |
841 | if (slot_reg & MRL_CHANGE_DETECTED) | |
0abe68ce | 842 | shpchp_handle_switch_change(hp_slot, ctrl); |
c4cecc19 KK |
843 | |
844 | if (slot_reg & BUTTON_PRESS_DETECTED) | |
0abe68ce | 845 | shpchp_handle_attention_button(hp_slot, ctrl); |
c4cecc19 KK |
846 | |
847 | if (slot_reg & PRSNT_CHANGE_DETECTED) | |
0abe68ce | 848 | shpchp_handle_presence_change(hp_slot, ctrl); |
c4cecc19 KK |
849 | |
850 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) | |
0abe68ce | 851 | shpchp_handle_power_fault(hp_slot, ctrl); |
c4cecc19 KK |
852 | |
853 | /* Clear all slot events */ | |
854 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
855 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 | 856 | } |
e4e73041 | 857 | out: |
1da177e4 LT |
858 | if (!shpchp_poll_mode) { |
859 | /* Unmask Global Interrupt Mask */ | |
c4cecc19 KK |
860 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
861 | serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); | |
862 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 | 863 | } |
9f593e30 | 864 | |
1da177e4 LT |
865 | return IRQ_HANDLED; |
866 | } | |
867 | ||
3749c51a | 868 | static int shpc_get_max_bus_speed(struct controller *ctrl) |
1da177e4 | 869 | { |
0afabe90 | 870 | int retval = 0; |
3749c51a | 871 | struct pci_bus *bus = ctrl->pci_dev->subordinate; |
1da177e4 | 872 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
873 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
874 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | |
875 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | |
1da177e4 | 876 | |
1da177e4 | 877 | if (pi == 2) { |
6558b6ab | 878 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
0afabe90 | 879 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
6558b6ab | 880 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
0afabe90 | 881 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
6558b6ab | 882 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
0afabe90 | 883 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
6558b6ab | 884 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
0afabe90 | 885 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
6558b6ab | 886 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
0afabe90 | 887 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
6558b6ab | 888 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
0afabe90 KK |
889 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
890 | } | |
891 | ||
892 | if (bus_speed == PCI_SPEED_UNKNOWN) { | |
6558b6ab | 893 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
0afabe90 | 894 | bus_speed = PCI_SPEED_133MHz_PCIX; |
6558b6ab | 895 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
0afabe90 | 896 | bus_speed = PCI_SPEED_100MHz_PCIX; |
6558b6ab | 897 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
0afabe90 | 898 | bus_speed = PCI_SPEED_66MHz_PCIX; |
6558b6ab | 899 | else if (slot_avail2 & SLOT_66MHZ) |
0afabe90 | 900 | bus_speed = PCI_SPEED_66MHz; |
6558b6ab | 901 | else if (slot_avail1 & SLOT_33MHZ) |
0afabe90 KK |
902 | bus_speed = PCI_SPEED_33MHz; |
903 | else | |
904 | retval = -ENODEV; | |
1da177e4 LT |
905 | } |
906 | ||
3749c51a | 907 | bus->max_bus_speed = bus_speed; |
f98ca311 | 908 | ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); |
1555b33d | 909 | |
1da177e4 LT |
910 | return retval; |
911 | } | |
912 | ||
bd790082 | 913 | static const struct hpc_ops shpchp_hpc_ops = { |
1da177e4 LT |
914 | .power_on_slot = hpc_power_on_slot, |
915 | .slot_enable = hpc_slot_enable, | |
916 | .slot_disable = hpc_slot_disable, | |
9f593e30 | 917 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1da177e4 LT |
918 | .set_attention_status = hpc_set_attention_status, |
919 | .get_power_status = hpc_get_power_status, | |
920 | .get_attention_status = hpc_get_attention_status, | |
921 | .get_latch_status = hpc_get_latch_status, | |
922 | .get_adapter_status = hpc_get_adapter_status, | |
923 | ||
1da177e4 LT |
924 | .get_adapter_speed = hpc_get_adapter_speed, |
925 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, | |
926 | .get_prog_int = hpc_get_prog_int, | |
927 | ||
928 | .query_power_fault = hpc_query_power_fault, | |
929 | .green_led_on = hpc_set_green_led_on, | |
930 | .green_led_off = hpc_set_green_led_off, | |
931 | .green_led_blink = hpc_set_green_led_blink, | |
9f593e30 | 932 | |
1da177e4 | 933 | .release_ctlr = hpc_release_ctlr, |
1da177e4 LT |
934 | }; |
935 | ||
0abe68ce | 936 | int shpc_init(struct controller *ctrl, struct pci_dev *pdev) |
1da177e4 | 937 | { |
662a98fb | 938 | int rc = -1, num_slots = 0; |
1da177e4 | 939 | u8 hp_slot; |
0455986c | 940 | u32 shpc_base_offset; |
75d97c59 | 941 | u32 tempdword, slot_reg, slot_config; |
1da177e4 LT |
942 | u8 i; |
943 | ||
0455986c | 944 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
be7bce25 | 945 | ctrl_dbg(ctrl, "Hotplug Controller:\n"); |
0455986c | 946 | |
4cac2eb1 BH |
947 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
948 | pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { | |
0455986c KK |
949 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
950 | ctrl->mmio_base = pci_resource_start(pdev, 0); | |
951 | ctrl->mmio_size = pci_resource_len(pdev, 0); | |
1da177e4 | 952 | } else { |
0455986c KK |
953 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
954 | if (!ctrl->cap_offset) { | |
be7bce25 | 955 | ctrl_err(ctrl, "Cannot find PCI capability\n"); |
0abe68ce | 956 | goto abort; |
1da177e4 | 957 | } |
be7bce25 | 958 | ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); |
0455986c | 959 | |
75d97c59 | 960 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1da177e4 | 961 | if (rc) { |
be7bce25 | 962 | ctrl_err(ctrl, "Cannot read base_offset\n"); |
0abe68ce | 963 | goto abort; |
1da177e4 | 964 | } |
0455986c | 965 | |
75d97c59 | 966 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1da177e4 | 967 | if (rc) { |
be7bce25 | 968 | ctrl_err(ctrl, "Cannot read slot config\n"); |
0abe68ce | 969 | goto abort; |
1da177e4 | 970 | } |
0455986c | 971 | num_slots = tempdword & SLOT_NUM; |
be7bce25 | 972 | ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); |
1da177e4 | 973 | |
0455986c | 974 | for (i = 0; i < 9 + num_slots; i++) { |
75d97c59 | 975 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
1da177e4 | 976 | if (rc) { |
227f0647 RD |
977 | ctrl_err(ctrl, "Cannot read creg (index = %d)\n", |
978 | i); | |
0abe68ce | 979 | goto abort; |
1da177e4 | 980 | } |
be7bce25 | 981 | ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); |
1da177e4 | 982 | } |
0455986c KK |
983 | |
984 | ctrl->mmio_base = | |
985 | pci_resource_start(pdev, 0) + shpc_base_offset; | |
986 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; | |
1da177e4 LT |
987 | } |
988 | ||
f98ca311 TI |
989 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
990 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
991 | pdev->subsystem_device); | |
9f593e30 | 992 | |
662a98fb AL |
993 | rc = pci_enable_device(pdev); |
994 | if (rc) { | |
be7bce25 | 995 | ctrl_err(ctrl, "pci_enable_device failed\n"); |
0abe68ce | 996 | goto abort; |
662a98fb | 997 | } |
1da177e4 | 998 | |
0455986c | 999 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
be7bce25 | 1000 | ctrl_err(ctrl, "Cannot reserve MMIO region\n"); |
662a98fb | 1001 | rc = -1; |
0abe68ce | 1002 | goto abort; |
1da177e4 LT |
1003 | } |
1004 | ||
0abe68ce KK |
1005 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1006 | if (!ctrl->creg) { | |
be7bce25 TI |
1007 | ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", |
1008 | ctrl->mmio_size, ctrl->mmio_base); | |
0455986c | 1009 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
662a98fb | 1010 | rc = -1; |
0abe68ce | 1011 | goto abort; |
1da177e4 | 1012 | } |
be7bce25 | 1013 | ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); |
1da177e4 | 1014 | |
6aa4cdd0 | 1015 | mutex_init(&ctrl->crit_sect); |
d29aadda KK |
1016 | mutex_init(&ctrl->cmd_lock); |
1017 | ||
1da177e4 LT |
1018 | /* Setup wait queue */ |
1019 | init_waitqueue_head(&ctrl->queue); | |
1020 | ||
75d97c59 KK |
1021 | ctrl->hpc_ops = &shpchp_hpc_ops; |
1022 | ||
1da177e4 | 1023 | /* Return PCI Controller Info */ |
75d97c59 | 1024 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
0abe68ce KK |
1025 | ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; |
1026 | ctrl->num_slots = slot_config & SLOT_NUM; | |
1027 | ctrl->first_slot = (slot_config & PSN) >> 16; | |
1028 | ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | |
1da177e4 LT |
1029 | |
1030 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | |
75d97c59 | 1031 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
be7bce25 | 1032 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
e7138723 KK |
1033 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
1034 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
1035 | tempdword &= ~SERR_INTR_RSVDZ_MASK; | |
75d97c59 KK |
1036 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1037 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
be7bce25 | 1038 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1da177e4 LT |
1039 | |
1040 | /* Mask the MRL sensor SERR Mask of individual slot in | |
1041 | * Slot SERR-INT Mask & clear all the existing event if any | |
1042 | */ | |
0abe68ce | 1043 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
2b34da7e | 1044 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
be7bce25 TI |
1045 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1046 | hp_slot, slot_reg); | |
795eb5c4 KK |
1047 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1048 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1049 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
1050 | CON_PFAULT_SERR_MASK); | |
1051 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
1052 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 | 1053 | } |
9f593e30 | 1054 | |
0abe68ce KK |
1055 | if (shpchp_poll_mode) { |
1056 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
1057 | init_timer(&ctrl->poll_timer); | |
1058 | start_int_poll_timer(ctrl, 10); | |
1da177e4 LT |
1059 | } else { |
1060 | /* Installs the interrupt handler */ | |
1061 | rc = pci_enable_msi(pdev); | |
1062 | if (rc) { | |
227f0647 RD |
1063 | ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); |
1064 | ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); | |
0abe68ce | 1065 | } |
9f593e30 | 1066 | |
0abe68ce KK |
1067 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
1068 | MY_NAME, (void *)ctrl); | |
e24dcbef TH |
1069 | ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", |
1070 | ctrl->pci_dev->irq, rc); | |
1da177e4 | 1071 | if (rc) { |
227f0647 RD |
1072 | ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", |
1073 | ctrl->pci_dev->irq); | |
0abe68ce | 1074 | goto abort_iounmap; |
1da177e4 | 1075 | } |
1da177e4 | 1076 | } |
be7bce25 | 1077 | ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); |
1da177e4 | 1078 | |
3749c51a MW |
1079 | shpc_get_max_bus_speed(ctrl); |
1080 | shpc_get_cur_bus_speed(ctrl); | |
1081 | ||
795eb5c4 KK |
1082 | /* |
1083 | * Unmask all event interrupts of all slots | |
1084 | */ | |
0abe68ce | 1085 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
2b34da7e | 1086 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
be7bce25 TI |
1087 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1088 | hp_slot, slot_reg); | |
795eb5c4 KK |
1089 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1090 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1091 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); | |
1092 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1093 | } |
1094 | if (!shpchp_poll_mode) { | |
1095 | /* Unmask all general input interrupts and SERR */ | |
75d97c59 | 1096 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 KK |
1097 | tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
1098 | SERR_INTR_RSVDZ_MASK); | |
75d97c59 KK |
1099 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1100 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
be7bce25 | 1101 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1da177e4 LT |
1102 | } |
1103 | ||
1da177e4 LT |
1104 | return 0; |
1105 | ||
1106 | /* We end up here for the many possible ways to fail this API. */ | |
0abe68ce KK |
1107 | abort_iounmap: |
1108 | iounmap(ctrl->creg); | |
1da177e4 | 1109 | abort: |
662a98fb | 1110 | return rc; |
1da177e4 | 1111 | } |