x86: use 28 bits irq NR for pci msi/msix and ht
[deliverable/linux.git] / drivers / pci / htirq.c
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1/*
2 * File: htirq.c
3 * Purpose: Hypertransport Interrupt Capability
4 *
5 * Copyright (C) 2006 Linux Networx
6 * Copyright (C) Eric Biederman <ebiederman@lnxi.com>
7 */
8
9#include <linux/irq.h>
10#include <linux/pci.h>
11#include <linux/spinlock.h>
12#include <linux/slab.h>
13#include <linux/gfp.h>
95d77884 14#include <linux/htirq.h>
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15
16/* Global ht irq lock.
17 *
18 * This is needed to serialize access to the data port in hypertransport
19 * irq capability.
20 *
21 * With multiple simultaneous hypertransport irq devices it might pay
22 * to make this more fine grained. But start with simple, stupid, and correct.
23 */
24static DEFINE_SPINLOCK(ht_irq_lock);
25
26struct ht_irq_cfg {
27 struct pci_dev *dev;
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28 /* Update callback used to cope with buggy hardware */
29 ht_irq_update_t *update;
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30 unsigned pos;
31 unsigned idx;
ec68307c 32 struct ht_irq_msg msg;
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33};
34
8b955b0d 35
ec68307c 36void write_ht_irq_msg(unsigned int irq, struct ht_irq_msg *msg)
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37{
38 struct ht_irq_cfg *cfg = get_irq_data(irq);
39 unsigned long flags;
8b955b0d 40 spin_lock_irqsave(&ht_irq_lock, flags);
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41 if (cfg->msg.address_lo != msg->address_lo) {
42 pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx);
43 pci_write_config_dword(cfg->dev, cfg->pos + 4, msg->address_lo);
44 }
45 if (cfg->msg.address_hi != msg->address_hi) {
46 pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx + 1);
47 pci_write_config_dword(cfg->dev, cfg->pos + 4, msg->address_hi);
48 }
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49 if (cfg->update)
50 cfg->update(cfg->dev, irq, msg);
8b955b0d 51 spin_unlock_irqrestore(&ht_irq_lock, flags);
ec68307c 52 cfg->msg = *msg;
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53}
54
ec68307c 55void fetch_ht_irq_msg(unsigned int irq, struct ht_irq_msg *msg)
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56{
57 struct ht_irq_cfg *cfg = get_irq_data(irq);
ec68307c 58 *msg = cfg->msg;
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59}
60
61void mask_ht_irq(unsigned int irq)
62{
63 struct ht_irq_cfg *cfg;
ec68307c 64 struct ht_irq_msg msg;
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65
66 cfg = get_irq_data(irq);
67
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68 msg = cfg->msg;
69 msg.address_lo |= 1;
70 write_ht_irq_msg(irq, &msg);
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71}
72
73void unmask_ht_irq(unsigned int irq)
74{
75 struct ht_irq_cfg *cfg;
ec68307c 76 struct ht_irq_msg msg;
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77
78 cfg = get_irq_data(irq);
79
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80 msg = cfg->msg;
81 msg.address_lo &= ~1;
82 write_ht_irq_msg(irq, &msg);
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83}
84
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85static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
86{
87 unsigned int irq;
88
89 irq = dev->bus->number;
90 irq <<= 8;
91 irq |= dev->devfn;
92 irq <<= 12;
93
94 return irq;
95}
96
8b955b0d 97/**
43539c38 98 * __ht_create_irq - create an irq and attach it to a device.
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99 * @dev: The hypertransport device to find the irq capability on.
100 * @idx: Which of the possible irqs to attach to.
43539c38 101 * @update: Function to be called when changing the htirq message
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102 *
103 * The irq number of the new irq or a negative error value is returned.
104 */
43539c38 105int __ht_create_irq(struct pci_dev *dev, int idx, ht_irq_update_t *update)
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106{
107 struct ht_irq_cfg *cfg;
108 unsigned long flags;
109 u32 data;
110 int max_irq;
111 int pos;
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112 unsigned int irq;
113 unsigned int irq_want;
8b955b0d 114
120a50df 115 pos = pci_find_ht_capability(dev, HT_CAPTYPE_IRQ);
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116 if (!pos)
117 return -EINVAL;
118
119 /* Verify the idx I want to use is in range */
120 spin_lock_irqsave(&ht_irq_lock, flags);
121 pci_write_config_byte(dev, pos + 2, 1);
122 pci_read_config_dword(dev, pos + 4, &data);
123 spin_unlock_irqrestore(&ht_irq_lock, flags);
124
125 max_irq = (data >> 16) & 0xff;
126 if ( idx > max_irq)
127 return -EINVAL;
128
129 cfg = kmalloc(sizeof(*cfg), GFP_KERNEL);
130 if (!cfg)
131 return -ENOMEM;
132
133 cfg->dev = dev;
43539c38 134 cfg->update = update;
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135 cfg->pos = pos;
136 cfg->idx = 0x10 + (idx * 2);
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137 /* Initialize msg to a value that will never match the first write. */
138 cfg->msg.address_lo = 0xffffffff;
139 cfg->msg.address_hi = 0xffffffff;
8b955b0d 140
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141 irq_want= build_irq_for_pci_dev(dev);
142#ifdef CONFIG_HAVE_SPARSE_IRQ
143 irq = create_irq_nr(irq_want + idx);
144#else
8b955b0d 145 irq = create_irq();
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146#endif
147 if (irq == 0) {
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148 kfree(cfg);
149 return -EBUSY;
150 }
151 set_irq_data(irq, cfg);
152
153 if (arch_setup_ht_irq(irq, dev) < 0) {
154 ht_destroy_irq(irq);
155 return -EBUSY;
156 }
157
158 return irq;
159}
160
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161/**
162 * ht_create_irq - create an irq and attach it to a device.
163 * @dev: The hypertransport device to find the irq capability on.
164 * @idx: Which of the possible irqs to attach to.
165 *
166 * ht_create_irq needs to be called for all hypertransport devices
167 * that generate irqs.
168 *
169 * The irq number of the new irq or a negative error value is returned.
170 */
171int ht_create_irq(struct pci_dev *dev, int idx)
172{
173 return __ht_create_irq(dev, idx, NULL);
174}
175
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176/**
177 * ht_destroy_irq - destroy an irq created with ht_create_irq
178 *
179 * This reverses ht_create_irq removing the specified irq from
180 * existence. The irq should be free before this happens.
181 */
182void ht_destroy_irq(unsigned int irq)
183{
184 struct ht_irq_cfg *cfg;
185
186 cfg = get_irq_data(irq);
187 set_irq_chip(irq, NULL);
188 set_irq_data(irq, NULL);
189 destroy_irq(irq);
190
191 kfree(cfg);
192}
193
43539c38 194EXPORT_SYMBOL(__ht_create_irq);
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195EXPORT_SYMBOL(ht_create_irq);
196EXPORT_SYMBOL(ht_destroy_irq);
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