Commit | Line | Data |
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5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 SS |
3 | #include <linux/spinlock.h> |
4 | #include <linux/jiffies.h> | |
5 | #include <linux/pci.h> | |
b6fcb33a | 6 | #include <linux/irq.h> |
ad3ad3f6 SS |
7 | #include <asm/io_apic.h> |
8 | #include "intel-iommu.h" | |
9 | #include "intr_remapping.h" | |
10 | ||
11 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; | |
12 | static int ir_ioapic_num; | |
2ae21010 SS |
13 | int intr_remapping_enabled; |
14 | ||
5aeecaf4 | 15 | struct irq_2_iommu { |
b6fcb33a SS |
16 | struct intel_iommu *iommu; |
17 | u16 irte_index; | |
18 | u16 sub_handle; | |
19 | u8 irte_mask; | |
5aeecaf4 YL |
20 | }; |
21 | ||
22 | #ifdef CONFIG_HAVE_DYNA_ARRAY | |
23 | static struct irq_2_iommu *irq_2_iommu; | |
24 | DEFINE_DYN_ARRAY(irq_2_iommu, sizeof(struct irq_2_iommu), nr_irqs, PAGE_SIZE, NULL); | |
25 | #else | |
26 | static struct irq_2_iommu irq_2_iommu[NR_IRQS]; | |
27 | #endif | |
b6fcb33a SS |
28 | |
29 | static DEFINE_SPINLOCK(irq_2_ir_lock); | |
30 | ||
31 | int irq_remapped(int irq) | |
32 | { | |
a06148c3 | 33 | if (irq > nr_irqs) |
b6fcb33a SS |
34 | return 0; |
35 | ||
36 | if (!irq_2_iommu[irq].iommu) | |
37 | return 0; | |
38 | ||
39 | return 1; | |
40 | } | |
41 | ||
42 | int get_irte(int irq, struct irte *entry) | |
43 | { | |
44 | int index; | |
45 | ||
a06148c3 | 46 | if (!entry || irq > nr_irqs) |
b6fcb33a SS |
47 | return -1; |
48 | ||
49 | spin_lock(&irq_2_ir_lock); | |
50 | if (!irq_2_iommu[irq].iommu) { | |
51 | spin_unlock(&irq_2_ir_lock); | |
52 | return -1; | |
53 | } | |
54 | ||
55 | index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle; | |
56 | *entry = *(irq_2_iommu[irq].iommu->ir_table->base + index); | |
57 | ||
58 | spin_unlock(&irq_2_ir_lock); | |
59 | return 0; | |
60 | } | |
61 | ||
62 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
63 | { | |
64 | struct ir_table *table = iommu->ir_table; | |
65 | u16 index, start_index; | |
66 | unsigned int mask = 0; | |
67 | int i; | |
68 | ||
69 | if (!count) | |
70 | return -1; | |
71 | ||
72 | /* | |
73 | * start the IRTE search from index 0. | |
74 | */ | |
75 | index = start_index = 0; | |
76 | ||
77 | if (count > 1) { | |
78 | count = __roundup_pow_of_two(count); | |
79 | mask = ilog2(count); | |
80 | } | |
81 | ||
82 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
83 | printk(KERN_ERR | |
84 | "Requested mask %x exceeds the max invalidation handle" | |
85 | " mask value %Lx\n", mask, | |
86 | ecap_max_handle_mask(iommu->ecap)); | |
87 | return -1; | |
88 | } | |
89 | ||
90 | spin_lock(&irq_2_ir_lock); | |
91 | do { | |
92 | for (i = index; i < index + count; i++) | |
93 | if (table->base[i].present) | |
94 | break; | |
95 | /* empty index found */ | |
96 | if (i == index + count) | |
97 | break; | |
98 | ||
99 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
100 | ||
101 | if (index == start_index) { | |
102 | spin_unlock(&irq_2_ir_lock); | |
103 | printk(KERN_ERR "can't allocate an IRTE\n"); | |
104 | return -1; | |
105 | } | |
106 | } while (1); | |
107 | ||
108 | for (i = index; i < index + count; i++) | |
109 | table->base[i].present = 1; | |
110 | ||
111 | irq_2_iommu[irq].iommu = iommu; | |
112 | irq_2_iommu[irq].irte_index = index; | |
113 | irq_2_iommu[irq].sub_handle = 0; | |
114 | irq_2_iommu[irq].irte_mask = mask; | |
115 | ||
116 | spin_unlock(&irq_2_ir_lock); | |
117 | ||
118 | return index; | |
119 | } | |
120 | ||
121 | static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask) | |
122 | { | |
123 | struct qi_desc desc; | |
124 | ||
125 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
126 | | QI_IEC_SELECTIVE; | |
127 | desc.high = 0; | |
128 | ||
129 | qi_submit_sync(&desc, iommu); | |
130 | } | |
131 | ||
132 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
133 | { | |
134 | int index; | |
135 | ||
136 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 137 | if (irq >= nr_irqs || !irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
138 | spin_unlock(&irq_2_ir_lock); |
139 | return -1; | |
140 | } | |
141 | ||
142 | *sub_handle = irq_2_iommu[irq].sub_handle; | |
143 | index = irq_2_iommu[irq].irte_index; | |
144 | spin_unlock(&irq_2_ir_lock); | |
145 | return index; | |
146 | } | |
147 | ||
148 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
149 | { | |
150 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 151 | if (irq >= nr_irqs || irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
152 | spin_unlock(&irq_2_ir_lock); |
153 | return -1; | |
154 | } | |
155 | ||
156 | irq_2_iommu[irq].iommu = iommu; | |
157 | irq_2_iommu[irq].irte_index = index; | |
158 | irq_2_iommu[irq].sub_handle = subhandle; | |
159 | irq_2_iommu[irq].irte_mask = 0; | |
160 | ||
161 | spin_unlock(&irq_2_ir_lock); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index) | |
167 | { | |
168 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 169 | if (irq >= nr_irqs || !irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
170 | spin_unlock(&irq_2_ir_lock); |
171 | return -1; | |
172 | } | |
173 | ||
174 | irq_2_iommu[irq].iommu = NULL; | |
175 | irq_2_iommu[irq].irte_index = 0; | |
176 | irq_2_iommu[irq].sub_handle = 0; | |
177 | irq_2_iommu[irq].irte_mask = 0; | |
178 | ||
179 | spin_unlock(&irq_2_ir_lock); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | int modify_irte(int irq, struct irte *irte_modified) | |
185 | { | |
186 | int index; | |
187 | struct irte *irte; | |
188 | struct intel_iommu *iommu; | |
189 | ||
190 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 191 | if (irq >= nr_irqs || !irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
192 | spin_unlock(&irq_2_ir_lock); |
193 | return -1; | |
194 | } | |
195 | ||
196 | iommu = irq_2_iommu[irq].iommu; | |
197 | ||
198 | index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle; | |
199 | irte = &iommu->ir_table->base[index]; | |
200 | ||
201 | set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1)); | |
202 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); | |
203 | ||
204 | qi_flush_iec(iommu, index, 0); | |
205 | ||
206 | spin_unlock(&irq_2_ir_lock); | |
207 | return 0; | |
208 | } | |
209 | ||
210 | int flush_irte(int irq) | |
211 | { | |
212 | int index; | |
213 | struct intel_iommu *iommu; | |
214 | ||
215 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 216 | if (irq >= nr_irqs || !irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
217 | spin_unlock(&irq_2_ir_lock); |
218 | return -1; | |
219 | } | |
220 | ||
221 | iommu = irq_2_iommu[irq].iommu; | |
222 | ||
223 | index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle; | |
224 | ||
225 | qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask); | |
226 | spin_unlock(&irq_2_ir_lock); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
89027d35 SS |
231 | struct intel_iommu *map_ioapic_to_ir(int apic) |
232 | { | |
233 | int i; | |
234 | ||
235 | for (i = 0; i < MAX_IO_APICS; i++) | |
236 | if (ir_ioapic[i].id == apic) | |
237 | return ir_ioapic[i].iommu; | |
238 | return NULL; | |
239 | } | |
240 | ||
75c46fa6 SS |
241 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
242 | { | |
243 | struct dmar_drhd_unit *drhd; | |
244 | ||
245 | drhd = dmar_find_matched_drhd_unit(dev); | |
246 | if (!drhd) | |
247 | return NULL; | |
248 | ||
249 | return drhd->iommu; | |
250 | } | |
251 | ||
b6fcb33a SS |
252 | int free_irte(int irq) |
253 | { | |
254 | int index, i; | |
255 | struct irte *irte; | |
256 | struct intel_iommu *iommu; | |
257 | ||
258 | spin_lock(&irq_2_ir_lock); | |
a06148c3 | 259 | if (irq >= nr_irqs || !irq_2_iommu[irq].iommu) { |
b6fcb33a SS |
260 | spin_unlock(&irq_2_ir_lock); |
261 | return -1; | |
262 | } | |
263 | ||
264 | iommu = irq_2_iommu[irq].iommu; | |
265 | ||
266 | index = irq_2_iommu[irq].irte_index + irq_2_iommu[irq].sub_handle; | |
267 | irte = &iommu->ir_table->base[index]; | |
268 | ||
269 | if (!irq_2_iommu[irq].sub_handle) { | |
270 | for (i = 0; i < (1 << irq_2_iommu[irq].irte_mask); i++) | |
271 | set_64bit((unsigned long *)irte, 0); | |
272 | qi_flush_iec(iommu, index, irq_2_iommu[irq].irte_mask); | |
273 | } | |
274 | ||
275 | irq_2_iommu[irq].iommu = NULL; | |
276 | irq_2_iommu[irq].irte_index = 0; | |
277 | irq_2_iommu[irq].sub_handle = 0; | |
278 | irq_2_iommu[irq].irte_mask = 0; | |
279 | ||
280 | spin_unlock(&irq_2_ir_lock); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
2ae21010 SS |
285 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
286 | { | |
287 | u64 addr; | |
288 | u32 cmd, sts; | |
289 | unsigned long flags; | |
290 | ||
291 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
292 | ||
293 | spin_lock_irqsave(&iommu->register_lock, flags); | |
294 | ||
295 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
296 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
297 | ||
298 | /* Set interrupt-remapping table pointer */ | |
299 | cmd = iommu->gcmd | DMA_GCMD_SIRTP; | |
300 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | |
301 | ||
302 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
303 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
304 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
305 | ||
306 | /* | |
307 | * global invalidation of interrupt entry cache before enabling | |
308 | * interrupt-remapping. | |
309 | */ | |
310 | qi_global_iec(iommu); | |
311 | ||
312 | spin_lock_irqsave(&iommu->register_lock, flags); | |
313 | ||
314 | /* Enable interrupt-remapping */ | |
315 | cmd = iommu->gcmd | DMA_GCMD_IRE; | |
316 | iommu->gcmd |= DMA_GCMD_IRE; | |
317 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | |
318 | ||
319 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
320 | readl, (sts & DMA_GSTS_IRES), sts); | |
321 | ||
322 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
323 | } | |
324 | ||
325 | ||
326 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) | |
327 | { | |
328 | struct ir_table *ir_table; | |
329 | struct page *pages; | |
330 | ||
331 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
332 | GFP_KERNEL); | |
333 | ||
334 | if (!iommu->ir_table) | |
335 | return -ENOMEM; | |
336 | ||
337 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER); | |
338 | ||
339 | if (!pages) { | |
340 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
341 | INTR_REMAP_PAGE_ORDER); | |
342 | kfree(iommu->ir_table); | |
343 | return -ENOMEM; | |
344 | } | |
345 | ||
346 | ir_table->base = page_address(pages); | |
347 | ||
348 | iommu_set_intr_remapping(iommu, mode); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | int __init enable_intr_remapping(int eim) | |
353 | { | |
354 | struct dmar_drhd_unit *drhd; | |
355 | int setup = 0; | |
356 | ||
357 | /* | |
358 | * check for the Interrupt-remapping support | |
359 | */ | |
360 | for_each_drhd_unit(drhd) { | |
361 | struct intel_iommu *iommu = drhd->iommu; | |
362 | ||
363 | if (!ecap_ir_support(iommu->ecap)) | |
364 | continue; | |
365 | ||
366 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
367 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
368 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
369 | return -1; | |
370 | } | |
371 | } | |
372 | ||
373 | /* | |
374 | * Enable queued invalidation for all the DRHD's. | |
375 | */ | |
376 | for_each_drhd_unit(drhd) { | |
377 | int ret; | |
378 | struct intel_iommu *iommu = drhd->iommu; | |
379 | ret = dmar_enable_qi(iommu); | |
380 | ||
381 | if (ret) { | |
382 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
383 | " invalidation, ecap %Lx, ret %d\n", | |
384 | drhd->reg_base_addr, iommu->ecap, ret); | |
385 | return -1; | |
386 | } | |
387 | } | |
388 | ||
389 | /* | |
390 | * Setup Interrupt-remapping for all the DRHD's now. | |
391 | */ | |
392 | for_each_drhd_unit(drhd) { | |
393 | struct intel_iommu *iommu = drhd->iommu; | |
394 | ||
395 | if (!ecap_ir_support(iommu->ecap)) | |
396 | continue; | |
397 | ||
398 | if (setup_intr_remapping(iommu, eim)) | |
399 | goto error; | |
400 | ||
401 | setup = 1; | |
402 | } | |
403 | ||
404 | if (!setup) | |
405 | goto error; | |
406 | ||
407 | intr_remapping_enabled = 1; | |
408 | ||
409 | return 0; | |
410 | ||
411 | error: | |
412 | /* | |
413 | * handle error condition gracefully here! | |
414 | */ | |
415 | return -1; | |
416 | } | |
ad3ad3f6 SS |
417 | |
418 | static int ir_parse_ioapic_scope(struct acpi_dmar_header *header, | |
419 | struct intel_iommu *iommu) | |
420 | { | |
421 | struct acpi_dmar_hardware_unit *drhd; | |
422 | struct acpi_dmar_device_scope *scope; | |
423 | void *start, *end; | |
424 | ||
425 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
426 | ||
427 | start = (void *)(drhd + 1); | |
428 | end = ((void *)drhd) + header->length; | |
429 | ||
430 | while (start < end) { | |
431 | scope = start; | |
432 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
433 | if (ir_ioapic_num == MAX_IO_APICS) { | |
434 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
435 | return -1; | |
436 | } | |
437 | ||
438 | printk(KERN_INFO "IOAPIC id %d under DRHD base" | |
439 | " 0x%Lx\n", scope->enumeration_id, | |
440 | drhd->address); | |
441 | ||
442 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
443 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
444 | ir_ioapic_num++; | |
445 | } | |
446 | start += scope->length; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /* | |
453 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
454 | * hardware unit. | |
455 | */ | |
456 | int __init parse_ioapics_under_ir(void) | |
457 | { | |
458 | struct dmar_drhd_unit *drhd; | |
459 | int ir_supported = 0; | |
460 | ||
461 | for_each_drhd_unit(drhd) { | |
462 | struct intel_iommu *iommu = drhd->iommu; | |
463 | ||
464 | if (ecap_ir_support(iommu->ecap)) { | |
465 | if (ir_parse_ioapic_scope(drhd->hdr, iommu)) | |
466 | return -1; | |
467 | ||
468 | ir_supported = 1; | |
469 | } | |
470 | } | |
471 | ||
472 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
473 | printk(KERN_WARNING | |
474 | "Not all IO-APIC's listed under remapping hardware\n"); | |
475 | return -1; | |
476 | } | |
477 | ||
478 | return ir_supported; | |
479 | } |