Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
27 | static DEFINE_SPINLOCK(msi_lock); | |
28 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; | |
29 | static kmem_cache_t* msi_cachep; | |
30 | ||
31 | static int pci_msi_enable = 1; | |
1da177e4 | 32 | |
1da177e4 LT |
33 | static int msi_cache_init(void) |
34 | { | |
57181784 PE |
35 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
36 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
37 | if (!msi_cachep) |
38 | return -ENOMEM; | |
39 | ||
40 | return 0; | |
41 | } | |
42 | ||
1ce03373 | 43 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
44 | { |
45 | struct msi_desc *entry; | |
46 | ||
1ce03373 | 47 | entry = msi_desc[irq]; |
277bc33b | 48 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
49 | switch (entry->msi_attrib.type) { |
50 | case PCI_CAP_ID_MSI: | |
277bc33b EB |
51 | if (entry->msi_attrib.maskbit) { |
52 | int pos; | |
53 | u32 mask_bits; | |
54 | ||
55 | pos = (long)entry->mask_base; | |
56 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
57 | mask_bits &= ~(1); | |
58 | mask_bits |= flag; | |
59 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
60 | } | |
1da177e4 | 61 | break; |
1da177e4 LT |
62 | case PCI_CAP_ID_MSIX: |
63 | { | |
64 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
65 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
66 | writel(flag, entry->mask_base + offset); | |
67 | break; | |
68 | } | |
69 | default: | |
277bc33b | 70 | BUG(); |
1da177e4 LT |
71 | break; |
72 | } | |
73 | } | |
74 | ||
3b7d1921 | 75 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 76 | { |
3b7d1921 | 77 | struct msi_desc *entry = get_irq_data(irq); |
0366f8f7 EB |
78 | switch(entry->msi_attrib.type) { |
79 | case PCI_CAP_ID_MSI: | |
80 | { | |
81 | struct pci_dev *dev = entry->dev; | |
82 | int pos = entry->msi_attrib.pos; | |
83 | u16 data; | |
84 | ||
85 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
86 | &msg->address_lo); | |
87 | if (entry->msi_attrib.is_64) { | |
88 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
89 | &msg->address_hi); | |
90 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
91 | } else { | |
92 | msg->address_hi = 0; | |
93 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
94 | } | |
95 | msg->data = data; | |
96 | break; | |
97 | } | |
98 | case PCI_CAP_ID_MSIX: | |
99 | { | |
100 | void __iomem *base; | |
101 | base = entry->mask_base + | |
102 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
103 | ||
104 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
105 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
106 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
107 | break; | |
108 | } | |
109 | default: | |
110 | BUG(); | |
111 | } | |
112 | } | |
1da177e4 | 113 | |
3b7d1921 | 114 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 115 | { |
3b7d1921 | 116 | struct msi_desc *entry = get_irq_data(irq); |
1da177e4 LT |
117 | switch (entry->msi_attrib.type) { |
118 | case PCI_CAP_ID_MSI: | |
119 | { | |
0366f8f7 EB |
120 | struct pci_dev *dev = entry->dev; |
121 | int pos = entry->msi_attrib.pos; | |
122 | ||
123 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
124 | msg->address_lo); | |
125 | if (entry->msi_attrib.is_64) { | |
126 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
127 | msg->address_hi); | |
128 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
129 | msg->data); | |
130 | } else { | |
131 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
132 | msg->data); | |
133 | } | |
1da177e4 LT |
134 | break; |
135 | } | |
136 | case PCI_CAP_ID_MSIX: | |
137 | { | |
0366f8f7 EB |
138 | void __iomem *base; |
139 | base = entry->mask_base + | |
140 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
141 | ||
142 | writel(msg->address_lo, | |
143 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
144 | writel(msg->address_hi, | |
145 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
146 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
147 | break; |
148 | } | |
149 | default: | |
0366f8f7 | 150 | BUG(); |
1da177e4 LT |
151 | } |
152 | } | |
0366f8f7 | 153 | |
3b7d1921 | 154 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 155 | { |
1ce03373 | 156 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
157 | } |
158 | ||
3b7d1921 | 159 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 160 | { |
1ce03373 | 161 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
162 | } |
163 | ||
1ce03373 | 164 | static int msi_free_irq(struct pci_dev* dev, int irq); |
1da177e4 LT |
165 | static int msi_init(void) |
166 | { | |
167 | static int status = -ENOMEM; | |
168 | ||
169 | if (!status) | |
170 | return status; | |
171 | ||
172 | if (pci_msi_quirk) { | |
173 | pci_msi_enable = 0; | |
174 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); | |
175 | status = -EINVAL; | |
176 | return status; | |
177 | } | |
178 | ||
b64c05e7 GG |
179 | status = msi_cache_init(); |
180 | if (status < 0) { | |
1da177e4 LT |
181 | pci_msi_enable = 0; |
182 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
183 | return status; | |
184 | } | |
fd58e55f | 185 | |
1da177e4 LT |
186 | return status; |
187 | } | |
188 | ||
1da177e4 LT |
189 | static struct msi_desc* alloc_msi_entry(void) |
190 | { | |
191 | struct msi_desc *entry; | |
192 | ||
57181784 | 193 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
194 | if (!entry) |
195 | return NULL; | |
196 | ||
1da177e4 LT |
197 | entry->link.tail = entry->link.head = 0; /* single message */ |
198 | entry->dev = NULL; | |
199 | ||
200 | return entry; | |
201 | } | |
202 | ||
1ce03373 | 203 | static void attach_msi_entry(struct msi_desc *entry, int irq) |
1da177e4 LT |
204 | { |
205 | unsigned long flags; | |
206 | ||
207 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 | 208 | msi_desc[irq] = entry; |
1da177e4 LT |
209 | spin_unlock_irqrestore(&msi_lock, flags); |
210 | } | |
211 | ||
3b7d1921 | 212 | static int create_msi_irq(void) |
1da177e4 | 213 | { |
1ce03373 EB |
214 | struct msi_desc *entry; |
215 | int irq; | |
216 | ||
217 | entry = alloc_msi_entry(); | |
218 | if (!entry) | |
219 | return -ENOMEM; | |
f6bc2666 | 220 | |
1ce03373 EB |
221 | irq = create_irq(); |
222 | if (irq < 0) { | |
223 | kmem_cache_free(msi_cachep, entry); | |
224 | return -EBUSY; | |
1da177e4 | 225 | } |
1ce03373 | 226 | |
1ce03373 EB |
227 | set_irq_data(irq, entry); |
228 | ||
229 | return irq; | |
230 | } | |
231 | ||
232 | static void destroy_msi_irq(unsigned int irq) | |
233 | { | |
234 | struct msi_desc *entry; | |
235 | ||
236 | entry = get_irq_data(irq); | |
237 | set_irq_chip(irq, NULL); | |
238 | set_irq_data(irq, NULL); | |
239 | destroy_irq(irq); | |
240 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
241 | } |
242 | ||
243 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
244 | { | |
245 | u16 control; | |
246 | ||
247 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
248 | if (type == PCI_CAP_ID_MSI) { | |
249 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
250 | msi_enable(control, 1); | |
251 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 252 | dev->msi_enabled = 1; |
1da177e4 LT |
253 | } else { |
254 | msix_enable(control); | |
255 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 256 | dev->msix_enabled = 1; |
1da177e4 LT |
257 | } |
258 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
259 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 260 | pci_intx(dev, 0); /* disable intx */ |
1da177e4 LT |
261 | } |
262 | } | |
263 | ||
4602b88d | 264 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
265 | { |
266 | u16 control; | |
267 | ||
268 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
269 | if (type == PCI_CAP_ID_MSI) { | |
270 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
271 | msi_disable(control); | |
272 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 273 | dev->msi_enabled = 0; |
1da177e4 LT |
274 | } else { |
275 | msix_disable(control); | |
276 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 277 | dev->msix_enabled = 0; |
1da177e4 LT |
278 | } |
279 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
280 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 281 | pci_intx(dev, 1); /* enable intx */ |
1da177e4 LT |
282 | } |
283 | } | |
284 | ||
1ce03373 | 285 | static int msi_lookup_irq(struct pci_dev *dev, int type) |
1da177e4 | 286 | { |
1ce03373 | 287 | int irq; |
1da177e4 LT |
288 | unsigned long flags; |
289 | ||
290 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
291 | for (irq = 0; irq < NR_IRQS; irq++) { |
292 | if (!msi_desc[irq] || msi_desc[irq]->dev != dev || | |
293 | msi_desc[irq]->msi_attrib.type != type || | |
294 | msi_desc[irq]->msi_attrib.default_irq != dev->irq) | |
1da177e4 LT |
295 | continue; |
296 | spin_unlock_irqrestore(&msi_lock, flags); | |
1ce03373 EB |
297 | /* This pre-assigned MSI irq for this device |
298 | already exits. Override dev->irq with this irq */ | |
299 | dev->irq = irq; | |
1da177e4 LT |
300 | return 0; |
301 | } | |
302 | spin_unlock_irqrestore(&msi_lock, flags); | |
303 | ||
304 | return -EACCES; | |
305 | } | |
306 | ||
307 | void pci_scan_msi_device(struct pci_dev *dev) | |
308 | { | |
309 | if (!dev) | |
310 | return; | |
1da177e4 LT |
311 | } |
312 | ||
41017f0c SL |
313 | #ifdef CONFIG_PM |
314 | int pci_save_msi_state(struct pci_dev *dev) | |
315 | { | |
316 | int pos, i = 0; | |
317 | u16 control; | |
318 | struct pci_cap_saved_state *save_state; | |
319 | u32 *cap; | |
320 | ||
321 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
322 | if (pos <= 0 || dev->no_msi) | |
323 | return 0; | |
324 | ||
325 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
326 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
327 | return 0; | |
328 | ||
329 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
330 | GFP_KERNEL); | |
331 | if (!save_state) { | |
332 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
333 | return -ENOMEM; | |
334 | } | |
335 | cap = &save_state->data[0]; | |
336 | ||
337 | pci_read_config_dword(dev, pos, &cap[i++]); | |
338 | control = cap[0] >> 16; | |
339 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
340 | if (control & PCI_MSI_FLAGS_64BIT) { | |
341 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
342 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
343 | } else | |
344 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
345 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
346 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
347 | save_state->cap_nr = PCI_CAP_ID_MSI; |
348 | pci_add_saved_cap(dev, save_state); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | void pci_restore_msi_state(struct pci_dev *dev) | |
353 | { | |
354 | int i = 0, pos; | |
355 | u16 control; | |
356 | struct pci_cap_saved_state *save_state; | |
357 | u32 *cap; | |
358 | ||
359 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); | |
360 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
361 | if (!save_state || pos <= 0) | |
362 | return; | |
363 | cap = &save_state->data[0]; | |
364 | ||
365 | control = cap[i++] >> 16; | |
366 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); | |
367 | if (control & PCI_MSI_FLAGS_64BIT) { | |
368 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
369 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
370 | } else | |
371 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
372 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
373 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
374 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
375 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
376 | pci_remove_saved_cap(save_state); | |
377 | kfree(save_state); | |
378 | } | |
379 | ||
380 | int pci_save_msix_state(struct pci_dev *dev) | |
381 | { | |
382 | int pos; | |
fd58e55f | 383 | int temp; |
1ce03373 | 384 | int irq, head, tail = 0; |
41017f0c SL |
385 | u16 control; |
386 | struct pci_cap_saved_state *save_state; | |
387 | ||
388 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
389 | if (pos <= 0 || dev->no_msi) | |
390 | return 0; | |
391 | ||
fd58e55f | 392 | /* save the capability */ |
41017f0c SL |
393 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
394 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
395 | return 0; | |
396 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), | |
397 | GFP_KERNEL); | |
398 | if (!save_state) { | |
399 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
400 | return -ENOMEM; | |
401 | } | |
402 | *((u16 *)&save_state->data[0]) = control; | |
403 | ||
fd58e55f MM |
404 | /* save the table */ |
405 | temp = dev->irq; | |
1ce03373 | 406 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
fd58e55f MM |
407 | kfree(save_state); |
408 | return -EINVAL; | |
409 | } | |
410 | ||
1ce03373 | 411 | irq = head = dev->irq; |
fd58e55f | 412 | while (head != tail) { |
fd58e55f MM |
413 | struct msi_desc *entry; |
414 | ||
1ce03373 | 415 | entry = msi_desc[irq]; |
3b7d1921 | 416 | read_msi_msg(irq, &entry->msg_save); |
fd58e55f | 417 | |
1ce03373 EB |
418 | tail = msi_desc[irq]->link.tail; |
419 | irq = tail; | |
fd58e55f MM |
420 | } |
421 | dev->irq = temp; | |
422 | ||
41017f0c SL |
423 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
424 | pci_add_saved_cap(dev, save_state); | |
425 | return 0; | |
426 | } | |
427 | ||
428 | void pci_restore_msix_state(struct pci_dev *dev) | |
429 | { | |
430 | u16 save; | |
431 | int pos; | |
1ce03373 | 432 | int irq, head, tail = 0; |
41017f0c SL |
433 | struct msi_desc *entry; |
434 | int temp; | |
435 | struct pci_cap_saved_state *save_state; | |
436 | ||
437 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); | |
438 | if (!save_state) | |
439 | return; | |
440 | save = *((u16 *)&save_state->data[0]); | |
441 | pci_remove_saved_cap(save_state); | |
442 | kfree(save_state); | |
443 | ||
444 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
445 | if (pos <= 0) | |
446 | return; | |
447 | ||
448 | /* route the table */ | |
449 | temp = dev->irq; | |
1ce03373 | 450 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) |
41017f0c | 451 | return; |
1ce03373 | 452 | irq = head = dev->irq; |
41017f0c | 453 | while (head != tail) { |
1ce03373 | 454 | entry = msi_desc[irq]; |
3b7d1921 | 455 | write_msi_msg(irq, &entry->msg_save); |
41017f0c | 456 | |
1ce03373 EB |
457 | tail = msi_desc[irq]->link.tail; |
458 | irq = tail; | |
41017f0c SL |
459 | } |
460 | dev->irq = temp; | |
461 | ||
462 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
463 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
464 | } | |
465 | #endif | |
466 | ||
1da177e4 LT |
467 | /** |
468 | * msi_capability_init - configure device's MSI capability structure | |
469 | * @dev: pointer to the pci_dev data structure of MSI device function | |
470 | * | |
eaae4b3a | 471 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 472 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 473 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 474 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
475 | **/ |
476 | static int msi_capability_init(struct pci_dev *dev) | |
477 | { | |
fd58e55f | 478 | int status; |
1da177e4 | 479 | struct msi_desc *entry; |
1ce03373 | 480 | int pos, irq; |
1da177e4 LT |
481 | u16 control; |
482 | ||
483 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
484 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
485 | /* MSI Entry Initialization */ | |
3b7d1921 | 486 | irq = create_msi_irq(); |
1ce03373 EB |
487 | if (irq < 0) |
488 | return irq; | |
489 | ||
490 | entry = get_irq_data(irq); | |
491 | entry->link.head = irq; | |
492 | entry->link.tail = irq; | |
1da177e4 | 493 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 494 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
495 | entry->msi_attrib.entry_nr = 0; |
496 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 497 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 498 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
499 | if (is_mask_bit_support(control)) { |
500 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
501 | is_64bit_address(control)); | |
502 | } | |
3b7d1921 EB |
503 | entry->dev = dev; |
504 | if (entry->msi_attrib.maskbit) { | |
505 | unsigned int maskbits, temp; | |
506 | /* All MSIs are unmasked by default, Mask them all */ | |
507 | pci_read_config_dword(dev, | |
508 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
509 | &maskbits); | |
510 | temp = (1 << multi_msi_capable(control)); | |
511 | temp = ((temp - 1) & ~temp); | |
512 | maskbits |= temp; | |
513 | pci_write_config_dword(dev, | |
514 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
515 | maskbits); | |
516 | } | |
1da177e4 | 517 | /* Configure MSI capability structure */ |
3b7d1921 EB |
518 | status = arch_setup_msi_irq(irq, dev); |
519 | if (status < 0) { | |
1ce03373 | 520 | destroy_msi_irq(irq); |
fd58e55f MM |
521 | return status; |
522 | } | |
41017f0c | 523 | |
1ce03373 | 524 | attach_msi_entry(entry, irq); |
1da177e4 LT |
525 | /* Set MSI enabled bits */ |
526 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
527 | ||
3b7d1921 | 528 | dev->irq = irq; |
1da177e4 LT |
529 | return 0; |
530 | } | |
531 | ||
532 | /** | |
533 | * msix_capability_init - configure device's MSI-X capability | |
534 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
535 | * @entries: pointer to an array of struct msix_entry entries |
536 | * @nvec: number of @entries | |
1da177e4 | 537 | * |
eaae4b3a | 538 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
539 | * single MSI-X irq. A return of zero indicates the successful setup of |
540 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
541 | **/ |
542 | static int msix_capability_init(struct pci_dev *dev, | |
543 | struct msix_entry *entries, int nvec) | |
544 | { | |
545 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
fd58e55f | 546 | int status; |
1ce03373 | 547 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
548 | unsigned long phys_addr; |
549 | u32 table_offset; | |
1da177e4 LT |
550 | u16 control; |
551 | u8 bir; | |
552 | void __iomem *base; | |
553 | ||
554 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
555 | /* Request & Map MSI-X table region */ | |
556 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
557 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
558 | |
559 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 560 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
561 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
562 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
563 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
564 | if (base == NULL) | |
565 | return -ENOMEM; | |
566 | ||
567 | /* MSI-X Table Initialization */ | |
568 | for (i = 0; i < nvec; i++) { | |
3b7d1921 | 569 | irq = create_msi_irq(); |
1ce03373 | 570 | if (irq < 0) |
1da177e4 | 571 | break; |
1da177e4 | 572 | |
1ce03373 | 573 | entry = get_irq_data(irq); |
1da177e4 | 574 | j = entries[i].entry; |
1ce03373 | 575 | entries[i].vector = irq; |
1da177e4 | 576 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 577 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
578 | entry->msi_attrib.entry_nr = j; |
579 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 580 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 581 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
582 | entry->dev = dev; |
583 | entry->mask_base = base; | |
584 | if (!head) { | |
1ce03373 EB |
585 | entry->link.head = irq; |
586 | entry->link.tail = irq; | |
1da177e4 LT |
587 | head = entry; |
588 | } else { | |
589 | entry->link.head = temp; | |
590 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
591 | tail->link.tail = irq; |
592 | head->link.head = irq; | |
1da177e4 | 593 | } |
1ce03373 | 594 | temp = irq; |
1da177e4 | 595 | tail = entry; |
1da177e4 | 596 | /* Configure MSI-X capability structure */ |
3b7d1921 | 597 | status = arch_setup_msi_irq(irq, dev); |
1ce03373 EB |
598 | if (status < 0) { |
599 | destroy_msi_irq(irq); | |
fd58e55f | 600 | break; |
1ce03373 | 601 | } |
fd58e55f | 602 | |
1ce03373 | 603 | attach_msi_entry(entry, irq); |
1da177e4 LT |
604 | } |
605 | if (i != nvec) { | |
92db6d10 | 606 | int avail = i - 1; |
1da177e4 LT |
607 | i--; |
608 | for (; i >= 0; i--) { | |
1ce03373 EB |
609 | irq = (entries + i)->vector; |
610 | msi_free_irq(dev, irq); | |
1da177e4 LT |
611 | (entries + i)->vector = 0; |
612 | } | |
92db6d10 EB |
613 | /* If we had some success report the number of irqs |
614 | * we succeeded in setting up. | |
615 | */ | |
616 | if (avail <= 0) | |
617 | avail = -EBUSY; | |
618 | return avail; | |
1da177e4 LT |
619 | } |
620 | /* Set MSI-X enabled bits */ | |
621 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
24334a12 BG |
626 | /** |
627 | * pci_msi_supported - check whether MSI may be enabled on device | |
628 | * @dev: pointer to the pci_dev data structure of MSI device function | |
629 | * | |
0306ebfa BG |
630 | * Look at global flags, the device itself, and its parent busses |
631 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
632 | **/ |
633 | static | |
634 | int pci_msi_supported(struct pci_dev * dev) | |
635 | { | |
636 | struct pci_bus *bus; | |
637 | ||
0306ebfa | 638 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
639 | if (!pci_msi_enable || !dev || dev->no_msi) |
640 | return -EINVAL; | |
641 | ||
0306ebfa BG |
642 | /* Any bridge which does NOT route MSI transactions from it's |
643 | * secondary bus to it's primary bus must set NO_MSI flag on | |
644 | * the secondary pci_bus. | |
645 | * We expect only arch-specific PCI host bus controller driver | |
646 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
647 | */ | |
24334a12 BG |
648 | for (bus = dev->bus; bus; bus = bus->parent) |
649 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
650 | return -EINVAL; | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
1da177e4 LT |
655 | /** |
656 | * pci_enable_msi - configure device's MSI capability structure | |
657 | * @dev: pointer to the pci_dev data structure of MSI device function | |
658 | * | |
659 | * Setup the MSI capability structure of device function with | |
1ce03373 | 660 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
661 | * MSI mode enabled on its hardware device function. A return of zero |
662 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 663 | * irq or non-zero for otherwise. |
1da177e4 LT |
664 | **/ |
665 | int pci_enable_msi(struct pci_dev* dev) | |
666 | { | |
24334a12 | 667 | int pos, temp, status; |
1da177e4 | 668 | |
24334a12 BG |
669 | if (pci_msi_supported(dev) < 0) |
670 | return -EINVAL; | |
6e325a62 | 671 | |
1da177e4 LT |
672 | temp = dev->irq; |
673 | ||
b64c05e7 GG |
674 | status = msi_init(); |
675 | if (status < 0) | |
1da177e4 LT |
676 | return status; |
677 | ||
b64c05e7 GG |
678 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
679 | if (!pos) | |
1da177e4 LT |
680 | return -EINVAL; |
681 | ||
1ce03373 | 682 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI)); |
1da177e4 | 683 | |
1ce03373 | 684 | /* Check whether driver already requested for MSI-X irqs */ |
b64c05e7 | 685 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 | 686 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1da177e4 | 687 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
1ce03373 | 688 | "Device already has MSI-X irq assigned\n", |
1da177e4 LT |
689 | pci_name(dev)); |
690 | dev->irq = temp; | |
691 | return -EINVAL; | |
692 | } | |
693 | status = msi_capability_init(dev); | |
1da177e4 LT |
694 | return status; |
695 | } | |
696 | ||
697 | void pci_disable_msi(struct pci_dev* dev) | |
698 | { | |
699 | struct msi_desc *entry; | |
1ce03373 | 700 | int pos, default_irq; |
1da177e4 LT |
701 | u16 control; |
702 | unsigned long flags; | |
703 | ||
309e57df MW |
704 | if (!pci_msi_enable) |
705 | return; | |
b64c05e7 GG |
706 | if (!dev) |
707 | return; | |
309e57df | 708 | |
b64c05e7 GG |
709 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
710 | if (!pos) | |
1da177e4 LT |
711 | return; |
712 | ||
713 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
714 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
715 | return; | |
716 | ||
7bd007e4 EB |
717 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); |
718 | ||
1da177e4 LT |
719 | spin_lock_irqsave(&msi_lock, flags); |
720 | entry = msi_desc[dev->irq]; | |
721 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
722 | spin_unlock_irqrestore(&msi_lock, flags); | |
723 | return; | |
724 | } | |
1f80025e | 725 | if (irq_has_action(dev->irq)) { |
1da177e4 LT |
726 | spin_unlock_irqrestore(&msi_lock, flags); |
727 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " | |
1ce03373 | 728 | "free_irq() on MSI irq %d\n", |
1da177e4 | 729 | pci_name(dev), dev->irq); |
1f80025e | 730 | BUG_ON(irq_has_action(dev->irq)); |
1da177e4 | 731 | } else { |
1ce03373 | 732 | default_irq = entry->msi_attrib.default_irq; |
1da177e4 | 733 | spin_unlock_irqrestore(&msi_lock, flags); |
1ce03373 | 734 | msi_free_irq(dev, dev->irq); |
7bd007e4 | 735 | |
1ce03373 EB |
736 | /* Restore dev->irq to its default pin-assertion irq */ |
737 | dev->irq = default_irq; | |
1da177e4 LT |
738 | } |
739 | } | |
740 | ||
1ce03373 | 741 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
742 | { |
743 | struct msi_desc *entry; | |
744 | int head, entry_nr, type; | |
745 | void __iomem *base; | |
746 | unsigned long flags; | |
747 | ||
3b7d1921 | 748 | arch_teardown_msi_irq(irq); |
fd58e55f | 749 | |
1da177e4 | 750 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 751 | entry = msi_desc[irq]; |
1da177e4 LT |
752 | if (!entry || entry->dev != dev) { |
753 | spin_unlock_irqrestore(&msi_lock, flags); | |
754 | return -EINVAL; | |
755 | } | |
756 | type = entry->msi_attrib.type; | |
757 | entry_nr = entry->msi_attrib.entry_nr; | |
758 | head = entry->link.head; | |
759 | base = entry->mask_base; | |
760 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
761 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
762 | entry->dev = NULL; | |
1ce03373 | 763 | msi_desc[irq] = NULL; |
1da177e4 LT |
764 | spin_unlock_irqrestore(&msi_lock, flags); |
765 | ||
1ce03373 | 766 | destroy_msi_irq(irq); |
1da177e4 LT |
767 | |
768 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
769 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
770 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 771 | |
1ce03373 | 772 | if (head == irq) |
1da177e4 | 773 | iounmap(base); |
1da177e4 LT |
774 | } |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
1da177e4 LT |
779 | /** |
780 | * pci_enable_msix - configure device's MSI-X capability structure | |
781 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 782 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 783 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
784 | * |
785 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 786 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
787 | * MSI-X mode enabled on its hardware device function. A return of zero |
788 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 789 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 790 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 791 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
792 | * its request. |
793 | **/ | |
794 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
795 | { | |
92db6d10 | 796 | int status, pos, nr_entries; |
1da177e4 LT |
797 | int i, j, temp; |
798 | u16 control; | |
1da177e4 | 799 | |
24334a12 | 800 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
801 | return -EINVAL; |
802 | ||
b64c05e7 GG |
803 | status = msi_init(); |
804 | if (status < 0) | |
1da177e4 LT |
805 | return status; |
806 | ||
b64c05e7 GG |
807 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
808 | if (!pos) | |
1da177e4 LT |
809 | return -EINVAL; |
810 | ||
811 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
812 | nr_entries = multi_msix_capable(control); |
813 | if (nvec > nr_entries) | |
814 | return -EINVAL; | |
815 | ||
816 | /* Check for any invalid entries */ | |
817 | for (i = 0; i < nvec; i++) { | |
818 | if (entries[i].entry >= nr_entries) | |
819 | return -EINVAL; /* invalid entry */ | |
820 | for (j = i + 1; j < nvec; j++) { | |
821 | if (entries[i].entry == entries[j].entry) | |
822 | return -EINVAL; /* duplicate entry */ | |
823 | } | |
824 | } | |
825 | temp = dev->irq; | |
1ce03373 | 826 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)); |
7bd007e4 | 827 | |
1ce03373 | 828 | /* Check whether driver already requested for MSI irq */ |
1da177e4 | 829 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && |
1ce03373 | 830 | !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1da177e4 | 831 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 832 | "Device already has an MSI irq assigned\n", |
1da177e4 LT |
833 | pci_name(dev)); |
834 | dev->irq = temp; | |
835 | return -EINVAL; | |
836 | } | |
1da177e4 | 837 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
838 | return status; |
839 | } | |
840 | ||
841 | void pci_disable_msix(struct pci_dev* dev) | |
842 | { | |
843 | int pos, temp; | |
844 | u16 control; | |
845 | ||
309e57df MW |
846 | if (!pci_msi_enable) |
847 | return; | |
b64c05e7 GG |
848 | if (!dev) |
849 | return; | |
850 | ||
851 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
852 | if (!pos) | |
1da177e4 LT |
853 | return; |
854 | ||
855 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
856 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
857 | return; | |
858 | ||
7bd007e4 EB |
859 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); |
860 | ||
1da177e4 | 861 | temp = dev->irq; |
1ce03373 | 862 | if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1f80025e | 863 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
864 | unsigned long flags; |
865 | ||
1ce03373 | 866 | irq = head = dev->irq; |
7bd007e4 | 867 | dev->irq = temp; /* Restore pin IRQ */ |
1da177e4 | 868 | while (head != tail) { |
7bd007e4 | 869 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 870 | tail = msi_desc[irq]->link.tail; |
7bd007e4 | 871 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 872 | if (irq_has_action(irq)) |
1da177e4 | 873 | warning = 1; |
1ce03373 EB |
874 | else if (irq != head) /* Release MSI-X irq */ |
875 | msi_free_irq(dev, irq); | |
876 | irq = tail; | |
1da177e4 | 877 | } |
1ce03373 | 878 | msi_free_irq(dev, irq); |
1da177e4 | 879 | if (warning) { |
1da177e4 | 880 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " |
1ce03373 | 881 | "free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
882 | pci_name(dev)); |
883 | BUG_ON(warning > 0); | |
1da177e4 LT |
884 | } |
885 | } | |
886 | } | |
887 | ||
888 | /** | |
1ce03373 | 889 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
890 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
891 | * | |
eaae4b3a | 892 | * Being called during hotplug remove, from which the device function |
1ce03373 | 893 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
894 | * allocated for this device function, are reclaimed to unused state, |
895 | * which may be used later on. | |
896 | **/ | |
897 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
898 | { | |
1f80025e | 899 | int pos, temp; |
1da177e4 LT |
900 | unsigned long flags; |
901 | ||
902 | if (!pci_msi_enable || !dev) | |
903 | return; | |
904 | ||
905 | temp = dev->irq; /* Save IOAPIC IRQ */ | |
b64c05e7 | 906 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1ce03373 | 907 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1f80025e | 908 | if (irq_has_action(dev->irq)) { |
1da177e4 | 909 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 910 | "called without free_irq() on MSI irq %d\n", |
1da177e4 | 911 | pci_name(dev), dev->irq); |
1f80025e | 912 | BUG_ON(irq_has_action(dev->irq)); |
1ce03373 EB |
913 | } else /* Release MSI irq assigned to this device */ |
914 | msi_free_irq(dev, dev->irq); | |
1da177e4 LT |
915 | dev->irq = temp; /* Restore IOAPIC IRQ */ |
916 | } | |
b64c05e7 | 917 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 EB |
918 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
919 | int irq, head, tail = 0, warning = 0; | |
1da177e4 LT |
920 | void __iomem *base = NULL; |
921 | ||
1ce03373 | 922 | irq = head = dev->irq; |
1da177e4 LT |
923 | while (head != tail) { |
924 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
925 | tail = msi_desc[irq]->link.tail; |
926 | base = msi_desc[irq]->mask_base; | |
1da177e4 | 927 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 928 | if (irq_has_action(irq)) |
1da177e4 | 929 | warning = 1; |
1ce03373 EB |
930 | else if (irq != head) /* Release MSI-X irq */ |
931 | msi_free_irq(dev, irq); | |
932 | irq = tail; | |
1da177e4 | 933 | } |
1ce03373 | 934 | msi_free_irq(dev, irq); |
1da177e4 | 935 | if (warning) { |
1da177e4 LT |
936 | iounmap(base); |
937 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 938 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
939 | pci_name(dev)); |
940 | BUG_ON(warning > 0); | |
941 | } | |
942 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
943 | } | |
944 | } | |
945 | ||
309e57df MW |
946 | void pci_no_msi(void) |
947 | { | |
948 | pci_msi_enable = 0; | |
949 | } | |
950 | ||
1da177e4 LT |
951 | EXPORT_SYMBOL(pci_enable_msi); |
952 | EXPORT_SYMBOL(pci_disable_msi); | |
953 | EXPORT_SYMBOL(pci_enable_msix); | |
954 | EXPORT_SYMBOL(pci_disable_msix); |