Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
3878eaef | 23 | #include <linux/irqdomain.h> |
b6eec9b7 | 24 | #include <linux/of_irq.h> |
1da177e4 LT |
25 | |
26 | #include "pci.h" | |
1da177e4 | 27 | |
1da177e4 | 28 | static int pci_msi_enable = 1; |
38737d82 | 29 | int pci_msi_ignore_mask; |
1da177e4 | 30 | |
527eee29 BH |
31 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
32 | ||
8e047ada JL |
33 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
34 | static struct irq_domain *pci_msi_default_domain; | |
35 | static DEFINE_MUTEX(pci_msi_domain_lock); | |
36 | ||
37 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) | |
38 | { | |
39 | return pci_msi_default_domain; | |
40 | } | |
41 | ||
020c3126 MZ |
42 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
43 | { | |
d8a1cb75 | 44 | struct irq_domain *domain; |
020c3126 | 45 | |
d8a1cb75 MZ |
46 | domain = dev_get_msi_domain(&dev->dev); |
47 | if (domain) | |
48 | return domain; | |
020c3126 | 49 | |
d8a1cb75 | 50 | return arch_get_pci_msi_domain(dev); |
020c3126 MZ |
51 | } |
52 | ||
8e047ada JL |
53 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
54 | { | |
55 | struct irq_domain *domain; | |
56 | ||
020c3126 | 57 | domain = pci_msi_get_domain(dev); |
3845d295 | 58 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
59 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); |
60 | ||
61 | return arch_setup_msi_irqs(dev, nvec, type); | |
62 | } | |
63 | ||
64 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
65 | { | |
66 | struct irq_domain *domain; | |
67 | ||
020c3126 | 68 | domain = pci_msi_get_domain(dev); |
3845d295 | 69 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
70 | pci_msi_domain_free_irqs(domain, dev); |
71 | else | |
72 | arch_teardown_msi_irqs(dev); | |
73 | } | |
74 | #else | |
75 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
76 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
77 | #endif | |
527eee29 | 78 | |
6a9e7f20 AB |
79 | /* Arch hooks */ |
80 | ||
4287d824 TP |
81 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
82 | { | |
2291ec09 | 83 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
84 | int err; |
85 | ||
86 | if (!chip || !chip->setup_irq) | |
87 | return -EINVAL; | |
88 | ||
89 | err = chip->setup_irq(chip, dev, desc); | |
90 | if (err < 0) | |
91 | return err; | |
92 | ||
93 | irq_set_chip_data(desc->irq, chip); | |
94 | ||
95 | return 0; | |
4287d824 TP |
96 | } |
97 | ||
98 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 99 | { |
c2791b80 | 100 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
101 | |
102 | if (!chip || !chip->teardown_irq) | |
103 | return; | |
104 | ||
105 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
106 | } |
107 | ||
4287d824 | 108 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 109 | { |
339e5b44 | 110 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
111 | struct msi_desc *entry; |
112 | int ret; | |
113 | ||
339e5b44 LS |
114 | if (chip && chip->setup_irqs) |
115 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
116 | /* |
117 | * If an architecture wants to support multiple MSI, it needs to | |
118 | * override arch_setup_msi_irqs() | |
119 | */ | |
120 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
121 | return 1; | |
122 | ||
5004e98a | 123 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 124 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 125 | if (ret < 0) |
6a9e7f20 | 126 | return ret; |
b5fbf533 ME |
127 | if (ret > 0) |
128 | return -ENOSPC; | |
6a9e7f20 AB |
129 | } |
130 | ||
131 | return 0; | |
132 | } | |
1525bf0d | 133 | |
4287d824 TP |
134 | /* |
135 | * We have a default implementation available as a separate non-weak | |
136 | * function, as it is used by the Xen x86 PCI code | |
137 | */ | |
1525bf0d | 138 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 139 | { |
63a7b17e | 140 | int i; |
6a9e7f20 AB |
141 | struct msi_desc *entry; |
142 | ||
5004e98a | 143 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
144 | if (entry->irq) |
145 | for (i = 0; i < entry->nvec_used; i++) | |
146 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
147 | } |
148 | ||
4287d824 TP |
149 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
150 | { | |
151 | return default_teardown_msi_irqs(dev); | |
152 | } | |
76ccc297 | 153 | |
ac8344c4 | 154 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
155 | { |
156 | struct msi_desc *entry; | |
157 | ||
158 | entry = NULL; | |
159 | if (dev->msix_enabled) { | |
5004e98a | 160 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
161 | if (irq == entry->irq) |
162 | break; | |
163 | } | |
164 | } else if (dev->msi_enabled) { | |
165 | entry = irq_get_msi_desc(irq); | |
166 | } | |
167 | ||
168 | if (entry) | |
83a18912 | 169 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 170 | } |
4287d824 | 171 | |
ac8344c4 | 172 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 173 | { |
ac8344c4 | 174 | return default_restore_msi_irqs(dev); |
4287d824 | 175 | } |
76ccc297 | 176 | |
bffac3c5 MW |
177 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
178 | { | |
0b49ec37 MW |
179 | /* Don't shift by >= width of type */ |
180 | if (x >= 5) | |
181 | return 0xffffffff; | |
182 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
183 | } |
184 | ||
ce6fce42 MW |
185 | /* |
186 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
187 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
188 | * reliably as devices without an INTx disable bit will then generate a | |
189 | * level IRQ which will never be cleared. | |
ce6fce42 | 190 | */ |
23ed8d57 | 191 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 192 | { |
f2440d9a | 193 | u32 mask_bits = desc->masked; |
1da177e4 | 194 | |
38737d82 | 195 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 196 | return 0; |
f2440d9a MW |
197 | |
198 | mask_bits &= ~mask; | |
199 | mask_bits |= flag; | |
e39758e0 JL |
200 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
201 | mask_bits); | |
12abb8ba HS |
202 | |
203 | return mask_bits; | |
204 | } | |
205 | ||
206 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
207 | { | |
23ed8d57 | 208 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
209 | } |
210 | ||
5eb6d660 CH |
211 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
212 | { | |
213 | return desc->mask_base + | |
214 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
215 | } | |
216 | ||
f2440d9a MW |
217 | /* |
218 | * This internal function does not flush PCI writes to the device. | |
219 | * All users must ensure that they read from the device before either | |
220 | * assuming that the device state is up to date, or returning out of this | |
221 | * file. This saves a few milliseconds when initialising devices with lots | |
222 | * of MSI-X interrupts. | |
223 | */ | |
23ed8d57 | 224 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
225 | { |
226 | u32 mask_bits = desc->masked; | |
38737d82 YW |
227 | |
228 | if (pci_msi_ignore_mask) | |
229 | return 0; | |
230 | ||
8d805286 SY |
231 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
232 | if (flag) | |
233 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
5eb6d660 | 234 | writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL); |
12abb8ba HS |
235 | |
236 | return mask_bits; | |
237 | } | |
238 | ||
239 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
240 | { | |
23ed8d57 | 241 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 242 | } |
24d27553 | 243 | |
1c9db525 | 244 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 245 | { |
c391f262 | 246 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 247 | |
f2440d9a MW |
248 | if (desc->msi_attrib.is_msix) { |
249 | msix_mask_irq(desc, flag); | |
250 | readl(desc->mask_base); /* Flush write to device */ | |
251 | } else { | |
a281b788 | 252 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 253 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 254 | } |
f2440d9a MW |
255 | } |
256 | ||
23ed8d57 TG |
257 | /** |
258 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
259 | * @data: pointer to irqdata associated to that interrupt | |
260 | */ | |
261 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 262 | { |
1c9db525 | 263 | msi_set_mask_bit(data, 1); |
f2440d9a | 264 | } |
a4289dc2 | 265 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 266 | |
23ed8d57 TG |
267 | /** |
268 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
269 | * @data: pointer to irqdata associated to that interrupt | |
270 | */ | |
271 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 272 | { |
1c9db525 | 273 | msi_set_mask_bit(data, 0); |
1da177e4 | 274 | } |
a4289dc2 | 275 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 276 | |
ac8344c4 D |
277 | void default_restore_msi_irqs(struct pci_dev *dev) |
278 | { | |
279 | struct msi_desc *entry; | |
280 | ||
5004e98a | 281 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 282 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
283 | } |
284 | ||
891d4a48 | 285 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 286 | { |
e39758e0 JL |
287 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
288 | ||
289 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
290 | |
291 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 292 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 BH |
293 | |
294 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
295 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
296 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
297 | } else { | |
f5322169 | 298 | int pos = dev->msi_cap; |
30da5524 BH |
299 | u16 data; |
300 | ||
9925ad0c BH |
301 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
302 | &msg->address_lo); | |
30da5524 | 303 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
304 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
305 | &msg->address_hi); | |
2f221349 | 306 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
307 | } else { |
308 | msg->address_hi = 0; | |
2f221349 | 309 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
310 | } |
311 | msg->data = data; | |
312 | } | |
313 | } | |
314 | ||
83a18912 | 315 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 316 | { |
e39758e0 JL |
317 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
318 | ||
319 | if (dev->current_state != PCI_D0) { | |
fcd097f3 BH |
320 | /* Don't touch the hardware now */ |
321 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 322 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 323 | |
2c21fd4b HS |
324 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
325 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
326 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 327 | } else { |
f5322169 | 328 | int pos = dev->msi_cap; |
1c8d7b0a MW |
329 | u16 msgctl; |
330 | ||
f84ecd28 | 331 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
332 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
333 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 334 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 335 | |
9925ad0c BH |
336 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
337 | msg->address_lo); | |
0366f8f7 | 338 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
339 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
340 | msg->address_hi); | |
2f221349 BH |
341 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
342 | msg->data); | |
0366f8f7 | 343 | } else { |
2f221349 BH |
344 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
345 | msg->data); | |
0366f8f7 | 346 | } |
1da177e4 | 347 | } |
392ee1e6 | 348 | entry->msg = *msg; |
1da177e4 | 349 | } |
0366f8f7 | 350 | |
83a18912 | 351 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 352 | { |
dced35ae | 353 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 354 | |
83a18912 | 355 | __pci_write_msi_msg(entry, msg); |
3145e941 | 356 | } |
83a18912 | 357 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 358 | |
f56e4481 HS |
359 | static void free_msi_irqs(struct pci_dev *dev) |
360 | { | |
5004e98a | 361 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 362 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
363 | struct attribute **msi_attrs; |
364 | struct device_attribute *dev_attr; | |
63a7b17e | 365 | int i, count = 0; |
f56e4481 | 366 | |
5004e98a | 367 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
368 | if (entry->irq) |
369 | for (i = 0; i < entry->nvec_used; i++) | |
370 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 371 | |
8e047ada | 372 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 373 | |
5004e98a | 374 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 375 | if (entry->msi_attrib.is_msix) { |
5004e98a | 376 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
377 | iounmap(entry->mask_base); |
378 | } | |
424eb391 | 379 | |
f56e4481 HS |
380 | list_del(&entry->list); |
381 | kfree(entry); | |
382 | } | |
1c51b50c GKH |
383 | |
384 | if (dev->msi_irq_groups) { | |
385 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
386 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 387 | while (msi_attrs[count]) { |
1c51b50c GKH |
388 | dev_attr = container_of(msi_attrs[count], |
389 | struct device_attribute, attr); | |
390 | kfree(dev_attr->attr.name); | |
391 | kfree(dev_attr); | |
392 | ++count; | |
393 | } | |
394 | kfree(msi_attrs); | |
395 | kfree(dev->msi_irq_groups[0]); | |
396 | kfree(dev->msi_irq_groups); | |
397 | dev->msi_irq_groups = NULL; | |
398 | } | |
f56e4481 | 399 | } |
c54c1879 | 400 | |
ba698ad4 DM |
401 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
402 | { | |
403 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
404 | pci_intx(dev, enable); | |
405 | } | |
406 | ||
8fed4b65 | 407 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 408 | { |
41017f0c | 409 | u16 control; |
392ee1e6 | 410 | struct msi_desc *entry; |
41017f0c | 411 | |
b1cbf4e4 EB |
412 | if (!dev->msi_enabled) |
413 | return; | |
414 | ||
dced35ae | 415 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 416 | |
ba698ad4 | 417 | pci_intx_for_msi(dev, 0); |
61b64abd | 418 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 419 | arch_restore_msi_irqs(dev); |
392ee1e6 | 420 | |
f5322169 | 421 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
422 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
423 | entry->masked); | |
abad2ec9 | 424 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 425 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 426 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
427 | } |
428 | ||
429 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 430 | { |
41017f0c | 431 | struct msi_desc *entry; |
41017f0c | 432 | |
ded86d8d EB |
433 | if (!dev->msix_enabled) |
434 | return; | |
5004e98a | 435 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 436 | |
41017f0c | 437 | /* route the table */ |
ba698ad4 | 438 | pci_intx_for_msi(dev, 0); |
61b64abd | 439 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 440 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 441 | |
ac8344c4 | 442 | arch_restore_msi_irqs(dev); |
5004e98a | 443 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 444 | msix_mask_irq(entry, entry->masked); |
41017f0c | 445 | |
61b64abd | 446 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 447 | } |
8fed4b65 ME |
448 | |
449 | void pci_restore_msi_state(struct pci_dev *dev) | |
450 | { | |
451 | __pci_restore_msi_state(dev); | |
452 | __pci_restore_msix_state(dev); | |
453 | } | |
94688cf2 | 454 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 455 | |
1c51b50c | 456 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
457 | char *buf) |
458 | { | |
1c51b50c GKH |
459 | struct msi_desc *entry; |
460 | unsigned long irq; | |
461 | int retval; | |
da8d1c8b | 462 | |
1c51b50c GKH |
463 | retval = kstrtoul(attr->attr.name, 10, &irq); |
464 | if (retval) | |
465 | return retval; | |
da8d1c8b | 466 | |
e11ece5a YW |
467 | entry = irq_get_msi_desc(irq); |
468 | if (entry) | |
469 | return sprintf(buf, "%s\n", | |
470 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
471 | ||
1c51b50c | 472 | return -ENODEV; |
da8d1c8b NH |
473 | } |
474 | ||
da8d1c8b NH |
475 | static int populate_msi_sysfs(struct pci_dev *pdev) |
476 | { | |
1c51b50c GKH |
477 | struct attribute **msi_attrs; |
478 | struct attribute *msi_attr; | |
479 | struct device_attribute *msi_dev_attr; | |
480 | struct attribute_group *msi_irq_group; | |
481 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 482 | struct msi_desc *entry; |
1c51b50c GKH |
483 | int ret = -ENOMEM; |
484 | int num_msi = 0; | |
da8d1c8b | 485 | int count = 0; |
a8676066 | 486 | int i; |
da8d1c8b | 487 | |
1c51b50c | 488 | /* Determine how many msi entries we have */ |
5004e98a | 489 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 490 | num_msi += entry->nvec_used; |
1c51b50c GKH |
491 | if (!num_msi) |
492 | return 0; | |
da8d1c8b | 493 | |
1c51b50c GKH |
494 | /* Dynamically create the MSI attributes for the PCI device */ |
495 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
496 | if (!msi_attrs) | |
497 | return -ENOMEM; | |
5004e98a | 498 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
499 | for (i = 0; i < entry->nvec_used; i++) { |
500 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
501 | if (!msi_dev_attr) | |
502 | goto error_attrs; | |
503 | msi_attrs[count] = &msi_dev_attr->attr; | |
504 | ||
505 | sysfs_attr_init(&msi_dev_attr->attr); | |
506 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
507 | entry->irq + i); | |
508 | if (!msi_dev_attr->attr.name) | |
509 | goto error_attrs; | |
510 | msi_dev_attr->attr.mode = S_IRUGO; | |
511 | msi_dev_attr->show = msi_mode_show; | |
512 | ++count; | |
513 | } | |
da8d1c8b NH |
514 | } |
515 | ||
1c51b50c GKH |
516 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
517 | if (!msi_irq_group) | |
518 | goto error_attrs; | |
519 | msi_irq_group->name = "msi_irqs"; | |
520 | msi_irq_group->attrs = msi_attrs; | |
521 | ||
522 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
523 | if (!msi_irq_groups) | |
524 | goto error_irq_group; | |
525 | msi_irq_groups[0] = msi_irq_group; | |
526 | ||
527 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
528 | if (ret) | |
529 | goto error_irq_groups; | |
530 | pdev->msi_irq_groups = msi_irq_groups; | |
531 | ||
da8d1c8b NH |
532 | return 0; |
533 | ||
1c51b50c GKH |
534 | error_irq_groups: |
535 | kfree(msi_irq_groups); | |
536 | error_irq_group: | |
537 | kfree(msi_irq_group); | |
538 | error_attrs: | |
539 | count = 0; | |
540 | msi_attr = msi_attrs[count]; | |
541 | while (msi_attr) { | |
542 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
543 | kfree(msi_attr->name); | |
544 | kfree(msi_dev_attr); | |
545 | ++count; | |
546 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 547 | } |
29237756 | 548 | kfree(msi_attrs); |
da8d1c8b NH |
549 | return ret; |
550 | } | |
551 | ||
63a7b17e | 552 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
d873b4d4 YW |
553 | { |
554 | u16 control; | |
555 | struct msi_desc *entry; | |
556 | ||
557 | /* MSI Entry Initialization */ | |
aa48b6f7 | 558 | entry = alloc_msi_entry(&dev->dev); |
d873b4d4 YW |
559 | if (!entry) |
560 | return NULL; | |
561 | ||
562 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
563 | ||
564 | entry->msi_attrib.is_msix = 0; | |
565 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
566 | entry->msi_attrib.entry_nr = 0; | |
567 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
568 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 569 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e JL |
570 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
571 | entry->nvec_used = nvec; | |
4ef33685 | 572 | entry->affinity = dev->irq_affinity; |
d873b4d4 YW |
573 | |
574 | if (control & PCI_MSI_FLAGS_64BIT) | |
575 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
576 | else | |
577 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
578 | ||
579 | /* Save the initial mask status */ | |
580 | if (entry->msi_attrib.maskbit) | |
581 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
582 | ||
583 | return entry; | |
584 | } | |
585 | ||
f144d149 BH |
586 | static int msi_verify_entries(struct pci_dev *dev) |
587 | { | |
588 | struct msi_desc *entry; | |
589 | ||
5004e98a | 590 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
591 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
592 | continue; | |
593 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
594 | " tried to assign one above 4G\n"); | |
595 | return -EIO; | |
596 | } | |
597 | return 0; | |
598 | } | |
599 | ||
1da177e4 LT |
600 | /** |
601 | * msi_capability_init - configure device's MSI capability structure | |
602 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 603 | * @nvec: number of interrupts to allocate |
1da177e4 | 604 | * |
1c8d7b0a MW |
605 | * Setup the MSI capability structure of the device with the requested |
606 | * number of interrupts. A return value of zero indicates the successful | |
607 | * setup of an entry with the new MSI irq. A negative return value indicates | |
608 | * an error, and a positive return value indicates the number of interrupts | |
609 | * which could have been allocated. | |
610 | */ | |
611 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
612 | { |
613 | struct msi_desc *entry; | |
f465136d | 614 | int ret; |
f2440d9a | 615 | unsigned mask; |
1da177e4 | 616 | |
61b64abd | 617 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 618 | |
63a7b17e | 619 | entry = msi_setup_entry(dev, nvec); |
f7feaca7 EB |
620 | if (!entry) |
621 | return -ENOMEM; | |
1ce03373 | 622 | |
f2440d9a | 623 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 624 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
625 | msi_mask_irq(entry, mask, mask); |
626 | ||
5004e98a | 627 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 628 | |
1da177e4 | 629 | /* Configure MSI capability structure */ |
8e047ada | 630 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 631 | if (ret) { |
7ba1930d | 632 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 633 | free_msi_irqs(dev); |
7fe3730d | 634 | return ret; |
fd58e55f | 635 | } |
f7feaca7 | 636 | |
f144d149 BH |
637 | ret = msi_verify_entries(dev); |
638 | if (ret) { | |
639 | msi_mask_irq(entry, mask, ~mask); | |
640 | free_msi_irqs(dev); | |
641 | return ret; | |
642 | } | |
643 | ||
da8d1c8b NH |
644 | ret = populate_msi_sysfs(dev); |
645 | if (ret) { | |
646 | msi_mask_irq(entry, mask, ~mask); | |
647 | free_msi_irqs(dev); | |
648 | return ret; | |
649 | } | |
650 | ||
1da177e4 | 651 | /* Set MSI enabled bits */ |
ba698ad4 | 652 | pci_intx_for_msi(dev, 0); |
61b64abd | 653 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 654 | dev->msi_enabled = 1; |
1da177e4 | 655 | |
5f226991 | 656 | pcibios_free_irq(dev); |
7fe3730d | 657 | dev->irq = entry->irq; |
1da177e4 LT |
658 | return 0; |
659 | } | |
660 | ||
520fe9dc | 661 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 662 | { |
4302e0fb | 663 | resource_size_t phys_addr; |
5a05a9d8 | 664 | u32 table_offset; |
6a878e50 | 665 | unsigned long flags; |
5a05a9d8 HS |
666 | u8 bir; |
667 | ||
909094c6 BH |
668 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
669 | &table_offset); | |
4d18760c | 670 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
671 | flags = pci_resource_flags(dev, bir); |
672 | if (!flags || (flags & IORESOURCE_UNSET)) | |
673 | return NULL; | |
674 | ||
4d18760c | 675 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
676 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
677 | ||
678 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
679 | } | |
680 | ||
520fe9dc GS |
681 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
682 | struct msix_entry *entries, int nvec) | |
d9d7070e | 683 | { |
4ef33685 | 684 | const struct cpumask *mask = NULL; |
d9d7070e | 685 | struct msi_desc *entry; |
4ef33685 | 686 | int cpu = -1, i; |
d9d7070e HS |
687 | |
688 | for (i = 0; i < nvec; i++) { | |
4ef33685 CH |
689 | if (dev->irq_affinity) { |
690 | cpu = cpumask_next(cpu, dev->irq_affinity); | |
691 | if (cpu >= nr_cpu_ids) | |
692 | cpu = cpumask_first(dev->irq_affinity); | |
693 | mask = cpumask_of(cpu); | |
694 | } | |
695 | ||
aa48b6f7 | 696 | entry = alloc_msi_entry(&dev->dev); |
d9d7070e HS |
697 | if (!entry) { |
698 | if (!i) | |
699 | iounmap(base); | |
700 | else | |
701 | free_msi_irqs(dev); | |
702 | /* No enough memory. Don't try again */ | |
703 | return -ENOMEM; | |
704 | } | |
705 | ||
706 | entry->msi_attrib.is_msix = 1; | |
707 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
708 | if (entries) |
709 | entry->msi_attrib.entry_nr = entries[i].entry; | |
710 | else | |
711 | entry->msi_attrib.entry_nr = i; | |
d9d7070e | 712 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e | 713 | entry->mask_base = base; |
63a7b17e | 714 | entry->nvec_used = 1; |
4ef33685 | 715 | entry->affinity = mask; |
d9d7070e | 716 | |
5004e98a | 717 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
d9d7070e HS |
718 | } |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
75cb3426 | 723 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 724 | struct msix_entry *entries) |
75cb3426 HS |
725 | { |
726 | struct msi_desc *entry; | |
727 | int i = 0; | |
728 | ||
5004e98a | 729 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
730 | if (entries) |
731 | entries[i++].vector = entry->irq; | |
12eb21de CH |
732 | entry->masked = readl(pci_msix_desc_addr(entry) + |
733 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
75cb3426 | 734 | msix_mask_irq(entry, 1); |
75cb3426 HS |
735 | } |
736 | } | |
737 | ||
1da177e4 LT |
738 | /** |
739 | * msix_capability_init - configure device's MSI-X capability | |
740 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
741 | * @entries: pointer to an array of struct msix_entry entries |
742 | * @nvec: number of @entries | |
1da177e4 | 743 | * |
eaae4b3a | 744 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
745 | * single MSI-X irq. A return of zero indicates the successful setup of |
746 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
747 | **/ |
748 | static int msix_capability_init(struct pci_dev *dev, | |
749 | struct msix_entry *entries, int nvec) | |
750 | { | |
520fe9dc | 751 | int ret; |
5a05a9d8 | 752 | u16 control; |
1da177e4 LT |
753 | void __iomem *base; |
754 | ||
f598282f | 755 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 756 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 757 | |
66f0d0c4 | 758 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 759 | /* Request & Map MSI-X table region */ |
527eee29 | 760 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 761 | if (!base) |
1da177e4 LT |
762 | return -ENOMEM; |
763 | ||
520fe9dc | 764 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
765 | if (ret) |
766 | return ret; | |
9c831334 | 767 | |
8e047ada | 768 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 769 | if (ret) |
2adc7907 | 770 | goto out_avail; |
9c831334 | 771 | |
f144d149 BH |
772 | /* Check if all MSI entries honor device restrictions */ |
773 | ret = msi_verify_entries(dev); | |
774 | if (ret) | |
775 | goto out_free; | |
776 | ||
f598282f MW |
777 | /* |
778 | * Some devices require MSI-X to be enabled before we can touch the | |
779 | * MSI-X registers. We need to mask all the vectors to prevent | |
780 | * interrupts coming in before they're fully set up. | |
781 | */ | |
61b64abd | 782 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 783 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 784 | |
75cb3426 | 785 | msix_program_entries(dev, entries); |
f598282f | 786 | |
da8d1c8b | 787 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
788 | if (ret) |
789 | goto out_free; | |
da8d1c8b | 790 | |
f598282f | 791 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 792 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 793 | dev->msix_enabled = 1; |
61b64abd | 794 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 795 | |
5f226991 | 796 | pcibios_free_irq(dev); |
1da177e4 | 797 | return 0; |
583871d4 | 798 | |
2adc7907 | 799 | out_avail: |
583871d4 HS |
800 | if (ret < 0) { |
801 | /* | |
802 | * If we had some success, report the number of irqs | |
803 | * we succeeded in setting up. | |
804 | */ | |
d9d7070e | 805 | struct msi_desc *entry; |
583871d4 HS |
806 | int avail = 0; |
807 | ||
5004e98a | 808 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
809 | if (entry->irq != 0) |
810 | avail++; | |
811 | } | |
812 | if (avail != 0) | |
813 | ret = avail; | |
814 | } | |
815 | ||
2adc7907 | 816 | out_free: |
583871d4 HS |
817 | free_msi_irqs(dev); |
818 | ||
819 | return ret; | |
1da177e4 LT |
820 | } |
821 | ||
24334a12 | 822 | /** |
a06cd74c | 823 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 824 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 825 | * @nvec: how many MSIs have been requested ? |
24334a12 | 826 | * |
f7625980 | 827 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 828 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 829 | * supported return 1, else return 0. |
24334a12 | 830 | **/ |
a06cd74c | 831 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
832 | { |
833 | struct pci_bus *bus; | |
834 | ||
0306ebfa | 835 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 836 | if (!pci_msi_enable) |
a06cd74c | 837 | return 0; |
27e20603 AG |
838 | |
839 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 840 | return 0; |
24334a12 | 841 | |
314e77b3 ME |
842 | /* |
843 | * You can't ask to have 0 or less MSIs configured. | |
844 | * a) it's stupid .. | |
845 | * b) the list manipulation code assumes nvec >= 1. | |
846 | */ | |
847 | if (nvec < 1) | |
a06cd74c | 848 | return 0; |
314e77b3 | 849 | |
500559a9 HS |
850 | /* |
851 | * Any bridge which does NOT route MSI transactions from its | |
852 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
853 | * the secondary pci_bus. |
854 | * We expect only arch-specific PCI host bus controller driver | |
855 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
856 | */ | |
24334a12 BG |
857 | for (bus = dev->bus; bus; bus = bus->parent) |
858 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 859 | return 0; |
24334a12 | 860 | |
a06cd74c | 861 | return 1; |
24334a12 BG |
862 | } |
863 | ||
d1ac1d26 AG |
864 | /** |
865 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
866 | * @dev: device to report about | |
867 | * | |
868 | * This function returns the number of MSI vectors a device requested via | |
869 | * Multiple Message Capable register. It returns a negative errno if the | |
870 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
871 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
872 | * MSI specification. | |
873 | **/ | |
874 | int pci_msi_vec_count(struct pci_dev *dev) | |
875 | { | |
876 | int ret; | |
877 | u16 msgctl; | |
878 | ||
879 | if (!dev->msi_cap) | |
880 | return -EINVAL; | |
881 | ||
882 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
883 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
884 | ||
885 | return ret; | |
886 | } | |
887 | EXPORT_SYMBOL(pci_msi_vec_count); | |
888 | ||
f2440d9a | 889 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 890 | { |
f2440d9a MW |
891 | struct msi_desc *desc; |
892 | u32 mask; | |
1da177e4 | 893 | |
128bc5fc | 894 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
895 | return; |
896 | ||
5004e98a | 897 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 898 | desc = first_pci_msi_entry(dev); |
110828c9 | 899 | |
61b64abd | 900 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 901 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 902 | dev->msi_enabled = 0; |
7bd007e4 | 903 | |
12abb8ba | 904 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 905 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 906 | /* Keep cached state to be restored */ |
23ed8d57 | 907 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
908 | |
909 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 910 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 911 | pcibios_alloc_irq(dev); |
d52877c7 | 912 | } |
24d27553 | 913 | |
500559a9 | 914 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 915 | { |
d52877c7 YL |
916 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
917 | return; | |
918 | ||
919 | pci_msi_shutdown(dev); | |
f56e4481 | 920 | free_msi_irqs(dev); |
1da177e4 | 921 | } |
4cc086fa | 922 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 923 | |
a52e2e35 | 924 | /** |
ff1aa430 | 925 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 926 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
927 | * This function returns the number of device's MSI-X table entries and |
928 | * therefore the number of MSI-X vectors device is capable of sending. | |
929 | * It returns a negative errno if the device is not capable of sending MSI-X | |
930 | * interrupts. | |
931 | **/ | |
932 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 933 | { |
a52e2e35 RW |
934 | u16 control; |
935 | ||
520fe9dc | 936 | if (!dev->msix_cap) |
ff1aa430 | 937 | return -EINVAL; |
a52e2e35 | 938 | |
f84ecd28 | 939 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 940 | return msix_table_size(control); |
a52e2e35 | 941 | } |
ff1aa430 | 942 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 943 | |
1da177e4 LT |
944 | /** |
945 | * pci_enable_msix - configure device's MSI-X capability structure | |
946 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
3ac020e0 | 947 | * @entries: pointer to an array of MSI-X entries (optional) |
1ce03373 | 948 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
949 | * |
950 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 951 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
952 | * MSI-X mode enabled on its hardware device function. A return of zero |
953 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 954 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 955 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
956 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
957 | * re-send its request. | |
1da177e4 | 958 | **/ |
500559a9 | 959 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 960 | { |
5ec09405 | 961 | int nr_entries; |
ded86d8d | 962 | int i, j; |
1da177e4 | 963 | |
a06cd74c AG |
964 | if (!pci_msi_supported(dev, nvec)) |
965 | return -EINVAL; | |
c9953a73 | 966 | |
ff1aa430 AG |
967 | nr_entries = pci_msix_vec_count(dev); |
968 | if (nr_entries < 0) | |
969 | return nr_entries; | |
1da177e4 | 970 | if (nvec > nr_entries) |
57fbf52c | 971 | return nr_entries; |
1da177e4 | 972 | |
3ac020e0 CH |
973 | if (entries) { |
974 | /* Check for any invalid entries */ | |
975 | for (i = 0; i < nvec; i++) { | |
976 | if (entries[i].entry >= nr_entries) | |
977 | return -EINVAL; /* invalid entry */ | |
978 | for (j = i + 1; j < nvec; j++) { | |
979 | if (entries[i].entry == entries[j].entry) | |
980 | return -EINVAL; /* duplicate entry */ | |
981 | } | |
1da177e4 LT |
982 | } |
983 | } | |
ded86d8d | 984 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 985 | |
1ce03373 | 986 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 987 | if (dev->msi_enabled) { |
227f0647 | 988 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
989 | return -EINVAL; |
990 | } | |
5ec09405 | 991 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 992 | } |
4cc086fa | 993 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 994 | |
500559a9 | 995 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 996 | { |
12abb8ba HS |
997 | struct msi_desc *entry; |
998 | ||
128bc5fc | 999 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1000 | return; |
1001 | ||
12abb8ba | 1002 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 1003 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 1004 | /* Keep cached states to be restored */ |
23ed8d57 | 1005 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
1006 | } |
1007 | ||
61b64abd | 1008 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1009 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1010 | dev->msix_enabled = 0; |
5f226991 | 1011 | pcibios_alloc_irq(dev); |
d52877c7 | 1012 | } |
c901851f | 1013 | |
500559a9 | 1014 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1015 | { |
1016 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1017 | return; | |
1018 | ||
1019 | pci_msix_shutdown(dev); | |
f56e4481 | 1020 | free_msi_irqs(dev); |
1da177e4 | 1021 | } |
4cc086fa | 1022 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1023 | |
309e57df MW |
1024 | void pci_no_msi(void) |
1025 | { | |
1026 | pci_msi_enable = 0; | |
1027 | } | |
c9953a73 | 1028 | |
07ae95f9 AP |
1029 | /** |
1030 | * pci_msi_enabled - is MSI enabled? | |
1031 | * | |
1032 | * Returns true if MSI has not been disabled by the command-line option | |
1033 | * pci=nomsi. | |
1034 | **/ | |
1035 | int pci_msi_enabled(void) | |
d389fec6 | 1036 | { |
07ae95f9 | 1037 | return pci_msi_enable; |
d389fec6 | 1038 | } |
07ae95f9 | 1039 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1040 | |
4ef33685 CH |
1041 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
1042 | unsigned int flags) | |
302a2523 | 1043 | { |
034cd97e | 1044 | int nvec; |
302a2523 AG |
1045 | int rc; |
1046 | ||
a06cd74c AG |
1047 | if (!pci_msi_supported(dev, minvec)) |
1048 | return -EINVAL; | |
034cd97e AG |
1049 | |
1050 | WARN_ON(!!dev->msi_enabled); | |
1051 | ||
1052 | /* Check whether driver already requested MSI-X irqs */ | |
1053 | if (dev->msix_enabled) { | |
1054 | dev_info(&dev->dev, | |
1055 | "can't enable MSI (MSI-X already enabled)\n"); | |
1056 | return -EINVAL; | |
1057 | } | |
1058 | ||
302a2523 AG |
1059 | if (maxvec < minvec) |
1060 | return -ERANGE; | |
1061 | ||
034cd97e AG |
1062 | nvec = pci_msi_vec_count(dev); |
1063 | if (nvec < 0) | |
1064 | return nvec; | |
4ef33685 | 1065 | if (nvec < minvec) |
034cd97e | 1066 | return -EINVAL; |
4ef33685 CH |
1067 | |
1068 | if (nvec > maxvec) | |
034cd97e AG |
1069 | nvec = maxvec; |
1070 | ||
4ef33685 CH |
1071 | for (;;) { |
1072 | if (!(flags & PCI_IRQ_NOAFFINITY)) { | |
1073 | dev->irq_affinity = irq_create_affinity_mask(&nvec); | |
1074 | if (nvec < minvec) | |
1075 | return -ENOSPC; | |
1076 | } | |
1077 | ||
034cd97e | 1078 | rc = msi_capability_init(dev, nvec); |
4ef33685 CH |
1079 | if (rc == 0) |
1080 | return nvec; | |
1081 | ||
1082 | kfree(dev->irq_affinity); | |
1083 | dev->irq_affinity = NULL; | |
1084 | ||
1085 | if (rc < 0) | |
302a2523 | 1086 | return rc; |
4ef33685 CH |
1087 | if (rc < minvec) |
1088 | return -ENOSPC; | |
1089 | ||
1090 | nvec = rc; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /** | |
1095 | * pci_enable_msi_range - configure device's MSI capability structure | |
1096 | * @dev: device to configure | |
1097 | * @minvec: minimal number of interrupts to configure | |
1098 | * @maxvec: maximum number of interrupts to configure | |
1099 | * | |
1100 | * This function tries to allocate a maximum possible number of interrupts in a | |
1101 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1102 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1103 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1104 | * the other interrupt numbers allocated to this device are consecutive. | |
1105 | **/ | |
1106 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1107 | { | |
1108 | return __pci_enable_msi_range(dev, minvec, maxvec, PCI_IRQ_NOAFFINITY); | |
1109 | } | |
1110 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1111 | ||
1112 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
1113 | struct msix_entry *entries, int minvec, int maxvec, | |
1114 | unsigned int flags) | |
1115 | { | |
1116 | int nvec = maxvec; | |
1117 | int rc; | |
1118 | ||
1119 | if (maxvec < minvec) | |
1120 | return -ERANGE; | |
1121 | ||
1122 | for (;;) { | |
1123 | if (!(flags & PCI_IRQ_NOAFFINITY)) { | |
1124 | dev->irq_affinity = irq_create_affinity_mask(&nvec); | |
1125 | if (nvec < minvec) | |
302a2523 | 1126 | return -ENOSPC; |
302a2523 | 1127 | } |
302a2523 | 1128 | |
4ef33685 CH |
1129 | rc = pci_enable_msix(dev, entries, nvec); |
1130 | if (rc == 0) | |
1131 | return nvec; | |
1132 | ||
1133 | kfree(dev->irq_affinity); | |
1134 | dev->irq_affinity = NULL; | |
1135 | ||
1136 | if (rc < 0) | |
1137 | return rc; | |
1138 | if (rc < minvec) | |
1139 | return -ENOSPC; | |
1140 | ||
1141 | nvec = rc; | |
1142 | } | |
302a2523 | 1143 | } |
302a2523 AG |
1144 | |
1145 | /** | |
1146 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1147 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1148 | * @entries: pointer to an array of MSI-X entries | |
1149 | * @minvec: minimum number of MSI-X irqs requested | |
1150 | * @maxvec: maximum number of MSI-X irqs requested | |
1151 | * | |
1152 | * Setup the MSI-X capability structure of device function with a maximum | |
1153 | * possible number of interrupts in the range between @minvec and @maxvec | |
1154 | * upon its software driver call to request for MSI-X mode enabled on its | |
1155 | * hardware device function. It returns a negative errno if an error occurs. | |
1156 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1157 | * indicates the successful configuration of MSI-X capability structure | |
1158 | * with new allocated MSI-X interrupts. | |
1159 | **/ | |
1160 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1161 | int minvec, int maxvec) |
302a2523 | 1162 | { |
4ef33685 CH |
1163 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, |
1164 | PCI_IRQ_NOAFFINITY); | |
302a2523 AG |
1165 | } |
1166 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1167 | |
aff17164 CH |
1168 | /** |
1169 | * pci_alloc_irq_vectors - allocate multiple IRQs for a device | |
1170 | * @dev: PCI device to operate on | |
1171 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1172 | * @max_vecs: maximum (desired) number of vectors | |
1173 | * @flags: flags or quirks for the allocation | |
1174 | * | |
1175 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1176 | * vectors if available, and fall back to a single legacy vector | |
1177 | * if neither is available. Return the number of vectors allocated, | |
1178 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1179 | * error code on error. If less than @min_vecs interrupt vectors are | |
1180 | * available for @dev the function will fail with -ENOSPC. | |
1181 | * | |
1182 | * To get the Linux IRQ number used for a vector that can be passed to | |
1183 | * request_irq() use the pci_irq_vector() helper. | |
1184 | */ | |
1185 | int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1186 | unsigned int max_vecs, unsigned int flags) | |
1187 | { | |
1188 | int vecs = -ENOSPC; | |
1189 | ||
1190 | if (!(flags & PCI_IRQ_NOMSIX)) { | |
4ef33685 CH |
1191 | vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
1192 | flags); | |
aff17164 CH |
1193 | if (vecs > 0) |
1194 | return vecs; | |
1195 | } | |
1196 | ||
1197 | if (!(flags & PCI_IRQ_NOMSI)) { | |
4ef33685 | 1198 | vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, flags); |
aff17164 CH |
1199 | if (vecs > 0) |
1200 | return vecs; | |
1201 | } | |
1202 | ||
1203 | /* use legacy irq if allowed */ | |
1204 | if (!(flags & PCI_IRQ_NOLEGACY) && min_vecs == 1) | |
1205 | return 1; | |
1206 | return vecs; | |
1207 | } | |
1208 | EXPORT_SYMBOL(pci_alloc_irq_vectors); | |
1209 | ||
1210 | /** | |
1211 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1212 | * @dev: PCI device to operate on | |
1213 | * | |
1214 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1215 | */ | |
1216 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1217 | { | |
1218 | pci_disable_msix(dev); | |
1219 | pci_disable_msi(dev); | |
1220 | } | |
1221 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1222 | ||
1223 | /** | |
1224 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1225 | * @dev: PCI device to operate on | |
1226 | * @nr: device-relative interrupt vector index (0-based). | |
1227 | */ | |
1228 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1229 | { | |
1230 | if (dev->msix_enabled) { | |
1231 | struct msi_desc *entry; | |
1232 | int i = 0; | |
1233 | ||
1234 | for_each_pci_msi_entry(entry, dev) { | |
1235 | if (i == nr) | |
1236 | return entry->irq; | |
1237 | i++; | |
1238 | } | |
1239 | WARN_ON_ONCE(1); | |
1240 | return -EINVAL; | |
1241 | } | |
1242 | ||
1243 | if (dev->msi_enabled) { | |
1244 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1245 | ||
1246 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1247 | return -EINVAL; | |
1248 | } else { | |
1249 | if (WARN_ON_ONCE(nr > 0)) | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | ||
1253 | return dev->irq + nr; | |
1254 | } | |
1255 | EXPORT_SYMBOL(pci_irq_vector); | |
1256 | ||
25a98bd4 JL |
1257 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1258 | { | |
1259 | return to_pci_dev(desc->dev); | |
1260 | } | |
a4289dc2 | 1261 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1262 | |
c179c9b9 JL |
1263 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1264 | { | |
1265 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1266 | ||
1267 | return dev->bus->sysdata; | |
1268 | } | |
1269 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1270 | ||
3878eaef JL |
1271 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1272 | /** | |
1273 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1274 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1275 | * @msg: Pointer to the message | |
1276 | */ | |
1277 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1278 | { | |
507a883e | 1279 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1280 | |
1281 | /* | |
1282 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1283 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1284 | */ | |
1285 | if (desc->irq == irq_data->irq) | |
1286 | __pci_write_msi_msg(desc, msg); | |
1287 | } | |
1288 | ||
1289 | /** | |
1290 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1291 | * @dev: Pointer to the PCI device | |
1292 | * @desc: Pointer to the msi descriptor | |
1293 | * | |
1294 | * The ID number is only used within the irqdomain. | |
1295 | */ | |
1296 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1297 | struct msi_desc *desc) | |
1298 | { | |
1299 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1300 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1301 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1302 | } | |
1303 | ||
1304 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1305 | { | |
1306 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1307 | } | |
1308 | ||
1309 | /** | |
1310 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1311 | * @domain: The interrupt domain to check | |
1312 | * @info: The domain info for verification | |
1313 | * @dev: The device to check | |
1314 | * | |
1315 | * Returns: | |
1316 | * 0 if the functionality is supported | |
1317 | * 1 if Multi MSI is requested, but the domain does not support it | |
1318 | * -ENOTSUPP otherwise | |
1319 | */ | |
1320 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1321 | struct msi_domain_info *info, struct device *dev) | |
1322 | { | |
1323 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1324 | ||
1325 | /* Special handling to support pci_enable_msi_range() */ | |
1326 | if (pci_msi_desc_is_multi_msi(desc) && | |
1327 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1328 | return 1; | |
1329 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1330 | return -ENOTSUPP; | |
1331 | ||
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1336 | struct msi_desc *desc, int error) | |
1337 | { | |
1338 | /* Special handling to support pci_enable_msi_range() */ | |
1339 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1340 | return 1; | |
1341 | ||
1342 | return error; | |
1343 | } | |
1344 | ||
1345 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1346 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1347 | struct msi_desc *desc) | |
1348 | { | |
1349 | arg->desc = desc; | |
1350 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1351 | desc); | |
1352 | } | |
1353 | #else | |
1354 | #define pci_msi_domain_set_desc NULL | |
1355 | #endif | |
1356 | ||
1357 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1358 | .set_desc = pci_msi_domain_set_desc, | |
1359 | .msi_check = pci_msi_domain_check_cap, | |
1360 | .handle_error = pci_msi_domain_handle_error, | |
1361 | }; | |
1362 | ||
1363 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1364 | { | |
1365 | struct msi_domain_ops *ops = info->ops; | |
1366 | ||
1367 | if (ops == NULL) { | |
1368 | info->ops = &pci_msi_domain_ops_default; | |
1369 | } else { | |
1370 | if (ops->set_desc == NULL) | |
1371 | ops->set_desc = pci_msi_domain_set_desc; | |
1372 | if (ops->msi_check == NULL) | |
1373 | ops->msi_check = pci_msi_domain_check_cap; | |
1374 | if (ops->handle_error == NULL) | |
1375 | ops->handle_error = pci_msi_domain_handle_error; | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1380 | { | |
1381 | struct irq_chip *chip = info->chip; | |
1382 | ||
1383 | BUG_ON(!chip); | |
1384 | if (!chip->irq_write_msi_msg) | |
1385 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1386 | if (!chip->irq_mask) |
1387 | chip->irq_mask = pci_msi_mask_irq; | |
1388 | if (!chip->irq_unmask) | |
1389 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1390 | } |
1391 | ||
1392 | /** | |
be5436c8 MZ |
1393 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1394 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1395 | * @info: MSI domain info |
1396 | * @parent: Parent irq domain | |
1397 | * | |
1398 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1399 | * | |
1400 | * Returns: | |
1401 | * A domain pointer or NULL in case of failure. | |
1402 | */ | |
be5436c8 | 1403 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1404 | struct msi_domain_info *info, |
1405 | struct irq_domain *parent) | |
1406 | { | |
0380839d MZ |
1407 | struct irq_domain *domain; |
1408 | ||
3878eaef JL |
1409 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1410 | pci_msi_domain_update_dom_ops(info); | |
1411 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1412 | pci_msi_domain_update_chip_ops(info); | |
1413 | ||
be5436c8 | 1414 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1415 | if (!domain) |
1416 | return NULL; | |
1417 | ||
1418 | domain->bus_token = DOMAIN_BUS_PCI_MSI; | |
1419 | return domain; | |
3878eaef | 1420 | } |
a4289dc2 | 1421 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef JL |
1422 | |
1423 | /** | |
1424 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1425 | * @domain: The interrupt domain to allocate from | |
1426 | * @dev: The device for which to allocate | |
1427 | * @nvec: The number of interrupts to allocate | |
1428 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1429 | * | |
1430 | * Returns: | |
1431 | * A virtual interrupt number or an error code in case of failure | |
1432 | */ | |
1433 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1434 | int nvec, int type) | |
1435 | { | |
1436 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1441 | * @domain: The interrupt domain | |
1442 | * @dev: The device for which to free interrupts | |
1443 | */ | |
1444 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1445 | { | |
1446 | msi_domain_free_irqs(domain, &dev->dev); | |
1447 | } | |
8e047ada JL |
1448 | |
1449 | /** | |
1450 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain | |
be5436c8 | 1451 | * @fwnode: Optional fwnode of the interrupt controller |
8e047ada JL |
1452 | * @info: MSI domain info |
1453 | * @parent: Parent irq domain | |
1454 | * | |
1455 | * Returns: A domain pointer or NULL in case of failure. If successful | |
1456 | * the default PCI/MSI irqdomain pointer is updated. | |
1457 | */ | |
be5436c8 | 1458 | struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode, |
8e047ada JL |
1459 | struct msi_domain_info *info, struct irq_domain *parent) |
1460 | { | |
1461 | struct irq_domain *domain; | |
1462 | ||
1463 | mutex_lock(&pci_msi_domain_lock); | |
1464 | if (pci_msi_default_domain) { | |
1465 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); | |
1466 | domain = NULL; | |
1467 | } else { | |
be5436c8 | 1468 | domain = pci_msi_create_irq_domain(fwnode, info, parent); |
8e047ada JL |
1469 | pci_msi_default_domain = domain; |
1470 | } | |
1471 | mutex_unlock(&pci_msi_domain_lock); | |
1472 | ||
1473 | return domain; | |
1474 | } | |
b6eec9b7 DD |
1475 | |
1476 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) | |
1477 | { | |
1478 | u32 *pa = data; | |
1479 | ||
1480 | *pa = alias; | |
1481 | return 0; | |
1482 | } | |
1483 | /** | |
1484 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1485 | * @domain: The interrupt domain | |
1486 | * @pdev: The PCI device. | |
1487 | * | |
1488 | * The RID for a device is formed from the alias, with a firmware | |
1489 | * supplied mapping applied | |
1490 | * | |
1491 | * Returns: The RID. | |
1492 | */ | |
1493 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1494 | { | |
1495 | struct device_node *of_node; | |
1496 | u32 rid = 0; | |
1497 | ||
1498 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1499 | ||
1500 | of_node = irq_domain_get_of_node(domain); | |
1501 | if (of_node) | |
1502 | rid = of_msi_map_rid(&pdev->dev, of_node, rid); | |
1503 | ||
1504 | return rid; | |
1505 | } | |
54fa97ee MZ |
1506 | |
1507 | /** | |
1508 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1509 | * @pdev: The PCI device | |
1510 | * | |
1511 | * Use the firmware data to find a device-specific MSI domain | |
1512 | * (i.e. not one that is ste as a default). | |
1513 | * | |
1514 | * Returns: The coresponding MSI domain or NULL if none has been found. | |
1515 | */ | |
1516 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1517 | { | |
1518 | u32 rid = 0; | |
1519 | ||
1520 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1521 | return of_msi_map_get_device_domain(&pdev->dev, rid); | |
1522 | } | |
3878eaef | 1523 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |