Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
3878eaef | 22 | #include <linux/irqdomain.h> |
b6eec9b7 | 23 | #include <linux/of_irq.h> |
1da177e4 LT |
24 | |
25 | #include "pci.h" | |
1da177e4 | 26 | |
1da177e4 | 27 | static int pci_msi_enable = 1; |
38737d82 | 28 | int pci_msi_ignore_mask; |
1da177e4 | 29 | |
527eee29 BH |
30 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
31 | ||
8e047ada JL |
32 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
33 | static struct irq_domain *pci_msi_default_domain; | |
34 | static DEFINE_MUTEX(pci_msi_domain_lock); | |
35 | ||
36 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) | |
37 | { | |
38 | return pci_msi_default_domain; | |
39 | } | |
40 | ||
020c3126 MZ |
41 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
42 | { | |
d8a1cb75 | 43 | struct irq_domain *domain; |
020c3126 | 44 | |
d8a1cb75 MZ |
45 | domain = dev_get_msi_domain(&dev->dev); |
46 | if (domain) | |
47 | return domain; | |
020c3126 | 48 | |
d8a1cb75 | 49 | return arch_get_pci_msi_domain(dev); |
020c3126 MZ |
50 | } |
51 | ||
8e047ada JL |
52 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
53 | { | |
54 | struct irq_domain *domain; | |
55 | ||
020c3126 | 56 | domain = pci_msi_get_domain(dev); |
3845d295 | 57 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
58 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); |
59 | ||
60 | return arch_setup_msi_irqs(dev, nvec, type); | |
61 | } | |
62 | ||
63 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct irq_domain *domain; | |
66 | ||
020c3126 | 67 | domain = pci_msi_get_domain(dev); |
3845d295 | 68 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
69 | pci_msi_domain_free_irqs(domain, dev); |
70 | else | |
71 | arch_teardown_msi_irqs(dev); | |
72 | } | |
73 | #else | |
74 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
75 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
76 | #endif | |
527eee29 | 77 | |
6a9e7f20 AB |
78 | /* Arch hooks */ |
79 | ||
4287d824 TP |
80 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
81 | { | |
2291ec09 | 82 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
83 | int err; |
84 | ||
85 | if (!chip || !chip->setup_irq) | |
86 | return -EINVAL; | |
87 | ||
88 | err = chip->setup_irq(chip, dev, desc); | |
89 | if (err < 0) | |
90 | return err; | |
91 | ||
92 | irq_set_chip_data(desc->irq, chip); | |
93 | ||
94 | return 0; | |
4287d824 TP |
95 | } |
96 | ||
97 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 98 | { |
c2791b80 | 99 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
100 | |
101 | if (!chip || !chip->teardown_irq) | |
102 | return; | |
103 | ||
104 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
105 | } |
106 | ||
4287d824 | 107 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 108 | { |
339e5b44 | 109 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
110 | struct msi_desc *entry; |
111 | int ret; | |
112 | ||
339e5b44 LS |
113 | if (chip && chip->setup_irqs) |
114 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
115 | /* |
116 | * If an architecture wants to support multiple MSI, it needs to | |
117 | * override arch_setup_msi_irqs() | |
118 | */ | |
119 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
120 | return 1; | |
121 | ||
5004e98a | 122 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 123 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 124 | if (ret < 0) |
6a9e7f20 | 125 | return ret; |
b5fbf533 ME |
126 | if (ret > 0) |
127 | return -ENOSPC; | |
6a9e7f20 AB |
128 | } |
129 | ||
130 | return 0; | |
131 | } | |
1525bf0d | 132 | |
4287d824 TP |
133 | /* |
134 | * We have a default implementation available as a separate non-weak | |
135 | * function, as it is used by the Xen x86 PCI code | |
136 | */ | |
1525bf0d | 137 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 138 | { |
63a7b17e | 139 | int i; |
6a9e7f20 AB |
140 | struct msi_desc *entry; |
141 | ||
5004e98a | 142 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
143 | if (entry->irq) |
144 | for (i = 0; i < entry->nvec_used; i++) | |
145 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
146 | } |
147 | ||
4287d824 TP |
148 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
149 | { | |
150 | return default_teardown_msi_irqs(dev); | |
151 | } | |
76ccc297 | 152 | |
ac8344c4 | 153 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
154 | { |
155 | struct msi_desc *entry; | |
156 | ||
157 | entry = NULL; | |
158 | if (dev->msix_enabled) { | |
5004e98a | 159 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
160 | if (irq == entry->irq) |
161 | break; | |
162 | } | |
163 | } else if (dev->msi_enabled) { | |
164 | entry = irq_get_msi_desc(irq); | |
165 | } | |
166 | ||
167 | if (entry) | |
83a18912 | 168 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 169 | } |
4287d824 | 170 | |
ac8344c4 | 171 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 172 | { |
ac8344c4 | 173 | return default_restore_msi_irqs(dev); |
4287d824 | 174 | } |
76ccc297 | 175 | |
bffac3c5 MW |
176 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
177 | { | |
0b49ec37 MW |
178 | /* Don't shift by >= width of type */ |
179 | if (x >= 5) | |
180 | return 0xffffffff; | |
181 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
182 | } |
183 | ||
ce6fce42 MW |
184 | /* |
185 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
186 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
187 | * reliably as devices without an INTx disable bit will then generate a | |
188 | * level IRQ which will never be cleared. | |
ce6fce42 | 189 | */ |
23ed8d57 | 190 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 191 | { |
f2440d9a | 192 | u32 mask_bits = desc->masked; |
1da177e4 | 193 | |
38737d82 | 194 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 195 | return 0; |
f2440d9a MW |
196 | |
197 | mask_bits &= ~mask; | |
198 | mask_bits |= flag; | |
e39758e0 JL |
199 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
200 | mask_bits); | |
12abb8ba HS |
201 | |
202 | return mask_bits; | |
203 | } | |
204 | ||
205 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
206 | { | |
23ed8d57 | 207 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
208 | } |
209 | ||
210 | /* | |
211 | * This internal function does not flush PCI writes to the device. | |
212 | * All users must ensure that they read from the device before either | |
213 | * assuming that the device state is up to date, or returning out of this | |
214 | * file. This saves a few milliseconds when initialising devices with lots | |
215 | * of MSI-X interrupts. | |
216 | */ | |
23ed8d57 | 217 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
218 | { |
219 | u32 mask_bits = desc->masked; | |
220 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 221 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
38737d82 YW |
222 | |
223 | if (pci_msi_ignore_mask) | |
224 | return 0; | |
225 | ||
8d805286 SY |
226 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
227 | if (flag) | |
228 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 229 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
230 | |
231 | return mask_bits; | |
232 | } | |
233 | ||
234 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
235 | { | |
23ed8d57 | 236 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 237 | } |
24d27553 | 238 | |
1c9db525 | 239 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 240 | { |
c391f262 | 241 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 242 | |
f2440d9a MW |
243 | if (desc->msi_attrib.is_msix) { |
244 | msix_mask_irq(desc, flag); | |
245 | readl(desc->mask_base); /* Flush write to device */ | |
246 | } else { | |
a281b788 | 247 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 248 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 249 | } |
f2440d9a MW |
250 | } |
251 | ||
23ed8d57 TG |
252 | /** |
253 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
254 | * @data: pointer to irqdata associated to that interrupt | |
255 | */ | |
256 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 257 | { |
1c9db525 | 258 | msi_set_mask_bit(data, 1); |
f2440d9a | 259 | } |
a4289dc2 | 260 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 261 | |
23ed8d57 TG |
262 | /** |
263 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
264 | * @data: pointer to irqdata associated to that interrupt | |
265 | */ | |
266 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 267 | { |
1c9db525 | 268 | msi_set_mask_bit(data, 0); |
1da177e4 | 269 | } |
a4289dc2 | 270 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 271 | |
ac8344c4 D |
272 | void default_restore_msi_irqs(struct pci_dev *dev) |
273 | { | |
274 | struct msi_desc *entry; | |
275 | ||
5004e98a | 276 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 277 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
278 | } |
279 | ||
891d4a48 | 280 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 281 | { |
e39758e0 JL |
282 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
283 | ||
284 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
285 | |
286 | if (entry->msi_attrib.is_msix) { | |
287 | void __iomem *base = entry->mask_base + | |
288 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
289 | ||
290 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
291 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
292 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
293 | } else { | |
f5322169 | 294 | int pos = dev->msi_cap; |
30da5524 BH |
295 | u16 data; |
296 | ||
9925ad0c BH |
297 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
298 | &msg->address_lo); | |
30da5524 | 299 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
300 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
301 | &msg->address_hi); | |
2f221349 | 302 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
303 | } else { |
304 | msg->address_hi = 0; | |
2f221349 | 305 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
306 | } |
307 | msg->data = data; | |
308 | } | |
309 | } | |
310 | ||
83a18912 | 311 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 312 | { |
e39758e0 JL |
313 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
314 | ||
315 | if (dev->current_state != PCI_D0) { | |
fcd097f3 BH |
316 | /* Don't touch the hardware now */ |
317 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
318 | void __iomem *base; |
319 | base = entry->mask_base + | |
320 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
321 | ||
2c21fd4b HS |
322 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
323 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
324 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 325 | } else { |
f5322169 | 326 | int pos = dev->msi_cap; |
1c8d7b0a MW |
327 | u16 msgctl; |
328 | ||
f84ecd28 | 329 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
330 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
331 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 332 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 333 | |
9925ad0c BH |
334 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
335 | msg->address_lo); | |
0366f8f7 | 336 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
337 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
338 | msg->address_hi); | |
2f221349 BH |
339 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
340 | msg->data); | |
0366f8f7 | 341 | } else { |
2f221349 BH |
342 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
343 | msg->data); | |
0366f8f7 | 344 | } |
1da177e4 | 345 | } |
392ee1e6 | 346 | entry->msg = *msg; |
1da177e4 | 347 | } |
0366f8f7 | 348 | |
83a18912 | 349 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 350 | { |
dced35ae | 351 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 352 | |
83a18912 | 353 | __pci_write_msi_msg(entry, msg); |
3145e941 | 354 | } |
83a18912 | 355 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 356 | |
f56e4481 HS |
357 | static void free_msi_irqs(struct pci_dev *dev) |
358 | { | |
5004e98a | 359 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 360 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
361 | struct attribute **msi_attrs; |
362 | struct device_attribute *dev_attr; | |
63a7b17e | 363 | int i, count = 0; |
f56e4481 | 364 | |
5004e98a | 365 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
366 | if (entry->irq) |
367 | for (i = 0; i < entry->nvec_used; i++) | |
368 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 369 | |
8e047ada | 370 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 371 | |
5004e98a | 372 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 373 | if (entry->msi_attrib.is_msix) { |
5004e98a | 374 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
375 | iounmap(entry->mask_base); |
376 | } | |
424eb391 | 377 | |
f56e4481 HS |
378 | list_del(&entry->list); |
379 | kfree(entry); | |
380 | } | |
1c51b50c GKH |
381 | |
382 | if (dev->msi_irq_groups) { | |
383 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
384 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 385 | while (msi_attrs[count]) { |
1c51b50c GKH |
386 | dev_attr = container_of(msi_attrs[count], |
387 | struct device_attribute, attr); | |
388 | kfree(dev_attr->attr.name); | |
389 | kfree(dev_attr); | |
390 | ++count; | |
391 | } | |
392 | kfree(msi_attrs); | |
393 | kfree(dev->msi_irq_groups[0]); | |
394 | kfree(dev->msi_irq_groups); | |
395 | dev->msi_irq_groups = NULL; | |
396 | } | |
f56e4481 | 397 | } |
c54c1879 | 398 | |
ba698ad4 DM |
399 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
400 | { | |
401 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
402 | pci_intx(dev, enable); | |
403 | } | |
404 | ||
8fed4b65 | 405 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 406 | { |
41017f0c | 407 | u16 control; |
392ee1e6 | 408 | struct msi_desc *entry; |
41017f0c | 409 | |
b1cbf4e4 EB |
410 | if (!dev->msi_enabled) |
411 | return; | |
412 | ||
dced35ae | 413 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 414 | |
ba698ad4 | 415 | pci_intx_for_msi(dev, 0); |
61b64abd | 416 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 417 | arch_restore_msi_irqs(dev); |
392ee1e6 | 418 | |
f5322169 | 419 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
420 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
421 | entry->masked); | |
abad2ec9 | 422 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 423 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 424 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
425 | } |
426 | ||
427 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 428 | { |
41017f0c | 429 | struct msi_desc *entry; |
41017f0c | 430 | |
ded86d8d EB |
431 | if (!dev->msix_enabled) |
432 | return; | |
5004e98a | 433 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 434 | |
41017f0c | 435 | /* route the table */ |
ba698ad4 | 436 | pci_intx_for_msi(dev, 0); |
61b64abd | 437 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 438 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 439 | |
ac8344c4 | 440 | arch_restore_msi_irqs(dev); |
5004e98a | 441 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 442 | msix_mask_irq(entry, entry->masked); |
41017f0c | 443 | |
61b64abd | 444 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 445 | } |
8fed4b65 ME |
446 | |
447 | void pci_restore_msi_state(struct pci_dev *dev) | |
448 | { | |
449 | __pci_restore_msi_state(dev); | |
450 | __pci_restore_msix_state(dev); | |
451 | } | |
94688cf2 | 452 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 453 | |
1c51b50c | 454 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
455 | char *buf) |
456 | { | |
1c51b50c GKH |
457 | struct msi_desc *entry; |
458 | unsigned long irq; | |
459 | int retval; | |
da8d1c8b | 460 | |
1c51b50c GKH |
461 | retval = kstrtoul(attr->attr.name, 10, &irq); |
462 | if (retval) | |
463 | return retval; | |
da8d1c8b | 464 | |
e11ece5a YW |
465 | entry = irq_get_msi_desc(irq); |
466 | if (entry) | |
467 | return sprintf(buf, "%s\n", | |
468 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
469 | ||
1c51b50c | 470 | return -ENODEV; |
da8d1c8b NH |
471 | } |
472 | ||
da8d1c8b NH |
473 | static int populate_msi_sysfs(struct pci_dev *pdev) |
474 | { | |
1c51b50c GKH |
475 | struct attribute **msi_attrs; |
476 | struct attribute *msi_attr; | |
477 | struct device_attribute *msi_dev_attr; | |
478 | struct attribute_group *msi_irq_group; | |
479 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 480 | struct msi_desc *entry; |
1c51b50c GKH |
481 | int ret = -ENOMEM; |
482 | int num_msi = 0; | |
da8d1c8b | 483 | int count = 0; |
a8676066 | 484 | int i; |
da8d1c8b | 485 | |
1c51b50c | 486 | /* Determine how many msi entries we have */ |
5004e98a | 487 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 488 | num_msi += entry->nvec_used; |
1c51b50c GKH |
489 | if (!num_msi) |
490 | return 0; | |
da8d1c8b | 491 | |
1c51b50c GKH |
492 | /* Dynamically create the MSI attributes for the PCI device */ |
493 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
494 | if (!msi_attrs) | |
495 | return -ENOMEM; | |
5004e98a | 496 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
497 | for (i = 0; i < entry->nvec_used; i++) { |
498 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
499 | if (!msi_dev_attr) | |
500 | goto error_attrs; | |
501 | msi_attrs[count] = &msi_dev_attr->attr; | |
502 | ||
503 | sysfs_attr_init(&msi_dev_attr->attr); | |
504 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
505 | entry->irq + i); | |
506 | if (!msi_dev_attr->attr.name) | |
507 | goto error_attrs; | |
508 | msi_dev_attr->attr.mode = S_IRUGO; | |
509 | msi_dev_attr->show = msi_mode_show; | |
510 | ++count; | |
511 | } | |
da8d1c8b NH |
512 | } |
513 | ||
1c51b50c GKH |
514 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
515 | if (!msi_irq_group) | |
516 | goto error_attrs; | |
517 | msi_irq_group->name = "msi_irqs"; | |
518 | msi_irq_group->attrs = msi_attrs; | |
519 | ||
520 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
521 | if (!msi_irq_groups) | |
522 | goto error_irq_group; | |
523 | msi_irq_groups[0] = msi_irq_group; | |
524 | ||
525 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
526 | if (ret) | |
527 | goto error_irq_groups; | |
528 | pdev->msi_irq_groups = msi_irq_groups; | |
529 | ||
da8d1c8b NH |
530 | return 0; |
531 | ||
1c51b50c GKH |
532 | error_irq_groups: |
533 | kfree(msi_irq_groups); | |
534 | error_irq_group: | |
535 | kfree(msi_irq_group); | |
536 | error_attrs: | |
537 | count = 0; | |
538 | msi_attr = msi_attrs[count]; | |
539 | while (msi_attr) { | |
540 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
541 | kfree(msi_attr->name); | |
542 | kfree(msi_dev_attr); | |
543 | ++count; | |
544 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 545 | } |
29237756 | 546 | kfree(msi_attrs); |
da8d1c8b NH |
547 | return ret; |
548 | } | |
549 | ||
63a7b17e | 550 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
d873b4d4 YW |
551 | { |
552 | u16 control; | |
553 | struct msi_desc *entry; | |
554 | ||
555 | /* MSI Entry Initialization */ | |
aa48b6f7 | 556 | entry = alloc_msi_entry(&dev->dev); |
d873b4d4 YW |
557 | if (!entry) |
558 | return NULL; | |
559 | ||
560 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
561 | ||
562 | entry->msi_attrib.is_msix = 0; | |
563 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
564 | entry->msi_attrib.entry_nr = 0; | |
565 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
566 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 567 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e JL |
568 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
569 | entry->nvec_used = nvec; | |
d873b4d4 YW |
570 | |
571 | if (control & PCI_MSI_FLAGS_64BIT) | |
572 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
573 | else | |
574 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
575 | ||
576 | /* Save the initial mask status */ | |
577 | if (entry->msi_attrib.maskbit) | |
578 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
579 | ||
580 | return entry; | |
581 | } | |
582 | ||
f144d149 BH |
583 | static int msi_verify_entries(struct pci_dev *dev) |
584 | { | |
585 | struct msi_desc *entry; | |
586 | ||
5004e98a | 587 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
588 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
589 | continue; | |
590 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
591 | " tried to assign one above 4G\n"); | |
592 | return -EIO; | |
593 | } | |
594 | return 0; | |
595 | } | |
596 | ||
1da177e4 LT |
597 | /** |
598 | * msi_capability_init - configure device's MSI capability structure | |
599 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 600 | * @nvec: number of interrupts to allocate |
1da177e4 | 601 | * |
1c8d7b0a MW |
602 | * Setup the MSI capability structure of the device with the requested |
603 | * number of interrupts. A return value of zero indicates the successful | |
604 | * setup of an entry with the new MSI irq. A negative return value indicates | |
605 | * an error, and a positive return value indicates the number of interrupts | |
606 | * which could have been allocated. | |
607 | */ | |
608 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
609 | { |
610 | struct msi_desc *entry; | |
f465136d | 611 | int ret; |
f2440d9a | 612 | unsigned mask; |
1da177e4 | 613 | |
61b64abd | 614 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 615 | |
63a7b17e | 616 | entry = msi_setup_entry(dev, nvec); |
f7feaca7 EB |
617 | if (!entry) |
618 | return -ENOMEM; | |
1ce03373 | 619 | |
f2440d9a | 620 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 621 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
622 | msi_mask_irq(entry, mask, mask); |
623 | ||
5004e98a | 624 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 625 | |
1da177e4 | 626 | /* Configure MSI capability structure */ |
8e047ada | 627 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 628 | if (ret) { |
7ba1930d | 629 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 630 | free_msi_irqs(dev); |
7fe3730d | 631 | return ret; |
fd58e55f | 632 | } |
f7feaca7 | 633 | |
f144d149 BH |
634 | ret = msi_verify_entries(dev); |
635 | if (ret) { | |
636 | msi_mask_irq(entry, mask, ~mask); | |
637 | free_msi_irqs(dev); | |
638 | return ret; | |
639 | } | |
640 | ||
da8d1c8b NH |
641 | ret = populate_msi_sysfs(dev); |
642 | if (ret) { | |
643 | msi_mask_irq(entry, mask, ~mask); | |
644 | free_msi_irqs(dev); | |
645 | return ret; | |
646 | } | |
647 | ||
1da177e4 | 648 | /* Set MSI enabled bits */ |
ba698ad4 | 649 | pci_intx_for_msi(dev, 0); |
61b64abd | 650 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 651 | dev->msi_enabled = 1; |
1da177e4 | 652 | |
5f226991 | 653 | pcibios_free_irq(dev); |
7fe3730d | 654 | dev->irq = entry->irq; |
1da177e4 LT |
655 | return 0; |
656 | } | |
657 | ||
520fe9dc | 658 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 659 | { |
4302e0fb | 660 | resource_size_t phys_addr; |
5a05a9d8 | 661 | u32 table_offset; |
6a878e50 | 662 | unsigned long flags; |
5a05a9d8 HS |
663 | u8 bir; |
664 | ||
909094c6 BH |
665 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
666 | &table_offset); | |
4d18760c | 667 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
668 | flags = pci_resource_flags(dev, bir); |
669 | if (!flags || (flags & IORESOURCE_UNSET)) | |
670 | return NULL; | |
671 | ||
4d18760c | 672 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
673 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
674 | ||
675 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
676 | } | |
677 | ||
520fe9dc GS |
678 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
679 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
680 | { |
681 | struct msi_desc *entry; | |
682 | int i; | |
683 | ||
684 | for (i = 0; i < nvec; i++) { | |
aa48b6f7 | 685 | entry = alloc_msi_entry(&dev->dev); |
d9d7070e HS |
686 | if (!entry) { |
687 | if (!i) | |
688 | iounmap(base); | |
689 | else | |
690 | free_msi_irqs(dev); | |
691 | /* No enough memory. Don't try again */ | |
692 | return -ENOMEM; | |
693 | } | |
694 | ||
695 | entry->msi_attrib.is_msix = 1; | |
696 | entry->msi_attrib.is_64 = 1; | |
697 | entry->msi_attrib.entry_nr = entries[i].entry; | |
698 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e | 699 | entry->mask_base = base; |
63a7b17e | 700 | entry->nvec_used = 1; |
d9d7070e | 701 | |
5004e98a | 702 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
d9d7070e HS |
703 | } |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
75cb3426 | 708 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 709 | struct msix_entry *entries) |
75cb3426 HS |
710 | { |
711 | struct msi_desc *entry; | |
712 | int i = 0; | |
713 | ||
5004e98a | 714 | for_each_pci_msi_entry(entry, dev) { |
75cb3426 HS |
715 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + |
716 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
717 | ||
718 | entries[i].vector = entry->irq; | |
75cb3426 HS |
719 | entry->masked = readl(entry->mask_base + offset); |
720 | msix_mask_irq(entry, 1); | |
721 | i++; | |
722 | } | |
723 | } | |
724 | ||
1da177e4 LT |
725 | /** |
726 | * msix_capability_init - configure device's MSI-X capability | |
727 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
728 | * @entries: pointer to an array of struct msix_entry entries |
729 | * @nvec: number of @entries | |
1da177e4 | 730 | * |
eaae4b3a | 731 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
732 | * single MSI-X irq. A return of zero indicates the successful setup of |
733 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
734 | **/ |
735 | static int msix_capability_init(struct pci_dev *dev, | |
736 | struct msix_entry *entries, int nvec) | |
737 | { | |
520fe9dc | 738 | int ret; |
5a05a9d8 | 739 | u16 control; |
1da177e4 LT |
740 | void __iomem *base; |
741 | ||
f598282f | 742 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 743 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 744 | |
66f0d0c4 | 745 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 746 | /* Request & Map MSI-X table region */ |
527eee29 | 747 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 748 | if (!base) |
1da177e4 LT |
749 | return -ENOMEM; |
750 | ||
520fe9dc | 751 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
752 | if (ret) |
753 | return ret; | |
9c831334 | 754 | |
8e047ada | 755 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 756 | if (ret) |
2adc7907 | 757 | goto out_avail; |
9c831334 | 758 | |
f144d149 BH |
759 | /* Check if all MSI entries honor device restrictions */ |
760 | ret = msi_verify_entries(dev); | |
761 | if (ret) | |
762 | goto out_free; | |
763 | ||
f598282f MW |
764 | /* |
765 | * Some devices require MSI-X to be enabled before we can touch the | |
766 | * MSI-X registers. We need to mask all the vectors to prevent | |
767 | * interrupts coming in before they're fully set up. | |
768 | */ | |
61b64abd | 769 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 770 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 771 | |
75cb3426 | 772 | msix_program_entries(dev, entries); |
f598282f | 773 | |
da8d1c8b | 774 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
775 | if (ret) |
776 | goto out_free; | |
da8d1c8b | 777 | |
f598282f | 778 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 779 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 780 | dev->msix_enabled = 1; |
61b64abd | 781 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 782 | |
5f226991 | 783 | pcibios_free_irq(dev); |
1da177e4 | 784 | return 0; |
583871d4 | 785 | |
2adc7907 | 786 | out_avail: |
583871d4 HS |
787 | if (ret < 0) { |
788 | /* | |
789 | * If we had some success, report the number of irqs | |
790 | * we succeeded in setting up. | |
791 | */ | |
d9d7070e | 792 | struct msi_desc *entry; |
583871d4 HS |
793 | int avail = 0; |
794 | ||
5004e98a | 795 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
796 | if (entry->irq != 0) |
797 | avail++; | |
798 | } | |
799 | if (avail != 0) | |
800 | ret = avail; | |
801 | } | |
802 | ||
2adc7907 | 803 | out_free: |
583871d4 HS |
804 | free_msi_irqs(dev); |
805 | ||
806 | return ret; | |
1da177e4 LT |
807 | } |
808 | ||
24334a12 | 809 | /** |
a06cd74c | 810 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 811 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 812 | * @nvec: how many MSIs have been requested ? |
24334a12 | 813 | * |
f7625980 | 814 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 815 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 816 | * supported return 1, else return 0. |
24334a12 | 817 | **/ |
a06cd74c | 818 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
819 | { |
820 | struct pci_bus *bus; | |
821 | ||
0306ebfa | 822 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 823 | if (!pci_msi_enable) |
a06cd74c | 824 | return 0; |
27e20603 AG |
825 | |
826 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 827 | return 0; |
24334a12 | 828 | |
314e77b3 ME |
829 | /* |
830 | * You can't ask to have 0 or less MSIs configured. | |
831 | * a) it's stupid .. | |
832 | * b) the list manipulation code assumes nvec >= 1. | |
833 | */ | |
834 | if (nvec < 1) | |
a06cd74c | 835 | return 0; |
314e77b3 | 836 | |
500559a9 HS |
837 | /* |
838 | * Any bridge which does NOT route MSI transactions from its | |
839 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
840 | * the secondary pci_bus. |
841 | * We expect only arch-specific PCI host bus controller driver | |
842 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
843 | */ | |
24334a12 BG |
844 | for (bus = dev->bus; bus; bus = bus->parent) |
845 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 846 | return 0; |
24334a12 | 847 | |
a06cd74c | 848 | return 1; |
24334a12 BG |
849 | } |
850 | ||
d1ac1d26 AG |
851 | /** |
852 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
853 | * @dev: device to report about | |
854 | * | |
855 | * This function returns the number of MSI vectors a device requested via | |
856 | * Multiple Message Capable register. It returns a negative errno if the | |
857 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
858 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
859 | * MSI specification. | |
860 | **/ | |
861 | int pci_msi_vec_count(struct pci_dev *dev) | |
862 | { | |
863 | int ret; | |
864 | u16 msgctl; | |
865 | ||
866 | if (!dev->msi_cap) | |
867 | return -EINVAL; | |
868 | ||
869 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
870 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
871 | ||
872 | return ret; | |
873 | } | |
874 | EXPORT_SYMBOL(pci_msi_vec_count); | |
875 | ||
f2440d9a | 876 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 877 | { |
f2440d9a MW |
878 | struct msi_desc *desc; |
879 | u32 mask; | |
1da177e4 | 880 | |
128bc5fc | 881 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
882 | return; |
883 | ||
5004e98a | 884 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 885 | desc = first_pci_msi_entry(dev); |
110828c9 | 886 | |
61b64abd | 887 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 888 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 889 | dev->msi_enabled = 0; |
7bd007e4 | 890 | |
12abb8ba | 891 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 892 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 893 | /* Keep cached state to be restored */ |
23ed8d57 | 894 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
895 | |
896 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 897 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 898 | pcibios_alloc_irq(dev); |
d52877c7 | 899 | } |
24d27553 | 900 | |
500559a9 | 901 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 902 | { |
d52877c7 YL |
903 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
904 | return; | |
905 | ||
906 | pci_msi_shutdown(dev); | |
f56e4481 | 907 | free_msi_irqs(dev); |
1da177e4 | 908 | } |
4cc086fa | 909 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 910 | |
a52e2e35 | 911 | /** |
ff1aa430 | 912 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 913 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
914 | * This function returns the number of device's MSI-X table entries and |
915 | * therefore the number of MSI-X vectors device is capable of sending. | |
916 | * It returns a negative errno if the device is not capable of sending MSI-X | |
917 | * interrupts. | |
918 | **/ | |
919 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 920 | { |
a52e2e35 RW |
921 | u16 control; |
922 | ||
520fe9dc | 923 | if (!dev->msix_cap) |
ff1aa430 | 924 | return -EINVAL; |
a52e2e35 | 925 | |
f84ecd28 | 926 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 927 | return msix_table_size(control); |
a52e2e35 | 928 | } |
ff1aa430 | 929 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 930 | |
1da177e4 LT |
931 | /** |
932 | * pci_enable_msix - configure device's MSI-X capability structure | |
933 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 934 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 935 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
936 | * |
937 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 938 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
939 | * MSI-X mode enabled on its hardware device function. A return of zero |
940 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 941 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 942 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
943 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
944 | * re-send its request. | |
1da177e4 | 945 | **/ |
500559a9 | 946 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 947 | { |
5ec09405 | 948 | int nr_entries; |
ded86d8d | 949 | int i, j; |
1da177e4 | 950 | |
a06cd74c AG |
951 | if (!pci_msi_supported(dev, nvec)) |
952 | return -EINVAL; | |
c9953a73 | 953 | |
27e20603 AG |
954 | if (!entries) |
955 | return -EINVAL; | |
956 | ||
ff1aa430 AG |
957 | nr_entries = pci_msix_vec_count(dev); |
958 | if (nr_entries < 0) | |
959 | return nr_entries; | |
1da177e4 | 960 | if (nvec > nr_entries) |
57fbf52c | 961 | return nr_entries; |
1da177e4 LT |
962 | |
963 | /* Check for any invalid entries */ | |
964 | for (i = 0; i < nvec; i++) { | |
965 | if (entries[i].entry >= nr_entries) | |
966 | return -EINVAL; /* invalid entry */ | |
967 | for (j = i + 1; j < nvec; j++) { | |
968 | if (entries[i].entry == entries[j].entry) | |
969 | return -EINVAL; /* duplicate entry */ | |
970 | } | |
971 | } | |
ded86d8d | 972 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 973 | |
1ce03373 | 974 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 975 | if (dev->msi_enabled) { |
227f0647 | 976 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
977 | return -EINVAL; |
978 | } | |
5ec09405 | 979 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 980 | } |
4cc086fa | 981 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 982 | |
500559a9 | 983 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 984 | { |
12abb8ba HS |
985 | struct msi_desc *entry; |
986 | ||
128bc5fc | 987 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
988 | return; |
989 | ||
12abb8ba | 990 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 991 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 992 | /* Keep cached states to be restored */ |
23ed8d57 | 993 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
994 | } |
995 | ||
61b64abd | 996 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 997 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 998 | dev->msix_enabled = 0; |
5f226991 | 999 | pcibios_alloc_irq(dev); |
d52877c7 | 1000 | } |
c901851f | 1001 | |
500559a9 | 1002 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1003 | { |
1004 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1005 | return; | |
1006 | ||
1007 | pci_msix_shutdown(dev); | |
f56e4481 | 1008 | free_msi_irqs(dev); |
1da177e4 | 1009 | } |
4cc086fa | 1010 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1011 | |
309e57df MW |
1012 | void pci_no_msi(void) |
1013 | { | |
1014 | pci_msi_enable = 0; | |
1015 | } | |
c9953a73 | 1016 | |
07ae95f9 AP |
1017 | /** |
1018 | * pci_msi_enabled - is MSI enabled? | |
1019 | * | |
1020 | * Returns true if MSI has not been disabled by the command-line option | |
1021 | * pci=nomsi. | |
1022 | **/ | |
1023 | int pci_msi_enabled(void) | |
d389fec6 | 1024 | { |
07ae95f9 | 1025 | return pci_msi_enable; |
d389fec6 | 1026 | } |
07ae95f9 | 1027 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1028 | |
302a2523 AG |
1029 | /** |
1030 | * pci_enable_msi_range - configure device's MSI capability structure | |
1031 | * @dev: device to configure | |
1032 | * @minvec: minimal number of interrupts to configure | |
1033 | * @maxvec: maximum number of interrupts to configure | |
1034 | * | |
1035 | * This function tries to allocate a maximum possible number of interrupts in a | |
1036 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1037 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1038 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1039 | * the other interrupt numbers allocated to this device are consecutive. | |
1040 | **/ | |
1041 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1042 | { | |
034cd97e | 1043 | int nvec; |
302a2523 AG |
1044 | int rc; |
1045 | ||
a06cd74c AG |
1046 | if (!pci_msi_supported(dev, minvec)) |
1047 | return -EINVAL; | |
034cd97e AG |
1048 | |
1049 | WARN_ON(!!dev->msi_enabled); | |
1050 | ||
1051 | /* Check whether driver already requested MSI-X irqs */ | |
1052 | if (dev->msix_enabled) { | |
1053 | dev_info(&dev->dev, | |
1054 | "can't enable MSI (MSI-X already enabled)\n"); | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
302a2523 AG |
1058 | if (maxvec < minvec) |
1059 | return -ERANGE; | |
1060 | ||
034cd97e AG |
1061 | nvec = pci_msi_vec_count(dev); |
1062 | if (nvec < 0) | |
1063 | return nvec; | |
1064 | else if (nvec < minvec) | |
1065 | return -EINVAL; | |
1066 | else if (nvec > maxvec) | |
1067 | nvec = maxvec; | |
1068 | ||
302a2523 | 1069 | do { |
034cd97e | 1070 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1071 | if (rc < 0) { |
1072 | return rc; | |
1073 | } else if (rc > 0) { | |
1074 | if (rc < minvec) | |
1075 | return -ENOSPC; | |
1076 | nvec = rc; | |
1077 | } | |
1078 | } while (rc); | |
1079 | ||
1080 | return nvec; | |
1081 | } | |
1082 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1083 | ||
1084 | /** | |
1085 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1086 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1087 | * @entries: pointer to an array of MSI-X entries | |
1088 | * @minvec: minimum number of MSI-X irqs requested | |
1089 | * @maxvec: maximum number of MSI-X irqs requested | |
1090 | * | |
1091 | * Setup the MSI-X capability structure of device function with a maximum | |
1092 | * possible number of interrupts in the range between @minvec and @maxvec | |
1093 | * upon its software driver call to request for MSI-X mode enabled on its | |
1094 | * hardware device function. It returns a negative errno if an error occurs. | |
1095 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1096 | * indicates the successful configuration of MSI-X capability structure | |
1097 | * with new allocated MSI-X interrupts. | |
1098 | **/ | |
1099 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1100 | int minvec, int maxvec) | |
1101 | { | |
1102 | int nvec = maxvec; | |
1103 | int rc; | |
1104 | ||
1105 | if (maxvec < minvec) | |
1106 | return -ERANGE; | |
1107 | ||
1108 | do { | |
1109 | rc = pci_enable_msix(dev, entries, nvec); | |
1110 | if (rc < 0) { | |
1111 | return rc; | |
1112 | } else if (rc > 0) { | |
1113 | if (rc < minvec) | |
1114 | return -ENOSPC; | |
1115 | nvec = rc; | |
1116 | } | |
1117 | } while (rc); | |
1118 | ||
1119 | return nvec; | |
1120 | } | |
1121 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1122 | |
25a98bd4 JL |
1123 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1124 | { | |
1125 | return to_pci_dev(desc->dev); | |
1126 | } | |
a4289dc2 | 1127 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1128 | |
c179c9b9 JL |
1129 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1130 | { | |
1131 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1132 | ||
1133 | return dev->bus->sysdata; | |
1134 | } | |
1135 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1136 | ||
3878eaef JL |
1137 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1138 | /** | |
1139 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1140 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1141 | * @msg: Pointer to the message | |
1142 | */ | |
1143 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1144 | { | |
507a883e | 1145 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1146 | |
1147 | /* | |
1148 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1149 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1150 | */ | |
1151 | if (desc->irq == irq_data->irq) | |
1152 | __pci_write_msi_msg(desc, msg); | |
1153 | } | |
1154 | ||
1155 | /** | |
1156 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1157 | * @dev: Pointer to the PCI device | |
1158 | * @desc: Pointer to the msi descriptor | |
1159 | * | |
1160 | * The ID number is only used within the irqdomain. | |
1161 | */ | |
1162 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1163 | struct msi_desc *desc) | |
1164 | { | |
1165 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1166 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1167 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1168 | } | |
1169 | ||
1170 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1171 | { | |
1172 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1173 | } | |
1174 | ||
1175 | /** | |
1176 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1177 | * @domain: The interrupt domain to check | |
1178 | * @info: The domain info for verification | |
1179 | * @dev: The device to check | |
1180 | * | |
1181 | * Returns: | |
1182 | * 0 if the functionality is supported | |
1183 | * 1 if Multi MSI is requested, but the domain does not support it | |
1184 | * -ENOTSUPP otherwise | |
1185 | */ | |
1186 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1187 | struct msi_domain_info *info, struct device *dev) | |
1188 | { | |
1189 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1190 | ||
1191 | /* Special handling to support pci_enable_msi_range() */ | |
1192 | if (pci_msi_desc_is_multi_msi(desc) && | |
1193 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1194 | return 1; | |
1195 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1196 | return -ENOTSUPP; | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1202 | struct msi_desc *desc, int error) | |
1203 | { | |
1204 | /* Special handling to support pci_enable_msi_range() */ | |
1205 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1206 | return 1; | |
1207 | ||
1208 | return error; | |
1209 | } | |
1210 | ||
1211 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1212 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1213 | struct msi_desc *desc) | |
1214 | { | |
1215 | arg->desc = desc; | |
1216 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1217 | desc); | |
1218 | } | |
1219 | #else | |
1220 | #define pci_msi_domain_set_desc NULL | |
1221 | #endif | |
1222 | ||
1223 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1224 | .set_desc = pci_msi_domain_set_desc, | |
1225 | .msi_check = pci_msi_domain_check_cap, | |
1226 | .handle_error = pci_msi_domain_handle_error, | |
1227 | }; | |
1228 | ||
1229 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1230 | { | |
1231 | struct msi_domain_ops *ops = info->ops; | |
1232 | ||
1233 | if (ops == NULL) { | |
1234 | info->ops = &pci_msi_domain_ops_default; | |
1235 | } else { | |
1236 | if (ops->set_desc == NULL) | |
1237 | ops->set_desc = pci_msi_domain_set_desc; | |
1238 | if (ops->msi_check == NULL) | |
1239 | ops->msi_check = pci_msi_domain_check_cap; | |
1240 | if (ops->handle_error == NULL) | |
1241 | ops->handle_error = pci_msi_domain_handle_error; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1246 | { | |
1247 | struct irq_chip *chip = info->chip; | |
1248 | ||
1249 | BUG_ON(!chip); | |
1250 | if (!chip->irq_write_msi_msg) | |
1251 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1252 | if (!chip->irq_mask) |
1253 | chip->irq_mask = pci_msi_mask_irq; | |
1254 | if (!chip->irq_unmask) | |
1255 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1256 | } |
1257 | ||
1258 | /** | |
be5436c8 MZ |
1259 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1260 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1261 | * @info: MSI domain info |
1262 | * @parent: Parent irq domain | |
1263 | * | |
1264 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1265 | * | |
1266 | * Returns: | |
1267 | * A domain pointer or NULL in case of failure. | |
1268 | */ | |
be5436c8 | 1269 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1270 | struct msi_domain_info *info, |
1271 | struct irq_domain *parent) | |
1272 | { | |
0380839d MZ |
1273 | struct irq_domain *domain; |
1274 | ||
3878eaef JL |
1275 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1276 | pci_msi_domain_update_dom_ops(info); | |
1277 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1278 | pci_msi_domain_update_chip_ops(info); | |
1279 | ||
be5436c8 | 1280 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1281 | if (!domain) |
1282 | return NULL; | |
1283 | ||
1284 | domain->bus_token = DOMAIN_BUS_PCI_MSI; | |
1285 | return domain; | |
3878eaef | 1286 | } |
a4289dc2 | 1287 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef JL |
1288 | |
1289 | /** | |
1290 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1291 | * @domain: The interrupt domain to allocate from | |
1292 | * @dev: The device for which to allocate | |
1293 | * @nvec: The number of interrupts to allocate | |
1294 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1295 | * | |
1296 | * Returns: | |
1297 | * A virtual interrupt number or an error code in case of failure | |
1298 | */ | |
1299 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1300 | int nvec, int type) | |
1301 | { | |
1302 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1303 | } | |
1304 | ||
1305 | /** | |
1306 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1307 | * @domain: The interrupt domain | |
1308 | * @dev: The device for which to free interrupts | |
1309 | */ | |
1310 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1311 | { | |
1312 | msi_domain_free_irqs(domain, &dev->dev); | |
1313 | } | |
8e047ada JL |
1314 | |
1315 | /** | |
1316 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain | |
be5436c8 | 1317 | * @fwnode: Optional fwnode of the interrupt controller |
8e047ada JL |
1318 | * @info: MSI domain info |
1319 | * @parent: Parent irq domain | |
1320 | * | |
1321 | * Returns: A domain pointer or NULL in case of failure. If successful | |
1322 | * the default PCI/MSI irqdomain pointer is updated. | |
1323 | */ | |
be5436c8 | 1324 | struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode, |
8e047ada JL |
1325 | struct msi_domain_info *info, struct irq_domain *parent) |
1326 | { | |
1327 | struct irq_domain *domain; | |
1328 | ||
1329 | mutex_lock(&pci_msi_domain_lock); | |
1330 | if (pci_msi_default_domain) { | |
1331 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); | |
1332 | domain = NULL; | |
1333 | } else { | |
be5436c8 | 1334 | domain = pci_msi_create_irq_domain(fwnode, info, parent); |
8e047ada JL |
1335 | pci_msi_default_domain = domain; |
1336 | } | |
1337 | mutex_unlock(&pci_msi_domain_lock); | |
1338 | ||
1339 | return domain; | |
1340 | } | |
b6eec9b7 DD |
1341 | |
1342 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) | |
1343 | { | |
1344 | u32 *pa = data; | |
1345 | ||
1346 | *pa = alias; | |
1347 | return 0; | |
1348 | } | |
1349 | /** | |
1350 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1351 | * @domain: The interrupt domain | |
1352 | * @pdev: The PCI device. | |
1353 | * | |
1354 | * The RID for a device is formed from the alias, with a firmware | |
1355 | * supplied mapping applied | |
1356 | * | |
1357 | * Returns: The RID. | |
1358 | */ | |
1359 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1360 | { | |
1361 | struct device_node *of_node; | |
1362 | u32 rid = 0; | |
1363 | ||
1364 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1365 | ||
1366 | of_node = irq_domain_get_of_node(domain); | |
1367 | if (of_node) | |
1368 | rid = of_msi_map_rid(&pdev->dev, of_node, rid); | |
1369 | ||
1370 | return rid; | |
1371 | } | |
54fa97ee MZ |
1372 | |
1373 | /** | |
1374 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1375 | * @pdev: The PCI device | |
1376 | * | |
1377 | * Use the firmware data to find a device-specific MSI domain | |
1378 | * (i.e. not one that is ste as a default). | |
1379 | * | |
1380 | * Returns: The coresponding MSI domain or NULL if none has been found. | |
1381 | */ | |
1382 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1383 | { | |
1384 | u32 rid = 0; | |
1385 | ||
1386 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1387 | return of_msi_map_get_device_domain(&pdev->dev, rid); | |
1388 | } | |
3878eaef | 1389 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |