Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
4287d824 TP |
33 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
34 | { | |
0cbdcfcf TR |
35 | struct msi_chip *chip = dev->bus->msi; |
36 | int err; | |
37 | ||
38 | if (!chip || !chip->setup_irq) | |
39 | return -EINVAL; | |
40 | ||
41 | err = chip->setup_irq(chip, dev, desc); | |
42 | if (err < 0) | |
43 | return err; | |
44 | ||
45 | irq_set_chip_data(desc->irq, chip); | |
46 | ||
47 | return 0; | |
4287d824 TP |
48 | } |
49 | ||
50 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 51 | { |
0cbdcfcf TR |
52 | struct msi_chip *chip = irq_get_chip_data(irq); |
53 | ||
54 | if (!chip || !chip->teardown_irq) | |
55 | return; | |
56 | ||
57 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
58 | } |
59 | ||
4287d824 TP |
60 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
61 | { | |
0cbdcfcf TR |
62 | struct msi_chip *chip = dev->bus->msi; |
63 | ||
64 | if (!chip || !chip->check_device) | |
65 | return 0; | |
66 | ||
67 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 68 | } |
1525bf0d | 69 | |
4287d824 | 70 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
71 | { |
72 | struct msi_desc *entry; | |
73 | int ret; | |
74 | ||
1c8d7b0a MW |
75 | /* |
76 | * If an architecture wants to support multiple MSI, it needs to | |
77 | * override arch_setup_msi_irqs() | |
78 | */ | |
79 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
80 | return 1; | |
81 | ||
6a9e7f20 AB |
82 | list_for_each_entry(entry, &dev->msi_list, list) { |
83 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 84 | if (ret < 0) |
6a9e7f20 | 85 | return ret; |
b5fbf533 ME |
86 | if (ret > 0) |
87 | return -ENOSPC; | |
6a9e7f20 AB |
88 | } |
89 | ||
90 | return 0; | |
91 | } | |
1525bf0d | 92 | |
4287d824 TP |
93 | /* |
94 | * We have a default implementation available as a separate non-weak | |
95 | * function, as it is used by the Xen x86 PCI code | |
96 | */ | |
1525bf0d | 97 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
98 | { |
99 | struct msi_desc *entry; | |
100 | ||
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
102 | int i, nvec; |
103 | if (entry->irq == 0) | |
104 | continue; | |
65f6ae66 AG |
105 | if (entry->nvec_used) |
106 | nvec = entry->nvec_used; | |
107 | else | |
108 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
109 | for (i = 0; i < nvec; i++) |
110 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
111 | } |
112 | } | |
113 | ||
4287d824 TP |
114 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
115 | { | |
116 | return default_teardown_msi_irqs(dev); | |
117 | } | |
76ccc297 | 118 | |
76ccc297 KRW |
119 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) |
120 | { | |
121 | struct msi_desc *entry; | |
122 | ||
123 | entry = NULL; | |
124 | if (dev->msix_enabled) { | |
125 | list_for_each_entry(entry, &dev->msi_list, list) { | |
126 | if (irq == entry->irq) | |
127 | break; | |
128 | } | |
129 | } else if (dev->msi_enabled) { | |
130 | entry = irq_get_msi_desc(irq); | |
131 | } | |
132 | ||
133 | if (entry) | |
134 | write_msi_msg(irq, &entry->msg); | |
135 | } | |
4287d824 TP |
136 | |
137 | void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) | |
138 | { | |
139 | return default_restore_msi_irqs(dev, irq); | |
140 | } | |
76ccc297 | 141 | |
e375b561 | 142 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 143 | { |
b1cbf4e4 EB |
144 | u16 control; |
145 | ||
e375b561 | 146 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
147 | control &= ~PCI_MSI_FLAGS_ENABLE; |
148 | if (enable) | |
149 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 150 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
151 | } |
152 | ||
b1cbf4e4 EB |
153 | static void msix_set_enable(struct pci_dev *dev, int enable) |
154 | { | |
b1cbf4e4 EB |
155 | u16 control; |
156 | ||
e375b561 GS |
157 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
158 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
159 | if (enable) | |
160 | control |= PCI_MSIX_FLAGS_ENABLE; | |
161 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
162 | } |
163 | ||
bffac3c5 MW |
164 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
165 | { | |
0b49ec37 MW |
166 | /* Don't shift by >= width of type */ |
167 | if (x >= 5) | |
168 | return 0xffffffff; | |
169 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
170 | } |
171 | ||
f2440d9a | 172 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 173 | { |
f2440d9a MW |
174 | return msi_mask((control >> 1) & 7); |
175 | } | |
988cbb15 | 176 | |
f2440d9a MW |
177 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
178 | { | |
179 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
180 | } |
181 | ||
ce6fce42 MW |
182 | /* |
183 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
184 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
185 | * reliably as devices without an INTx disable bit will then generate a | |
186 | * level IRQ which will never be cleared. | |
ce6fce42 | 187 | */ |
12abb8ba | 188 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 189 | { |
f2440d9a | 190 | u32 mask_bits = desc->masked; |
1da177e4 | 191 | |
f2440d9a | 192 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 193 | return 0; |
f2440d9a MW |
194 | |
195 | mask_bits &= ~mask; | |
196 | mask_bits |= flag; | |
197 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
198 | |
199 | return mask_bits; | |
200 | } | |
201 | ||
202 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
203 | { | |
204 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
205 | } |
206 | ||
207 | /* | |
208 | * This internal function does not flush PCI writes to the device. | |
209 | * All users must ensure that they read from the device before either | |
210 | * assuming that the device state is up to date, or returning out of this | |
211 | * file. This saves a few milliseconds when initialising devices with lots | |
212 | * of MSI-X interrupts. | |
213 | */ | |
12abb8ba | 214 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
215 | { |
216 | u32 mask_bits = desc->masked; | |
217 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 218 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
219 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
220 | if (flag) | |
221 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 222 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
223 | |
224 | return mask_bits; | |
225 | } | |
226 | ||
227 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
228 | { | |
229 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 230 | } |
24d27553 | 231 | |
9a4da8a5 JG |
232 | #ifdef CONFIG_GENERIC_HARDIRQS |
233 | ||
1c9db525 | 234 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 235 | { |
1c9db525 | 236 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 237 | |
f2440d9a MW |
238 | if (desc->msi_attrib.is_msix) { |
239 | msix_mask_irq(desc, flag); | |
240 | readl(desc->mask_base); /* Flush write to device */ | |
241 | } else { | |
1c9db525 | 242 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 243 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 244 | } |
f2440d9a MW |
245 | } |
246 | ||
1c9db525 | 247 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 248 | { |
1c9db525 | 249 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
250 | } |
251 | ||
1c9db525 | 252 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 253 | { |
1c9db525 | 254 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
255 | } |
256 | ||
9a4da8a5 JG |
257 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
258 | ||
39431acb | 259 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 260 | { |
30da5524 BH |
261 | BUG_ON(entry->dev->current_state != PCI_D0); |
262 | ||
263 | if (entry->msi_attrib.is_msix) { | |
264 | void __iomem *base = entry->mask_base + | |
265 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
266 | ||
267 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
268 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
269 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
270 | } else { | |
271 | struct pci_dev *dev = entry->dev; | |
f5322169 | 272 | int pos = dev->msi_cap; |
30da5524 BH |
273 | u16 data; |
274 | ||
9925ad0c BH |
275 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
276 | &msg->address_lo); | |
30da5524 | 277 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
278 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
279 | &msg->address_hi); | |
2f221349 | 280 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
281 | } else { |
282 | msg->address_hi = 0; | |
2f221349 | 283 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
284 | } |
285 | msg->data = data; | |
286 | } | |
287 | } | |
288 | ||
289 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
290 | { | |
dced35ae | 291 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 292 | |
39431acb | 293 | __read_msi_msg(entry, msg); |
30da5524 BH |
294 | } |
295 | ||
39431acb | 296 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 297 | { |
30da5524 | 298 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
299 | * valid messages are not all-zeroes. */ |
300 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
301 | entry->msg.data)); | |
0366f8f7 | 302 | |
fcd097f3 | 303 | *msg = entry->msg; |
0366f8f7 | 304 | } |
1da177e4 | 305 | |
30da5524 | 306 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 307 | { |
dced35ae | 308 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 309 | |
39431acb | 310 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
311 | } |
312 | ||
39431acb | 313 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 314 | { |
fcd097f3 BH |
315 | if (entry->dev->current_state != PCI_D0) { |
316 | /* Don't touch the hardware now */ | |
317 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
318 | void __iomem *base; |
319 | base = entry->mask_base + | |
320 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
321 | ||
2c21fd4b HS |
322 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
323 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
324 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 325 | } else { |
0366f8f7 | 326 | struct pci_dev *dev = entry->dev; |
f5322169 | 327 | int pos = dev->msi_cap; |
1c8d7b0a MW |
328 | u16 msgctl; |
329 | ||
f84ecd28 | 330 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
331 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
332 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 333 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 334 | |
9925ad0c BH |
335 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
336 | msg->address_lo); | |
0366f8f7 | 337 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
338 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
339 | msg->address_hi); | |
2f221349 BH |
340 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
341 | msg->data); | |
0366f8f7 | 342 | } else { |
2f221349 BH |
343 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
344 | msg->data); | |
0366f8f7 | 345 | } |
1da177e4 | 346 | } |
392ee1e6 | 347 | entry->msg = *msg; |
1da177e4 | 348 | } |
0366f8f7 | 349 | |
3145e941 YL |
350 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
351 | { | |
dced35ae | 352 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 353 | |
39431acb | 354 | __write_msi_msg(entry, msg); |
3145e941 YL |
355 | } |
356 | ||
f56e4481 HS |
357 | static void free_msi_irqs(struct pci_dev *dev) |
358 | { | |
359 | struct msi_desc *entry, *tmp; | |
360 | ||
361 | list_for_each_entry(entry, &dev->msi_list, list) { | |
362 | int i, nvec; | |
363 | if (!entry->irq) | |
364 | continue; | |
65f6ae66 AG |
365 | if (entry->nvec_used) |
366 | nvec = entry->nvec_used; | |
367 | else | |
368 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 369 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
370 | for (i = 0; i < nvec; i++) |
371 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 372 | #endif |
f56e4481 HS |
373 | } |
374 | ||
375 | arch_teardown_msi_irqs(dev); | |
376 | ||
377 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
378 | if (entry->msi_attrib.is_msix) { | |
379 | if (list_is_last(&entry->list, &dev->msi_list)) | |
380 | iounmap(entry->mask_base); | |
381 | } | |
424eb391 NH |
382 | |
383 | /* | |
384 | * Its possible that we get into this path | |
385 | * When populate_msi_sysfs fails, which means the entries | |
386 | * were not registered with sysfs. In that case don't | |
387 | * unregister them. | |
388 | */ | |
389 | if (entry->kobj.parent) { | |
390 | kobject_del(&entry->kobj); | |
391 | kobject_put(&entry->kobj); | |
392 | } | |
393 | ||
f56e4481 HS |
394 | list_del(&entry->list); |
395 | kfree(entry); | |
396 | } | |
397 | } | |
c54c1879 | 398 | |
379f5327 | 399 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 400 | { |
379f5327 MW |
401 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
402 | if (!desc) | |
1da177e4 LT |
403 | return NULL; |
404 | ||
379f5327 MW |
405 | INIT_LIST_HEAD(&desc->list); |
406 | desc->dev = dev; | |
1da177e4 | 407 | |
379f5327 | 408 | return desc; |
1da177e4 LT |
409 | } |
410 | ||
ba698ad4 DM |
411 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
412 | { | |
413 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
414 | pci_intx(dev, enable); | |
415 | } | |
416 | ||
8fed4b65 | 417 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 418 | { |
41017f0c | 419 | u16 control; |
392ee1e6 | 420 | struct msi_desc *entry; |
41017f0c | 421 | |
b1cbf4e4 EB |
422 | if (!dev->msi_enabled) |
423 | return; | |
424 | ||
dced35ae | 425 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 426 | |
ba698ad4 | 427 | pci_intx_for_msi(dev, 0); |
e375b561 | 428 | msi_set_enable(dev, 0); |
76ccc297 | 429 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 | 430 | |
f5322169 | 431 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 432 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 433 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 434 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 435 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
436 | } |
437 | ||
438 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 439 | { |
41017f0c | 440 | struct msi_desc *entry; |
392ee1e6 | 441 | u16 control; |
41017f0c | 442 | |
ded86d8d EB |
443 | if (!dev->msix_enabled) |
444 | return; | |
f598282f | 445 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 446 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 447 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 448 | |
41017f0c | 449 | /* route the table */ |
ba698ad4 | 450 | pci_intx_for_msi(dev, 0); |
f598282f | 451 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 452 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 453 | |
4aa9bc95 | 454 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 455 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 456 | msix_mask_irq(entry, entry->masked); |
41017f0c | 457 | } |
41017f0c | 458 | |
392ee1e6 | 459 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 460 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 461 | } |
8fed4b65 ME |
462 | |
463 | void pci_restore_msi_state(struct pci_dev *dev) | |
464 | { | |
465 | __pci_restore_msi_state(dev); | |
466 | __pci_restore_msix_state(dev); | |
467 | } | |
94688cf2 | 468 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 469 | |
da8d1c8b NH |
470 | |
471 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
472 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
473 | ||
474 | struct msi_attribute { | |
475 | struct attribute attr; | |
476 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
477 | char *buf); | |
478 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
479 | const char *buf, size_t count); | |
480 | }; | |
481 | ||
482 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
483 | char *buf) | |
484 | { | |
485 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
486 | } | |
487 | ||
488 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
489 | struct attribute *attr, char *buf) | |
490 | { | |
491 | struct msi_attribute *attribute = to_msi_attr(attr); | |
492 | struct msi_desc *entry = to_msi_desc(kobj); | |
493 | ||
494 | if (!attribute->show) | |
495 | return -EIO; | |
496 | ||
497 | return attribute->show(entry, attribute, buf); | |
498 | } | |
499 | ||
500 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
501 | .show = msi_irq_attr_show, | |
502 | }; | |
503 | ||
504 | static struct msi_attribute mode_attribute = | |
505 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
506 | ||
507 | ||
9738abed | 508 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
509 | &mode_attribute.attr, |
510 | NULL | |
511 | }; | |
512 | ||
9738abed | 513 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
514 | { |
515 | struct msi_desc *entry = to_msi_desc(kobj); | |
516 | ||
517 | pci_dev_put(entry->dev); | |
518 | } | |
519 | ||
520 | static struct kobj_type msi_irq_ktype = { | |
521 | .release = msi_kobj_release, | |
522 | .sysfs_ops = &msi_irq_sysfs_ops, | |
523 | .default_attrs = msi_irq_default_attrs, | |
524 | }; | |
525 | ||
526 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
527 | { | |
528 | struct msi_desc *entry; | |
529 | struct kobject *kobj; | |
530 | int ret; | |
531 | int count = 0; | |
532 | ||
533 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
534 | if (!pdev->msi_kset) | |
535 | return -ENOMEM; | |
536 | ||
537 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
538 | kobj = &entry->kobj; | |
539 | kobj->kset = pdev->msi_kset; | |
540 | pci_dev_get(pdev); | |
541 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
542 | "%u", entry->irq); | |
543 | if (ret) | |
544 | goto out_unroll; | |
545 | ||
546 | count++; | |
547 | } | |
548 | ||
549 | return 0; | |
550 | ||
551 | out_unroll: | |
552 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
553 | if (!count) | |
554 | break; | |
555 | kobject_del(&entry->kobj); | |
556 | kobject_put(&entry->kobj); | |
557 | count--; | |
558 | } | |
559 | return ret; | |
560 | } | |
561 | ||
1da177e4 LT |
562 | /** |
563 | * msi_capability_init - configure device's MSI capability structure | |
564 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 565 | * @nvec: number of interrupts to allocate |
1da177e4 | 566 | * |
1c8d7b0a MW |
567 | * Setup the MSI capability structure of the device with the requested |
568 | * number of interrupts. A return value of zero indicates the successful | |
569 | * setup of an entry with the new MSI irq. A negative return value indicates | |
570 | * an error, and a positive return value indicates the number of interrupts | |
571 | * which could have been allocated. | |
572 | */ | |
573 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
574 | { |
575 | struct msi_desc *entry; | |
f465136d | 576 | int ret; |
1da177e4 | 577 | u16 control; |
f2440d9a | 578 | unsigned mask; |
1da177e4 | 579 | |
e375b561 | 580 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 581 | |
f84ecd28 | 582 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 583 | /* MSI Entry Initialization */ |
379f5327 | 584 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
585 | if (!entry) |
586 | return -ENOMEM; | |
1ce03373 | 587 | |
500559a9 | 588 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 589 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 590 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 591 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 592 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 593 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 594 | |
e5f66eaf DC |
595 | if (control & PCI_MSI_FLAGS_64BIT) |
596 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
597 | else | |
598 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
599 | /* All MSIs are unmasked by default, Mask them all */ |
600 | if (entry->msi_attrib.maskbit) | |
601 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
602 | mask = msi_capable_mask(control); | |
603 | msi_mask_irq(entry, mask, mask); | |
604 | ||
0dd11f9b | 605 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 606 | |
1da177e4 | 607 | /* Configure MSI capability structure */ |
1c8d7b0a | 608 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 609 | if (ret) { |
7ba1930d | 610 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 611 | free_msi_irqs(dev); |
7fe3730d | 612 | return ret; |
fd58e55f | 613 | } |
f7feaca7 | 614 | |
da8d1c8b NH |
615 | ret = populate_msi_sysfs(dev); |
616 | if (ret) { | |
617 | msi_mask_irq(entry, mask, ~mask); | |
618 | free_msi_irqs(dev); | |
619 | return ret; | |
620 | } | |
621 | ||
1da177e4 | 622 | /* Set MSI enabled bits */ |
ba698ad4 | 623 | pci_intx_for_msi(dev, 0); |
e375b561 | 624 | msi_set_enable(dev, 1); |
b1cbf4e4 | 625 | dev->msi_enabled = 1; |
1da177e4 | 626 | |
7fe3730d | 627 | dev->irq = entry->irq; |
1da177e4 LT |
628 | return 0; |
629 | } | |
630 | ||
520fe9dc | 631 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 632 | { |
4302e0fb | 633 | resource_size_t phys_addr; |
5a05a9d8 HS |
634 | u32 table_offset; |
635 | u8 bir; | |
636 | ||
909094c6 BH |
637 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
638 | &table_offset); | |
4d18760c BH |
639 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
640 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
641 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
642 | ||
643 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
644 | } | |
645 | ||
520fe9dc GS |
646 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
647 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
648 | { |
649 | struct msi_desc *entry; | |
650 | int i; | |
651 | ||
652 | for (i = 0; i < nvec; i++) { | |
653 | entry = alloc_msi_entry(dev); | |
654 | if (!entry) { | |
655 | if (!i) | |
656 | iounmap(base); | |
657 | else | |
658 | free_msi_irqs(dev); | |
659 | /* No enough memory. Don't try again */ | |
660 | return -ENOMEM; | |
661 | } | |
662 | ||
663 | entry->msi_attrib.is_msix = 1; | |
664 | entry->msi_attrib.is_64 = 1; | |
665 | entry->msi_attrib.entry_nr = entries[i].entry; | |
666 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 667 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
668 | entry->mask_base = base; |
669 | ||
670 | list_add_tail(&entry->list, &dev->msi_list); | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
75cb3426 | 676 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 677 | struct msix_entry *entries) |
75cb3426 HS |
678 | { |
679 | struct msi_desc *entry; | |
680 | int i = 0; | |
681 | ||
682 | list_for_each_entry(entry, &dev->msi_list, list) { | |
683 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
684 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
685 | ||
686 | entries[i].vector = entry->irq; | |
dced35ae | 687 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
688 | entry->masked = readl(entry->mask_base + offset); |
689 | msix_mask_irq(entry, 1); | |
690 | i++; | |
691 | } | |
692 | } | |
693 | ||
1da177e4 LT |
694 | /** |
695 | * msix_capability_init - configure device's MSI-X capability | |
696 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
697 | * @entries: pointer to an array of struct msix_entry entries |
698 | * @nvec: number of @entries | |
1da177e4 | 699 | * |
eaae4b3a | 700 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
701 | * single MSI-X irq. A return of zero indicates the successful setup of |
702 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
703 | **/ |
704 | static int msix_capability_init(struct pci_dev *dev, | |
705 | struct msix_entry *entries, int nvec) | |
706 | { | |
520fe9dc | 707 | int ret; |
5a05a9d8 | 708 | u16 control; |
1da177e4 LT |
709 | void __iomem *base; |
710 | ||
520fe9dc | 711 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
712 | |
713 | /* Ensure MSI-X is disabled while it is set up */ | |
714 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 715 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 716 | |
1da177e4 | 717 | /* Request & Map MSI-X table region */ |
527eee29 | 718 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 719 | if (!base) |
1da177e4 LT |
720 | return -ENOMEM; |
721 | ||
520fe9dc | 722 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
723 | if (ret) |
724 | return ret; | |
9c831334 ME |
725 | |
726 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
727 | if (ret) |
728 | goto error; | |
9c831334 | 729 | |
f598282f MW |
730 | /* |
731 | * Some devices require MSI-X to be enabled before we can touch the | |
732 | * MSI-X registers. We need to mask all the vectors to prevent | |
733 | * interrupts coming in before they're fully set up. | |
734 | */ | |
735 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 736 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 737 | |
75cb3426 | 738 | msix_program_entries(dev, entries); |
f598282f | 739 | |
da8d1c8b NH |
740 | ret = populate_msi_sysfs(dev); |
741 | if (ret) { | |
742 | ret = 0; | |
743 | goto error; | |
744 | } | |
745 | ||
f598282f | 746 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 747 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 748 | dev->msix_enabled = 1; |
1da177e4 | 749 | |
f598282f | 750 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 751 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 752 | |
1da177e4 | 753 | return 0; |
583871d4 HS |
754 | |
755 | error: | |
756 | if (ret < 0) { | |
757 | /* | |
758 | * If we had some success, report the number of irqs | |
759 | * we succeeded in setting up. | |
760 | */ | |
d9d7070e | 761 | struct msi_desc *entry; |
583871d4 HS |
762 | int avail = 0; |
763 | ||
764 | list_for_each_entry(entry, &dev->msi_list, list) { | |
765 | if (entry->irq != 0) | |
766 | avail++; | |
767 | } | |
768 | if (avail != 0) | |
769 | ret = avail; | |
770 | } | |
771 | ||
772 | free_msi_irqs(dev); | |
773 | ||
774 | return ret; | |
1da177e4 LT |
775 | } |
776 | ||
24334a12 | 777 | /** |
17bbc12a | 778 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 779 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 780 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 781 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 782 | * |
0306ebfa | 783 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
784 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
785 | * supported return 0, else return an error code. | |
24334a12 | 786 | **/ |
500559a9 | 787 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
788 | { |
789 | struct pci_bus *bus; | |
c9953a73 | 790 | int ret; |
24334a12 | 791 | |
0306ebfa | 792 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
793 | if (!pci_msi_enable || !dev || dev->no_msi) |
794 | return -EINVAL; | |
795 | ||
314e77b3 ME |
796 | /* |
797 | * You can't ask to have 0 or less MSIs configured. | |
798 | * a) it's stupid .. | |
799 | * b) the list manipulation code assumes nvec >= 1. | |
800 | */ | |
801 | if (nvec < 1) | |
802 | return -ERANGE; | |
803 | ||
500559a9 HS |
804 | /* |
805 | * Any bridge which does NOT route MSI transactions from its | |
806 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
807 | * the secondary pci_bus. |
808 | * We expect only arch-specific PCI host bus controller driver | |
809 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
810 | */ | |
24334a12 BG |
811 | for (bus = dev->bus; bus; bus = bus->parent) |
812 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
813 | return -EINVAL; | |
814 | ||
c9953a73 ME |
815 | ret = arch_msi_check_device(dev, nvec, type); |
816 | if (ret) | |
817 | return ret; | |
818 | ||
24334a12 BG |
819 | return 0; |
820 | } | |
821 | ||
1da177e4 | 822 | /** |
1c8d7b0a MW |
823 | * pci_enable_msi_block - configure device's MSI capability structure |
824 | * @dev: device to configure | |
825 | * @nvec: number of interrupts to configure | |
1da177e4 | 826 | * |
1c8d7b0a MW |
827 | * Allocate IRQs for a device with the MSI capability. |
828 | * This function returns a negative errno if an error occurs. If it | |
829 | * is unable to allocate the number of interrupts requested, it returns | |
830 | * the number of interrupts it might be able to allocate. If it successfully | |
831 | * allocates at least the number of interrupts requested, it returns 0 and | |
832 | * updates the @dev's irq member to the lowest new interrupt number; the | |
833 | * other interrupt numbers allocated to this device are consecutive. | |
834 | */ | |
835 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 836 | { |
f465136d | 837 | int status, maxvec; |
1c8d7b0a MW |
838 | u16 msgctl; |
839 | ||
f465136d | 840 | if (!dev->msi_cap) |
1c8d7b0a | 841 | return -EINVAL; |
f465136d GS |
842 | |
843 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
844 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
845 | if (nvec > maxvec) | |
846 | return maxvec; | |
1da177e4 | 847 | |
1c8d7b0a | 848 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
849 | if (status) |
850 | return status; | |
1da177e4 | 851 | |
ded86d8d | 852 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 853 | |
1c8d7b0a | 854 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 855 | if (dev->msix_enabled) { |
80ccba11 BH |
856 | dev_info(&dev->dev, "can't enable MSI " |
857 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 858 | return -EINVAL; |
1da177e4 | 859 | } |
1c8d7b0a MW |
860 | |
861 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
862 | return status; |
863 | } | |
1c8d7b0a | 864 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 865 | |
08261d87 AG |
866 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
867 | { | |
f465136d | 868 | int ret, nvec; |
08261d87 AG |
869 | u16 msgctl; |
870 | ||
f465136d | 871 | if (!dev->msi_cap) |
08261d87 AG |
872 | return -EINVAL; |
873 | ||
f465136d | 874 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
875 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
876 | ||
877 | if (maxvec) | |
878 | *maxvec = ret; | |
879 | ||
880 | do { | |
881 | nvec = ret; | |
882 | ret = pci_enable_msi_block(dev, nvec); | |
883 | } while (ret > 0); | |
884 | ||
885 | if (ret < 0) | |
886 | return ret; | |
887 | return nvec; | |
888 | } | |
889 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
890 | ||
f2440d9a | 891 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 892 | { |
f2440d9a MW |
893 | struct msi_desc *desc; |
894 | u32 mask; | |
895 | u16 ctrl; | |
1da177e4 | 896 | |
128bc5fc | 897 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
898 | return; |
899 | ||
110828c9 MW |
900 | BUG_ON(list_empty(&dev->msi_list)); |
901 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 902 | |
e375b561 | 903 | msi_set_enable(dev, 0); |
ba698ad4 | 904 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 905 | dev->msi_enabled = 0; |
7bd007e4 | 906 | |
12abb8ba | 907 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 908 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 909 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
910 | /* Keep cached state to be restored */ |
911 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
912 | |
913 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 914 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 915 | } |
24d27553 | 916 | |
500559a9 | 917 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 918 | { |
d52877c7 YL |
919 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
920 | return; | |
921 | ||
922 | pci_msi_shutdown(dev); | |
f56e4481 | 923 | free_msi_irqs(dev); |
da8d1c8b NH |
924 | kset_unregister(dev->msi_kset); |
925 | dev->msi_kset = NULL; | |
1da177e4 | 926 | } |
4cc086fa | 927 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 928 | |
a52e2e35 RW |
929 | /** |
930 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
931 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
932 | */ | |
933 | int pci_msix_table_size(struct pci_dev *dev) | |
934 | { | |
a52e2e35 RW |
935 | u16 control; |
936 | ||
520fe9dc | 937 | if (!dev->msix_cap) |
a52e2e35 RW |
938 | return 0; |
939 | ||
f84ecd28 | 940 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 941 | return msix_table_size(control); |
a52e2e35 RW |
942 | } |
943 | ||
1da177e4 LT |
944 | /** |
945 | * pci_enable_msix - configure device's MSI-X capability structure | |
946 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 947 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 948 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
949 | * |
950 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 951 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
952 | * MSI-X mode enabled on its hardware device function. A return of zero |
953 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 954 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 955 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
956 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
957 | * re-send its request. | |
1da177e4 | 958 | **/ |
500559a9 | 959 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 960 | { |
a52e2e35 | 961 | int status, nr_entries; |
ded86d8d | 962 | int i, j; |
1da177e4 | 963 | |
cdf1fd4d | 964 | if (!entries || !dev->msix_cap) |
500559a9 | 965 | return -EINVAL; |
1da177e4 | 966 | |
c9953a73 ME |
967 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
968 | if (status) | |
969 | return status; | |
970 | ||
a52e2e35 | 971 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 972 | if (nvec > nr_entries) |
57fbf52c | 973 | return nr_entries; |
1da177e4 LT |
974 | |
975 | /* Check for any invalid entries */ | |
976 | for (i = 0; i < nvec; i++) { | |
977 | if (entries[i].entry >= nr_entries) | |
978 | return -EINVAL; /* invalid entry */ | |
979 | for (j = i + 1; j < nvec; j++) { | |
980 | if (entries[i].entry == entries[j].entry) | |
981 | return -EINVAL; /* duplicate entry */ | |
982 | } | |
983 | } | |
ded86d8d | 984 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 985 | |
1ce03373 | 986 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 987 | if (dev->msi_enabled) { |
80ccba11 BH |
988 | dev_info(&dev->dev, "can't enable MSI-X " |
989 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
990 | return -EINVAL; |
991 | } | |
1da177e4 | 992 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
993 | return status; |
994 | } | |
4cc086fa | 995 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 996 | |
500559a9 | 997 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 998 | { |
12abb8ba HS |
999 | struct msi_desc *entry; |
1000 | ||
128bc5fc | 1001 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1002 | return; |
1003 | ||
12abb8ba HS |
1004 | /* Return the device with MSI-X masked as initial states */ |
1005 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1006 | /* Keep cached states to be restored */ | |
1007 | __msix_mask_irq(entry, 1); | |
1008 | } | |
1009 | ||
b1cbf4e4 | 1010 | msix_set_enable(dev, 0); |
ba698ad4 | 1011 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1012 | dev->msix_enabled = 0; |
d52877c7 | 1013 | } |
c901851f | 1014 | |
500559a9 | 1015 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1016 | { |
1017 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1018 | return; | |
1019 | ||
1020 | pci_msix_shutdown(dev); | |
f56e4481 | 1021 | free_msi_irqs(dev); |
da8d1c8b NH |
1022 | kset_unregister(dev->msi_kset); |
1023 | dev->msi_kset = NULL; | |
1da177e4 | 1024 | } |
4cc086fa | 1025 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1026 | |
1027 | /** | |
1ce03373 | 1028 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1029 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1030 | * | |
eaae4b3a | 1031 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1032 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1033 | * allocated for this device function, are reclaimed to unused state, |
1034 | * which may be used later on. | |
1035 | **/ | |
500559a9 | 1036 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1037 | { |
1da177e4 | 1038 | if (!pci_msi_enable || !dev) |
500559a9 | 1039 | return; |
1da177e4 | 1040 | |
f56e4481 HS |
1041 | if (dev->msi_enabled || dev->msix_enabled) |
1042 | free_msi_irqs(dev); | |
1da177e4 LT |
1043 | } |
1044 | ||
309e57df MW |
1045 | void pci_no_msi(void) |
1046 | { | |
1047 | pci_msi_enable = 0; | |
1048 | } | |
c9953a73 | 1049 | |
07ae95f9 AP |
1050 | /** |
1051 | * pci_msi_enabled - is MSI enabled? | |
1052 | * | |
1053 | * Returns true if MSI has not been disabled by the command-line option | |
1054 | * pci=nomsi. | |
1055 | **/ | |
1056 | int pci_msi_enabled(void) | |
d389fec6 | 1057 | { |
07ae95f9 | 1058 | return pci_msi_enable; |
d389fec6 | 1059 | } |
07ae95f9 | 1060 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1061 | |
07ae95f9 | 1062 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1063 | { |
07ae95f9 | 1064 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1065 | |
1066 | /* Disable the msi hardware to avoid screaming interrupts | |
1067 | * during boot. This is the power on reset default so | |
1068 | * usually this should be a noop. | |
1069 | */ | |
e375b561 GS |
1070 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1071 | if (dev->msi_cap) | |
1072 | msi_set_enable(dev, 0); | |
1073 | ||
1074 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1075 | if (dev->msix_cap) | |
1076 | msix_set_enable(dev, 0); | |
d389fec6 | 1077 | } |