Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
18 | ||
19 | #include <asm/errno.h> | |
20 | #include <asm/io.h> | |
21 | #include <asm/smp.h> | |
22 | ||
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
26 | static DEFINE_SPINLOCK(msi_lock); | |
27 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; | |
28 | static kmem_cache_t* msi_cachep; | |
29 | ||
30 | static int pci_msi_enable = 1; | |
1da177e4 | 31 | |
fd58e55f MM |
32 | static struct msi_ops *msi_ops; |
33 | ||
34 | int | |
35 | msi_register(struct msi_ops *ops) | |
36 | { | |
37 | msi_ops = ops; | |
38 | return 0; | |
39 | } | |
40 | ||
1da177e4 LT |
41 | static int msi_cache_init(void) |
42 | { | |
57181784 PE |
43 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
44 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
45 | if (!msi_cachep) |
46 | return -ENOMEM; | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
1ce03373 | 51 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
52 | { |
53 | struct msi_desc *entry; | |
54 | ||
1ce03373 | 55 | entry = msi_desc[irq]; |
1da177e4 LT |
56 | if (!entry || !entry->dev || !entry->mask_base) |
57 | return; | |
58 | switch (entry->msi_attrib.type) { | |
59 | case PCI_CAP_ID_MSI: | |
60 | { | |
61 | int pos; | |
62 | u32 mask_bits; | |
63 | ||
64 | pos = (long)entry->mask_base; | |
65 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
66 | mask_bits &= ~(1); | |
67 | mask_bits |= flag; | |
68 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
69 | break; | |
70 | } | |
71 | case PCI_CAP_ID_MSIX: | |
72 | { | |
73 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
74 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
75 | writel(flag, entry->mask_base + offset); | |
76 | break; | |
77 | } | |
78 | default: | |
79 | break; | |
80 | } | |
81 | } | |
82 | ||
0366f8f7 | 83 | static void read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 84 | { |
0366f8f7 EB |
85 | switch(entry->msi_attrib.type) { |
86 | case PCI_CAP_ID_MSI: | |
87 | { | |
88 | struct pci_dev *dev = entry->dev; | |
89 | int pos = entry->msi_attrib.pos; | |
90 | u16 data; | |
91 | ||
92 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
93 | &msg->address_lo); | |
94 | if (entry->msi_attrib.is_64) { | |
95 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
96 | &msg->address_hi); | |
97 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
98 | } else { | |
99 | msg->address_hi = 0; | |
100 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
101 | } | |
102 | msg->data = data; | |
103 | break; | |
104 | } | |
105 | case PCI_CAP_ID_MSIX: | |
106 | { | |
107 | void __iomem *base; | |
108 | base = entry->mask_base + | |
109 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
110 | ||
111 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
112 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
113 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
114 | break; | |
115 | } | |
116 | default: | |
117 | BUG(); | |
118 | } | |
119 | } | |
1da177e4 | 120 | |
0366f8f7 EB |
121 | static void write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
122 | { | |
1da177e4 LT |
123 | switch (entry->msi_attrib.type) { |
124 | case PCI_CAP_ID_MSI: | |
125 | { | |
0366f8f7 EB |
126 | struct pci_dev *dev = entry->dev; |
127 | int pos = entry->msi_attrib.pos; | |
128 | ||
129 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
130 | msg->address_lo); | |
131 | if (entry->msi_attrib.is_64) { | |
132 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
133 | msg->address_hi); | |
134 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
135 | msg->data); | |
136 | } else { | |
137 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
138 | msg->data); | |
139 | } | |
1da177e4 LT |
140 | break; |
141 | } | |
142 | case PCI_CAP_ID_MSIX: | |
143 | { | |
0366f8f7 EB |
144 | void __iomem *base; |
145 | base = entry->mask_base + | |
146 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
147 | ||
148 | writel(msg->address_lo, | |
149 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
150 | writel(msg->address_hi, | |
151 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
152 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
153 | break; |
154 | } | |
155 | default: | |
0366f8f7 | 156 | BUG(); |
1da177e4 LT |
157 | } |
158 | } | |
0366f8f7 EB |
159 | |
160 | #ifdef CONFIG_SMP | |
38bc0361 | 161 | static void set_msi_affinity(unsigned int irq, cpumask_t cpu_mask) |
0366f8f7 EB |
162 | { |
163 | struct msi_desc *entry; | |
164 | struct msi_msg msg; | |
0366f8f7 | 165 | |
38bc0361 | 166 | entry = msi_desc[irq]; |
0366f8f7 EB |
167 | if (!entry || !entry->dev) |
168 | return; | |
169 | ||
170 | read_msi_msg(entry, &msg); | |
38bc0361 | 171 | msi_ops->target(irq, cpu_mask, &msg); |
0366f8f7 EB |
172 | write_msi_msg(entry, &msg); |
173 | set_native_irq_info(irq, cpu_mask); | |
174 | } | |
8169b5d2 GG |
175 | #else |
176 | #define set_msi_affinity NULL | |
1da177e4 LT |
177 | #endif /* CONFIG_SMP */ |
178 | ||
1ce03373 | 179 | static void mask_MSI_irq(unsigned int irq) |
1da177e4 | 180 | { |
1ce03373 | 181 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
182 | } |
183 | ||
1ce03373 | 184 | static void unmask_MSI_irq(unsigned int irq) |
1da177e4 | 185 | { |
1ce03373 | 186 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
187 | } |
188 | ||
1ce03373 | 189 | static unsigned int startup_msi_irq_wo_maskbit(unsigned int irq) |
1da177e4 | 190 | { |
1da177e4 LT |
191 | return 0; /* never anything pending */ |
192 | } | |
193 | ||
1ce03373 | 194 | static unsigned int startup_msi_irq_w_maskbit(unsigned int irq) |
1da177e4 | 195 | { |
1ce03373 EB |
196 | startup_msi_irq_wo_maskbit(irq); |
197 | unmask_MSI_irq(irq); | |
70549ad9 | 198 | return 0; /* never anything pending */ |
1da177e4 LT |
199 | } |
200 | ||
1ce03373 | 201 | static void shutdown_msi_irq(unsigned int irq) |
1da177e4 | 202 | { |
1da177e4 LT |
203 | } |
204 | ||
1ce03373 | 205 | static void end_msi_irq_wo_maskbit(unsigned int irq) |
70549ad9 | 206 | { |
1ce03373 | 207 | move_native_irq(irq); |
70549ad9 GKH |
208 | ack_APIC_irq(); |
209 | } | |
1da177e4 | 210 | |
1ce03373 | 211 | static void end_msi_irq_w_maskbit(unsigned int irq) |
1da177e4 | 212 | { |
1ce03373 EB |
213 | move_native_irq(irq); |
214 | unmask_MSI_irq(irq); | |
1da177e4 LT |
215 | ack_APIC_irq(); |
216 | } | |
217 | ||
1ce03373 | 218 | static void do_nothing(unsigned int irq) |
70549ad9 GKH |
219 | { |
220 | } | |
221 | ||
1da177e4 LT |
222 | /* |
223 | * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, | |
224 | * which implement the MSI-X Capability Structure. | |
225 | */ | |
226 | static struct hw_interrupt_type msix_irq_type = { | |
227 | .typename = "PCI-MSI-X", | |
228 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
229 | .shutdown = shutdown_msi_irq, |
230 | .enable = unmask_MSI_irq, | |
231 | .disable = mask_MSI_irq, | |
232 | .ack = mask_MSI_irq, | |
1da177e4 | 233 | .end = end_msi_irq_w_maskbit, |
8169b5d2 | 234 | .set_affinity = set_msi_affinity |
1da177e4 LT |
235 | }; |
236 | ||
237 | /* | |
238 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
239 | * which implement the MSI Capability Structure with | |
240 | * Mask-and-Pending Bits. | |
241 | */ | |
242 | static struct hw_interrupt_type msi_irq_w_maskbit_type = { | |
243 | .typename = "PCI-MSI", | |
244 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
245 | .shutdown = shutdown_msi_irq, |
246 | .enable = unmask_MSI_irq, | |
247 | .disable = mask_MSI_irq, | |
248 | .ack = mask_MSI_irq, | |
1da177e4 | 249 | .end = end_msi_irq_w_maskbit, |
8169b5d2 | 250 | .set_affinity = set_msi_affinity |
1da177e4 LT |
251 | }; |
252 | ||
253 | /* | |
254 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
255 | * which implement the MSI Capability Structure without | |
256 | * Mask-and-Pending Bits. | |
257 | */ | |
258 | static struct hw_interrupt_type msi_irq_wo_maskbit_type = { | |
259 | .typename = "PCI-MSI", | |
260 | .startup = startup_msi_irq_wo_maskbit, | |
70549ad9 GKH |
261 | .shutdown = shutdown_msi_irq, |
262 | .enable = do_nothing, | |
263 | .disable = do_nothing, | |
264 | .ack = do_nothing, | |
1da177e4 | 265 | .end = end_msi_irq_wo_maskbit, |
8169b5d2 | 266 | .set_affinity = set_msi_affinity |
1da177e4 LT |
267 | }; |
268 | ||
1ce03373 | 269 | static int msi_free_irq(struct pci_dev* dev, int irq); |
1da177e4 LT |
270 | static int msi_init(void) |
271 | { | |
272 | static int status = -ENOMEM; | |
273 | ||
274 | if (!status) | |
275 | return status; | |
276 | ||
277 | if (pci_msi_quirk) { | |
278 | pci_msi_enable = 0; | |
279 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); | |
280 | status = -EINVAL; | |
281 | return status; | |
282 | } | |
283 | ||
fd58e55f MM |
284 | status = msi_arch_init(); |
285 | if (status < 0) { | |
286 | pci_msi_enable = 0; | |
287 | printk(KERN_WARNING | |
288 | "PCI: MSI arch init failed. MSI disabled.\n"); | |
289 | return status; | |
290 | } | |
291 | ||
292 | if (! msi_ops) { | |
1ce03373 | 293 | pci_msi_enable = 0; |
fd58e55f MM |
294 | printk(KERN_WARNING |
295 | "PCI: MSI ops not registered. MSI disabled.\n"); | |
296 | status = -EINVAL; | |
297 | return status; | |
298 | } | |
299 | ||
b64c05e7 GG |
300 | status = msi_cache_init(); |
301 | if (status < 0) { | |
1da177e4 LT |
302 | pci_msi_enable = 0; |
303 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
304 | return status; | |
305 | } | |
fd58e55f | 306 | |
1da177e4 LT |
307 | return status; |
308 | } | |
309 | ||
1da177e4 LT |
310 | static struct msi_desc* alloc_msi_entry(void) |
311 | { | |
312 | struct msi_desc *entry; | |
313 | ||
57181784 | 314 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
315 | if (!entry) |
316 | return NULL; | |
317 | ||
1da177e4 LT |
318 | entry->link.tail = entry->link.head = 0; /* single message */ |
319 | entry->dev = NULL; | |
320 | ||
321 | return entry; | |
322 | } | |
323 | ||
1ce03373 | 324 | static void attach_msi_entry(struct msi_desc *entry, int irq) |
1da177e4 LT |
325 | { |
326 | unsigned long flags; | |
327 | ||
328 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 | 329 | msi_desc[irq] = entry; |
1da177e4 LT |
330 | spin_unlock_irqrestore(&msi_lock, flags); |
331 | } | |
332 | ||
1ce03373 | 333 | static int create_msi_irq(struct hw_interrupt_type *handler) |
1da177e4 | 334 | { |
1ce03373 EB |
335 | struct msi_desc *entry; |
336 | int irq; | |
337 | ||
338 | entry = alloc_msi_entry(); | |
339 | if (!entry) | |
340 | return -ENOMEM; | |
f6bc2666 | 341 | |
1ce03373 EB |
342 | irq = create_irq(); |
343 | if (irq < 0) { | |
344 | kmem_cache_free(msi_cachep, entry); | |
345 | return -EBUSY; | |
1da177e4 | 346 | } |
1ce03373 EB |
347 | |
348 | set_irq_chip(irq, handler); | |
349 | set_irq_data(irq, entry); | |
350 | ||
351 | return irq; | |
352 | } | |
353 | ||
354 | static void destroy_msi_irq(unsigned int irq) | |
355 | { | |
356 | struct msi_desc *entry; | |
357 | ||
358 | entry = get_irq_data(irq); | |
359 | set_irq_chip(irq, NULL); | |
360 | set_irq_data(irq, NULL); | |
361 | destroy_irq(irq); | |
362 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
363 | } |
364 | ||
365 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
366 | { | |
367 | u16 control; | |
368 | ||
369 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
370 | if (type == PCI_CAP_ID_MSI) { | |
371 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
372 | msi_enable(control, 1); | |
373 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 374 | dev->msi_enabled = 1; |
1da177e4 LT |
375 | } else { |
376 | msix_enable(control); | |
377 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 378 | dev->msix_enabled = 1; |
1da177e4 LT |
379 | } |
380 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
381 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 382 | pci_intx(dev, 0); /* disable intx */ |
1da177e4 LT |
383 | } |
384 | } | |
385 | ||
4602b88d | 386 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
387 | { |
388 | u16 control; | |
389 | ||
390 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
391 | if (type == PCI_CAP_ID_MSI) { | |
392 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
393 | msi_disable(control); | |
394 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 395 | dev->msi_enabled = 0; |
1da177e4 LT |
396 | } else { |
397 | msix_disable(control); | |
398 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 399 | dev->msix_enabled = 0; |
1da177e4 LT |
400 | } |
401 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
402 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 403 | pci_intx(dev, 1); /* enable intx */ |
1da177e4 LT |
404 | } |
405 | } | |
406 | ||
1ce03373 | 407 | static int msi_lookup_irq(struct pci_dev *dev, int type) |
1da177e4 | 408 | { |
1ce03373 | 409 | int irq; |
1da177e4 LT |
410 | unsigned long flags; |
411 | ||
412 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
413 | for (irq = 0; irq < NR_IRQS; irq++) { |
414 | if (!msi_desc[irq] || msi_desc[irq]->dev != dev || | |
415 | msi_desc[irq]->msi_attrib.type != type || | |
416 | msi_desc[irq]->msi_attrib.default_irq != dev->irq) | |
1da177e4 LT |
417 | continue; |
418 | spin_unlock_irqrestore(&msi_lock, flags); | |
1ce03373 EB |
419 | /* This pre-assigned MSI irq for this device |
420 | already exits. Override dev->irq with this irq */ | |
421 | dev->irq = irq; | |
1da177e4 LT |
422 | return 0; |
423 | } | |
424 | spin_unlock_irqrestore(&msi_lock, flags); | |
425 | ||
426 | return -EACCES; | |
427 | } | |
428 | ||
429 | void pci_scan_msi_device(struct pci_dev *dev) | |
430 | { | |
431 | if (!dev) | |
432 | return; | |
1da177e4 LT |
433 | } |
434 | ||
41017f0c SL |
435 | #ifdef CONFIG_PM |
436 | int pci_save_msi_state(struct pci_dev *dev) | |
437 | { | |
438 | int pos, i = 0; | |
439 | u16 control; | |
440 | struct pci_cap_saved_state *save_state; | |
441 | u32 *cap; | |
442 | ||
443 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
444 | if (pos <= 0 || dev->no_msi) | |
445 | return 0; | |
446 | ||
447 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
448 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
449 | return 0; | |
450 | ||
451 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
452 | GFP_KERNEL); | |
453 | if (!save_state) { | |
454 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
455 | return -ENOMEM; | |
456 | } | |
457 | cap = &save_state->data[0]; | |
458 | ||
459 | pci_read_config_dword(dev, pos, &cap[i++]); | |
460 | control = cap[0] >> 16; | |
461 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
462 | if (control & PCI_MSI_FLAGS_64BIT) { | |
463 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
464 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
465 | } else | |
466 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
467 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
468 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
469 | save_state->cap_nr = PCI_CAP_ID_MSI; |
470 | pci_add_saved_cap(dev, save_state); | |
471 | return 0; | |
472 | } | |
473 | ||
474 | void pci_restore_msi_state(struct pci_dev *dev) | |
475 | { | |
476 | int i = 0, pos; | |
477 | u16 control; | |
478 | struct pci_cap_saved_state *save_state; | |
479 | u32 *cap; | |
480 | ||
481 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); | |
482 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
483 | if (!save_state || pos <= 0) | |
484 | return; | |
485 | cap = &save_state->data[0]; | |
486 | ||
487 | control = cap[i++] >> 16; | |
488 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); | |
489 | if (control & PCI_MSI_FLAGS_64BIT) { | |
490 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
491 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
492 | } else | |
493 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
494 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
495 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
496 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
497 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
498 | pci_remove_saved_cap(save_state); | |
499 | kfree(save_state); | |
500 | } | |
501 | ||
502 | int pci_save_msix_state(struct pci_dev *dev) | |
503 | { | |
504 | int pos; | |
fd58e55f | 505 | int temp; |
1ce03373 | 506 | int irq, head, tail = 0; |
41017f0c SL |
507 | u16 control; |
508 | struct pci_cap_saved_state *save_state; | |
509 | ||
510 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
511 | if (pos <= 0 || dev->no_msi) | |
512 | return 0; | |
513 | ||
fd58e55f | 514 | /* save the capability */ |
41017f0c SL |
515 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
516 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
517 | return 0; | |
518 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), | |
519 | GFP_KERNEL); | |
520 | if (!save_state) { | |
521 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
522 | return -ENOMEM; | |
523 | } | |
524 | *((u16 *)&save_state->data[0]) = control; | |
525 | ||
fd58e55f MM |
526 | /* save the table */ |
527 | temp = dev->irq; | |
1ce03373 | 528 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
fd58e55f MM |
529 | kfree(save_state); |
530 | return -EINVAL; | |
531 | } | |
532 | ||
1ce03373 | 533 | irq = head = dev->irq; |
fd58e55f | 534 | while (head != tail) { |
fd58e55f MM |
535 | struct msi_desc *entry; |
536 | ||
1ce03373 | 537 | entry = msi_desc[irq]; |
0366f8f7 | 538 | read_msi_msg(entry, &entry->msg_save); |
fd58e55f | 539 | |
1ce03373 EB |
540 | tail = msi_desc[irq]->link.tail; |
541 | irq = tail; | |
fd58e55f MM |
542 | } |
543 | dev->irq = temp; | |
544 | ||
41017f0c SL |
545 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
546 | pci_add_saved_cap(dev, save_state); | |
547 | return 0; | |
548 | } | |
549 | ||
550 | void pci_restore_msix_state(struct pci_dev *dev) | |
551 | { | |
552 | u16 save; | |
553 | int pos; | |
1ce03373 | 554 | int irq, head, tail = 0; |
41017f0c SL |
555 | struct msi_desc *entry; |
556 | int temp; | |
557 | struct pci_cap_saved_state *save_state; | |
558 | ||
559 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); | |
560 | if (!save_state) | |
561 | return; | |
562 | save = *((u16 *)&save_state->data[0]); | |
563 | pci_remove_saved_cap(save_state); | |
564 | kfree(save_state); | |
565 | ||
566 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
567 | if (pos <= 0) | |
568 | return; | |
569 | ||
570 | /* route the table */ | |
571 | temp = dev->irq; | |
1ce03373 | 572 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) |
41017f0c | 573 | return; |
1ce03373 | 574 | irq = head = dev->irq; |
41017f0c | 575 | while (head != tail) { |
1ce03373 | 576 | entry = msi_desc[irq]; |
0366f8f7 | 577 | write_msi_msg(entry, &entry->msg_save); |
41017f0c | 578 | |
1ce03373 EB |
579 | tail = msi_desc[irq]->link.tail; |
580 | irq = tail; | |
41017f0c SL |
581 | } |
582 | dev->irq = temp; | |
583 | ||
584 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
585 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
586 | } | |
587 | #endif | |
588 | ||
fd58e55f | 589 | static int msi_register_init(struct pci_dev *dev, struct msi_desc *entry) |
41017f0c | 590 | { |
fd58e55f | 591 | int status; |
0366f8f7 | 592 | struct msi_msg msg; |
38bc0361 | 593 | int pos; |
41017f0c SL |
594 | u16 control; |
595 | ||
0366f8f7 | 596 | pos = entry->msi_attrib.pos; |
41017f0c | 597 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
fd58e55f | 598 | |
41017f0c | 599 | /* Configure MSI capability structure */ |
38bc0361 | 600 | status = msi_ops->setup(dev, dev->irq, &msg); |
fd58e55f MM |
601 | if (status < 0) |
602 | return status; | |
603 | ||
0366f8f7 | 604 | write_msi_msg(entry, &msg); |
41017f0c SL |
605 | if (entry->msi_attrib.maskbit) { |
606 | unsigned int maskbits, temp; | |
607 | /* All MSIs are unmasked by default, Mask them all */ | |
608 | pci_read_config_dword(dev, | |
609 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
610 | &maskbits); | |
611 | temp = (1 << multi_msi_capable(control)); | |
612 | temp = ((temp - 1) & ~temp); | |
613 | maskbits |= temp; | |
614 | pci_write_config_dword(dev, | |
615 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
616 | maskbits); | |
617 | } | |
fd58e55f MM |
618 | |
619 | return 0; | |
41017f0c SL |
620 | } |
621 | ||
1da177e4 LT |
622 | /** |
623 | * msi_capability_init - configure device's MSI capability structure | |
624 | * @dev: pointer to the pci_dev data structure of MSI device function | |
625 | * | |
eaae4b3a | 626 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 627 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 628 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 629 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
630 | **/ |
631 | static int msi_capability_init(struct pci_dev *dev) | |
632 | { | |
fd58e55f | 633 | int status; |
1da177e4 | 634 | struct msi_desc *entry; |
1ce03373 | 635 | int pos, irq; |
1da177e4 | 636 | u16 control; |
1ce03373 | 637 | struct hw_interrupt_type *handler; |
1da177e4 LT |
638 | |
639 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
640 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
641 | /* MSI Entry Initialization */ | |
1ce03373 EB |
642 | handler = &msi_irq_wo_maskbit_type; |
643 | if (is_mask_bit_support(control)) | |
644 | handler = &msi_irq_w_maskbit_type; | |
1da177e4 | 645 | |
1ce03373 EB |
646 | irq = create_msi_irq(handler); |
647 | if (irq < 0) | |
648 | return irq; | |
649 | ||
650 | entry = get_irq_data(irq); | |
651 | entry->link.head = irq; | |
652 | entry->link.tail = irq; | |
1da177e4 | 653 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 654 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
655 | entry->msi_attrib.entry_nr = 0; |
656 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 657 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 658 | entry->msi_attrib.pos = pos; |
1ce03373 | 659 | dev->irq = irq; |
1da177e4 LT |
660 | entry->dev = dev; |
661 | if (is_mask_bit_support(control)) { | |
662 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
663 | is_64bit_address(control)); | |
664 | } | |
1da177e4 | 665 | /* Configure MSI capability structure */ |
fd58e55f MM |
666 | status = msi_register_init(dev, entry); |
667 | if (status != 0) { | |
1ce03373 EB |
668 | dev->irq = entry->msi_attrib.default_irq; |
669 | destroy_msi_irq(irq); | |
fd58e55f MM |
670 | return status; |
671 | } | |
41017f0c | 672 | |
1ce03373 | 673 | attach_msi_entry(entry, irq); |
1da177e4 LT |
674 | /* Set MSI enabled bits */ |
675 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | /** | |
681 | * msix_capability_init - configure device's MSI-X capability | |
682 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
683 | * @entries: pointer to an array of struct msix_entry entries |
684 | * @nvec: number of @entries | |
1da177e4 | 685 | * |
eaae4b3a | 686 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
687 | * single MSI-X irq. A return of zero indicates the successful setup of |
688 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
689 | **/ |
690 | static int msix_capability_init(struct pci_dev *dev, | |
691 | struct msix_entry *entries, int nvec) | |
692 | { | |
693 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
0366f8f7 | 694 | struct msi_msg msg; |
fd58e55f | 695 | int status; |
1ce03373 | 696 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
697 | unsigned long phys_addr; |
698 | u32 table_offset; | |
1da177e4 LT |
699 | u16 control; |
700 | u8 bir; | |
701 | void __iomem *base; | |
702 | ||
703 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
704 | /* Request & Map MSI-X table region */ | |
705 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
706 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
707 | |
708 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 709 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
710 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
711 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
712 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
713 | if (base == NULL) | |
714 | return -ENOMEM; | |
715 | ||
716 | /* MSI-X Table Initialization */ | |
717 | for (i = 0; i < nvec; i++) { | |
1ce03373 EB |
718 | irq = create_msi_irq(&msix_irq_type); |
719 | if (irq < 0) | |
1da177e4 | 720 | break; |
1da177e4 | 721 | |
1ce03373 | 722 | entry = get_irq_data(irq); |
1da177e4 | 723 | j = entries[i].entry; |
1ce03373 | 724 | entries[i].vector = irq; |
1da177e4 | 725 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 726 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
727 | entry->msi_attrib.entry_nr = j; |
728 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 729 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 730 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
731 | entry->dev = dev; |
732 | entry->mask_base = base; | |
733 | if (!head) { | |
1ce03373 EB |
734 | entry->link.head = irq; |
735 | entry->link.tail = irq; | |
1da177e4 LT |
736 | head = entry; |
737 | } else { | |
738 | entry->link.head = temp; | |
739 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
740 | tail->link.tail = irq; |
741 | head->link.head = irq; | |
1da177e4 | 742 | } |
1ce03373 | 743 | temp = irq; |
1da177e4 | 744 | tail = entry; |
1da177e4 | 745 | /* Configure MSI-X capability structure */ |
1ce03373 EB |
746 | status = msi_ops->setup(dev, irq, &msg); |
747 | if (status < 0) { | |
748 | destroy_msi_irq(irq); | |
fd58e55f | 749 | break; |
1ce03373 | 750 | } |
fd58e55f | 751 | |
0366f8f7 | 752 | write_msi_msg(entry, &msg); |
1ce03373 | 753 | attach_msi_entry(entry, irq); |
1da177e4 LT |
754 | } |
755 | if (i != nvec) { | |
92db6d10 | 756 | int avail = i - 1; |
1da177e4 LT |
757 | i--; |
758 | for (; i >= 0; i--) { | |
1ce03373 EB |
759 | irq = (entries + i)->vector; |
760 | msi_free_irq(dev, irq); | |
1da177e4 LT |
761 | (entries + i)->vector = 0; |
762 | } | |
92db6d10 EB |
763 | /* If we had some success report the number of irqs |
764 | * we succeeded in setting up. | |
765 | */ | |
766 | if (avail <= 0) | |
767 | avail = -EBUSY; | |
768 | return avail; | |
1da177e4 LT |
769 | } |
770 | /* Set MSI-X enabled bits */ | |
771 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
24334a12 BG |
776 | /** |
777 | * pci_msi_supported - check whether MSI may be enabled on device | |
778 | * @dev: pointer to the pci_dev data structure of MSI device function | |
779 | * | |
780 | * MSI must be globally enabled and supported by the device and its root | |
781 | * bus. But, the root bus is not easy to find since some architectures | |
782 | * have virtual busses on top of the PCI hierarchy (for instance the | |
783 | * hypertransport bus), while the actual bus where MSI must be supported | |
784 | * is below. So we test the MSI flag on all parent busses and assume | |
785 | * that no quirk will ever set the NO_MSI flag on a non-root bus. | |
786 | **/ | |
787 | static | |
788 | int pci_msi_supported(struct pci_dev * dev) | |
789 | { | |
790 | struct pci_bus *bus; | |
791 | ||
792 | if (!pci_msi_enable || !dev || dev->no_msi) | |
793 | return -EINVAL; | |
794 | ||
795 | /* check MSI flags of all parent busses */ | |
796 | for (bus = dev->bus; bus; bus = bus->parent) | |
797 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
798 | return -EINVAL; | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
1da177e4 LT |
803 | /** |
804 | * pci_enable_msi - configure device's MSI capability structure | |
805 | * @dev: pointer to the pci_dev data structure of MSI device function | |
806 | * | |
807 | * Setup the MSI capability structure of device function with | |
1ce03373 | 808 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
809 | * MSI mode enabled on its hardware device function. A return of zero |
810 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 811 | * irq or non-zero for otherwise. |
1da177e4 LT |
812 | **/ |
813 | int pci_enable_msi(struct pci_dev* dev) | |
814 | { | |
24334a12 | 815 | int pos, temp, status; |
38bc0361 | 816 | u16 control; |
1da177e4 | 817 | |
24334a12 BG |
818 | if (pci_msi_supported(dev) < 0) |
819 | return -EINVAL; | |
6e325a62 | 820 | |
1da177e4 LT |
821 | temp = dev->irq; |
822 | ||
b64c05e7 GG |
823 | status = msi_init(); |
824 | if (status < 0) | |
1da177e4 LT |
825 | return status; |
826 | ||
b64c05e7 GG |
827 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
828 | if (!pos) | |
1da177e4 LT |
829 | return -EINVAL; |
830 | ||
38bc0361 EB |
831 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
832 | if (!is_64bit_address(control) && msi_ops->needs_64bit_address) | |
833 | return -EINVAL; | |
834 | ||
1ce03373 | 835 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI)); |
1da177e4 | 836 | |
1ce03373 | 837 | /* Check whether driver already requested for MSI-X irqs */ |
b64c05e7 | 838 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 | 839 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1da177e4 | 840 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
1ce03373 | 841 | "Device already has MSI-X irq assigned\n", |
1da177e4 LT |
842 | pci_name(dev)); |
843 | dev->irq = temp; | |
844 | return -EINVAL; | |
845 | } | |
846 | status = msi_capability_init(dev); | |
1da177e4 LT |
847 | return status; |
848 | } | |
849 | ||
850 | void pci_disable_msi(struct pci_dev* dev) | |
851 | { | |
852 | struct msi_desc *entry; | |
1ce03373 | 853 | int pos, default_irq; |
1da177e4 LT |
854 | u16 control; |
855 | unsigned long flags; | |
856 | ||
309e57df MW |
857 | if (!pci_msi_enable) |
858 | return; | |
b64c05e7 GG |
859 | if (!dev) |
860 | return; | |
309e57df | 861 | |
b64c05e7 GG |
862 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
863 | if (!pos) | |
1da177e4 LT |
864 | return; |
865 | ||
866 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
867 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
868 | return; | |
869 | ||
7bd007e4 EB |
870 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); |
871 | ||
1da177e4 LT |
872 | spin_lock_irqsave(&msi_lock, flags); |
873 | entry = msi_desc[dev->irq]; | |
874 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
875 | spin_unlock_irqrestore(&msi_lock, flags); | |
876 | return; | |
877 | } | |
1f80025e | 878 | if (irq_has_action(dev->irq)) { |
1da177e4 LT |
879 | spin_unlock_irqrestore(&msi_lock, flags); |
880 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " | |
1ce03373 | 881 | "free_irq() on MSI irq %d\n", |
1da177e4 | 882 | pci_name(dev), dev->irq); |
1f80025e | 883 | BUG_ON(irq_has_action(dev->irq)); |
1da177e4 | 884 | } else { |
1ce03373 | 885 | default_irq = entry->msi_attrib.default_irq; |
1da177e4 | 886 | spin_unlock_irqrestore(&msi_lock, flags); |
1ce03373 | 887 | msi_free_irq(dev, dev->irq); |
7bd007e4 | 888 | |
1ce03373 EB |
889 | /* Restore dev->irq to its default pin-assertion irq */ |
890 | dev->irq = default_irq; | |
1da177e4 LT |
891 | } |
892 | } | |
893 | ||
1ce03373 | 894 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
895 | { |
896 | struct msi_desc *entry; | |
897 | int head, entry_nr, type; | |
898 | void __iomem *base; | |
899 | unsigned long flags; | |
900 | ||
1ce03373 | 901 | msi_ops->teardown(irq); |
fd58e55f | 902 | |
1da177e4 | 903 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 904 | entry = msi_desc[irq]; |
1da177e4 LT |
905 | if (!entry || entry->dev != dev) { |
906 | spin_unlock_irqrestore(&msi_lock, flags); | |
907 | return -EINVAL; | |
908 | } | |
909 | type = entry->msi_attrib.type; | |
910 | entry_nr = entry->msi_attrib.entry_nr; | |
911 | head = entry->link.head; | |
912 | base = entry->mask_base; | |
913 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
914 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
915 | entry->dev = NULL; | |
1ce03373 | 916 | msi_desc[irq] = NULL; |
1da177e4 LT |
917 | spin_unlock_irqrestore(&msi_lock, flags); |
918 | ||
1ce03373 | 919 | destroy_msi_irq(irq); |
1da177e4 LT |
920 | |
921 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
922 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
923 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 924 | |
1ce03373 | 925 | if (head == irq) |
1da177e4 | 926 | iounmap(base); |
1da177e4 LT |
927 | } |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
1da177e4 LT |
932 | /** |
933 | * pci_enable_msix - configure device's MSI-X capability structure | |
934 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 935 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 936 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
937 | * |
938 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 939 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
940 | * MSI-X mode enabled on its hardware device function. A return of zero |
941 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 942 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 943 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 944 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
945 | * its request. |
946 | **/ | |
947 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
948 | { | |
92db6d10 | 949 | int status, pos, nr_entries; |
1da177e4 LT |
950 | int i, j, temp; |
951 | u16 control; | |
1da177e4 | 952 | |
24334a12 | 953 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
954 | return -EINVAL; |
955 | ||
b64c05e7 GG |
956 | status = msi_init(); |
957 | if (status < 0) | |
1da177e4 LT |
958 | return status; |
959 | ||
b64c05e7 GG |
960 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
961 | if (!pos) | |
1da177e4 LT |
962 | return -EINVAL; |
963 | ||
964 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
965 | nr_entries = multi_msix_capable(control); |
966 | if (nvec > nr_entries) | |
967 | return -EINVAL; | |
968 | ||
969 | /* Check for any invalid entries */ | |
970 | for (i = 0; i < nvec; i++) { | |
971 | if (entries[i].entry >= nr_entries) | |
972 | return -EINVAL; /* invalid entry */ | |
973 | for (j = i + 1; j < nvec; j++) { | |
974 | if (entries[i].entry == entries[j].entry) | |
975 | return -EINVAL; /* duplicate entry */ | |
976 | } | |
977 | } | |
978 | temp = dev->irq; | |
1ce03373 | 979 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)); |
7bd007e4 | 980 | |
1ce03373 | 981 | /* Check whether driver already requested for MSI irq */ |
1da177e4 | 982 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && |
1ce03373 | 983 | !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1da177e4 | 984 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 985 | "Device already has an MSI irq assigned\n", |
1da177e4 LT |
986 | pci_name(dev)); |
987 | dev->irq = temp; | |
988 | return -EINVAL; | |
989 | } | |
1da177e4 | 990 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
991 | return status; |
992 | } | |
993 | ||
994 | void pci_disable_msix(struct pci_dev* dev) | |
995 | { | |
996 | int pos, temp; | |
997 | u16 control; | |
998 | ||
309e57df MW |
999 | if (!pci_msi_enable) |
1000 | return; | |
b64c05e7 GG |
1001 | if (!dev) |
1002 | return; | |
1003 | ||
1004 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1005 | if (!pos) | |
1da177e4 LT |
1006 | return; |
1007 | ||
1008 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1009 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
1010 | return; | |
1011 | ||
7bd007e4 EB |
1012 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); |
1013 | ||
1da177e4 | 1014 | temp = dev->irq; |
1ce03373 | 1015 | if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1f80025e | 1016 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
1017 | unsigned long flags; |
1018 | ||
1ce03373 | 1019 | irq = head = dev->irq; |
7bd007e4 | 1020 | dev->irq = temp; /* Restore pin IRQ */ |
1da177e4 | 1021 | while (head != tail) { |
7bd007e4 | 1022 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 1023 | tail = msi_desc[irq]->link.tail; |
7bd007e4 | 1024 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 1025 | if (irq_has_action(irq)) |
1da177e4 | 1026 | warning = 1; |
1ce03373 EB |
1027 | else if (irq != head) /* Release MSI-X irq */ |
1028 | msi_free_irq(dev, irq); | |
1029 | irq = tail; | |
1da177e4 | 1030 | } |
1ce03373 | 1031 | msi_free_irq(dev, irq); |
1da177e4 | 1032 | if (warning) { |
1da177e4 | 1033 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " |
1ce03373 | 1034 | "free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
1035 | pci_name(dev)); |
1036 | BUG_ON(warning > 0); | |
1da177e4 LT |
1037 | } |
1038 | } | |
1039 | } | |
1040 | ||
1041 | /** | |
1ce03373 | 1042 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1043 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1044 | * | |
eaae4b3a | 1045 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1046 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1047 | * allocated for this device function, are reclaimed to unused state, |
1048 | * which may be used later on. | |
1049 | **/ | |
1050 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
1051 | { | |
1f80025e | 1052 | int pos, temp; |
1da177e4 LT |
1053 | unsigned long flags; |
1054 | ||
1055 | if (!pci_msi_enable || !dev) | |
1056 | return; | |
1057 | ||
1058 | temp = dev->irq; /* Save IOAPIC IRQ */ | |
b64c05e7 | 1059 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1ce03373 | 1060 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1f80025e | 1061 | if (irq_has_action(dev->irq)) { |
1da177e4 | 1062 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 1063 | "called without free_irq() on MSI irq %d\n", |
1da177e4 | 1064 | pci_name(dev), dev->irq); |
1f80025e | 1065 | BUG_ON(irq_has_action(dev->irq)); |
1ce03373 EB |
1066 | } else /* Release MSI irq assigned to this device */ |
1067 | msi_free_irq(dev, dev->irq); | |
1da177e4 LT |
1068 | dev->irq = temp; /* Restore IOAPIC IRQ */ |
1069 | } | |
b64c05e7 | 1070 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 EB |
1071 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1072 | int irq, head, tail = 0, warning = 0; | |
1da177e4 LT |
1073 | void __iomem *base = NULL; |
1074 | ||
1ce03373 | 1075 | irq = head = dev->irq; |
1da177e4 LT |
1076 | while (head != tail) { |
1077 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
1078 | tail = msi_desc[irq]->link.tail; |
1079 | base = msi_desc[irq]->mask_base; | |
1da177e4 | 1080 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 1081 | if (irq_has_action(irq)) |
1da177e4 | 1082 | warning = 1; |
1ce03373 EB |
1083 | else if (irq != head) /* Release MSI-X irq */ |
1084 | msi_free_irq(dev, irq); | |
1085 | irq = tail; | |
1da177e4 | 1086 | } |
1ce03373 | 1087 | msi_free_irq(dev, irq); |
1da177e4 | 1088 | if (warning) { |
1da177e4 LT |
1089 | iounmap(base); |
1090 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 1091 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
1092 | pci_name(dev)); |
1093 | BUG_ON(warning > 0); | |
1094 | } | |
1095 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
1096 | } | |
1097 | } | |
1098 | ||
309e57df MW |
1099 | void pci_no_msi(void) |
1100 | { | |
1101 | pci_msi_enable = 0; | |
1102 | } | |
1103 | ||
1da177e4 LT |
1104 | EXPORT_SYMBOL(pci_enable_msi); |
1105 | EXPORT_SYMBOL(pci_disable_msi); | |
1106 | EXPORT_SYMBOL(pci_enable_msix); | |
1107 | EXPORT_SYMBOL(pci_disable_msix); |