Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
43 | list_for_each_entry(entry, &dev->msi_list, list) { | |
44 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 45 | if (ret < 0) |
6a9e7f20 | 46 | return ret; |
b5fbf533 ME |
47 | if (ret > 0) |
48 | return -ENOSPC; | |
6a9e7f20 AB |
49 | } |
50 | ||
51 | return 0; | |
52 | } | |
11df1f05 | 53 | #endif |
6a9e7f20 | 54 | |
11df1f05 ME |
55 | #ifndef arch_teardown_msi_irqs |
56 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
57 | { |
58 | struct msi_desc *entry; | |
59 | ||
60 | list_for_each_entry(entry, &dev->msi_list, list) { | |
61 | if (entry->irq != 0) | |
62 | arch_teardown_msi_irq(entry->irq); | |
63 | } | |
64 | } | |
11df1f05 | 65 | #endif |
6a9e7f20 | 66 | |
5ca5c02f | 67 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 68 | { |
b1cbf4e4 EB |
69 | u16 control; |
70 | ||
b1cbf4e4 EB |
71 | if (pos) { |
72 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
73 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
74 | if (enable) | |
75 | control |= PCI_MSI_FLAGS_ENABLE; | |
76 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
77 | } | |
78 | } | |
79 | ||
5ca5c02f HS |
80 | static void msi_set_enable(struct pci_dev *dev, int enable) |
81 | { | |
82 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
83 | } | |
84 | ||
b1cbf4e4 EB |
85 | static void msix_set_enable(struct pci_dev *dev, int enable) |
86 | { | |
87 | int pos; | |
88 | u16 control; | |
89 | ||
90 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
91 | if (pos) { | |
92 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
93 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
94 | if (enable) | |
95 | control |= PCI_MSIX_FLAGS_ENABLE; | |
96 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
97 | } | |
98 | } | |
99 | ||
bffac3c5 MW |
100 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
101 | { | |
0b49ec37 MW |
102 | /* Don't shift by >= width of type */ |
103 | if (x >= 5) | |
104 | return 0xffffffff; | |
105 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
106 | } |
107 | ||
3145e941 | 108 | static void msix_flush_writes(struct irq_desc *desc) |
988cbb15 MW |
109 | { |
110 | struct msi_desc *entry; | |
111 | ||
3145e941 | 112 | entry = get_irq_desc_msi(desc); |
379f5327 | 113 | BUG_ON(!entry); |
24d27553 | 114 | if (entry->msi_attrib.is_msix) { |
988cbb15 MW |
115 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + |
116 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
117 | readl(entry->mask_base + offset); | |
988cbb15 MW |
118 | } |
119 | } | |
120 | ||
ce6fce42 MW |
121 | /* |
122 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
123 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
124 | * reliably as devices without an INTx disable bit will then generate a | |
125 | * level IRQ which will never be cleared. | |
126 | * | |
127 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
128 | * doesn't support MSI masking. | |
129 | */ | |
3145e941 | 130 | static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) |
1da177e4 LT |
131 | { |
132 | struct msi_desc *entry; | |
133 | ||
3145e941 | 134 | entry = get_irq_desc_msi(desc); |
379f5327 | 135 | BUG_ON(!entry); |
24d27553 | 136 | if (entry->msi_attrib.is_msix) { |
1da177e4 LT |
137 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + |
138 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
139 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 140 | readl(entry->mask_base + offset); |
24d27553 MW |
141 | } else { |
142 | int pos; | |
143 | u32 mask_bits; | |
144 | ||
145 | if (!entry->msi_attrib.maskbit) | |
146 | return 0; | |
147 | ||
148 | pos = (long)entry->mask_base; | |
149 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
150 | mask_bits &= ~mask; | |
151 | mask_bits |= flag & mask; | |
152 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
1da177e4 | 153 | } |
392ee1e6 | 154 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 155 | return 1; |
1da177e4 LT |
156 | } |
157 | ||
3145e941 | 158 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 159 | { |
3145e941 | 160 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
161 | if (entry->msi_attrib.is_msix) { |
162 | void __iomem *base = entry->mask_base + | |
163 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
164 | ||
165 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
166 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
167 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
168 | } else { | |
0366f8f7 EB |
169 | struct pci_dev *dev = entry->dev; |
170 | int pos = entry->msi_attrib.pos; | |
171 | u16 data; | |
172 | ||
173 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
174 | &msg->address_lo); | |
175 | if (entry->msi_attrib.is_64) { | |
176 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
177 | &msg->address_hi); | |
178 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
179 | } else { | |
180 | msg->address_hi = 0; | |
cbf5d9e6 | 181 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
182 | } |
183 | msg->data = data; | |
0366f8f7 EB |
184 | } |
185 | } | |
1da177e4 | 186 | |
3145e941 | 187 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 188 | { |
3145e941 YL |
189 | struct irq_desc *desc = irq_to_desc(irq); |
190 | ||
191 | read_msi_msg_desc(desc, msg); | |
192 | } | |
193 | ||
194 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
195 | { | |
196 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
197 | if (entry->msi_attrib.is_msix) { |
198 | void __iomem *base; | |
199 | base = entry->mask_base + | |
200 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
201 | ||
202 | writel(msg->address_lo, | |
203 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
204 | writel(msg->address_hi, | |
205 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
206 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
207 | } else { | |
0366f8f7 EB |
208 | struct pci_dev *dev = entry->dev; |
209 | int pos = entry->msi_attrib.pos; | |
210 | ||
211 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
212 | msg->address_lo); | |
213 | if (entry->msi_attrib.is_64) { | |
214 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
215 | msg->address_hi); | |
216 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
217 | msg->data); | |
218 | } else { | |
219 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
220 | msg->data); | |
221 | } | |
1da177e4 | 222 | } |
392ee1e6 | 223 | entry->msg = *msg; |
1da177e4 | 224 | } |
0366f8f7 | 225 | |
3145e941 YL |
226 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
227 | { | |
228 | struct irq_desc *desc = irq_to_desc(irq); | |
229 | ||
230 | write_msi_msg_desc(desc, msg); | |
231 | } | |
232 | ||
3b7d1921 | 233 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 234 | { |
3145e941 YL |
235 | struct irq_desc *desc = irq_to_desc(irq); |
236 | ||
237 | msi_set_mask_bits(desc, 1, 1); | |
238 | msix_flush_writes(desc); | |
1da177e4 LT |
239 | } |
240 | ||
3b7d1921 | 241 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 242 | { |
3145e941 YL |
243 | struct irq_desc *desc = irq_to_desc(irq); |
244 | ||
245 | msi_set_mask_bits(desc, 1, 0); | |
246 | msix_flush_writes(desc); | |
1da177e4 LT |
247 | } |
248 | ||
032de8e2 | 249 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 250 | |
379f5327 | 251 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 252 | { |
379f5327 MW |
253 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
254 | if (!desc) | |
1da177e4 LT |
255 | return NULL; |
256 | ||
379f5327 MW |
257 | INIT_LIST_HEAD(&desc->list); |
258 | desc->dev = dev; | |
1da177e4 | 259 | |
379f5327 | 260 | return desc; |
1da177e4 LT |
261 | } |
262 | ||
ba698ad4 DM |
263 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
264 | { | |
265 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
266 | pci_intx(dev, enable); | |
267 | } | |
268 | ||
8fed4b65 | 269 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 270 | { |
392ee1e6 | 271 | int pos; |
41017f0c | 272 | u16 control; |
392ee1e6 | 273 | struct msi_desc *entry; |
41017f0c | 274 | |
b1cbf4e4 EB |
275 | if (!dev->msi_enabled) |
276 | return; | |
277 | ||
392ee1e6 EB |
278 | entry = get_irq_msi(dev->irq); |
279 | pos = entry->msi_attrib.pos; | |
41017f0c | 280 | |
ba698ad4 | 281 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 282 | msi_set_enable(dev, 0); |
392ee1e6 | 283 | write_msi_msg(dev->irq, &entry->msg); |
3145e941 YL |
284 | if (entry->msi_attrib.maskbit) { |
285 | struct irq_desc *desc = irq_to_desc(dev->irq); | |
286 | msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, | |
8e149e09 | 287 | entry->msi_attrib.masked); |
3145e941 | 288 | } |
392ee1e6 EB |
289 | |
290 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
abad2ec9 JB |
291 | control &= ~PCI_MSI_FLAGS_QSIZE; |
292 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 293 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
294 | } |
295 | ||
296 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 297 | { |
41017f0c | 298 | int pos; |
41017f0c | 299 | struct msi_desc *entry; |
392ee1e6 | 300 | u16 control; |
41017f0c | 301 | |
ded86d8d EB |
302 | if (!dev->msix_enabled) |
303 | return; | |
304 | ||
41017f0c | 305 | /* route the table */ |
ba698ad4 | 306 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 307 | msix_set_enable(dev, 0); |
41017f0c | 308 | |
4aa9bc95 | 309 | list_for_each_entry(entry, &dev->msi_list, list) { |
3145e941 | 310 | struct irq_desc *desc = irq_to_desc(entry->irq); |
4aa9bc95 | 311 | write_msi_msg(entry->irq, &entry->msg); |
3145e941 | 312 | msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); |
41017f0c | 313 | } |
41017f0c | 314 | |
314e77b3 ME |
315 | BUG_ON(list_empty(&dev->msi_list)); |
316 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 317 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
318 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
319 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
320 | control |= PCI_MSIX_FLAGS_ENABLE; | |
321 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 322 | } |
8fed4b65 ME |
323 | |
324 | void pci_restore_msi_state(struct pci_dev *dev) | |
325 | { | |
326 | __pci_restore_msi_state(dev); | |
327 | __pci_restore_msix_state(dev); | |
328 | } | |
94688cf2 | 329 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 330 | |
1da177e4 LT |
331 | /** |
332 | * msi_capability_init - configure device's MSI capability structure | |
333 | * @dev: pointer to the pci_dev data structure of MSI device function | |
334 | * | |
eaae4b3a | 335 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 336 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 337 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 338 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
339 | **/ |
340 | static int msi_capability_init(struct pci_dev *dev) | |
341 | { | |
342 | struct msi_desc *entry; | |
7fe3730d | 343 | int pos, ret; |
1da177e4 LT |
344 | u16 control; |
345 | ||
b1cbf4e4 EB |
346 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
347 | ||
1da177e4 LT |
348 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
349 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
350 | /* MSI Entry Initialization */ | |
379f5327 | 351 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
352 | if (!entry) |
353 | return -ENOMEM; | |
1ce03373 | 354 | |
24d27553 | 355 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 356 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
357 | entry->msi_attrib.entry_nr = 0; |
358 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 359 | entry->msi_attrib.masked = 1; |
1ce03373 | 360 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 361 | entry->msi_attrib.pos = pos; |
3b7d1921 | 362 | if (entry->msi_attrib.maskbit) { |
0db29af1 HS |
363 | unsigned int base, maskbits, temp; |
364 | ||
365 | base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); | |
366 | entry->mask_base = (void __iomem *)(long)base; | |
367 | ||
3b7d1921 | 368 | /* All MSIs are unmasked by default, Mask them all */ |
0db29af1 | 369 | pci_read_config_dword(dev, base, &maskbits); |
bffac3c5 | 370 | temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1); |
3b7d1921 | 371 | maskbits |= temp; |
0db29af1 | 372 | pci_write_config_dword(dev, base, maskbits); |
8e149e09 | 373 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 374 | } |
0dd11f9b | 375 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 376 | |
1da177e4 | 377 | /* Configure MSI capability structure */ |
9c831334 | 378 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 379 | if (ret) { |
032de8e2 | 380 | msi_free_irqs(dev); |
7fe3730d | 381 | return ret; |
fd58e55f | 382 | } |
f7feaca7 | 383 | |
1da177e4 | 384 | /* Set MSI enabled bits */ |
ba698ad4 | 385 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
386 | msi_set_enable(dev, 1); |
387 | dev->msi_enabled = 1; | |
1da177e4 | 388 | |
7fe3730d | 389 | dev->irq = entry->irq; |
1da177e4 LT |
390 | return 0; |
391 | } | |
392 | ||
393 | /** | |
394 | * msix_capability_init - configure device's MSI-X capability | |
395 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
396 | * @entries: pointer to an array of struct msix_entry entries |
397 | * @nvec: number of @entries | |
1da177e4 | 398 | * |
eaae4b3a | 399 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
400 | * single MSI-X irq. A return of zero indicates the successful setup of |
401 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
402 | **/ |
403 | static int msix_capability_init(struct pci_dev *dev, | |
404 | struct msix_entry *entries, int nvec) | |
405 | { | |
4aa9bc95 | 406 | struct msi_desc *entry; |
9c831334 | 407 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
408 | unsigned long phys_addr; |
409 | u32 table_offset; | |
1da177e4 LT |
410 | u16 control; |
411 | u8 bir; | |
412 | void __iomem *base; | |
413 | ||
b1cbf4e4 EB |
414 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
415 | ||
1da177e4 LT |
416 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
417 | /* Request & Map MSI-X table region */ | |
418 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
419 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
420 | |
421 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 422 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
423 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
424 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
425 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
426 | if (base == NULL) | |
427 | return -ENOMEM; | |
428 | ||
429 | /* MSI-X Table Initialization */ | |
430 | for (i = 0; i < nvec; i++) { | |
379f5327 | 431 | entry = alloc_msi_entry(dev); |
f7feaca7 | 432 | if (!entry) |
1da177e4 | 433 | break; |
1da177e4 LT |
434 | |
435 | j = entries[i].entry; | |
24d27553 | 436 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 437 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
438 | entry->msi_attrib.entry_nr = j; |
439 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 440 | entry->msi_attrib.masked = 1; |
1ce03373 | 441 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 442 | entry->msi_attrib.pos = pos; |
1da177e4 | 443 | entry->mask_base = base; |
f7feaca7 | 444 | |
0dd11f9b | 445 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 446 | } |
9c831334 ME |
447 | |
448 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
b5fbf533 ME |
449 | if (ret < 0) { |
450 | /* If we had some success report the number of irqs | |
451 | * we succeeded in setting up. */ | |
9c831334 ME |
452 | int avail = 0; |
453 | list_for_each_entry(entry, &dev->msi_list, list) { | |
454 | if (entry->irq != 0) { | |
455 | avail++; | |
9c831334 | 456 | } |
1da177e4 | 457 | } |
9c831334 | 458 | |
b5fbf533 ME |
459 | if (avail != 0) |
460 | ret = avail; | |
461 | } | |
032de8e2 | 462 | |
b5fbf533 ME |
463 | if (ret) { |
464 | msi_free_irqs(dev); | |
465 | return ret; | |
1da177e4 | 466 | } |
9c831334 ME |
467 | |
468 | i = 0; | |
469 | list_for_each_entry(entry, &dev->msi_list, list) { | |
470 | entries[i].vector = entry->irq; | |
471 | set_irq_msi(entry->irq, entry); | |
472 | i++; | |
473 | } | |
1da177e4 | 474 | /* Set MSI-X enabled bits */ |
ba698ad4 | 475 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
476 | msix_set_enable(dev, 1); |
477 | dev->msix_enabled = 1; | |
1da177e4 LT |
478 | |
479 | return 0; | |
480 | } | |
481 | ||
24334a12 | 482 | /** |
17bbc12a | 483 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 484 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 485 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 486 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 487 | * |
0306ebfa | 488 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
489 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
490 | * supported return 0, else return an error code. | |
24334a12 | 491 | **/ |
c9953a73 | 492 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
493 | { |
494 | struct pci_bus *bus; | |
c9953a73 | 495 | int ret; |
24334a12 | 496 | |
0306ebfa | 497 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
498 | if (!pci_msi_enable || !dev || dev->no_msi) |
499 | return -EINVAL; | |
500 | ||
314e77b3 ME |
501 | /* |
502 | * You can't ask to have 0 or less MSIs configured. | |
503 | * a) it's stupid .. | |
504 | * b) the list manipulation code assumes nvec >= 1. | |
505 | */ | |
506 | if (nvec < 1) | |
507 | return -ERANGE; | |
508 | ||
0306ebfa BG |
509 | /* Any bridge which does NOT route MSI transactions from it's |
510 | * secondary bus to it's primary bus must set NO_MSI flag on | |
511 | * the secondary pci_bus. | |
512 | * We expect only arch-specific PCI host bus controller driver | |
513 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
514 | */ | |
24334a12 BG |
515 | for (bus = dev->bus; bus; bus = bus->parent) |
516 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
517 | return -EINVAL; | |
518 | ||
c9953a73 ME |
519 | ret = arch_msi_check_device(dev, nvec, type); |
520 | if (ret) | |
521 | return ret; | |
522 | ||
b1e2303d ME |
523 | if (!pci_find_capability(dev, type)) |
524 | return -EINVAL; | |
525 | ||
24334a12 BG |
526 | return 0; |
527 | } | |
528 | ||
1da177e4 LT |
529 | /** |
530 | * pci_enable_msi - configure device's MSI capability structure | |
531 | * @dev: pointer to the pci_dev data structure of MSI device function | |
532 | * | |
533 | * Setup the MSI capability structure of device function with | |
1ce03373 | 534 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
535 | * MSI mode enabled on its hardware device function. A return of zero |
536 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 537 | * irq or non-zero for otherwise. |
1da177e4 LT |
538 | **/ |
539 | int pci_enable_msi(struct pci_dev* dev) | |
540 | { | |
b1e2303d | 541 | int status; |
1da177e4 | 542 | |
c9953a73 ME |
543 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
544 | if (status) | |
545 | return status; | |
1da177e4 | 546 | |
ded86d8d | 547 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 548 | |
1ce03373 | 549 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 550 | if (dev->msix_enabled) { |
80ccba11 BH |
551 | dev_info(&dev->dev, "can't enable MSI " |
552 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 553 | return -EINVAL; |
1da177e4 LT |
554 | } |
555 | status = msi_capability_init(dev); | |
1da177e4 LT |
556 | return status; |
557 | } | |
4cc086fa | 558 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 559 | |
d52877c7 | 560 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
561 | { |
562 | struct msi_desc *entry; | |
1da177e4 | 563 | |
128bc5fc | 564 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
565 | return; |
566 | ||
b1cbf4e4 | 567 | msi_set_enable(dev, 0); |
ba698ad4 | 568 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 569 | dev->msi_enabled = 0; |
7bd007e4 | 570 | |
314e77b3 ME |
571 | BUG_ON(list_empty(&dev->msi_list)); |
572 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
573 | /* Return the the pci reset with msi irqs unmasked */ |
574 | if (entry->msi_attrib.maskbit) { | |
575 | u32 mask = entry->msi_attrib.maskbits_mask; | |
3145e941 YL |
576 | struct irq_desc *desc = irq_to_desc(dev->irq); |
577 | msi_set_mask_bits(desc, mask, ~mask); | |
8e149e09 | 578 | } |
379f5327 | 579 | if (entry->msi_attrib.is_msix) |
1da177e4 | 580 | return; |
e387b9ee ME |
581 | |
582 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
583 | dev->irq = entry->msi_attrib.default_irq; |
584 | } | |
24d27553 | 585 | |
d52877c7 YL |
586 | void pci_disable_msi(struct pci_dev* dev) |
587 | { | |
588 | struct msi_desc *entry; | |
589 | ||
590 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
591 | return; | |
592 | ||
593 | pci_msi_shutdown(dev); | |
594 | ||
595 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
379f5327 | 596 | if (entry->msi_attrib.is_msix) |
d52877c7 YL |
597 | return; |
598 | ||
599 | msi_free_irqs(dev); | |
1da177e4 | 600 | } |
4cc086fa | 601 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 602 | |
032de8e2 | 603 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 604 | { |
032de8e2 | 605 | struct msi_desc *entry, *tmp; |
7ede9c1f | 606 | |
b3b7cc7b DM |
607 | list_for_each_entry(entry, &dev->msi_list, list) { |
608 | if (entry->irq) | |
609 | BUG_ON(irq_has_action(entry->irq)); | |
610 | } | |
1da177e4 | 611 | |
032de8e2 | 612 | arch_teardown_msi_irqs(dev); |
1da177e4 | 613 | |
032de8e2 | 614 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
24d27553 | 615 | if (entry->msi_attrib.is_msix) { |
032de8e2 ME |
616 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
617 | * PCI_MSIX_ENTRY_SIZE | |
618 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
619 | |
620 | if (list_is_last(&entry->list, &dev->msi_list)) | |
621 | iounmap(entry->mask_base); | |
032de8e2 ME |
622 | } |
623 | list_del(&entry->list); | |
624 | kfree(entry); | |
1da177e4 LT |
625 | } |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
a52e2e35 RW |
630 | /** |
631 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
632 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
633 | */ | |
634 | int pci_msix_table_size(struct pci_dev *dev) | |
635 | { | |
636 | int pos; | |
637 | u16 control; | |
638 | ||
639 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
640 | if (!pos) | |
641 | return 0; | |
642 | ||
643 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
644 | return multi_msix_capable(control); | |
645 | } | |
646 | ||
1da177e4 LT |
647 | /** |
648 | * pci_enable_msix - configure device's MSI-X capability structure | |
649 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 650 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 651 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
652 | * |
653 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 654 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
655 | * MSI-X mode enabled on its hardware device function. A return of zero |
656 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 657 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 658 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 659 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
660 | * its request. |
661 | **/ | |
662 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
663 | { | |
a52e2e35 | 664 | int status, nr_entries; |
ded86d8d | 665 | int i, j; |
1da177e4 | 666 | |
c9953a73 | 667 | if (!entries) |
1da177e4 LT |
668 | return -EINVAL; |
669 | ||
c9953a73 ME |
670 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
671 | if (status) | |
672 | return status; | |
673 | ||
a52e2e35 | 674 | nr_entries = pci_msix_table_size(dev); |
1da177e4 LT |
675 | if (nvec > nr_entries) |
676 | return -EINVAL; | |
677 | ||
678 | /* Check for any invalid entries */ | |
679 | for (i = 0; i < nvec; i++) { | |
680 | if (entries[i].entry >= nr_entries) | |
681 | return -EINVAL; /* invalid entry */ | |
682 | for (j = i + 1; j < nvec; j++) { | |
683 | if (entries[i].entry == entries[j].entry) | |
684 | return -EINVAL; /* duplicate entry */ | |
685 | } | |
686 | } | |
ded86d8d | 687 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 688 | |
1ce03373 | 689 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 690 | if (dev->msi_enabled) { |
80ccba11 BH |
691 | dev_info(&dev->dev, "can't enable MSI-X " |
692 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
693 | return -EINVAL; |
694 | } | |
1da177e4 | 695 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
696 | return status; |
697 | } | |
4cc086fa | 698 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 699 | |
fc4afc7b | 700 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 701 | { |
032de8e2 | 702 | msi_free_irqs(dev); |
fc4afc7b ME |
703 | } |
704 | ||
d52877c7 | 705 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 706 | { |
128bc5fc | 707 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
708 | return; |
709 | ||
b1cbf4e4 | 710 | msix_set_enable(dev, 0); |
ba698ad4 | 711 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 712 | dev->msix_enabled = 0; |
d52877c7 YL |
713 | } |
714 | void pci_disable_msix(struct pci_dev* dev) | |
715 | { | |
716 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
717 | return; | |
718 | ||
719 | pci_msix_shutdown(dev); | |
7bd007e4 | 720 | |
fc4afc7b | 721 | msix_free_all_irqs(dev); |
1da177e4 | 722 | } |
4cc086fa | 723 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
724 | |
725 | /** | |
1ce03373 | 726 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
727 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
728 | * | |
eaae4b3a | 729 | * Being called during hotplug remove, from which the device function |
1ce03373 | 730 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
731 | * allocated for this device function, are reclaimed to unused state, |
732 | * which may be used later on. | |
733 | **/ | |
734 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
735 | { | |
1da177e4 LT |
736 | if (!pci_msi_enable || !dev) |
737 | return; | |
738 | ||
032de8e2 ME |
739 | if (dev->msi_enabled) |
740 | msi_free_irqs(dev); | |
1da177e4 | 741 | |
fc4afc7b ME |
742 | if (dev->msix_enabled) |
743 | msix_free_all_irqs(dev); | |
1da177e4 LT |
744 | } |
745 | ||
309e57df MW |
746 | void pci_no_msi(void) |
747 | { | |
748 | pci_msi_enable = 0; | |
749 | } | |
c9953a73 | 750 | |
07ae95f9 AP |
751 | /** |
752 | * pci_msi_enabled - is MSI enabled? | |
753 | * | |
754 | * Returns true if MSI has not been disabled by the command-line option | |
755 | * pci=nomsi. | |
756 | **/ | |
757 | int pci_msi_enabled(void) | |
d389fec6 | 758 | { |
07ae95f9 | 759 | return pci_msi_enable; |
d389fec6 | 760 | } |
07ae95f9 | 761 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 762 | |
07ae95f9 | 763 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 764 | { |
07ae95f9 | 765 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 766 | } |