Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
3878eaef | 22 | #include <linux/irqdomain.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
38737d82 | 27 | int pci_msi_ignore_mask; |
1da177e4 | 28 | |
527eee29 BH |
29 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
30 | ||
31 | ||
6a9e7f20 AB |
32 | /* Arch hooks */ |
33 | ||
262a2baf YW |
34 | struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev) |
35 | { | |
36 | return NULL; | |
37 | } | |
38 | ||
39 | static struct msi_controller *pci_msi_controller(struct pci_dev *dev) | |
40 | { | |
41 | struct msi_controller *msi_ctrl = dev->bus->msi; | |
42 | ||
43 | if (msi_ctrl) | |
44 | return msi_ctrl; | |
45 | ||
46 | return pcibios_msi_controller(dev); | |
47 | } | |
48 | ||
4287d824 TP |
49 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
50 | { | |
262a2baf | 51 | struct msi_controller *chip = pci_msi_controller(dev); |
0cbdcfcf TR |
52 | int err; |
53 | ||
54 | if (!chip || !chip->setup_irq) | |
55 | return -EINVAL; | |
56 | ||
57 | err = chip->setup_irq(chip, dev, desc); | |
58 | if (err < 0) | |
59 | return err; | |
60 | ||
61 | irq_set_chip_data(desc->irq, chip); | |
62 | ||
63 | return 0; | |
4287d824 TP |
64 | } |
65 | ||
66 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 67 | { |
c2791b80 | 68 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
69 | |
70 | if (!chip || !chip->teardown_irq) | |
71 | return; | |
72 | ||
73 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
74 | } |
75 | ||
4287d824 | 76 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
77 | { |
78 | struct msi_desc *entry; | |
79 | int ret; | |
80 | ||
1c8d7b0a MW |
81 | /* |
82 | * If an architecture wants to support multiple MSI, it needs to | |
83 | * override arch_setup_msi_irqs() | |
84 | */ | |
85 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
86 | return 1; | |
87 | ||
6a9e7f20 AB |
88 | list_for_each_entry(entry, &dev->msi_list, list) { |
89 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 90 | if (ret < 0) |
6a9e7f20 | 91 | return ret; |
b5fbf533 ME |
92 | if (ret > 0) |
93 | return -ENOSPC; | |
6a9e7f20 AB |
94 | } |
95 | ||
96 | return 0; | |
97 | } | |
1525bf0d | 98 | |
4287d824 TP |
99 | /* |
100 | * We have a default implementation available as a separate non-weak | |
101 | * function, as it is used by the Xen x86 PCI code | |
102 | */ | |
1525bf0d | 103 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 104 | { |
63a7b17e | 105 | int i; |
6a9e7f20 AB |
106 | struct msi_desc *entry; |
107 | ||
63a7b17e JL |
108 | list_for_each_entry(entry, &dev->msi_list, list) |
109 | if (entry->irq) | |
110 | for (i = 0; i < entry->nvec_used; i++) | |
111 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
112 | } |
113 | ||
4287d824 TP |
114 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
115 | { | |
116 | return default_teardown_msi_irqs(dev); | |
117 | } | |
76ccc297 | 118 | |
ac8344c4 | 119 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
120 | { |
121 | struct msi_desc *entry; | |
122 | ||
123 | entry = NULL; | |
124 | if (dev->msix_enabled) { | |
125 | list_for_each_entry(entry, &dev->msi_list, list) { | |
126 | if (irq == entry->irq) | |
127 | break; | |
128 | } | |
129 | } else if (dev->msi_enabled) { | |
130 | entry = irq_get_msi_desc(irq); | |
131 | } | |
132 | ||
133 | if (entry) | |
83a18912 | 134 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 135 | } |
4287d824 | 136 | |
ac8344c4 | 137 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 138 | { |
ac8344c4 | 139 | return default_restore_msi_irqs(dev); |
4287d824 | 140 | } |
76ccc297 | 141 | |
e375b561 | 142 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 143 | { |
b1cbf4e4 EB |
144 | u16 control; |
145 | ||
e375b561 | 146 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
147 | control &= ~PCI_MSI_FLAGS_ENABLE; |
148 | if (enable) | |
149 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 150 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
151 | } |
152 | ||
66f0d0c4 | 153 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 154 | { |
66f0d0c4 | 155 | u16 ctrl; |
b1cbf4e4 | 156 | |
66f0d0c4 YW |
157 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
158 | ctrl &= ~clear; | |
159 | ctrl |= set; | |
160 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
161 | } |
162 | ||
bffac3c5 MW |
163 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
164 | { | |
0b49ec37 MW |
165 | /* Don't shift by >= width of type */ |
166 | if (x >= 5) | |
167 | return 0xffffffff; | |
168 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
169 | } |
170 | ||
ce6fce42 MW |
171 | /* |
172 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
173 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
174 | * reliably as devices without an INTx disable bit will then generate a | |
175 | * level IRQ which will never be cleared. | |
ce6fce42 | 176 | */ |
23ed8d57 | 177 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 178 | { |
f2440d9a | 179 | u32 mask_bits = desc->masked; |
1da177e4 | 180 | |
38737d82 | 181 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 182 | return 0; |
f2440d9a MW |
183 | |
184 | mask_bits &= ~mask; | |
185 | mask_bits |= flag; | |
186 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
187 | |
188 | return mask_bits; | |
189 | } | |
190 | ||
191 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
192 | { | |
23ed8d57 | 193 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
194 | } |
195 | ||
196 | /* | |
197 | * This internal function does not flush PCI writes to the device. | |
198 | * All users must ensure that they read from the device before either | |
199 | * assuming that the device state is up to date, or returning out of this | |
200 | * file. This saves a few milliseconds when initialising devices with lots | |
201 | * of MSI-X interrupts. | |
202 | */ | |
23ed8d57 | 203 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
204 | { |
205 | u32 mask_bits = desc->masked; | |
206 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 207 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
38737d82 YW |
208 | |
209 | if (pci_msi_ignore_mask) | |
210 | return 0; | |
211 | ||
8d805286 SY |
212 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
213 | if (flag) | |
214 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 215 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
216 | |
217 | return mask_bits; | |
218 | } | |
219 | ||
220 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
221 | { | |
23ed8d57 | 222 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 223 | } |
24d27553 | 224 | |
1c9db525 | 225 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 226 | { |
1c9db525 | 227 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 228 | |
f2440d9a MW |
229 | if (desc->msi_attrib.is_msix) { |
230 | msix_mask_irq(desc, flag); | |
231 | readl(desc->mask_base); /* Flush write to device */ | |
232 | } else { | |
a281b788 | 233 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 234 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 235 | } |
f2440d9a MW |
236 | } |
237 | ||
23ed8d57 TG |
238 | /** |
239 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
240 | * @data: pointer to irqdata associated to that interrupt | |
241 | */ | |
242 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 243 | { |
1c9db525 | 244 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
245 | } |
246 | ||
23ed8d57 TG |
247 | /** |
248 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
249 | * @data: pointer to irqdata associated to that interrupt | |
250 | */ | |
251 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 252 | { |
1c9db525 | 253 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
254 | } |
255 | ||
ac8344c4 D |
256 | void default_restore_msi_irqs(struct pci_dev *dev) |
257 | { | |
258 | struct msi_desc *entry; | |
259 | ||
3f3cecae | 260 | list_for_each_entry(entry, &dev->msi_list, list) |
ac8344c4 | 261 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
262 | } |
263 | ||
891d4a48 | 264 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 265 | { |
30da5524 BH |
266 | BUG_ON(entry->dev->current_state != PCI_D0); |
267 | ||
268 | if (entry->msi_attrib.is_msix) { | |
269 | void __iomem *base = entry->mask_base + | |
270 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
271 | ||
272 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
273 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
274 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
275 | } else { | |
276 | struct pci_dev *dev = entry->dev; | |
f5322169 | 277 | int pos = dev->msi_cap; |
30da5524 BH |
278 | u16 data; |
279 | ||
9925ad0c BH |
280 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
281 | &msg->address_lo); | |
30da5524 | 282 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
283 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
284 | &msg->address_hi); | |
2f221349 | 285 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
286 | } else { |
287 | msg->address_hi = 0; | |
2f221349 | 288 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
289 | } |
290 | msg->data = data; | |
291 | } | |
292 | } | |
293 | ||
83a18912 | 294 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 295 | { |
fcd097f3 BH |
296 | if (entry->dev->current_state != PCI_D0) { |
297 | /* Don't touch the hardware now */ | |
298 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
299 | void __iomem *base; |
300 | base = entry->mask_base + | |
301 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
302 | ||
2c21fd4b HS |
303 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
304 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
305 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 306 | } else { |
0366f8f7 | 307 | struct pci_dev *dev = entry->dev; |
f5322169 | 308 | int pos = dev->msi_cap; |
1c8d7b0a MW |
309 | u16 msgctl; |
310 | ||
f84ecd28 | 311 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
312 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
313 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 314 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 315 | |
9925ad0c BH |
316 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
317 | msg->address_lo); | |
0366f8f7 | 318 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
319 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
320 | msg->address_hi); | |
2f221349 BH |
321 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
322 | msg->data); | |
0366f8f7 | 323 | } else { |
2f221349 BH |
324 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
325 | msg->data); | |
0366f8f7 | 326 | } |
1da177e4 | 327 | } |
392ee1e6 | 328 | entry->msg = *msg; |
1da177e4 | 329 | } |
0366f8f7 | 330 | |
83a18912 | 331 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 332 | { |
dced35ae | 333 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 334 | |
83a18912 | 335 | __pci_write_msi_msg(entry, msg); |
3145e941 | 336 | } |
83a18912 | 337 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 338 | |
f56e4481 HS |
339 | static void free_msi_irqs(struct pci_dev *dev) |
340 | { | |
341 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
342 | struct attribute **msi_attrs; |
343 | struct device_attribute *dev_attr; | |
63a7b17e | 344 | int i, count = 0; |
f56e4481 | 345 | |
63a7b17e JL |
346 | list_for_each_entry(entry, &dev->msi_list, list) |
347 | if (entry->irq) | |
348 | for (i = 0; i < entry->nvec_used; i++) | |
349 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 HS |
350 | |
351 | arch_teardown_msi_irqs(dev); | |
352 | ||
353 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
354 | if (entry->msi_attrib.is_msix) { | |
355 | if (list_is_last(&entry->list, &dev->msi_list)) | |
356 | iounmap(entry->mask_base); | |
357 | } | |
424eb391 | 358 | |
f56e4481 HS |
359 | list_del(&entry->list); |
360 | kfree(entry); | |
361 | } | |
1c51b50c GKH |
362 | |
363 | if (dev->msi_irq_groups) { | |
364 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
365 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 366 | while (msi_attrs[count]) { |
1c51b50c GKH |
367 | dev_attr = container_of(msi_attrs[count], |
368 | struct device_attribute, attr); | |
369 | kfree(dev_attr->attr.name); | |
370 | kfree(dev_attr); | |
371 | ++count; | |
372 | } | |
373 | kfree(msi_attrs); | |
374 | kfree(dev->msi_irq_groups[0]); | |
375 | kfree(dev->msi_irq_groups); | |
376 | dev->msi_irq_groups = NULL; | |
377 | } | |
f56e4481 | 378 | } |
c54c1879 | 379 | |
379f5327 | 380 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 381 | { |
379f5327 MW |
382 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
383 | if (!desc) | |
1da177e4 LT |
384 | return NULL; |
385 | ||
379f5327 MW |
386 | INIT_LIST_HEAD(&desc->list); |
387 | desc->dev = dev; | |
1da177e4 | 388 | |
379f5327 | 389 | return desc; |
1da177e4 LT |
390 | } |
391 | ||
ba698ad4 DM |
392 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
393 | { | |
394 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
395 | pci_intx(dev, enable); | |
396 | } | |
397 | ||
8fed4b65 | 398 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 399 | { |
41017f0c | 400 | u16 control; |
392ee1e6 | 401 | struct msi_desc *entry; |
41017f0c | 402 | |
b1cbf4e4 EB |
403 | if (!dev->msi_enabled) |
404 | return; | |
405 | ||
dced35ae | 406 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 407 | |
ba698ad4 | 408 | pci_intx_for_msi(dev, 0); |
e375b561 | 409 | msi_set_enable(dev, 0); |
ac8344c4 | 410 | arch_restore_msi_irqs(dev); |
392ee1e6 | 411 | |
f5322169 | 412 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
413 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
414 | entry->masked); | |
abad2ec9 | 415 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 416 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 417 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
418 | } |
419 | ||
420 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 421 | { |
41017f0c | 422 | struct msi_desc *entry; |
41017f0c | 423 | |
ded86d8d EB |
424 | if (!dev->msix_enabled) |
425 | return; | |
f598282f | 426 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 427 | |
41017f0c | 428 | /* route the table */ |
ba698ad4 | 429 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
430 | msix_clear_and_set_ctrl(dev, 0, |
431 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 432 | |
ac8344c4 | 433 | arch_restore_msi_irqs(dev); |
3f3cecae | 434 | list_for_each_entry(entry, &dev->msi_list, list) |
f2440d9a | 435 | msix_mask_irq(entry, entry->masked); |
41017f0c | 436 | |
66f0d0c4 | 437 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 438 | } |
8fed4b65 ME |
439 | |
440 | void pci_restore_msi_state(struct pci_dev *dev) | |
441 | { | |
442 | __pci_restore_msi_state(dev); | |
443 | __pci_restore_msix_state(dev); | |
444 | } | |
94688cf2 | 445 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 446 | |
1c51b50c | 447 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
448 | char *buf) |
449 | { | |
1c51b50c GKH |
450 | struct msi_desc *entry; |
451 | unsigned long irq; | |
452 | int retval; | |
da8d1c8b | 453 | |
1c51b50c GKH |
454 | retval = kstrtoul(attr->attr.name, 10, &irq); |
455 | if (retval) | |
456 | return retval; | |
da8d1c8b | 457 | |
e11ece5a YW |
458 | entry = irq_get_msi_desc(irq); |
459 | if (entry) | |
460 | return sprintf(buf, "%s\n", | |
461 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
462 | ||
1c51b50c | 463 | return -ENODEV; |
da8d1c8b NH |
464 | } |
465 | ||
da8d1c8b NH |
466 | static int populate_msi_sysfs(struct pci_dev *pdev) |
467 | { | |
1c51b50c GKH |
468 | struct attribute **msi_attrs; |
469 | struct attribute *msi_attr; | |
470 | struct device_attribute *msi_dev_attr; | |
471 | struct attribute_group *msi_irq_group; | |
472 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 473 | struct msi_desc *entry; |
1c51b50c GKH |
474 | int ret = -ENOMEM; |
475 | int num_msi = 0; | |
da8d1c8b NH |
476 | int count = 0; |
477 | ||
1c51b50c | 478 | /* Determine how many msi entries we have */ |
3f3cecae | 479 | list_for_each_entry(entry, &pdev->msi_list, list) |
1c51b50c | 480 | ++num_msi; |
1c51b50c GKH |
481 | if (!num_msi) |
482 | return 0; | |
da8d1c8b | 483 | |
1c51b50c GKH |
484 | /* Dynamically create the MSI attributes for the PCI device */ |
485 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
486 | if (!msi_attrs) | |
487 | return -ENOMEM; | |
da8d1c8b | 488 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 489 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 490 | if (!msi_dev_attr) |
1c51b50c | 491 | goto error_attrs; |
1406276c | 492 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 493 | |
1c51b50c | 494 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
495 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
496 | entry->irq); | |
497 | if (!msi_dev_attr->attr.name) | |
498 | goto error_attrs; | |
1c51b50c GKH |
499 | msi_dev_attr->attr.mode = S_IRUGO; |
500 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 501 | ++count; |
da8d1c8b NH |
502 | } |
503 | ||
1c51b50c GKH |
504 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
505 | if (!msi_irq_group) | |
506 | goto error_attrs; | |
507 | msi_irq_group->name = "msi_irqs"; | |
508 | msi_irq_group->attrs = msi_attrs; | |
509 | ||
510 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
511 | if (!msi_irq_groups) | |
512 | goto error_irq_group; | |
513 | msi_irq_groups[0] = msi_irq_group; | |
514 | ||
515 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
516 | if (ret) | |
517 | goto error_irq_groups; | |
518 | pdev->msi_irq_groups = msi_irq_groups; | |
519 | ||
da8d1c8b NH |
520 | return 0; |
521 | ||
1c51b50c GKH |
522 | error_irq_groups: |
523 | kfree(msi_irq_groups); | |
524 | error_irq_group: | |
525 | kfree(msi_irq_group); | |
526 | error_attrs: | |
527 | count = 0; | |
528 | msi_attr = msi_attrs[count]; | |
529 | while (msi_attr) { | |
530 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
531 | kfree(msi_attr->name); | |
532 | kfree(msi_dev_attr); | |
533 | ++count; | |
534 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 535 | } |
29237756 | 536 | kfree(msi_attrs); |
da8d1c8b NH |
537 | return ret; |
538 | } | |
539 | ||
63a7b17e | 540 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
d873b4d4 YW |
541 | { |
542 | u16 control; | |
543 | struct msi_desc *entry; | |
544 | ||
545 | /* MSI Entry Initialization */ | |
546 | entry = alloc_msi_entry(dev); | |
547 | if (!entry) | |
548 | return NULL; | |
549 | ||
550 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
551 | ||
552 | entry->msi_attrib.is_msix = 0; | |
553 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
554 | entry->msi_attrib.entry_nr = 0; | |
555 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
556 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 557 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e JL |
558 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
559 | entry->nvec_used = nvec; | |
d873b4d4 YW |
560 | |
561 | if (control & PCI_MSI_FLAGS_64BIT) | |
562 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
563 | else | |
564 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
565 | ||
566 | /* Save the initial mask status */ | |
567 | if (entry->msi_attrib.maskbit) | |
568 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
569 | ||
570 | return entry; | |
571 | } | |
572 | ||
1da177e4 LT |
573 | /** |
574 | * msi_capability_init - configure device's MSI capability structure | |
575 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 576 | * @nvec: number of interrupts to allocate |
1da177e4 | 577 | * |
1c8d7b0a MW |
578 | * Setup the MSI capability structure of the device with the requested |
579 | * number of interrupts. A return value of zero indicates the successful | |
580 | * setup of an entry with the new MSI irq. A negative return value indicates | |
581 | * an error, and a positive return value indicates the number of interrupts | |
582 | * which could have been allocated. | |
583 | */ | |
584 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
585 | { |
586 | struct msi_desc *entry; | |
f465136d | 587 | int ret; |
f2440d9a | 588 | unsigned mask; |
1da177e4 | 589 | |
e375b561 | 590 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 591 | |
63a7b17e | 592 | entry = msi_setup_entry(dev, nvec); |
f7feaca7 EB |
593 | if (!entry) |
594 | return -ENOMEM; | |
1ce03373 | 595 | |
f2440d9a | 596 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 597 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
598 | msi_mask_irq(entry, mask, mask); |
599 | ||
0dd11f9b | 600 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 601 | |
1da177e4 | 602 | /* Configure MSI capability structure */ |
1c8d7b0a | 603 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 604 | if (ret) { |
7ba1930d | 605 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 606 | free_msi_irqs(dev); |
7fe3730d | 607 | return ret; |
fd58e55f | 608 | } |
f7feaca7 | 609 | |
da8d1c8b NH |
610 | ret = populate_msi_sysfs(dev); |
611 | if (ret) { | |
612 | msi_mask_irq(entry, mask, ~mask); | |
613 | free_msi_irqs(dev); | |
614 | return ret; | |
615 | } | |
616 | ||
1da177e4 | 617 | /* Set MSI enabled bits */ |
ba698ad4 | 618 | pci_intx_for_msi(dev, 0); |
e375b561 | 619 | msi_set_enable(dev, 1); |
b1cbf4e4 | 620 | dev->msi_enabled = 1; |
1da177e4 | 621 | |
7fe3730d | 622 | dev->irq = entry->irq; |
1da177e4 LT |
623 | return 0; |
624 | } | |
625 | ||
520fe9dc | 626 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 627 | { |
4302e0fb | 628 | resource_size_t phys_addr; |
5a05a9d8 HS |
629 | u32 table_offset; |
630 | u8 bir; | |
631 | ||
909094c6 BH |
632 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
633 | &table_offset); | |
4d18760c BH |
634 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
635 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
636 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
637 | ||
638 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
639 | } | |
640 | ||
520fe9dc GS |
641 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
642 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
643 | { |
644 | struct msi_desc *entry; | |
645 | int i; | |
646 | ||
647 | for (i = 0; i < nvec; i++) { | |
648 | entry = alloc_msi_entry(dev); | |
649 | if (!entry) { | |
650 | if (!i) | |
651 | iounmap(base); | |
652 | else | |
653 | free_msi_irqs(dev); | |
654 | /* No enough memory. Don't try again */ | |
655 | return -ENOMEM; | |
656 | } | |
657 | ||
658 | entry->msi_attrib.is_msix = 1; | |
659 | entry->msi_attrib.is_64 = 1; | |
660 | entry->msi_attrib.entry_nr = entries[i].entry; | |
661 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e | 662 | entry->mask_base = base; |
63a7b17e | 663 | entry->nvec_used = 1; |
d9d7070e HS |
664 | |
665 | list_add_tail(&entry->list, &dev->msi_list); | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
75cb3426 | 671 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 672 | struct msix_entry *entries) |
75cb3426 HS |
673 | { |
674 | struct msi_desc *entry; | |
675 | int i = 0; | |
676 | ||
677 | list_for_each_entry(entry, &dev->msi_list, list) { | |
678 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
679 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
680 | ||
681 | entries[i].vector = entry->irq; | |
75cb3426 HS |
682 | entry->masked = readl(entry->mask_base + offset); |
683 | msix_mask_irq(entry, 1); | |
684 | i++; | |
685 | } | |
686 | } | |
687 | ||
1da177e4 LT |
688 | /** |
689 | * msix_capability_init - configure device's MSI-X capability | |
690 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
691 | * @entries: pointer to an array of struct msix_entry entries |
692 | * @nvec: number of @entries | |
1da177e4 | 693 | * |
eaae4b3a | 694 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
695 | * single MSI-X irq. A return of zero indicates the successful setup of |
696 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
697 | **/ |
698 | static int msix_capability_init(struct pci_dev *dev, | |
699 | struct msix_entry *entries, int nvec) | |
700 | { | |
520fe9dc | 701 | int ret; |
5a05a9d8 | 702 | u16 control; |
1da177e4 LT |
703 | void __iomem *base; |
704 | ||
f598282f | 705 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 706 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 707 | |
66f0d0c4 | 708 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 709 | /* Request & Map MSI-X table region */ |
527eee29 | 710 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 711 | if (!base) |
1da177e4 LT |
712 | return -ENOMEM; |
713 | ||
520fe9dc | 714 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
715 | if (ret) |
716 | return ret; | |
9c831334 ME |
717 | |
718 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 719 | if (ret) |
2adc7907 | 720 | goto out_avail; |
9c831334 | 721 | |
f598282f MW |
722 | /* |
723 | * Some devices require MSI-X to be enabled before we can touch the | |
724 | * MSI-X registers. We need to mask all the vectors to prevent | |
725 | * interrupts coming in before they're fully set up. | |
726 | */ | |
66f0d0c4 YW |
727 | msix_clear_and_set_ctrl(dev, 0, |
728 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 729 | |
75cb3426 | 730 | msix_program_entries(dev, entries); |
f598282f | 731 | |
da8d1c8b | 732 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
733 | if (ret) |
734 | goto out_free; | |
da8d1c8b | 735 | |
f598282f | 736 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 737 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 738 | dev->msix_enabled = 1; |
1da177e4 | 739 | |
66f0d0c4 | 740 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 741 | |
1da177e4 | 742 | return 0; |
583871d4 | 743 | |
2adc7907 | 744 | out_avail: |
583871d4 HS |
745 | if (ret < 0) { |
746 | /* | |
747 | * If we had some success, report the number of irqs | |
748 | * we succeeded in setting up. | |
749 | */ | |
d9d7070e | 750 | struct msi_desc *entry; |
583871d4 HS |
751 | int avail = 0; |
752 | ||
753 | list_for_each_entry(entry, &dev->msi_list, list) { | |
754 | if (entry->irq != 0) | |
755 | avail++; | |
756 | } | |
757 | if (avail != 0) | |
758 | ret = avail; | |
759 | } | |
760 | ||
2adc7907 | 761 | out_free: |
583871d4 HS |
762 | free_msi_irqs(dev); |
763 | ||
764 | return ret; | |
1da177e4 LT |
765 | } |
766 | ||
24334a12 | 767 | /** |
a06cd74c | 768 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 769 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 770 | * @nvec: how many MSIs have been requested ? |
24334a12 | 771 | * |
f7625980 | 772 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 773 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 774 | * supported return 1, else return 0. |
24334a12 | 775 | **/ |
a06cd74c | 776 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
777 | { |
778 | struct pci_bus *bus; | |
779 | ||
0306ebfa | 780 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 781 | if (!pci_msi_enable) |
a06cd74c | 782 | return 0; |
27e20603 AG |
783 | |
784 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 785 | return 0; |
24334a12 | 786 | |
314e77b3 ME |
787 | /* |
788 | * You can't ask to have 0 or less MSIs configured. | |
789 | * a) it's stupid .. | |
790 | * b) the list manipulation code assumes nvec >= 1. | |
791 | */ | |
792 | if (nvec < 1) | |
a06cd74c | 793 | return 0; |
314e77b3 | 794 | |
500559a9 HS |
795 | /* |
796 | * Any bridge which does NOT route MSI transactions from its | |
797 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
798 | * the secondary pci_bus. |
799 | * We expect only arch-specific PCI host bus controller driver | |
800 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
801 | */ | |
24334a12 BG |
802 | for (bus = dev->bus; bus; bus = bus->parent) |
803 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 804 | return 0; |
24334a12 | 805 | |
a06cd74c | 806 | return 1; |
24334a12 BG |
807 | } |
808 | ||
d1ac1d26 AG |
809 | /** |
810 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
811 | * @dev: device to report about | |
812 | * | |
813 | * This function returns the number of MSI vectors a device requested via | |
814 | * Multiple Message Capable register. It returns a negative errno if the | |
815 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
816 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
817 | * MSI specification. | |
818 | **/ | |
819 | int pci_msi_vec_count(struct pci_dev *dev) | |
820 | { | |
821 | int ret; | |
822 | u16 msgctl; | |
823 | ||
824 | if (!dev->msi_cap) | |
825 | return -EINVAL; | |
826 | ||
827 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
828 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
829 | ||
830 | return ret; | |
831 | } | |
832 | EXPORT_SYMBOL(pci_msi_vec_count); | |
833 | ||
f2440d9a | 834 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 835 | { |
f2440d9a MW |
836 | struct msi_desc *desc; |
837 | u32 mask; | |
1da177e4 | 838 | |
128bc5fc | 839 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
840 | return; |
841 | ||
110828c9 MW |
842 | BUG_ON(list_empty(&dev->msi_list)); |
843 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 844 | |
e375b561 | 845 | msi_set_enable(dev, 0); |
ba698ad4 | 846 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 847 | dev->msi_enabled = 0; |
7bd007e4 | 848 | |
12abb8ba | 849 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 850 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 851 | /* Keep cached state to be restored */ |
23ed8d57 | 852 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
853 | |
854 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 855 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 856 | } |
24d27553 | 857 | |
500559a9 | 858 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 859 | { |
d52877c7 YL |
860 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
861 | return; | |
862 | ||
863 | pci_msi_shutdown(dev); | |
f56e4481 | 864 | free_msi_irqs(dev); |
1da177e4 | 865 | } |
4cc086fa | 866 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 867 | |
a52e2e35 | 868 | /** |
ff1aa430 | 869 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 870 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
871 | * This function returns the number of device's MSI-X table entries and |
872 | * therefore the number of MSI-X vectors device is capable of sending. | |
873 | * It returns a negative errno if the device is not capable of sending MSI-X | |
874 | * interrupts. | |
875 | **/ | |
876 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 877 | { |
a52e2e35 RW |
878 | u16 control; |
879 | ||
520fe9dc | 880 | if (!dev->msix_cap) |
ff1aa430 | 881 | return -EINVAL; |
a52e2e35 | 882 | |
f84ecd28 | 883 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 884 | return msix_table_size(control); |
a52e2e35 | 885 | } |
ff1aa430 | 886 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 887 | |
1da177e4 LT |
888 | /** |
889 | * pci_enable_msix - configure device's MSI-X capability structure | |
890 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 891 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 892 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
893 | * |
894 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 895 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
896 | * MSI-X mode enabled on its hardware device function. A return of zero |
897 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 898 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 899 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
900 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
901 | * re-send its request. | |
1da177e4 | 902 | **/ |
500559a9 | 903 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 904 | { |
5ec09405 | 905 | int nr_entries; |
ded86d8d | 906 | int i, j; |
1da177e4 | 907 | |
a06cd74c AG |
908 | if (!pci_msi_supported(dev, nvec)) |
909 | return -EINVAL; | |
c9953a73 | 910 | |
27e20603 AG |
911 | if (!entries) |
912 | return -EINVAL; | |
913 | ||
ff1aa430 AG |
914 | nr_entries = pci_msix_vec_count(dev); |
915 | if (nr_entries < 0) | |
916 | return nr_entries; | |
1da177e4 | 917 | if (nvec > nr_entries) |
57fbf52c | 918 | return nr_entries; |
1da177e4 LT |
919 | |
920 | /* Check for any invalid entries */ | |
921 | for (i = 0; i < nvec; i++) { | |
922 | if (entries[i].entry >= nr_entries) | |
923 | return -EINVAL; /* invalid entry */ | |
924 | for (j = i + 1; j < nvec; j++) { | |
925 | if (entries[i].entry == entries[j].entry) | |
926 | return -EINVAL; /* duplicate entry */ | |
927 | } | |
928 | } | |
ded86d8d | 929 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 930 | |
1ce03373 | 931 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 932 | if (dev->msi_enabled) { |
227f0647 | 933 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
934 | return -EINVAL; |
935 | } | |
5ec09405 | 936 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 937 | } |
4cc086fa | 938 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 939 | |
500559a9 | 940 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 941 | { |
12abb8ba HS |
942 | struct msi_desc *entry; |
943 | ||
128bc5fc | 944 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
945 | return; |
946 | ||
12abb8ba HS |
947 | /* Return the device with MSI-X masked as initial states */ |
948 | list_for_each_entry(entry, &dev->msi_list, list) { | |
949 | /* Keep cached states to be restored */ | |
23ed8d57 | 950 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
951 | } |
952 | ||
66f0d0c4 | 953 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 954 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 955 | dev->msix_enabled = 0; |
d52877c7 | 956 | } |
c901851f | 957 | |
500559a9 | 958 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
959 | { |
960 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
961 | return; | |
962 | ||
963 | pci_msix_shutdown(dev); | |
f56e4481 | 964 | free_msi_irqs(dev); |
1da177e4 | 965 | } |
4cc086fa | 966 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 967 | |
309e57df MW |
968 | void pci_no_msi(void) |
969 | { | |
970 | pci_msi_enable = 0; | |
971 | } | |
c9953a73 | 972 | |
07ae95f9 AP |
973 | /** |
974 | * pci_msi_enabled - is MSI enabled? | |
975 | * | |
976 | * Returns true if MSI has not been disabled by the command-line option | |
977 | * pci=nomsi. | |
978 | **/ | |
979 | int pci_msi_enabled(void) | |
d389fec6 | 980 | { |
07ae95f9 | 981 | return pci_msi_enable; |
d389fec6 | 982 | } |
07ae95f9 | 983 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 984 | |
07ae95f9 | 985 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 986 | { |
07ae95f9 | 987 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
988 | |
989 | /* Disable the msi hardware to avoid screaming interrupts | |
990 | * during boot. This is the power on reset default so | |
991 | * usually this should be a noop. | |
992 | */ | |
e375b561 GS |
993 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
994 | if (dev->msi_cap) | |
995 | msi_set_enable(dev, 0); | |
996 | ||
997 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
998 | if (dev->msix_cap) | |
66f0d0c4 | 999 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1000 | } |
302a2523 AG |
1001 | |
1002 | /** | |
1003 | * pci_enable_msi_range - configure device's MSI capability structure | |
1004 | * @dev: device to configure | |
1005 | * @minvec: minimal number of interrupts to configure | |
1006 | * @maxvec: maximum number of interrupts to configure | |
1007 | * | |
1008 | * This function tries to allocate a maximum possible number of interrupts in a | |
1009 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1010 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1011 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1012 | * the other interrupt numbers allocated to this device are consecutive. | |
1013 | **/ | |
1014 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1015 | { | |
034cd97e | 1016 | int nvec; |
302a2523 AG |
1017 | int rc; |
1018 | ||
a06cd74c AG |
1019 | if (!pci_msi_supported(dev, minvec)) |
1020 | return -EINVAL; | |
034cd97e AG |
1021 | |
1022 | WARN_ON(!!dev->msi_enabled); | |
1023 | ||
1024 | /* Check whether driver already requested MSI-X irqs */ | |
1025 | if (dev->msix_enabled) { | |
1026 | dev_info(&dev->dev, | |
1027 | "can't enable MSI (MSI-X already enabled)\n"); | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | ||
302a2523 AG |
1031 | if (maxvec < minvec) |
1032 | return -ERANGE; | |
1033 | ||
034cd97e AG |
1034 | nvec = pci_msi_vec_count(dev); |
1035 | if (nvec < 0) | |
1036 | return nvec; | |
1037 | else if (nvec < minvec) | |
1038 | return -EINVAL; | |
1039 | else if (nvec > maxvec) | |
1040 | nvec = maxvec; | |
1041 | ||
302a2523 | 1042 | do { |
034cd97e | 1043 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1044 | if (rc < 0) { |
1045 | return rc; | |
1046 | } else if (rc > 0) { | |
1047 | if (rc < minvec) | |
1048 | return -ENOSPC; | |
1049 | nvec = rc; | |
1050 | } | |
1051 | } while (rc); | |
1052 | ||
1053 | return nvec; | |
1054 | } | |
1055 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1056 | ||
1057 | /** | |
1058 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1059 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1060 | * @entries: pointer to an array of MSI-X entries | |
1061 | * @minvec: minimum number of MSI-X irqs requested | |
1062 | * @maxvec: maximum number of MSI-X irqs requested | |
1063 | * | |
1064 | * Setup the MSI-X capability structure of device function with a maximum | |
1065 | * possible number of interrupts in the range between @minvec and @maxvec | |
1066 | * upon its software driver call to request for MSI-X mode enabled on its | |
1067 | * hardware device function. It returns a negative errno if an error occurs. | |
1068 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1069 | * indicates the successful configuration of MSI-X capability structure | |
1070 | * with new allocated MSI-X interrupts. | |
1071 | **/ | |
1072 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1073 | int minvec, int maxvec) | |
1074 | { | |
1075 | int nvec = maxvec; | |
1076 | int rc; | |
1077 | ||
1078 | if (maxvec < minvec) | |
1079 | return -ERANGE; | |
1080 | ||
1081 | do { | |
1082 | rc = pci_enable_msix(dev, entries, nvec); | |
1083 | if (rc < 0) { | |
1084 | return rc; | |
1085 | } else if (rc > 0) { | |
1086 | if (rc < minvec) | |
1087 | return -ENOSPC; | |
1088 | nvec = rc; | |
1089 | } | |
1090 | } while (rc); | |
1091 | ||
1092 | return nvec; | |
1093 | } | |
1094 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef JL |
1095 | |
1096 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN | |
1097 | /** | |
1098 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1099 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1100 | * @msg: Pointer to the message | |
1101 | */ | |
1102 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1103 | { | |
1104 | struct msi_desc *desc = irq_data->msi_desc; | |
1105 | ||
1106 | /* | |
1107 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1108 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1109 | */ | |
1110 | if (desc->irq == irq_data->irq) | |
1111 | __pci_write_msi_msg(desc, msg); | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1116 | * @dev: Pointer to the PCI device | |
1117 | * @desc: Pointer to the msi descriptor | |
1118 | * | |
1119 | * The ID number is only used within the irqdomain. | |
1120 | */ | |
1121 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1122 | struct msi_desc *desc) | |
1123 | { | |
1124 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1125 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1126 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1127 | } | |
1128 | ||
1129 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1130 | { | |
1131 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1132 | } | |
1133 | ||
1134 | /** | |
1135 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1136 | * @domain: The interrupt domain to check | |
1137 | * @info: The domain info for verification | |
1138 | * @dev: The device to check | |
1139 | * | |
1140 | * Returns: | |
1141 | * 0 if the functionality is supported | |
1142 | * 1 if Multi MSI is requested, but the domain does not support it | |
1143 | * -ENOTSUPP otherwise | |
1144 | */ | |
1145 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1146 | struct msi_domain_info *info, struct device *dev) | |
1147 | { | |
1148 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1149 | ||
1150 | /* Special handling to support pci_enable_msi_range() */ | |
1151 | if (pci_msi_desc_is_multi_msi(desc) && | |
1152 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1153 | return 1; | |
1154 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1155 | return -ENOTSUPP; | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1161 | struct msi_desc *desc, int error) | |
1162 | { | |
1163 | /* Special handling to support pci_enable_msi_range() */ | |
1164 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1165 | return 1; | |
1166 | ||
1167 | return error; | |
1168 | } | |
1169 | ||
1170 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1171 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1172 | struct msi_desc *desc) | |
1173 | { | |
1174 | arg->desc = desc; | |
1175 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1176 | desc); | |
1177 | } | |
1178 | #else | |
1179 | #define pci_msi_domain_set_desc NULL | |
1180 | #endif | |
1181 | ||
1182 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1183 | .set_desc = pci_msi_domain_set_desc, | |
1184 | .msi_check = pci_msi_domain_check_cap, | |
1185 | .handle_error = pci_msi_domain_handle_error, | |
1186 | }; | |
1187 | ||
1188 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1189 | { | |
1190 | struct msi_domain_ops *ops = info->ops; | |
1191 | ||
1192 | if (ops == NULL) { | |
1193 | info->ops = &pci_msi_domain_ops_default; | |
1194 | } else { | |
1195 | if (ops->set_desc == NULL) | |
1196 | ops->set_desc = pci_msi_domain_set_desc; | |
1197 | if (ops->msi_check == NULL) | |
1198 | ops->msi_check = pci_msi_domain_check_cap; | |
1199 | if (ops->handle_error == NULL) | |
1200 | ops->handle_error = pci_msi_domain_handle_error; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1205 | { | |
1206 | struct irq_chip *chip = info->chip; | |
1207 | ||
1208 | BUG_ON(!chip); | |
1209 | if (!chip->irq_write_msi_msg) | |
1210 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
1211 | } | |
1212 | ||
1213 | /** | |
1214 | * pci_msi_create_irq_domain - Creat a MSI interrupt domain | |
1215 | * @node: Optional device-tree node of the interrupt controller | |
1216 | * @info: MSI domain info | |
1217 | * @parent: Parent irq domain | |
1218 | * | |
1219 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1220 | * | |
1221 | * Returns: | |
1222 | * A domain pointer or NULL in case of failure. | |
1223 | */ | |
1224 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, | |
1225 | struct msi_domain_info *info, | |
1226 | struct irq_domain *parent) | |
1227 | { | |
1228 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) | |
1229 | pci_msi_domain_update_dom_ops(info); | |
1230 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1231 | pci_msi_domain_update_chip_ops(info); | |
1232 | ||
1233 | return msi_create_irq_domain(node, info, parent); | |
1234 | } | |
1235 | ||
1236 | /** | |
1237 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1238 | * @domain: The interrupt domain to allocate from | |
1239 | * @dev: The device for which to allocate | |
1240 | * @nvec: The number of interrupts to allocate | |
1241 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1242 | * | |
1243 | * Returns: | |
1244 | * A virtual interrupt number or an error code in case of failure | |
1245 | */ | |
1246 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1247 | int nvec, int type) | |
1248 | { | |
1249 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1250 | } | |
1251 | ||
1252 | /** | |
1253 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1254 | * @domain: The interrupt domain | |
1255 | * @dev: The device for which to free interrupts | |
1256 | */ | |
1257 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1258 | { | |
1259 | msi_domain_free_irqs(domain, &dev->dev); | |
1260 | } | |
1261 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |