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[PATCH] PCI: drivers/pci/: small cleanups
[deliverable/linux.git] / drivers / pci / msi.c
CommitLineData
1da177e4
LT		 1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9#include <linux/mm.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/init.h>
13#include <linux/config.h>
14#include <linux/ioport.h>
15#include <linux/smp_lock.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18
19#include <asm/errno.h>
20#include <asm/io.h>
21#include <asm/smp.h>
22
23#include "pci.h"
24#include "msi.h"
25
26static DEFINE_SPINLOCK(msi_lock);
27static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
28static kmem_cache_t* msi_cachep;
29
30static int pci_msi_enable = 1;
70549ad9
GKH		 31static int last_alloc_vector;
32static int nr_released_vectors;
1da177e4 33static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
70549ad9 34static int nr_msix_devices;
1da177e4
LT		 35
36#ifndef CONFIG_X86_IO_APIC
37int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
38u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
39#endif
40
41static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
42{
43 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
44}
45
46static int msi_cache_init(void)
47{
48 msi_cachep = kmem_cache_create("msi_cache",
49 NR_IRQS * sizeof(struct msi_desc),
50 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
51 if (!msi_cachep)
52 return -ENOMEM;
53
54 return 0;
55}
56
57static void msi_set_mask_bit(unsigned int vector, int flag)
58{
59 struct msi_desc *entry;
60
61 entry = (struct msi_desc *)msi_desc[vector];
62 if (!entry || !entry->dev || !entry->mask_base)
63 return;
64 switch (entry->msi_attrib.type) {
65 case PCI_CAP_ID_MSI:
66 {
67 int pos;
68 u32 mask_bits;
69
70 pos = (long)entry->mask_base;
71 pci_read_config_dword(entry->dev, pos, &mask_bits);
72 mask_bits &= ~(1);
73 mask_bits |= flag;
74 pci_write_config_dword(entry->dev, pos, mask_bits);
75 break;
76 }
77 case PCI_CAP_ID_MSIX:
78 {
79 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
80 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
81 writel(flag, entry->mask_base + offset);
82 break;
83 }
84 default:
85 break;
86 }
87}
88
89#ifdef CONFIG_SMP
90static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
91{
92 struct msi_desc *entry;
93 struct msg_address address;
54d5d424 94 unsigned int irq = vector;
1da177e4
LT		 95
96 entry = (struct msi_desc *)msi_desc[vector];
97 if (!entry || !entry->dev)
98 return;
99
100 switch (entry->msi_attrib.type) {
101 case PCI_CAP_ID_MSI:
102 {
103 int pos;
104
105 if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
106 return;
107
108 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
109 &address.lo_address.value);
110 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
111 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
112 MSI_TARGET_CPU_SHIFT);
113 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
114 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
115 address.lo_address.value);
54d5d424 116 set_native_irq_info(irq, cpu_mask);
1da177e4
LT		 117 break;
118 }
119 case PCI_CAP_ID_MSIX:
120 {
121 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
122 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
123
124 address.lo_address.value = readl(entry->mask_base + offset);
125 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
126 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
127 MSI_TARGET_CPU_SHIFT);
128 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
129 writel(address.lo_address.value, entry->mask_base + offset);
54d5d424 130 set_native_irq_info(irq, cpu_mask);
1da177e4
LT		 131 break;
132 }
133 default:
134 break;
135 }
136}
1da177e4
LT		 137#endif /* CONFIG_SMP */
138
139static void mask_MSI_irq(unsigned int vector)
140{
141 msi_set_mask_bit(vector, 1);
142}
143
144static void unmask_MSI_irq(unsigned int vector)
145{
146 msi_set_mask_bit(vector, 0);
147}
148
149static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
150{
151 struct msi_desc *entry;
152 unsigned long flags;
153
154 spin_lock_irqsave(&msi_lock, flags);
155 entry = msi_desc[vector];
156 if (!entry || !entry->dev) {
157 spin_unlock_irqrestore(&msi_lock, flags);
158 return 0;
159 }
160 entry->msi_attrib.state = 1; /* Mark it active */
161 spin_unlock_irqrestore(&msi_lock, flags);
162
163 return 0; /* never anything pending */
164}
165
70549ad9 166static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
1da177e4 167{
70549ad9
GKH		 168 startup_msi_irq_wo_maskbit(vector);
169 unmask_MSI_irq(vector);
170 return 0; /* never anything pending */
1da177e4
LT		 171}
172
70549ad9 173static void shutdown_msi_irq(unsigned int vector)
1da177e4
LT		 174{
175 struct msi_desc *entry;
176 unsigned long flags;
177
178 spin_lock_irqsave(&msi_lock, flags);
179 entry = msi_desc[vector];
70549ad9
GKH		 180 if (entry && entry->dev)
181 entry->msi_attrib.state = 0; /* Mark it not active */
1da177e4 182 spin_unlock_irqrestore(&msi_lock, flags);
1da177e4
LT		 183}
184
70549ad9
GKH		 185static void end_msi_irq_wo_maskbit(unsigned int vector)
186{
54d5d424 187 move_native_irq(vector);
70549ad9
GKH		 188 ack_APIC_irq();
189}
1da177e4
LT		 190
191static void end_msi_irq_w_maskbit(unsigned int vector)
192{
54d5d424 193 move_native_irq(vector);
1da177e4
LT		 194 unmask_MSI_irq(vector);
195 ack_APIC_irq();
196}
197
70549ad9
GKH		 198static void do_nothing(unsigned int vector)
199{
200}
201
1da177e4
LT		 202/*
203 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
204 * which implement the MSI-X Capability Structure.
205 */
206static struct hw_interrupt_type msix_irq_type = {
207 .typename = "PCI-MSI-X",
208 .startup = startup_msi_irq_w_maskbit,
70549ad9
GKH		 209 .shutdown = shutdown_msi_irq,
210 .enable = unmask_MSI_irq,
211 .disable = mask_MSI_irq,
212 .ack = mask_MSI_irq,
1da177e4
LT		 213 .end = end_msi_irq_w_maskbit,
214 .set_affinity = set_msi_irq_affinity
215};
216
217/*
218 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
219 * which implement the MSI Capability Structure with
220 * Mask-and-Pending Bits.
221 */
222static struct hw_interrupt_type msi_irq_w_maskbit_type = {
223 .typename = "PCI-MSI",
224 .startup = startup_msi_irq_w_maskbit,
70549ad9
GKH		 225 .shutdown = shutdown_msi_irq,
226 .enable = unmask_MSI_irq,
227 .disable = mask_MSI_irq,
228 .ack = mask_MSI_irq,
1da177e4
LT		 229 .end = end_msi_irq_w_maskbit,
230 .set_affinity = set_msi_irq_affinity
231};
232
233/*
234 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
235 * which implement the MSI Capability Structure without
236 * Mask-and-Pending Bits.
237 */
238static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
239 .typename = "PCI-MSI",
240 .startup = startup_msi_irq_wo_maskbit,
70549ad9
GKH		 241 .shutdown = shutdown_msi_irq,
242 .enable = do_nothing,
243 .disable = do_nothing,
244 .ack = do_nothing,
1da177e4
LT		 245 .end = end_msi_irq_wo_maskbit,
246 .set_affinity = set_msi_irq_affinity
247};
248
249static void msi_data_init(struct msg_data *msi_data,
250 unsigned int vector)
251{
252 memset(msi_data, 0, sizeof(struct msg_data));
253 msi_data->vector = (u8)vector;
254 msi_data->delivery_mode = MSI_DELIVERY_MODE;
255 msi_data->level = MSI_LEVEL_MODE;
256 msi_data->trigger = MSI_TRIGGER_MODE;
257}
258
259static void msi_address_init(struct msg_address *msi_address)
260{
261 unsigned int dest_id;
262
263 memset(msi_address, 0, sizeof(struct msg_address));
264 msi_address->hi_address = (u32)0;
265 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
266 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE;
267 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
268 msi_address->lo_address.u.dest_id = dest_id;
269 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT);
270}
271
272static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
273static int assign_msi_vector(void)
274{
275 static int new_vector_avail = 1;
276 int vector;
277 unsigned long flags;
278
279 /*
280 * msi_lock is provided to ensure that successful allocation of MSI
281 * vector is assigned unique among drivers.
282 */
283 spin_lock_irqsave(&msi_lock, flags);
284
285 if (!new_vector_avail) {
286 int free_vector = 0;
287
288 /*
289 * vector_irq[] = -1 indicates that this specific vector is:
290 * - assigned for MSI (since MSI have no associated IRQ) or
291 * - assigned for legacy if less than 16, or
292 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
293 * vector_irq[] = 0 indicates that this vector, previously
294 * assigned for MSI, is freed by hotplug removed operations.
295 * This vector will be reused for any subsequent hotplug added
296 * operations.
297 * vector_irq[] > 0 indicates that this vector is assigned for
298 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
299 * vector-to-IOxAPIC IRQ mapping.
300 */
301 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
302 if (vector_irq[vector] != 0)
303 continue;
304 free_vector = vector;
305 if (!msi_desc[vector])
306 break;
307 else
308 continue;
309 }
310 if (!free_vector) {
311 spin_unlock_irqrestore(&msi_lock, flags);
312 return -EBUSY;
313 }
314 vector_irq[free_vector] = -1;
315 nr_released_vectors--;
316 spin_unlock_irqrestore(&msi_lock, flags);
317 if (msi_desc[free_vector] != NULL) {
318 struct pci_dev *dev;
319 int tail;
320
321 /* free all linked vectors before re-assign */
322 do {
323 spin_lock_irqsave(&msi_lock, flags);
324 dev = msi_desc[free_vector]->dev;
325 tail = msi_desc[free_vector]->link.tail;
326 spin_unlock_irqrestore(&msi_lock, flags);
327 msi_free_vector(dev, tail, 1);
328 } while (free_vector != tail);
329 }
330
331 return free_vector;
332 }
333 vector = assign_irq_vector(AUTO_ASSIGN);
334 last_alloc_vector = vector;
335 if (vector == LAST_DEVICE_VECTOR)
336 new_vector_avail = 0;
337
338 spin_unlock_irqrestore(&msi_lock, flags);
339 return vector;
340}
341
342static int get_new_vector(void)
343{
344 int vector;
345
346 if ((vector = assign_msi_vector()) > 0)
347 set_intr_gate(vector, interrupt[vector]);
348
349 return vector;
350}
351
352static int msi_init(void)
353{
354 static int status = -ENOMEM;
355
356 if (!status)
357 return status;
358
359 if (pci_msi_quirk) {
360 pci_msi_enable = 0;
361 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
362 status = -EINVAL;
363 return status;
364 }
365
366 if ((status = msi_cache_init()) < 0) {
367 pci_msi_enable = 0;
368 printk(KERN_WARNING "PCI: MSI cache init failed\n");
369 return status;
370 }
371 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN);
372 if (last_alloc_vector < 0) {
373 pci_msi_enable = 0;
374 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n");
375 status = -EBUSY;
376 return status;
377 }
378 vector_irq[last_alloc_vector] = 0;
379 nr_released_vectors++;
380
381 return status;
382}
383
384static int get_msi_vector(struct pci_dev *dev)
385{
386 return get_new_vector();
387}
388
389static struct msi_desc* alloc_msi_entry(void)
390{
391 struct msi_desc *entry;
392
70549ad9 393 entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
1da177e4
LT		 394 if (!entry)
395 return NULL;
396
397 memset(entry, 0, sizeof(struct msi_desc));
398 entry->link.tail = entry->link.head = 0; /* single message */
399 entry->dev = NULL;
400
401 return entry;
402}
403
404static void attach_msi_entry(struct msi_desc *entry, int vector)
405{
406 unsigned long flags;
407
408 spin_lock_irqsave(&msi_lock, flags);
409 msi_desc[vector] = entry;
410 spin_unlock_irqrestore(&msi_lock, flags);
411}
412
413static void irq_handler_init(int cap_id, int pos, int mask)
414{
415 spin_lock(&irq_desc[pos].lock);
416 if (cap_id == PCI_CAP_ID_MSIX)
417 irq_desc[pos].handler = &msix_irq_type;
418 else {
419 if (!mask)
420 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
421 else
422 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
423 }
424 spin_unlock(&irq_desc[pos].lock);
425}
426
427static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
428{
429 u16 control;
430
431 pci_read_config_word(dev, msi_control_reg(pos), &control);
432 if (type == PCI_CAP_ID_MSI) {
433 /* Set enabled bits to single MSI & enable MSI_enable bit */
434 msi_enable(control, 1);
435 pci_write_config_word(dev, msi_control_reg(pos), control);
436 } else {
437 msix_enable(control);
438 pci_write_config_word(dev, msi_control_reg(pos), control);
439 }
440 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
441 /* PCI Express Endpoint device detected */
a04ce0ff 442 pci_intx(dev, 0); /* disable intx */
1da177e4
LT		 443 }
444}
445
4602b88d 446void disable_msi_mode(struct pci_dev *dev, int pos, int type)
1da177e4
LT		 447{
448 u16 control;
449
450 pci_read_config_word(dev, msi_control_reg(pos), &control);
451 if (type == PCI_CAP_ID_MSI) {
452 /* Set enabled bits to single MSI & enable MSI_enable bit */
453 msi_disable(control);
454 pci_write_config_word(dev, msi_control_reg(pos), control);
455 } else {
456 msix_disable(control);
457 pci_write_config_word(dev, msi_control_reg(pos), control);
458 }
459 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
460 /* PCI Express Endpoint device detected */
a04ce0ff 461 pci_intx(dev, 1); /* enable intx */
1da177e4
LT		 462 }
463}
464
465static int msi_lookup_vector(struct pci_dev *dev, int type)
466{
467 int vector;
468 unsigned long flags;
469
470 spin_lock_irqsave(&msi_lock, flags);
471 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
472 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
473 msi_desc[vector]->msi_attrib.type != type ||
474 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
475 continue;
476 spin_unlock_irqrestore(&msi_lock, flags);
477 /* This pre-assigned MSI vector for this device
478 already exits. Override dev->irq with this vector */
479 dev->irq = vector;
480 return 0;
481 }
482 spin_unlock_irqrestore(&msi_lock, flags);
483
484 return -EACCES;
485}
486
487void pci_scan_msi_device(struct pci_dev *dev)
488{
489 if (!dev)
490 return;
491
492 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0)
493 nr_msix_devices++;
494 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
495 nr_reserved_vectors++;
496}
497
498/**
499 * msi_capability_init - configure device's MSI capability structure
500 * @dev: pointer to the pci_dev data structure of MSI device function
501 *
eaae4b3a 502 * Setup the MSI capability structure of device function with a single
1da177e4
LT		 503 * MSI vector, regardless of device function is capable of handling
504 * multiple messages. A return of zero indicates the successful setup
505 * of an entry zero with the new MSI vector or non-zero for otherwise.
506 **/
507static int msi_capability_init(struct pci_dev *dev)
508{
509 struct msi_desc *entry;
510 struct msg_address address;
511 struct msg_data data;
512 int pos, vector;
513 u16 control;
514
515 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
516 pci_read_config_word(dev, msi_control_reg(pos), &control);
517 /* MSI Entry Initialization */
518 if (!(entry = alloc_msi_entry()))
519 return -ENOMEM;
520
521 if ((vector = get_msi_vector(dev)) < 0) {
522 kmem_cache_free(msi_cachep, entry);
523 return -EBUSY;
524 }
525 entry->link.head = vector;
526 entry->link.tail = vector;
527 entry->msi_attrib.type = PCI_CAP_ID_MSI;
528 entry->msi_attrib.state = 0; /* Mark it not active */
529 entry->msi_attrib.entry_nr = 0;
530 entry->msi_attrib.maskbit = is_mask_bit_support(control);
531 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */
532 dev->irq = vector;
533 entry->dev = dev;
534 if (is_mask_bit_support(control)) {
535 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
536 is_64bit_address(control));
537 }
538 /* Replace with MSI handler */
539 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
540 /* Configure MSI capability structure */
541 msi_address_init(&address);
542 msi_data_init(&data, vector);
543 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
544 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
545 pci_write_config_dword(dev, msi_lower_address_reg(pos),
546 address.lo_address.value);
547 if (is_64bit_address(control)) {
548 pci_write_config_dword(dev,
549 msi_upper_address_reg(pos), address.hi_address);
550 pci_write_config_word(dev,
551 msi_data_reg(pos, 1), *((u32*)&data));
552 } else
553 pci_write_config_word(dev,
554 msi_data_reg(pos, 0), *((u32*)&data));
555 if (entry->msi_attrib.maskbit) {
556 unsigned int maskbits, temp;
557 /* All MSIs are unmasked by default, Mask them all */
558 pci_read_config_dword(dev,
559 msi_mask_bits_reg(pos, is_64bit_address(control)),
560 &maskbits);
561 temp = (1 << multi_msi_capable(control));
562 temp = ((temp - 1) & ~temp);
563 maskbits |= temp;
564 pci_write_config_dword(dev,
565 msi_mask_bits_reg(pos, is_64bit_address(control)),
566 maskbits);
567 }
568 attach_msi_entry(entry, vector);
569 /* Set MSI enabled bits */
570 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
571
572 return 0;
573}
574
575/**
576 * msix_capability_init - configure device's MSI-X capability
577 * @dev: pointer to the pci_dev data structure of MSI-X device function
8f7020d3
RD		 578 * @entries: pointer to an array of struct msix_entry entries
579 * @nvec: number of @entries
1da177e4 580 *
eaae4b3a 581 * Setup the MSI-X capability structure of device function with a
1da177e4
LT		 582 * single MSI-X vector. A return of zero indicates the successful setup of
583 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
584 **/
585static int msix_capability_init(struct pci_dev *dev,
586 struct msix_entry *entries, int nvec)
587{
588 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
589 struct msg_address address;
590 struct msg_data data;
591 int vector, pos, i, j, nr_entries, temp = 0;
592 u32 phys_addr, table_offset;
593 u16 control;
594 u8 bir;
595 void __iomem *base;
596
597 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
598 /* Request & Map MSI-X table region */
599 pci_read_config_word(dev, msi_control_reg(pos), &control);
600 nr_entries = multi_msix_capable(control);
601 pci_read_config_dword(dev, msix_table_offset_reg(pos),
602 &table_offset);
603 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
604 phys_addr = pci_resource_start (dev, bir);
605 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
606 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
607 if (base == NULL)
608 return -ENOMEM;
609
610 /* MSI-X Table Initialization */
611 for (i = 0; i < nvec; i++) {
612 entry = alloc_msi_entry();
613 if (!entry)
614 break;
615 if ((vector = get_msi_vector(dev)) < 0)
616 break;
617
618 j = entries[i].entry;
619 entries[i].vector = vector;
620 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
621 entry->msi_attrib.state = 0; /* Mark it not active */
622 entry->msi_attrib.entry_nr = j;
623 entry->msi_attrib.maskbit = 1;
624 entry->msi_attrib.default_vector = dev->irq;
625 entry->dev = dev;
626 entry->mask_base = base;
627 if (!head) {
628 entry->link.head = vector;
629 entry->link.tail = vector;
630 head = entry;
631 } else {
632 entry->link.head = temp;
633 entry->link.tail = tail->link.tail;
634 tail->link.tail = vector;
635 head->link.head = vector;
636 }
637 temp = vector;
638 tail = entry;
639 /* Replace with MSI-X handler */
640 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
641 /* Configure MSI-X capability structure */
642 msi_address_init(&address);
643 msi_data_init(&data, vector);
644 entry->msi_attrib.current_cpu =
645 ((address.lo_address.u.dest_id >>
646 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
647 writel(address.lo_address.value,
648 base + j * PCI_MSIX_ENTRY_SIZE +
649 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
650 writel(address.hi_address,
651 base + j * PCI_MSIX_ENTRY_SIZE +
652 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
653 writel(*(u32*)&data,
654 base + j * PCI_MSIX_ENTRY_SIZE +
655 PCI_MSIX_ENTRY_DATA_OFFSET);
656 attach_msi_entry(entry, vector);
657 }
658 if (i != nvec) {
659 i--;
660 for (; i >= 0; i--) {
661 vector = (entries + i)->vector;
662 msi_free_vector(dev, vector, 0);
663 (entries + i)->vector = 0;
664 }
665 return -EBUSY;
666 }
667 /* Set MSI-X enabled bits */
668 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
669
670 return 0;
671}
672
673/**
674 * pci_enable_msi - configure device's MSI capability structure
675 * @dev: pointer to the pci_dev data structure of MSI device function
676 *
677 * Setup the MSI capability structure of device function with
678 * a single MSI vector upon its software driver call to request for
679 * MSI mode enabled on its hardware device function. A return of zero
680 * indicates the successful setup of an entry zero with the new MSI
681 * vector or non-zero for otherwise.
682 **/
683int pci_enable_msi(struct pci_dev* dev)
684{
685 int pos, temp, status = -EINVAL;
686 u16 control;
687
688 if (!pci_msi_enable || !dev)
689 return status;
690
4602b88d
KA		 691 if (dev->no_msi)
692 return status;
693
1da177e4
LT		 694 temp = dev->irq;
695
696 if ((status = msi_init()) < 0)
697 return status;
698
699 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
700 return -EINVAL;
701
702 pci_read_config_word(dev, msi_control_reg(pos), &control);
703 if (control & PCI_MSI_FLAGS_ENABLE)
704 return 0; /* Already in MSI mode */
705
706 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
707 /* Lookup Sucess */
708 unsigned long flags;
709
710 spin_lock_irqsave(&msi_lock, flags);
711 if (!vector_irq[dev->irq]) {
712 msi_desc[dev->irq]->msi_attrib.state = 0;
713 vector_irq[dev->irq] = -1;
714 nr_released_vectors--;
715 spin_unlock_irqrestore(&msi_lock, flags);
716 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
717 return 0;
718 }
719 spin_unlock_irqrestore(&msi_lock, flags);
720 dev->irq = temp;
721 }
722 /* Check whether driver already requested for MSI-X vectors */
723 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
724 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
725 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
726 "Device already has MSI-X vectors assigned\n",
727 pci_name(dev));
728 dev->irq = temp;
729 return -EINVAL;
730 }
731 status = msi_capability_init(dev);
732 if (!status) {
733 if (!pos)
734 nr_reserved_vectors--; /* Only MSI capable */
735 else if (nr_msix_devices > 0)
736 nr_msix_devices--; /* Both MSI and MSI-X capable,
737 but choose enabling MSI */
738 }
739
740 return status;
741}
742
743void pci_disable_msi(struct pci_dev* dev)
744{
745 struct msi_desc *entry;
746 int pos, default_vector;
747 u16 control;
748 unsigned long flags;
749
750 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
751 return;
752
753 pci_read_config_word(dev, msi_control_reg(pos), &control);
754 if (!(control & PCI_MSI_FLAGS_ENABLE))
755 return;
756
757 spin_lock_irqsave(&msi_lock, flags);
758 entry = msi_desc[dev->irq];
759 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
760 spin_unlock_irqrestore(&msi_lock, flags);
761 return;
762 }
763 if (entry->msi_attrib.state) {
764 spin_unlock_irqrestore(&msi_lock, flags);
765 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
766 "free_irq() on MSI vector %d\n",
767 pci_name(dev), dev->irq);
768 BUG_ON(entry->msi_attrib.state > 0);
769 } else {
770 vector_irq[dev->irq] = 0; /* free it */
771 nr_released_vectors++;
772 default_vector = entry->msi_attrib.default_vector;
773 spin_unlock_irqrestore(&msi_lock, flags);
774 /* Restore dev->irq to its default pin-assertion vector */
775 dev->irq = default_vector;
776 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
777 PCI_CAP_ID_MSI);
778 }
779}
780
1da177e4
LT		 781static int msi_free_vector(struct pci_dev* dev, int vector, int reassign)
782{
783 struct msi_desc *entry;
784 int head, entry_nr, type;
785 void __iomem *base;
786 unsigned long flags;
787
788 spin_lock_irqsave(&msi_lock, flags);
789 entry = msi_desc[vector];
790 if (!entry || entry->dev != dev) {
791 spin_unlock_irqrestore(&msi_lock, flags);
792 return -EINVAL;
793 }
794 type = entry->msi_attrib.type;
795 entry_nr = entry->msi_attrib.entry_nr;
796 head = entry->link.head;
797 base = entry->mask_base;
798 msi_desc[entry->link.head]->link.tail = entry->link.tail;
799 msi_desc[entry->link.tail]->link.head = entry->link.head;
800 entry->dev = NULL;
801 if (!reassign) {
802 vector_irq[vector] = 0;
803 nr_released_vectors++;
804 }
805 msi_desc[vector] = NULL;
806 spin_unlock_irqrestore(&msi_lock, flags);
807
808 kmem_cache_free(msi_cachep, entry);
809
810 if (type == PCI_CAP_ID_MSIX) {
811 if (!reassign)
812 writel(1, base +
813 entry_nr * PCI_MSIX_ENTRY_SIZE +
814 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
815
816 if (head == vector) {
817 /*
818 * Detect last MSI-X vector to be released.
819 * Release the MSI-X memory-mapped table.
820 */
821 int pos, nr_entries;
822 u32 phys_addr, table_offset;
823 u16 control;
824 u8 bir;
825
826 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
827 pci_read_config_word(dev, msi_control_reg(pos),
828 &control);
829 nr_entries = multi_msix_capable(control);
830 pci_read_config_dword(dev, msix_table_offset_reg(pos),
831 &table_offset);
832 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
833 phys_addr = pci_resource_start (dev, bir);
834 phys_addr += (u32)(table_offset &
835 ~PCI_MSIX_FLAGS_BIRMASK);
836 iounmap(base);
837 }
838 }
839
840 return 0;
841}
842
843static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec)
844{
845 int vector = head, tail = 0;
846 int i, j = 0, nr_entries = 0;
847 void __iomem *base;
848 unsigned long flags;
849
850 spin_lock_irqsave(&msi_lock, flags);
851 while (head != tail) {
852 nr_entries++;
853 tail = msi_desc[vector]->link.tail;
854 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr)
855 j = vector;
856 vector = tail;
857 }
858 if (*nvec > nr_entries) {
859 spin_unlock_irqrestore(&msi_lock, flags);
860 *nvec = nr_entries;
861 return -EINVAL;
862 }
863 vector = ((j > 0) ? j : head);
864 for (i = 0; i < *nvec; i++) {
865 j = msi_desc[vector]->msi_attrib.entry_nr;
866 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */
867 vector_irq[vector] = -1; /* Mark it busy */
868 nr_released_vectors--;
869 entries[i].vector = vector;
870 if (j != (entries + i)->entry) {
871 base = msi_desc[vector]->mask_base;
872 msi_desc[vector]->msi_attrib.entry_nr =
873 (entries + i)->entry;
874 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
875 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base +
876 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
877 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
878 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
879 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base +
880 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
881 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
882 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE +
883 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector,
884 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE +
885 PCI_MSIX_ENTRY_DATA_OFFSET);
886 }
887 vector = msi_desc[vector]->link.tail;
888 }
889 spin_unlock_irqrestore(&msi_lock, flags);
890
891 return 0;
892}
893
894/**
895 * pci_enable_msix - configure device's MSI-X capability structure
896 * @dev: pointer to the pci_dev data structure of MSI-X device function
70549ad9 897 * @entries: pointer to an array of MSI-X entries
1da177e4
LT		 898 * @nvec: number of MSI-X vectors requested for allocation by device driver
899 *
900 * Setup the MSI-X capability structure of device function with the number
901 * of requested vectors upon its software driver call to request for
902 * MSI-X mode enabled on its hardware device function. A return of zero
903 * indicates the successful configuration of MSI-X capability structure
904 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
905 * Or a return of > 0 indicates that driver request is exceeding the number
906 * of vectors available. Driver should use the returned value to re-send
907 * its request.
908 **/
909int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
910{
911 int status, pos, nr_entries, free_vectors;
912 int i, j, temp;
913 u16 control;
914 unsigned long flags;
915
916 if (!pci_msi_enable || !dev || !entries)
917 return -EINVAL;
918
919 if ((status = msi_init()) < 0)
920 return status;
921
922 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
923 return -EINVAL;
924
925 pci_read_config_word(dev, msi_control_reg(pos), &control);
926 if (control & PCI_MSIX_FLAGS_ENABLE)
927 return -EINVAL; /* Already in MSI-X mode */
928
929 nr_entries = multi_msix_capable(control);
930 if (nvec > nr_entries)
931 return -EINVAL;
932
933 /* Check for any invalid entries */
934 for (i = 0; i < nvec; i++) {
935 if (entries[i].entry >= nr_entries)
936 return -EINVAL; /* invalid entry */
937 for (j = i + 1; j < nvec; j++) {
938 if (entries[i].entry == entries[j].entry)
939 return -EINVAL; /* duplicate entry */
940 }
941 }
942 temp = dev->irq;
943 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
944 /* Lookup Sucess */
945 nr_entries = nvec;
946 /* Reroute MSI-X table */
947 if (reroute_msix_table(dev->irq, entries, &nr_entries)) {
948 /* #requested > #previous-assigned */
949 dev->irq = temp;
950 return nr_entries;
951 }
952 dev->irq = temp;
953 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
954 return 0;
955 }
956 /* Check whether driver already requested for MSI vector */
957 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
958 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
959 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
960 "Device already has an MSI vector assigned\n",
961 pci_name(dev));
962 dev->irq = temp;
963 return -EINVAL;
964 }
965
966 spin_lock_irqsave(&msi_lock, flags);
967 /*
968 * msi_lock is provided to ensure that enough vectors resources are
969 * available before granting.
970 */
971 free_vectors = pci_vector_resources(last_alloc_vector,
972 nr_released_vectors);
973 /* Ensure that each MSI/MSI-X device has one vector reserved by
974 default to avoid any MSI-X driver to take all available
975 resources */
976 free_vectors -= nr_reserved_vectors;
977 /* Find the average of free vectors among MSI-X devices */
978 if (nr_msix_devices > 0)
979 free_vectors /= nr_msix_devices;
980 spin_unlock_irqrestore(&msi_lock, flags);
981
982 if (nvec > free_vectors) {
983 if (free_vectors > 0)
984 return free_vectors;
985 else
986 return -EBUSY;
987 }
988
989 status = msix_capability_init(dev, entries, nvec);
990 if (!status && nr_msix_devices > 0)
991 nr_msix_devices--;
992
993 return status;
994}
995
996void pci_disable_msix(struct pci_dev* dev)
997{
998 int pos, temp;
999 u16 control;
1000
1001 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
1002 return;
1003
1004 pci_read_config_word(dev, msi_control_reg(pos), &control);
1005 if (!(control & PCI_MSIX_FLAGS_ENABLE))
1006 return;
1007
1008 temp = dev->irq;
1009 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1010 int state, vector, head, tail = 0, warning = 0;
1011 unsigned long flags;
1012
1013 vector = head = dev->irq;
1014 spin_lock_irqsave(&msi_lock, flags);
1015 while (head != tail) {
1016 state = msi_desc[vector]->msi_attrib.state;
1017 if (state)
1018 warning = 1;
1019 else {
1020 vector_irq[vector] = 0; /* free it */
1021 nr_released_vectors++;
1022 }
1023 tail = msi_desc[vector]->link.tail;
1024 vector = tail;
1025 }
1026 spin_unlock_irqrestore(&msi_lock, flags);
1027 if (warning) {
1028 dev->irq = temp;
1029 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
1030 "free_irq() on all MSI-X vectors\n",
1031 pci_name(dev));
1032 BUG_ON(warning > 0);
1033 } else {
1034 dev->irq = temp;
1035 disable_msi_mode(dev,
1036 pci_find_capability(dev, PCI_CAP_ID_MSIX),
1037 PCI_CAP_ID_MSIX);
1038
1039 }
1040 }
1041}
1042
1043/**
1044 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
1045 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1046 *
eaae4b3a 1047 * Being called during hotplug remove, from which the device function
1da177e4
LT		 1048 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
1049 * allocated for this device function, are reclaimed to unused state,
1050 * which may be used later on.
1051 **/
1052void msi_remove_pci_irq_vectors(struct pci_dev* dev)
1053{
1054 int state, pos, temp;
1055 unsigned long flags;
1056
1057 if (!pci_msi_enable || !dev)
1058 return;
1059
1060 temp = dev->irq; /* Save IOAPIC IRQ */
1061 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSI)) > 0 &&
1062 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
1063 spin_lock_irqsave(&msi_lock, flags);
1064 state = msi_desc[dev->irq]->msi_attrib.state;
1065 spin_unlock_irqrestore(&msi_lock, flags);
1066 if (state) {
1067 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1068 "called without free_irq() on MSI vector %d\n",
1069 pci_name(dev), dev->irq);
1070 BUG_ON(state > 0);
1071 } else /* Release MSI vector assigned to this device */
1072 msi_free_vector(dev, dev->irq, 0);
1073 dev->irq = temp; /* Restore IOAPIC IRQ */
1074 }
1075 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
1076 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1077 int vector, head, tail = 0, warning = 0;
1078 void __iomem *base = NULL;
1079
1080 vector = head = dev->irq;
1081 while (head != tail) {
1082 spin_lock_irqsave(&msi_lock, flags);
1083 state = msi_desc[vector]->msi_attrib.state;
1084 tail = msi_desc[vector]->link.tail;
1085 base = msi_desc[vector]->mask_base;
1086 spin_unlock_irqrestore(&msi_lock, flags);
1087 if (state)
1088 warning = 1;
1089 else if (vector != head) /* Release MSI-X vector */
1090 msi_free_vector(dev, vector, 0);
1091 vector = tail;
1092 }
1093 msi_free_vector(dev, vector, 0);
1094 if (warning) {
1095 /* Force to release the MSI-X memory-mapped table */
1096 u32 phys_addr, table_offset;
1097 u16 control;
1098 u8 bir;
1099
1100 pci_read_config_word(dev, msi_control_reg(pos),
1101 &control);
1102 pci_read_config_dword(dev, msix_table_offset_reg(pos),
1103 &table_offset);
1104 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
1105 phys_addr = pci_resource_start (dev, bir);
1106 phys_addr += (u32)(table_offset &
1107 ~PCI_MSIX_FLAGS_BIRMASK);
1108 iounmap(base);
1109 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1110 "called without free_irq() on all MSI-X vectors\n",
1111 pci_name(dev));
1112 BUG_ON(warning > 0);
1113 }
1114 dev->irq = temp; /* Restore IOAPIC IRQ */
1115 }
1116}
1117
1118EXPORT_SYMBOL(pci_enable_msi);
1119EXPORT_SYMBOL(pci_disable_msi);
1120EXPORT_SYMBOL(pci_enable_msix);
1121EXPORT_SYMBOL(pci_disable_msix);
Linux kernel - Deliverables
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