Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
527eee29 BH |
27 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
28 | ||
29 | ||
6a9e7f20 AB |
30 | /* Arch hooks */ |
31 | ||
4287d824 TP |
32 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
33 | { | |
0cbdcfcf TR |
34 | struct msi_chip *chip = dev->bus->msi; |
35 | int err; | |
36 | ||
37 | if (!chip || !chip->setup_irq) | |
38 | return -EINVAL; | |
39 | ||
40 | err = chip->setup_irq(chip, dev, desc); | |
41 | if (err < 0) | |
42 | return err; | |
43 | ||
44 | irq_set_chip_data(desc->irq, chip); | |
45 | ||
46 | return 0; | |
4287d824 TP |
47 | } |
48 | ||
49 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 50 | { |
0cbdcfcf TR |
51 | struct msi_chip *chip = irq_get_chip_data(irq); |
52 | ||
53 | if (!chip || !chip->teardown_irq) | |
54 | return; | |
55 | ||
56 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
57 | } |
58 | ||
4287d824 TP |
59 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
60 | { | |
0cbdcfcf TR |
61 | struct msi_chip *chip = dev->bus->msi; |
62 | ||
63 | if (!chip || !chip->check_device) | |
64 | return 0; | |
65 | ||
66 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 67 | } |
1525bf0d | 68 | |
4287d824 | 69 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
70 | { |
71 | struct msi_desc *entry; | |
72 | int ret; | |
73 | ||
1c8d7b0a MW |
74 | /* |
75 | * If an architecture wants to support multiple MSI, it needs to | |
76 | * override arch_setup_msi_irqs() | |
77 | */ | |
78 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
79 | return 1; | |
80 | ||
6a9e7f20 AB |
81 | list_for_each_entry(entry, &dev->msi_list, list) { |
82 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 83 | if (ret < 0) |
6a9e7f20 | 84 | return ret; |
b5fbf533 ME |
85 | if (ret > 0) |
86 | return -ENOSPC; | |
6a9e7f20 AB |
87 | } |
88 | ||
89 | return 0; | |
90 | } | |
1525bf0d | 91 | |
4287d824 TP |
92 | /* |
93 | * We have a default implementation available as a separate non-weak | |
94 | * function, as it is used by the Xen x86 PCI code | |
95 | */ | |
1525bf0d | 96 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
97 | { |
98 | struct msi_desc *entry; | |
99 | ||
100 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
101 | int i, nvec; |
102 | if (entry->irq == 0) | |
103 | continue; | |
65f6ae66 AG |
104 | if (entry->nvec_used) |
105 | nvec = entry->nvec_used; | |
106 | else | |
107 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
108 | for (i = 0; i < nvec; i++) |
109 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
110 | } |
111 | } | |
112 | ||
4287d824 TP |
113 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
114 | { | |
115 | return default_teardown_msi_irqs(dev); | |
116 | } | |
76ccc297 | 117 | |
ac8344c4 | 118 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
119 | { |
120 | struct msi_desc *entry; | |
121 | ||
122 | entry = NULL; | |
123 | if (dev->msix_enabled) { | |
124 | list_for_each_entry(entry, &dev->msi_list, list) { | |
125 | if (irq == entry->irq) | |
126 | break; | |
127 | } | |
128 | } else if (dev->msi_enabled) { | |
129 | entry = irq_get_msi_desc(irq); | |
130 | } | |
131 | ||
132 | if (entry) | |
133 | write_msi_msg(irq, &entry->msg); | |
134 | } | |
4287d824 | 135 | |
ac8344c4 | 136 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 137 | { |
ac8344c4 | 138 | return default_restore_msi_irqs(dev); |
4287d824 | 139 | } |
76ccc297 | 140 | |
e375b561 | 141 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 142 | { |
b1cbf4e4 EB |
143 | u16 control; |
144 | ||
e375b561 | 145 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
146 | control &= ~PCI_MSI_FLAGS_ENABLE; |
147 | if (enable) | |
148 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 149 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
150 | } |
151 | ||
66f0d0c4 | 152 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 153 | { |
66f0d0c4 | 154 | u16 ctrl; |
b1cbf4e4 | 155 | |
66f0d0c4 YW |
156 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
157 | ctrl &= ~clear; | |
158 | ctrl |= set; | |
159 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
160 | } |
161 | ||
bffac3c5 MW |
162 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
163 | { | |
0b49ec37 MW |
164 | /* Don't shift by >= width of type */ |
165 | if (x >= 5) | |
166 | return 0xffffffff; | |
167 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
168 | } |
169 | ||
ce6fce42 MW |
170 | /* |
171 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
172 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
173 | * reliably as devices without an INTx disable bit will then generate a | |
174 | * level IRQ which will never be cleared. | |
ce6fce42 | 175 | */ |
0e4ccb15 | 176 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 177 | { |
f2440d9a | 178 | u32 mask_bits = desc->masked; |
1da177e4 | 179 | |
f2440d9a | 180 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 181 | return 0; |
f2440d9a MW |
182 | |
183 | mask_bits &= ~mask; | |
184 | mask_bits |= flag; | |
185 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
186 | |
187 | return mask_bits; | |
188 | } | |
189 | ||
0e4ccb15 KRW |
190 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
191 | { | |
192 | return default_msi_mask_irq(desc, mask, flag); | |
193 | } | |
194 | ||
12abb8ba HS |
195 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
196 | { | |
0e4ccb15 | 197 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
198 | } |
199 | ||
200 | /* | |
201 | * This internal function does not flush PCI writes to the device. | |
202 | * All users must ensure that they read from the device before either | |
203 | * assuming that the device state is up to date, or returning out of this | |
204 | * file. This saves a few milliseconds when initialising devices with lots | |
205 | * of MSI-X interrupts. | |
206 | */ | |
0e4ccb15 | 207 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
208 | { |
209 | u32 mask_bits = desc->masked; | |
210 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 211 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
212 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
213 | if (flag) | |
214 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 215 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
216 | |
217 | return mask_bits; | |
218 | } | |
219 | ||
0e4ccb15 KRW |
220 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
221 | { | |
222 | return default_msix_mask_irq(desc, flag); | |
223 | } | |
224 | ||
12abb8ba HS |
225 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
226 | { | |
0e4ccb15 | 227 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 228 | } |
24d27553 | 229 | |
1c9db525 | 230 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 231 | { |
1c9db525 | 232 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 233 | |
f2440d9a MW |
234 | if (desc->msi_attrib.is_msix) { |
235 | msix_mask_irq(desc, flag); | |
236 | readl(desc->mask_base); /* Flush write to device */ | |
237 | } else { | |
1c9db525 | 238 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 239 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 240 | } |
f2440d9a MW |
241 | } |
242 | ||
1c9db525 | 243 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 244 | { |
1c9db525 | 245 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
246 | } |
247 | ||
1c9db525 | 248 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 249 | { |
1c9db525 | 250 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
251 | } |
252 | ||
ac8344c4 D |
253 | void default_restore_msi_irqs(struct pci_dev *dev) |
254 | { | |
255 | struct msi_desc *entry; | |
256 | ||
257 | list_for_each_entry(entry, &dev->msi_list, list) { | |
258 | default_restore_msi_irq(dev, entry->irq); | |
259 | } | |
260 | } | |
261 | ||
39431acb | 262 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 263 | { |
30da5524 BH |
264 | BUG_ON(entry->dev->current_state != PCI_D0); |
265 | ||
266 | if (entry->msi_attrib.is_msix) { | |
267 | void __iomem *base = entry->mask_base + | |
268 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
269 | ||
270 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
271 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
272 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
273 | } else { | |
274 | struct pci_dev *dev = entry->dev; | |
f5322169 | 275 | int pos = dev->msi_cap; |
30da5524 BH |
276 | u16 data; |
277 | ||
9925ad0c BH |
278 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
279 | &msg->address_lo); | |
30da5524 | 280 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
281 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
282 | &msg->address_hi); | |
2f221349 | 283 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
284 | } else { |
285 | msg->address_hi = 0; | |
2f221349 | 286 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
287 | } |
288 | msg->data = data; | |
289 | } | |
290 | } | |
291 | ||
292 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
293 | { | |
dced35ae | 294 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 295 | |
39431acb | 296 | __read_msi_msg(entry, msg); |
30da5524 BH |
297 | } |
298 | ||
39431acb | 299 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 300 | { |
30da5524 | 301 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
302 | * valid messages are not all-zeroes. */ |
303 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
304 | entry->msg.data)); | |
0366f8f7 | 305 | |
fcd097f3 | 306 | *msg = entry->msg; |
0366f8f7 | 307 | } |
1da177e4 | 308 | |
30da5524 | 309 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 310 | { |
dced35ae | 311 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 312 | |
39431acb | 313 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
314 | } |
315 | ||
39431acb | 316 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 317 | { |
fcd097f3 BH |
318 | if (entry->dev->current_state != PCI_D0) { |
319 | /* Don't touch the hardware now */ | |
320 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
321 | void __iomem *base; |
322 | base = entry->mask_base + | |
323 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
324 | ||
2c21fd4b HS |
325 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
326 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
327 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 328 | } else { |
0366f8f7 | 329 | struct pci_dev *dev = entry->dev; |
f5322169 | 330 | int pos = dev->msi_cap; |
1c8d7b0a MW |
331 | u16 msgctl; |
332 | ||
f84ecd28 | 333 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
334 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
335 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 336 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 337 | |
9925ad0c BH |
338 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
339 | msg->address_lo); | |
0366f8f7 | 340 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
341 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
342 | msg->address_hi); | |
2f221349 BH |
343 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
344 | msg->data); | |
0366f8f7 | 345 | } else { |
2f221349 BH |
346 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
347 | msg->data); | |
0366f8f7 | 348 | } |
1da177e4 | 349 | } |
392ee1e6 | 350 | entry->msg = *msg; |
1da177e4 | 351 | } |
0366f8f7 | 352 | |
3145e941 YL |
353 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
354 | { | |
dced35ae | 355 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 356 | |
39431acb | 357 | __write_msi_msg(entry, msg); |
3145e941 YL |
358 | } |
359 | ||
f56e4481 HS |
360 | static void free_msi_irqs(struct pci_dev *dev) |
361 | { | |
362 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
363 | struct attribute **msi_attrs; |
364 | struct device_attribute *dev_attr; | |
365 | int count = 0; | |
f56e4481 HS |
366 | |
367 | list_for_each_entry(entry, &dev->msi_list, list) { | |
368 | int i, nvec; | |
369 | if (!entry->irq) | |
370 | continue; | |
65f6ae66 AG |
371 | if (entry->nvec_used) |
372 | nvec = entry->nvec_used; | |
373 | else | |
374 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
375 | for (i = 0; i < nvec; i++) |
376 | BUG_ON(irq_has_action(entry->irq + i)); | |
377 | } | |
378 | ||
379 | arch_teardown_msi_irqs(dev); | |
380 | ||
381 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
382 | if (entry->msi_attrib.is_msix) { | |
383 | if (list_is_last(&entry->list, &dev->msi_list)) | |
384 | iounmap(entry->mask_base); | |
385 | } | |
424eb391 NH |
386 | |
387 | /* | |
388 | * Its possible that we get into this path | |
389 | * When populate_msi_sysfs fails, which means the entries | |
390 | * were not registered with sysfs. In that case don't | |
391 | * unregister them. | |
392 | */ | |
393 | if (entry->kobj.parent) { | |
394 | kobject_del(&entry->kobj); | |
395 | kobject_put(&entry->kobj); | |
396 | } | |
397 | ||
f56e4481 HS |
398 | list_del(&entry->list); |
399 | kfree(entry); | |
400 | } | |
1c51b50c GKH |
401 | |
402 | if (dev->msi_irq_groups) { | |
403 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
404 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 405 | while (msi_attrs[count]) { |
1c51b50c GKH |
406 | dev_attr = container_of(msi_attrs[count], |
407 | struct device_attribute, attr); | |
408 | kfree(dev_attr->attr.name); | |
409 | kfree(dev_attr); | |
410 | ++count; | |
411 | } | |
412 | kfree(msi_attrs); | |
413 | kfree(dev->msi_irq_groups[0]); | |
414 | kfree(dev->msi_irq_groups); | |
415 | dev->msi_irq_groups = NULL; | |
416 | } | |
f56e4481 | 417 | } |
c54c1879 | 418 | |
379f5327 | 419 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 420 | { |
379f5327 MW |
421 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
422 | if (!desc) | |
1da177e4 LT |
423 | return NULL; |
424 | ||
379f5327 MW |
425 | INIT_LIST_HEAD(&desc->list); |
426 | desc->dev = dev; | |
1da177e4 | 427 | |
379f5327 | 428 | return desc; |
1da177e4 LT |
429 | } |
430 | ||
ba698ad4 DM |
431 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
432 | { | |
433 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
434 | pci_intx(dev, enable); | |
435 | } | |
436 | ||
8fed4b65 | 437 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 438 | { |
41017f0c | 439 | u16 control; |
392ee1e6 | 440 | struct msi_desc *entry; |
41017f0c | 441 | |
b1cbf4e4 EB |
442 | if (!dev->msi_enabled) |
443 | return; | |
444 | ||
dced35ae | 445 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 446 | |
ba698ad4 | 447 | pci_intx_for_msi(dev, 0); |
e375b561 | 448 | msi_set_enable(dev, 0); |
ac8344c4 | 449 | arch_restore_msi_irqs(dev); |
392ee1e6 | 450 | |
f5322169 | 451 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
452 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
453 | entry->masked); | |
abad2ec9 | 454 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 455 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 456 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
457 | } |
458 | ||
459 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 460 | { |
41017f0c | 461 | struct msi_desc *entry; |
41017f0c | 462 | |
ded86d8d EB |
463 | if (!dev->msix_enabled) |
464 | return; | |
f598282f | 465 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 466 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
ded86d8d | 467 | |
41017f0c | 468 | /* route the table */ |
ba698ad4 | 469 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
470 | msix_clear_and_set_ctrl(dev, 0, |
471 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 472 | |
ac8344c4 | 473 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 474 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 475 | msix_mask_irq(entry, entry->masked); |
41017f0c | 476 | } |
41017f0c | 477 | |
66f0d0c4 | 478 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 479 | } |
8fed4b65 ME |
480 | |
481 | void pci_restore_msi_state(struct pci_dev *dev) | |
482 | { | |
483 | __pci_restore_msi_state(dev); | |
484 | __pci_restore_msix_state(dev); | |
485 | } | |
94688cf2 | 486 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 487 | |
1c51b50c | 488 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
489 | char *buf) |
490 | { | |
1c51b50c GKH |
491 | struct pci_dev *pdev = to_pci_dev(dev); |
492 | struct msi_desc *entry; | |
493 | unsigned long irq; | |
494 | int retval; | |
da8d1c8b | 495 | |
1c51b50c GKH |
496 | retval = kstrtoul(attr->attr.name, 10, &irq); |
497 | if (retval) | |
498 | return retval; | |
da8d1c8b | 499 | |
1c51b50c GKH |
500 | list_for_each_entry(entry, &pdev->msi_list, list) { |
501 | if (entry->irq == irq) { | |
502 | return sprintf(buf, "%s\n", | |
503 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
504 | } | |
505 | } | |
506 | return -ENODEV; | |
da8d1c8b NH |
507 | } |
508 | ||
da8d1c8b NH |
509 | static int populate_msi_sysfs(struct pci_dev *pdev) |
510 | { | |
1c51b50c GKH |
511 | struct attribute **msi_attrs; |
512 | struct attribute *msi_attr; | |
513 | struct device_attribute *msi_dev_attr; | |
514 | struct attribute_group *msi_irq_group; | |
515 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 516 | struct msi_desc *entry; |
1c51b50c GKH |
517 | int ret = -ENOMEM; |
518 | int num_msi = 0; | |
da8d1c8b NH |
519 | int count = 0; |
520 | ||
1c51b50c GKH |
521 | /* Determine how many msi entries we have */ |
522 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
523 | ++num_msi; | |
524 | } | |
525 | if (!num_msi) | |
526 | return 0; | |
da8d1c8b | 527 | |
1c51b50c GKH |
528 | /* Dynamically create the MSI attributes for the PCI device */ |
529 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
530 | if (!msi_attrs) | |
531 | return -ENOMEM; | |
da8d1c8b | 532 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 533 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 534 | if (!msi_dev_attr) |
1c51b50c | 535 | goto error_attrs; |
1406276c | 536 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 537 | |
1c51b50c | 538 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
539 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
540 | entry->irq); | |
541 | if (!msi_dev_attr->attr.name) | |
542 | goto error_attrs; | |
1c51b50c GKH |
543 | msi_dev_attr->attr.mode = S_IRUGO; |
544 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 545 | ++count; |
da8d1c8b NH |
546 | } |
547 | ||
1c51b50c GKH |
548 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
549 | if (!msi_irq_group) | |
550 | goto error_attrs; | |
551 | msi_irq_group->name = "msi_irqs"; | |
552 | msi_irq_group->attrs = msi_attrs; | |
553 | ||
554 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
555 | if (!msi_irq_groups) | |
556 | goto error_irq_group; | |
557 | msi_irq_groups[0] = msi_irq_group; | |
558 | ||
559 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
560 | if (ret) | |
561 | goto error_irq_groups; | |
562 | pdev->msi_irq_groups = msi_irq_groups; | |
563 | ||
da8d1c8b NH |
564 | return 0; |
565 | ||
1c51b50c GKH |
566 | error_irq_groups: |
567 | kfree(msi_irq_groups); | |
568 | error_irq_group: | |
569 | kfree(msi_irq_group); | |
570 | error_attrs: | |
571 | count = 0; | |
572 | msi_attr = msi_attrs[count]; | |
573 | while (msi_attr) { | |
574 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
575 | kfree(msi_attr->name); | |
576 | kfree(msi_dev_attr); | |
577 | ++count; | |
578 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 579 | } |
29237756 | 580 | kfree(msi_attrs); |
da8d1c8b NH |
581 | return ret; |
582 | } | |
583 | ||
d873b4d4 YW |
584 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev) |
585 | { | |
586 | u16 control; | |
587 | struct msi_desc *entry; | |
588 | ||
589 | /* MSI Entry Initialization */ | |
590 | entry = alloc_msi_entry(dev); | |
591 | if (!entry) | |
592 | return NULL; | |
593 | ||
594 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
595 | ||
596 | entry->msi_attrib.is_msix = 0; | |
597 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
598 | entry->msi_attrib.entry_nr = 0; | |
599 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
600 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
601 | entry->msi_attrib.pos = dev->msi_cap; | |
602 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; | |
603 | ||
604 | if (control & PCI_MSI_FLAGS_64BIT) | |
605 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
606 | else | |
607 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
608 | ||
609 | /* Save the initial mask status */ | |
610 | if (entry->msi_attrib.maskbit) | |
611 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
612 | ||
613 | return entry; | |
614 | } | |
615 | ||
1da177e4 LT |
616 | /** |
617 | * msi_capability_init - configure device's MSI capability structure | |
618 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 619 | * @nvec: number of interrupts to allocate |
1da177e4 | 620 | * |
1c8d7b0a MW |
621 | * Setup the MSI capability structure of the device with the requested |
622 | * number of interrupts. A return value of zero indicates the successful | |
623 | * setup of an entry with the new MSI irq. A negative return value indicates | |
624 | * an error, and a positive return value indicates the number of interrupts | |
625 | * which could have been allocated. | |
626 | */ | |
627 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
628 | { |
629 | struct msi_desc *entry; | |
f465136d | 630 | int ret; |
f2440d9a | 631 | unsigned mask; |
1da177e4 | 632 | |
e375b561 | 633 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 634 | |
d873b4d4 | 635 | entry = msi_setup_entry(dev); |
f7feaca7 EB |
636 | if (!entry) |
637 | return -ENOMEM; | |
1ce03373 | 638 | |
f2440d9a | 639 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 640 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
641 | msi_mask_irq(entry, mask, mask); |
642 | ||
0dd11f9b | 643 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 644 | |
1da177e4 | 645 | /* Configure MSI capability structure */ |
1c8d7b0a | 646 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 647 | if (ret) { |
7ba1930d | 648 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 649 | free_msi_irqs(dev); |
7fe3730d | 650 | return ret; |
fd58e55f | 651 | } |
f7feaca7 | 652 | |
da8d1c8b NH |
653 | ret = populate_msi_sysfs(dev); |
654 | if (ret) { | |
655 | msi_mask_irq(entry, mask, ~mask); | |
656 | free_msi_irqs(dev); | |
657 | return ret; | |
658 | } | |
659 | ||
1da177e4 | 660 | /* Set MSI enabled bits */ |
ba698ad4 | 661 | pci_intx_for_msi(dev, 0); |
e375b561 | 662 | msi_set_enable(dev, 1); |
b1cbf4e4 | 663 | dev->msi_enabled = 1; |
1da177e4 | 664 | |
7fe3730d | 665 | dev->irq = entry->irq; |
1da177e4 LT |
666 | return 0; |
667 | } | |
668 | ||
520fe9dc | 669 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 670 | { |
4302e0fb | 671 | resource_size_t phys_addr; |
5a05a9d8 HS |
672 | u32 table_offset; |
673 | u8 bir; | |
674 | ||
909094c6 BH |
675 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
676 | &table_offset); | |
4d18760c BH |
677 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
678 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
679 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
680 | ||
681 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
682 | } | |
683 | ||
520fe9dc GS |
684 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
685 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
686 | { |
687 | struct msi_desc *entry; | |
688 | int i; | |
689 | ||
690 | for (i = 0; i < nvec; i++) { | |
691 | entry = alloc_msi_entry(dev); | |
692 | if (!entry) { | |
693 | if (!i) | |
694 | iounmap(base); | |
695 | else | |
696 | free_msi_irqs(dev); | |
697 | /* No enough memory. Don't try again */ | |
698 | return -ENOMEM; | |
699 | } | |
700 | ||
701 | entry->msi_attrib.is_msix = 1; | |
702 | entry->msi_attrib.is_64 = 1; | |
703 | entry->msi_attrib.entry_nr = entries[i].entry; | |
704 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 705 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
706 | entry->mask_base = base; |
707 | ||
708 | list_add_tail(&entry->list, &dev->msi_list); | |
709 | } | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
75cb3426 | 714 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 715 | struct msix_entry *entries) |
75cb3426 HS |
716 | { |
717 | struct msi_desc *entry; | |
718 | int i = 0; | |
719 | ||
720 | list_for_each_entry(entry, &dev->msi_list, list) { | |
721 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
722 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
723 | ||
724 | entries[i].vector = entry->irq; | |
dced35ae | 725 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
726 | entry->masked = readl(entry->mask_base + offset); |
727 | msix_mask_irq(entry, 1); | |
728 | i++; | |
729 | } | |
730 | } | |
731 | ||
1da177e4 LT |
732 | /** |
733 | * msix_capability_init - configure device's MSI-X capability | |
734 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
735 | * @entries: pointer to an array of struct msix_entry entries |
736 | * @nvec: number of @entries | |
1da177e4 | 737 | * |
eaae4b3a | 738 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
739 | * single MSI-X irq. A return of zero indicates the successful setup of |
740 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
741 | **/ |
742 | static int msix_capability_init(struct pci_dev *dev, | |
743 | struct msix_entry *entries, int nvec) | |
744 | { | |
520fe9dc | 745 | int ret; |
5a05a9d8 | 746 | u16 control; |
1da177e4 LT |
747 | void __iomem *base; |
748 | ||
f598282f | 749 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 750 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 751 | |
66f0d0c4 | 752 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 753 | /* Request & Map MSI-X table region */ |
527eee29 | 754 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 755 | if (!base) |
1da177e4 LT |
756 | return -ENOMEM; |
757 | ||
520fe9dc | 758 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
759 | if (ret) |
760 | return ret; | |
9c831334 ME |
761 | |
762 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 763 | if (ret) |
2adc7907 | 764 | goto out_avail; |
9c831334 | 765 | |
f598282f MW |
766 | /* |
767 | * Some devices require MSI-X to be enabled before we can touch the | |
768 | * MSI-X registers. We need to mask all the vectors to prevent | |
769 | * interrupts coming in before they're fully set up. | |
770 | */ | |
66f0d0c4 YW |
771 | msix_clear_and_set_ctrl(dev, 0, |
772 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 773 | |
75cb3426 | 774 | msix_program_entries(dev, entries); |
f598282f | 775 | |
da8d1c8b | 776 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
777 | if (ret) |
778 | goto out_free; | |
da8d1c8b | 779 | |
f598282f | 780 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 781 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 782 | dev->msix_enabled = 1; |
1da177e4 | 783 | |
66f0d0c4 | 784 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 785 | |
1da177e4 | 786 | return 0; |
583871d4 | 787 | |
2adc7907 | 788 | out_avail: |
583871d4 HS |
789 | if (ret < 0) { |
790 | /* | |
791 | * If we had some success, report the number of irqs | |
792 | * we succeeded in setting up. | |
793 | */ | |
d9d7070e | 794 | struct msi_desc *entry; |
583871d4 HS |
795 | int avail = 0; |
796 | ||
797 | list_for_each_entry(entry, &dev->msi_list, list) { | |
798 | if (entry->irq != 0) | |
799 | avail++; | |
800 | } | |
801 | if (avail != 0) | |
802 | ret = avail; | |
803 | } | |
804 | ||
2adc7907 | 805 | out_free: |
583871d4 HS |
806 | free_msi_irqs(dev); |
807 | ||
808 | return ret; | |
1da177e4 LT |
809 | } |
810 | ||
24334a12 | 811 | /** |
17bbc12a | 812 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 813 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 814 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 815 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 816 | * |
f7625980 | 817 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
818 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
819 | * supported return 0, else return an error code. | |
24334a12 | 820 | **/ |
500559a9 | 821 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
822 | { |
823 | struct pci_bus *bus; | |
c9953a73 | 824 | int ret; |
24334a12 | 825 | |
0306ebfa | 826 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
827 | if (!pci_msi_enable || !dev || dev->no_msi) |
828 | return -EINVAL; | |
829 | ||
314e77b3 ME |
830 | /* |
831 | * You can't ask to have 0 or less MSIs configured. | |
832 | * a) it's stupid .. | |
833 | * b) the list manipulation code assumes nvec >= 1. | |
834 | */ | |
835 | if (nvec < 1) | |
836 | return -ERANGE; | |
837 | ||
500559a9 HS |
838 | /* |
839 | * Any bridge which does NOT route MSI transactions from its | |
840 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
841 | * the secondary pci_bus. |
842 | * We expect only arch-specific PCI host bus controller driver | |
843 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
844 | */ | |
24334a12 BG |
845 | for (bus = dev->bus; bus; bus = bus->parent) |
846 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
847 | return -EINVAL; | |
848 | ||
c9953a73 ME |
849 | ret = arch_msi_check_device(dev, nvec, type); |
850 | if (ret) | |
851 | return ret; | |
852 | ||
24334a12 BG |
853 | return 0; |
854 | } | |
855 | ||
d1ac1d26 AG |
856 | /** |
857 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
858 | * @dev: device to report about | |
859 | * | |
860 | * This function returns the number of MSI vectors a device requested via | |
861 | * Multiple Message Capable register. It returns a negative errno if the | |
862 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
863 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
864 | * MSI specification. | |
865 | **/ | |
866 | int pci_msi_vec_count(struct pci_dev *dev) | |
867 | { | |
868 | int ret; | |
869 | u16 msgctl; | |
870 | ||
871 | if (!dev->msi_cap) | |
872 | return -EINVAL; | |
873 | ||
874 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
875 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
876 | ||
877 | return ret; | |
878 | } | |
879 | EXPORT_SYMBOL(pci_msi_vec_count); | |
880 | ||
f2440d9a | 881 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 882 | { |
f2440d9a MW |
883 | struct msi_desc *desc; |
884 | u32 mask; | |
1da177e4 | 885 | |
128bc5fc | 886 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
887 | return; |
888 | ||
110828c9 MW |
889 | BUG_ON(list_empty(&dev->msi_list)); |
890 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 891 | |
e375b561 | 892 | msi_set_enable(dev, 0); |
ba698ad4 | 893 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 894 | dev->msi_enabled = 0; |
7bd007e4 | 895 | |
12abb8ba | 896 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 897 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 898 | /* Keep cached state to be restored */ |
0e4ccb15 | 899 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
900 | |
901 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 902 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 903 | } |
24d27553 | 904 | |
500559a9 | 905 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 906 | { |
d52877c7 YL |
907 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
908 | return; | |
909 | ||
910 | pci_msi_shutdown(dev); | |
f56e4481 | 911 | free_msi_irqs(dev); |
1da177e4 | 912 | } |
4cc086fa | 913 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 914 | |
a52e2e35 | 915 | /** |
ff1aa430 | 916 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 917 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
918 | * This function returns the number of device's MSI-X table entries and |
919 | * therefore the number of MSI-X vectors device is capable of sending. | |
920 | * It returns a negative errno if the device is not capable of sending MSI-X | |
921 | * interrupts. | |
922 | **/ | |
923 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 924 | { |
a52e2e35 RW |
925 | u16 control; |
926 | ||
520fe9dc | 927 | if (!dev->msix_cap) |
ff1aa430 | 928 | return -EINVAL; |
a52e2e35 | 929 | |
f84ecd28 | 930 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 931 | return msix_table_size(control); |
a52e2e35 | 932 | } |
ff1aa430 | 933 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 934 | |
1da177e4 LT |
935 | /** |
936 | * pci_enable_msix - configure device's MSI-X capability structure | |
937 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 938 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 939 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
940 | * |
941 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 942 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
943 | * MSI-X mode enabled on its hardware device function. A return of zero |
944 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 945 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 946 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
947 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
948 | * re-send its request. | |
1da177e4 | 949 | **/ |
500559a9 | 950 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 951 | { |
a52e2e35 | 952 | int status, nr_entries; |
ded86d8d | 953 | int i, j; |
1da177e4 | 954 | |
869a1615 | 955 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 956 | return -EINVAL; |
1da177e4 | 957 | |
c9953a73 ME |
958 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
959 | if (status) | |
960 | return status; | |
961 | ||
ff1aa430 AG |
962 | nr_entries = pci_msix_vec_count(dev); |
963 | if (nr_entries < 0) | |
964 | return nr_entries; | |
1da177e4 | 965 | if (nvec > nr_entries) |
57fbf52c | 966 | return nr_entries; |
1da177e4 LT |
967 | |
968 | /* Check for any invalid entries */ | |
969 | for (i = 0; i < nvec; i++) { | |
970 | if (entries[i].entry >= nr_entries) | |
971 | return -EINVAL; /* invalid entry */ | |
972 | for (j = i + 1; j < nvec; j++) { | |
973 | if (entries[i].entry == entries[j].entry) | |
974 | return -EINVAL; /* duplicate entry */ | |
975 | } | |
976 | } | |
ded86d8d | 977 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 978 | |
1ce03373 | 979 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 980 | if (dev->msi_enabled) { |
227f0647 | 981 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
982 | return -EINVAL; |
983 | } | |
1da177e4 | 984 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
985 | return status; |
986 | } | |
4cc086fa | 987 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 988 | |
500559a9 | 989 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 990 | { |
12abb8ba HS |
991 | struct msi_desc *entry; |
992 | ||
128bc5fc | 993 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
994 | return; |
995 | ||
12abb8ba HS |
996 | /* Return the device with MSI-X masked as initial states */ |
997 | list_for_each_entry(entry, &dev->msi_list, list) { | |
998 | /* Keep cached states to be restored */ | |
0e4ccb15 | 999 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
1000 | } |
1001 | ||
66f0d0c4 | 1002 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1003 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1004 | dev->msix_enabled = 0; |
d52877c7 | 1005 | } |
c901851f | 1006 | |
500559a9 | 1007 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1008 | { |
1009 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1010 | return; | |
1011 | ||
1012 | pci_msix_shutdown(dev); | |
f56e4481 | 1013 | free_msi_irqs(dev); |
1da177e4 | 1014 | } |
4cc086fa | 1015 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1016 | |
309e57df MW |
1017 | void pci_no_msi(void) |
1018 | { | |
1019 | pci_msi_enable = 0; | |
1020 | } | |
c9953a73 | 1021 | |
07ae95f9 AP |
1022 | /** |
1023 | * pci_msi_enabled - is MSI enabled? | |
1024 | * | |
1025 | * Returns true if MSI has not been disabled by the command-line option | |
1026 | * pci=nomsi. | |
1027 | **/ | |
1028 | int pci_msi_enabled(void) | |
d389fec6 | 1029 | { |
07ae95f9 | 1030 | return pci_msi_enable; |
d389fec6 | 1031 | } |
07ae95f9 | 1032 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1033 | |
07ae95f9 | 1034 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1035 | { |
07ae95f9 | 1036 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1037 | |
1038 | /* Disable the msi hardware to avoid screaming interrupts | |
1039 | * during boot. This is the power on reset default so | |
1040 | * usually this should be a noop. | |
1041 | */ | |
e375b561 GS |
1042 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1043 | if (dev->msi_cap) | |
1044 | msi_set_enable(dev, 0); | |
1045 | ||
1046 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1047 | if (dev->msix_cap) | |
66f0d0c4 | 1048 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1049 | } |
302a2523 AG |
1050 | |
1051 | /** | |
1052 | * pci_enable_msi_range - configure device's MSI capability structure | |
1053 | * @dev: device to configure | |
1054 | * @minvec: minimal number of interrupts to configure | |
1055 | * @maxvec: maximum number of interrupts to configure | |
1056 | * | |
1057 | * This function tries to allocate a maximum possible number of interrupts in a | |
1058 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1059 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1060 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1061 | * the other interrupt numbers allocated to this device are consecutive. | |
1062 | **/ | |
1063 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1064 | { | |
034cd97e | 1065 | int nvec; |
302a2523 AG |
1066 | int rc; |
1067 | ||
034cd97e AG |
1068 | if (dev->current_state != PCI_D0) |
1069 | return -EINVAL; | |
1070 | ||
1071 | WARN_ON(!!dev->msi_enabled); | |
1072 | ||
1073 | /* Check whether driver already requested MSI-X irqs */ | |
1074 | if (dev->msix_enabled) { | |
1075 | dev_info(&dev->dev, | |
1076 | "can't enable MSI (MSI-X already enabled)\n"); | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | ||
302a2523 AG |
1080 | if (maxvec < minvec) |
1081 | return -ERANGE; | |
1082 | ||
034cd97e AG |
1083 | nvec = pci_msi_vec_count(dev); |
1084 | if (nvec < 0) | |
1085 | return nvec; | |
1086 | else if (nvec < minvec) | |
1087 | return -EINVAL; | |
1088 | else if (nvec > maxvec) | |
1089 | nvec = maxvec; | |
1090 | ||
1091 | do { | |
1092 | rc = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); | |
1093 | if (rc < 0) { | |
1094 | return rc; | |
1095 | } else if (rc > 0) { | |
1096 | if (rc < minvec) | |
1097 | return -ENOSPC; | |
1098 | nvec = rc; | |
1099 | } | |
1100 | } while (rc); | |
1101 | ||
302a2523 | 1102 | do { |
034cd97e | 1103 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1104 | if (rc < 0) { |
1105 | return rc; | |
1106 | } else if (rc > 0) { | |
1107 | if (rc < minvec) | |
1108 | return -ENOSPC; | |
1109 | nvec = rc; | |
1110 | } | |
1111 | } while (rc); | |
1112 | ||
1113 | return nvec; | |
1114 | } | |
1115 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1116 | ||
1117 | /** | |
1118 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1119 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1120 | * @entries: pointer to an array of MSI-X entries | |
1121 | * @minvec: minimum number of MSI-X irqs requested | |
1122 | * @maxvec: maximum number of MSI-X irqs requested | |
1123 | * | |
1124 | * Setup the MSI-X capability structure of device function with a maximum | |
1125 | * possible number of interrupts in the range between @minvec and @maxvec | |
1126 | * upon its software driver call to request for MSI-X mode enabled on its | |
1127 | * hardware device function. It returns a negative errno if an error occurs. | |
1128 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1129 | * indicates the successful configuration of MSI-X capability structure | |
1130 | * with new allocated MSI-X interrupts. | |
1131 | **/ | |
1132 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1133 | int minvec, int maxvec) | |
1134 | { | |
1135 | int nvec = maxvec; | |
1136 | int rc; | |
1137 | ||
1138 | if (maxvec < minvec) | |
1139 | return -ERANGE; | |
1140 | ||
1141 | do { | |
1142 | rc = pci_enable_msix(dev, entries, nvec); | |
1143 | if (rc < 0) { | |
1144 | return rc; | |
1145 | } else if (rc > 0) { | |
1146 | if (rc < minvec) | |
1147 | return -ENOSPC; | |
1148 | nvec = rc; | |
1149 | } | |
1150 | } while (rc); | |
1151 | ||
1152 | return nvec; | |
1153 | } | |
1154 | EXPORT_SYMBOL(pci_enable_msix_range); |