Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
e18b890b | 27 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
28 | |
29 | static int pci_msi_enable = 1; | |
1da177e4 | 30 | |
1da177e4 LT |
31 | static int msi_cache_init(void) |
32 | { | |
57181784 PE |
33 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
34 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
35 | if (!msi_cachep) |
36 | return -ENOMEM; | |
37 | ||
38 | return 0; | |
39 | } | |
40 | ||
b1cbf4e4 EB |
41 | static void msi_set_enable(struct pci_dev *dev, int enable) |
42 | { | |
43 | int pos; | |
44 | u16 control; | |
45 | ||
46 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
47 | if (pos) { | |
48 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
49 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
50 | if (enable) | |
51 | control |= PCI_MSI_FLAGS_ENABLE; | |
52 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
53 | } | |
54 | } | |
55 | ||
56 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
57 | { | |
58 | int pos; | |
59 | u16 control; | |
60 | ||
61 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
62 | if (pos) { | |
63 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
64 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
65 | if (enable) | |
66 | control |= PCI_MSIX_FLAGS_ENABLE; | |
67 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
68 | } | |
69 | } | |
70 | ||
1ce03373 | 71 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
72 | { |
73 | struct msi_desc *entry; | |
74 | ||
5b912c10 | 75 | entry = get_irq_msi(irq); |
277bc33b | 76 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
77 | switch (entry->msi_attrib.type) { |
78 | case PCI_CAP_ID_MSI: | |
277bc33b | 79 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
80 | int pos; |
81 | u32 mask_bits; | |
277bc33b EB |
82 | |
83 | pos = (long)entry->mask_base; | |
84 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
85 | mask_bits &= ~(1); | |
86 | mask_bits |= flag; | |
87 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
88 | } else { |
89 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 90 | } |
1da177e4 | 91 | break; |
1da177e4 LT |
92 | case PCI_CAP_ID_MSIX: |
93 | { | |
94 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
95 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
96 | writel(flag, entry->mask_base + offset); | |
97 | break; | |
98 | } | |
99 | default: | |
277bc33b | 100 | BUG(); |
1da177e4 LT |
101 | break; |
102 | } | |
103 | } | |
104 | ||
3b7d1921 | 105 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 106 | { |
5b912c10 | 107 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
108 | switch(entry->msi_attrib.type) { |
109 | case PCI_CAP_ID_MSI: | |
110 | { | |
111 | struct pci_dev *dev = entry->dev; | |
112 | int pos = entry->msi_attrib.pos; | |
113 | u16 data; | |
114 | ||
115 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
116 | &msg->address_lo); | |
117 | if (entry->msi_attrib.is_64) { | |
118 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
119 | &msg->address_hi); | |
120 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
121 | } else { | |
122 | msg->address_hi = 0; | |
123 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
124 | } | |
125 | msg->data = data; | |
126 | break; | |
127 | } | |
128 | case PCI_CAP_ID_MSIX: | |
129 | { | |
130 | void __iomem *base; | |
131 | base = entry->mask_base + | |
132 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
133 | ||
134 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
135 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
136 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
137 | break; | |
138 | } | |
139 | default: | |
140 | BUG(); | |
141 | } | |
142 | } | |
1da177e4 | 143 | |
3b7d1921 | 144 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 145 | { |
5b912c10 | 146 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
147 | switch (entry->msi_attrib.type) { |
148 | case PCI_CAP_ID_MSI: | |
149 | { | |
0366f8f7 EB |
150 | struct pci_dev *dev = entry->dev; |
151 | int pos = entry->msi_attrib.pos; | |
152 | ||
153 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
154 | msg->address_lo); | |
155 | if (entry->msi_attrib.is_64) { | |
156 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
157 | msg->address_hi); | |
158 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
159 | msg->data); | |
160 | } else { | |
161 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
162 | msg->data); | |
163 | } | |
1da177e4 LT |
164 | break; |
165 | } | |
166 | case PCI_CAP_ID_MSIX: | |
167 | { | |
0366f8f7 EB |
168 | void __iomem *base; |
169 | base = entry->mask_base + | |
170 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
171 | ||
172 | writel(msg->address_lo, | |
173 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
174 | writel(msg->address_hi, | |
175 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
176 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
177 | break; |
178 | } | |
179 | default: | |
0366f8f7 | 180 | BUG(); |
1da177e4 LT |
181 | } |
182 | } | |
0366f8f7 | 183 | |
3b7d1921 | 184 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 185 | { |
1ce03373 | 186 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
187 | } |
188 | ||
3b7d1921 | 189 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 190 | { |
1ce03373 | 191 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
192 | } |
193 | ||
1ce03373 | 194 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 195 | |
1da177e4 LT |
196 | static int msi_init(void) |
197 | { | |
198 | static int status = -ENOMEM; | |
199 | ||
200 | if (!status) | |
201 | return status; | |
202 | ||
b64c05e7 GG |
203 | status = msi_cache_init(); |
204 | if (status < 0) { | |
1da177e4 LT |
205 | pci_msi_enable = 0; |
206 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
207 | return status; | |
208 | } | |
fd58e55f | 209 | |
1da177e4 LT |
210 | return status; |
211 | } | |
212 | ||
1da177e4 LT |
213 | static struct msi_desc* alloc_msi_entry(void) |
214 | { | |
215 | struct msi_desc *entry; | |
216 | ||
57181784 | 217 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
218 | if (!entry) |
219 | return NULL; | |
220 | ||
1da177e4 LT |
221 | entry->link.tail = entry->link.head = 0; /* single message */ |
222 | entry->dev = NULL; | |
223 | ||
224 | return entry; | |
225 | } | |
226 | ||
41017f0c | 227 | #ifdef CONFIG_PM |
8fed4b65 | 228 | static int __pci_save_msi_state(struct pci_dev *dev) |
41017f0c SL |
229 | { |
230 | int pos, i = 0; | |
231 | u16 control; | |
232 | struct pci_cap_saved_state *save_state; | |
233 | u32 *cap; | |
234 | ||
b1cbf4e4 | 235 | if (!dev->msi_enabled) |
41017f0c SL |
236 | return 0; |
237 | ||
b1cbf4e4 EB |
238 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
239 | if (pos <= 0) | |
41017f0c SL |
240 | return 0; |
241 | ||
242 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
243 | GFP_KERNEL); | |
244 | if (!save_state) { | |
245 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
246 | return -ENOMEM; | |
247 | } | |
248 | cap = &save_state->data[0]; | |
249 | ||
250 | pci_read_config_dword(dev, pos, &cap[i++]); | |
251 | control = cap[0] >> 16; | |
252 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
253 | if (control & PCI_MSI_FLAGS_64BIT) { | |
254 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
255 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
256 | } else | |
257 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
258 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
259 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
260 | save_state->cap_nr = PCI_CAP_ID_MSI; |
261 | pci_add_saved_cap(dev, save_state); | |
262 | return 0; | |
263 | } | |
264 | ||
8fed4b65 | 265 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c SL |
266 | { |
267 | int i = 0, pos; | |
268 | u16 control; | |
269 | struct pci_cap_saved_state *save_state; | |
270 | u32 *cap; | |
271 | ||
b1cbf4e4 EB |
272 | if (!dev->msi_enabled) |
273 | return; | |
274 | ||
41017f0c SL |
275 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); |
276 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
277 | if (!save_state || pos <= 0) | |
278 | return; | |
279 | cap = &save_state->data[0]; | |
280 | ||
b1cbf4e4 | 281 | pci_intx(dev, 0); /* disable intx */ |
41017f0c | 282 | control = cap[i++] >> 16; |
b1cbf4e4 | 283 | msi_set_enable(dev, 0); |
41017f0c SL |
284 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); |
285 | if (control & PCI_MSI_FLAGS_64BIT) { | |
286 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
287 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
288 | } else | |
289 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
290 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
291 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
292 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
41017f0c SL |
293 | pci_remove_saved_cap(save_state); |
294 | kfree(save_state); | |
295 | } | |
296 | ||
8fed4b65 | 297 | static int __pci_save_msix_state(struct pci_dev *dev) |
41017f0c SL |
298 | { |
299 | int pos; | |
1ce03373 | 300 | int irq, head, tail = 0; |
41017f0c SL |
301 | u16 control; |
302 | struct pci_cap_saved_state *save_state; | |
303 | ||
ded86d8d EB |
304 | if (!dev->msix_enabled) |
305 | return 0; | |
306 | ||
41017f0c | 307 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
b1cbf4e4 | 308 | if (pos <= 0) |
41017f0c SL |
309 | return 0; |
310 | ||
fd58e55f | 311 | /* save the capability */ |
41017f0c | 312 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
41017f0c SL |
313 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), |
314 | GFP_KERNEL); | |
315 | if (!save_state) { | |
316 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
317 | return -ENOMEM; | |
318 | } | |
319 | *((u16 *)&save_state->data[0]) = control; | |
320 | ||
fd58e55f | 321 | /* save the table */ |
ded86d8d | 322 | irq = head = dev->first_msi_irq; |
fd58e55f | 323 | while (head != tail) { |
fd58e55f MM |
324 | struct msi_desc *entry; |
325 | ||
5b912c10 | 326 | entry = get_irq_msi(irq); |
3b7d1921 | 327 | read_msi_msg(irq, &entry->msg_save); |
fd58e55f | 328 | |
5b912c10 | 329 | tail = entry->link.tail; |
1ce03373 | 330 | irq = tail; |
fd58e55f | 331 | } |
fd58e55f | 332 | |
41017f0c SL |
333 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
334 | pci_add_saved_cap(dev, save_state); | |
335 | return 0; | |
336 | } | |
337 | ||
8fed4b65 ME |
338 | int pci_save_msi_state(struct pci_dev *dev) |
339 | { | |
340 | int rc; | |
341 | ||
342 | rc = __pci_save_msi_state(dev); | |
343 | if (rc) | |
344 | return rc; | |
345 | ||
346 | rc = __pci_save_msix_state(dev); | |
347 | ||
348 | return rc; | |
349 | } | |
350 | ||
351 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c SL |
352 | { |
353 | u16 save; | |
354 | int pos; | |
1ce03373 | 355 | int irq, head, tail = 0; |
41017f0c | 356 | struct msi_desc *entry; |
41017f0c SL |
357 | struct pci_cap_saved_state *save_state; |
358 | ||
ded86d8d EB |
359 | if (!dev->msix_enabled) |
360 | return; | |
361 | ||
41017f0c SL |
362 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); |
363 | if (!save_state) | |
364 | return; | |
365 | save = *((u16 *)&save_state->data[0]); | |
366 | pci_remove_saved_cap(save_state); | |
367 | kfree(save_state); | |
368 | ||
369 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
370 | if (pos <= 0) | |
371 | return; | |
372 | ||
373 | /* route the table */ | |
b1cbf4e4 EB |
374 | pci_intx(dev, 0); /* disable intx */ |
375 | msix_set_enable(dev, 0); | |
ded86d8d | 376 | irq = head = dev->first_msi_irq; |
41017f0c | 377 | while (head != tail) { |
5b912c10 | 378 | entry = get_irq_msi(irq); |
3b7d1921 | 379 | write_msi_msg(irq, &entry->msg_save); |
41017f0c | 380 | |
5b912c10 | 381 | tail = entry->link.tail; |
1ce03373 | 382 | irq = tail; |
41017f0c | 383 | } |
41017f0c SL |
384 | |
385 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
41017f0c | 386 | } |
8fed4b65 ME |
387 | |
388 | void pci_restore_msi_state(struct pci_dev *dev) | |
389 | { | |
390 | __pci_restore_msi_state(dev); | |
391 | __pci_restore_msix_state(dev); | |
392 | } | |
c54c1879 | 393 | #endif /* CONFIG_PM */ |
41017f0c | 394 | |
1da177e4 LT |
395 | /** |
396 | * msi_capability_init - configure device's MSI capability structure | |
397 | * @dev: pointer to the pci_dev data structure of MSI device function | |
398 | * | |
eaae4b3a | 399 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 400 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 401 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 402 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
403 | **/ |
404 | static int msi_capability_init(struct pci_dev *dev) | |
405 | { | |
406 | struct msi_desc *entry; | |
1ce03373 | 407 | int pos, irq; |
1da177e4 LT |
408 | u16 control; |
409 | ||
b1cbf4e4 EB |
410 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
411 | ||
1da177e4 LT |
412 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
413 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
414 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
415 | entry = alloc_msi_entry(); |
416 | if (!entry) | |
417 | return -ENOMEM; | |
1ce03373 | 418 | |
1da177e4 | 419 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 420 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
421 | entry->msi_attrib.entry_nr = 0; |
422 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 423 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 424 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
425 | if (is_mask_bit_support(control)) { |
426 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
427 | is_64bit_address(control)); | |
428 | } | |
3b7d1921 EB |
429 | entry->dev = dev; |
430 | if (entry->msi_attrib.maskbit) { | |
431 | unsigned int maskbits, temp; | |
432 | /* All MSIs are unmasked by default, Mask them all */ | |
433 | pci_read_config_dword(dev, | |
434 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
435 | &maskbits); | |
436 | temp = (1 << multi_msi_capable(control)); | |
437 | temp = ((temp - 1) & ~temp); | |
438 | maskbits |= temp; | |
439 | pci_write_config_dword(dev, | |
440 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
441 | maskbits); | |
442 | } | |
1da177e4 | 443 | /* Configure MSI capability structure */ |
f7feaca7 EB |
444 | irq = arch_setup_msi_irq(dev, entry); |
445 | if (irq < 0) { | |
446 | kmem_cache_free(msi_cachep, entry); | |
447 | return irq; | |
fd58e55f | 448 | } |
f7feaca7 EB |
449 | entry->link.head = irq; |
450 | entry->link.tail = irq; | |
ded86d8d | 451 | dev->first_msi_irq = irq; |
5b912c10 | 452 | set_irq_msi(irq, entry); |
f7feaca7 | 453 | |
1da177e4 | 454 | /* Set MSI enabled bits */ |
b1cbf4e4 EB |
455 | pci_intx(dev, 0); /* disable intx */ |
456 | msi_set_enable(dev, 1); | |
457 | dev->msi_enabled = 1; | |
1da177e4 | 458 | |
3b7d1921 | 459 | dev->irq = irq; |
1da177e4 LT |
460 | return 0; |
461 | } | |
462 | ||
463 | /** | |
464 | * msix_capability_init - configure device's MSI-X capability | |
465 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
466 | * @entries: pointer to an array of struct msix_entry entries |
467 | * @nvec: number of @entries | |
1da177e4 | 468 | * |
eaae4b3a | 469 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
470 | * single MSI-X irq. A return of zero indicates the successful setup of |
471 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
472 | **/ |
473 | static int msix_capability_init(struct pci_dev *dev, | |
474 | struct msix_entry *entries, int nvec) | |
475 | { | |
476 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
1ce03373 | 477 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
478 | unsigned long phys_addr; |
479 | u32 table_offset; | |
1da177e4 LT |
480 | u16 control; |
481 | u8 bir; | |
482 | void __iomem *base; | |
483 | ||
b1cbf4e4 EB |
484 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
485 | ||
1da177e4 LT |
486 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
487 | /* Request & Map MSI-X table region */ | |
488 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
489 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
490 | |
491 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 492 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
493 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
494 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
495 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
496 | if (base == NULL) | |
497 | return -ENOMEM; | |
498 | ||
499 | /* MSI-X Table Initialization */ | |
500 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
501 | entry = alloc_msi_entry(); |
502 | if (!entry) | |
1da177e4 | 503 | break; |
1da177e4 LT |
504 | |
505 | j = entries[i].entry; | |
1da177e4 | 506 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 507 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
508 | entry->msi_attrib.entry_nr = j; |
509 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 510 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 511 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
512 | entry->dev = dev; |
513 | entry->mask_base = base; | |
f7feaca7 EB |
514 | |
515 | /* Configure MSI-X capability structure */ | |
516 | irq = arch_setup_msi_irq(dev, entry); | |
517 | if (irq < 0) { | |
518 | kmem_cache_free(msi_cachep, entry); | |
519 | break; | |
520 | } | |
521 | entries[i].vector = irq; | |
1da177e4 | 522 | if (!head) { |
1ce03373 EB |
523 | entry->link.head = irq; |
524 | entry->link.tail = irq; | |
1da177e4 LT |
525 | head = entry; |
526 | } else { | |
527 | entry->link.head = temp; | |
528 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
529 | tail->link.tail = irq; |
530 | head->link.head = irq; | |
1da177e4 | 531 | } |
1ce03373 | 532 | temp = irq; |
1da177e4 | 533 | tail = entry; |
fd58e55f | 534 | |
5b912c10 | 535 | set_irq_msi(irq, entry); |
1da177e4 LT |
536 | } |
537 | if (i != nvec) { | |
92db6d10 | 538 | int avail = i - 1; |
1da177e4 LT |
539 | i--; |
540 | for (; i >= 0; i--) { | |
1ce03373 EB |
541 | irq = (entries + i)->vector; |
542 | msi_free_irq(dev, irq); | |
1da177e4 LT |
543 | (entries + i)->vector = 0; |
544 | } | |
92db6d10 EB |
545 | /* If we had some success report the number of irqs |
546 | * we succeeded in setting up. | |
547 | */ | |
548 | if (avail <= 0) | |
549 | avail = -EBUSY; | |
550 | return avail; | |
1da177e4 | 551 | } |
ded86d8d | 552 | dev->first_msi_irq = entries[0].vector; |
1da177e4 | 553 | /* Set MSI-X enabled bits */ |
b1cbf4e4 EB |
554 | pci_intx(dev, 0); /* disable intx */ |
555 | msix_set_enable(dev, 1); | |
556 | dev->msix_enabled = 1; | |
1da177e4 LT |
557 | |
558 | return 0; | |
559 | } | |
560 | ||
24334a12 BG |
561 | /** |
562 | * pci_msi_supported - check whether MSI may be enabled on device | |
563 | * @dev: pointer to the pci_dev data structure of MSI device function | |
564 | * | |
0306ebfa BG |
565 | * Look at global flags, the device itself, and its parent busses |
566 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
567 | **/ |
568 | static | |
569 | int pci_msi_supported(struct pci_dev * dev) | |
570 | { | |
571 | struct pci_bus *bus; | |
572 | ||
0306ebfa | 573 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
574 | if (!pci_msi_enable || !dev || dev->no_msi) |
575 | return -EINVAL; | |
576 | ||
0306ebfa BG |
577 | /* Any bridge which does NOT route MSI transactions from it's |
578 | * secondary bus to it's primary bus must set NO_MSI flag on | |
579 | * the secondary pci_bus. | |
580 | * We expect only arch-specific PCI host bus controller driver | |
581 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
582 | */ | |
24334a12 BG |
583 | for (bus = dev->bus; bus; bus = bus->parent) |
584 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
585 | return -EINVAL; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
1da177e4 LT |
590 | /** |
591 | * pci_enable_msi - configure device's MSI capability structure | |
592 | * @dev: pointer to the pci_dev data structure of MSI device function | |
593 | * | |
594 | * Setup the MSI capability structure of device function with | |
1ce03373 | 595 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
596 | * MSI mode enabled on its hardware device function. A return of zero |
597 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 598 | * irq or non-zero for otherwise. |
1da177e4 LT |
599 | **/ |
600 | int pci_enable_msi(struct pci_dev* dev) | |
601 | { | |
ded86d8d | 602 | int pos, status; |
1da177e4 | 603 | |
24334a12 BG |
604 | if (pci_msi_supported(dev) < 0) |
605 | return -EINVAL; | |
6e325a62 | 606 | |
b64c05e7 GG |
607 | status = msi_init(); |
608 | if (status < 0) | |
1da177e4 LT |
609 | return status; |
610 | ||
b64c05e7 GG |
611 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
612 | if (!pos) | |
1da177e4 LT |
613 | return -EINVAL; |
614 | ||
ded86d8d | 615 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 616 | |
1ce03373 | 617 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
618 | if (dev->msix_enabled) { |
619 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
620 | "Device already has MSI-X enabled\n", | |
621 | pci_name(dev)); | |
622 | return -EINVAL; | |
1da177e4 LT |
623 | } |
624 | status = msi_capability_init(dev); | |
1da177e4 LT |
625 | return status; |
626 | } | |
627 | ||
628 | void pci_disable_msi(struct pci_dev* dev) | |
629 | { | |
630 | struct msi_desc *entry; | |
b1cbf4e4 | 631 | int default_irq; |
1da177e4 | 632 | |
309e57df MW |
633 | if (!pci_msi_enable) |
634 | return; | |
b64c05e7 GG |
635 | if (!dev) |
636 | return; | |
309e57df | 637 | |
ded86d8d EB |
638 | if (!dev->msi_enabled) |
639 | return; | |
640 | ||
b1cbf4e4 EB |
641 | msi_set_enable(dev, 0); |
642 | pci_intx(dev, 1); /* enable intx */ | |
643 | dev->msi_enabled = 0; | |
7bd007e4 | 644 | |
5b912c10 | 645 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 646 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
647 | return; |
648 | } | |
ded86d8d | 649 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 650 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " |
1ce03373 | 651 | "free_irq() on MSI irq %d\n", |
ded86d8d EB |
652 | pci_name(dev), dev->first_msi_irq); |
653 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1da177e4 | 654 | } else { |
1ce03373 | 655 | default_irq = entry->msi_attrib.default_irq; |
ded86d8d | 656 | msi_free_irq(dev, dev->first_msi_irq); |
7bd007e4 | 657 | |
1ce03373 EB |
658 | /* Restore dev->irq to its default pin-assertion irq */ |
659 | dev->irq = default_irq; | |
1da177e4 | 660 | } |
ded86d8d | 661 | dev->first_msi_irq = 0; |
1da177e4 LT |
662 | } |
663 | ||
1ce03373 | 664 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
665 | { |
666 | struct msi_desc *entry; | |
667 | int head, entry_nr, type; | |
668 | void __iomem *base; | |
1da177e4 | 669 | |
5b912c10 | 670 | entry = get_irq_msi(irq); |
1da177e4 | 671 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
672 | return -EINVAL; |
673 | } | |
674 | type = entry->msi_attrib.type; | |
675 | entry_nr = entry->msi_attrib.entry_nr; | |
676 | head = entry->link.head; | |
677 | base = entry->mask_base; | |
5b912c10 EB |
678 | get_irq_msi(entry->link.head)->link.tail = entry->link.tail; |
679 | get_irq_msi(entry->link.tail)->link.head = entry->link.head; | |
1da177e4 | 680 | |
f7feaca7 EB |
681 | arch_teardown_msi_irq(irq); |
682 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
683 | |
684 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
685 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
686 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 687 | |
1ce03373 | 688 | if (head == irq) |
1da177e4 | 689 | iounmap(base); |
1da177e4 LT |
690 | } |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
1da177e4 LT |
695 | /** |
696 | * pci_enable_msix - configure device's MSI-X capability structure | |
697 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 698 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 699 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
700 | * |
701 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 702 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
703 | * MSI-X mode enabled on its hardware device function. A return of zero |
704 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 705 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 706 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 707 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
708 | * its request. |
709 | **/ | |
710 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
711 | { | |
92db6d10 | 712 | int status, pos, nr_entries; |
ded86d8d | 713 | int i, j; |
1da177e4 | 714 | u16 control; |
1da177e4 | 715 | |
24334a12 | 716 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
717 | return -EINVAL; |
718 | ||
b64c05e7 GG |
719 | status = msi_init(); |
720 | if (status < 0) | |
1da177e4 LT |
721 | return status; |
722 | ||
b64c05e7 GG |
723 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
724 | if (!pos) | |
1da177e4 LT |
725 | return -EINVAL; |
726 | ||
727 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
728 | nr_entries = multi_msix_capable(control); |
729 | if (nvec > nr_entries) | |
730 | return -EINVAL; | |
731 | ||
732 | /* Check for any invalid entries */ | |
733 | for (i = 0; i < nvec; i++) { | |
734 | if (entries[i].entry >= nr_entries) | |
735 | return -EINVAL; /* invalid entry */ | |
736 | for (j = i + 1; j < nvec; j++) { | |
737 | if (entries[i].entry == entries[j].entry) | |
738 | return -EINVAL; /* duplicate entry */ | |
739 | } | |
740 | } | |
ded86d8d | 741 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 742 | |
1ce03373 | 743 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 744 | if (dev->msi_enabled) { |
1da177e4 | 745 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 746 | "Device already has an MSI irq assigned\n", |
1da177e4 | 747 | pci_name(dev)); |
1da177e4 LT |
748 | return -EINVAL; |
749 | } | |
1da177e4 | 750 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
751 | return status; |
752 | } | |
753 | ||
754 | void pci_disable_msix(struct pci_dev* dev) | |
755 | { | |
ded86d8d | 756 | int irq, head, tail = 0, warning = 0; |
1da177e4 | 757 | |
309e57df MW |
758 | if (!pci_msi_enable) |
759 | return; | |
b64c05e7 GG |
760 | if (!dev) |
761 | return; | |
762 | ||
ded86d8d EB |
763 | if (!dev->msix_enabled) |
764 | return; | |
765 | ||
b1cbf4e4 EB |
766 | msix_set_enable(dev, 0); |
767 | pci_intx(dev, 1); /* enable intx */ | |
768 | dev->msix_enabled = 0; | |
7bd007e4 | 769 | |
ded86d8d EB |
770 | irq = head = dev->first_msi_irq; |
771 | while (head != tail) { | |
5b912c10 | 772 | tail = get_irq_msi(irq)->link.tail; |
ded86d8d EB |
773 | if (irq_has_action(irq)) |
774 | warning = 1; | |
775 | else if (irq != head) /* Release MSI-X irq */ | |
776 | msi_free_irq(dev, irq); | |
777 | irq = tail; | |
778 | } | |
779 | msi_free_irq(dev, irq); | |
780 | if (warning) { | |
781 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
782 | "free_irq() on all MSI-X irqs\n", | |
783 | pci_name(dev)); | |
784 | BUG_ON(warning > 0); | |
1da177e4 | 785 | } |
ded86d8d | 786 | dev->first_msi_irq = 0; |
1da177e4 LT |
787 | } |
788 | ||
789 | /** | |
1ce03373 | 790 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
791 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
792 | * | |
eaae4b3a | 793 | * Being called during hotplug remove, from which the device function |
1ce03373 | 794 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
795 | * allocated for this device function, are reclaimed to unused state, |
796 | * which may be used later on. | |
797 | **/ | |
798 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
799 | { | |
1da177e4 LT |
800 | if (!pci_msi_enable || !dev) |
801 | return; | |
802 | ||
866a8c87 | 803 | if (dev->msi_enabled) { |
ded86d8d | 804 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 805 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 806 | "called without free_irq() on MSI irq %d\n", |
ded86d8d EB |
807 | pci_name(dev), dev->first_msi_irq); |
808 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1ce03373 | 809 | } else /* Release MSI irq assigned to this device */ |
ded86d8d | 810 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 811 | } |
866a8c87 | 812 | if (dev->msix_enabled) { |
1ce03373 | 813 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
814 | void __iomem *base = NULL; |
815 | ||
ded86d8d | 816 | irq = head = dev->first_msi_irq; |
1da177e4 | 817 | while (head != tail) { |
5b912c10 EB |
818 | tail = get_irq_msi(irq)->link.tail; |
819 | base = get_irq_msi(irq)->mask_base; | |
1f80025e | 820 | if (irq_has_action(irq)) |
1da177e4 | 821 | warning = 1; |
1ce03373 EB |
822 | else if (irq != head) /* Release MSI-X irq */ |
823 | msi_free_irq(dev, irq); | |
824 | irq = tail; | |
1da177e4 | 825 | } |
1ce03373 | 826 | msi_free_irq(dev, irq); |
1da177e4 | 827 | if (warning) { |
1da177e4 LT |
828 | iounmap(base); |
829 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 830 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
831 | pci_name(dev)); |
832 | BUG_ON(warning > 0); | |
833 | } | |
1da177e4 LT |
834 | } |
835 | } | |
836 | ||
309e57df MW |
837 | void pci_no_msi(void) |
838 | { | |
839 | pci_msi_enable = 0; | |
840 | } | |
841 | ||
1da177e4 LT |
842 | EXPORT_SYMBOL(pci_enable_msi); |
843 | EXPORT_SYMBOL(pci_disable_msi); | |
844 | EXPORT_SYMBOL(pci_enable_msix); | |
845 | EXPORT_SYMBOL(pci_disable_msix); |