Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
110828c9 | 78 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
110828c9 | 82 | BUG_ON(!pos); |
b1cbf4e4 | 83 | |
110828c9 MW |
84 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
85 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
86 | if (enable) | |
87 | control |= PCI_MSI_FLAGS_ENABLE; | |
88 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
89 | } |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
f2440d9a | 114 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 115 | { |
f2440d9a MW |
116 | return msi_mask((control >> 1) & 7); |
117 | } | |
988cbb15 | 118 | |
f2440d9a MW |
119 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
120 | { | |
121 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
122 | } |
123 | ||
ce6fce42 MW |
124 | /* |
125 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
126 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
127 | * reliably as devices without an INTx disable bit will then generate a | |
128 | * level IRQ which will never be cleared. | |
ce6fce42 | 129 | */ |
12abb8ba | 130 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 131 | { |
f2440d9a | 132 | u32 mask_bits = desc->masked; |
1da177e4 | 133 | |
f2440d9a | 134 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 135 | return 0; |
f2440d9a MW |
136 | |
137 | mask_bits &= ~mask; | |
138 | mask_bits |= flag; | |
139 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
140 | |
141 | return mask_bits; | |
142 | } | |
143 | ||
144 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
145 | { | |
146 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
147 | } |
148 | ||
149 | /* | |
150 | * This internal function does not flush PCI writes to the device. | |
151 | * All users must ensure that they read from the device before either | |
152 | * assuming that the device state is up to date, or returning out of this | |
153 | * file. This saves a few milliseconds when initialising devices with lots | |
154 | * of MSI-X interrupts. | |
155 | */ | |
12abb8ba | 156 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
157 | { |
158 | u32 mask_bits = desc->masked; | |
159 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 160 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
161 | mask_bits &= ~1; |
162 | mask_bits |= flag; | |
163 | writel(mask_bits, desc->mask_base + offset); | |
12abb8ba HS |
164 | |
165 | return mask_bits; | |
166 | } | |
167 | ||
168 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
169 | { | |
170 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 171 | } |
24d27553 | 172 | |
1c9db525 | 173 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 174 | { |
1c9db525 | 175 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 176 | |
f2440d9a MW |
177 | if (desc->msi_attrib.is_msix) { |
178 | msix_mask_irq(desc, flag); | |
179 | readl(desc->mask_base); /* Flush write to device */ | |
180 | } else { | |
1c9db525 | 181 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 182 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 183 | } |
f2440d9a MW |
184 | } |
185 | ||
1c9db525 | 186 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 187 | { |
1c9db525 | 188 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
189 | } |
190 | ||
1c9db525 | 191 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 192 | { |
1c9db525 | 193 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
194 | } |
195 | ||
39431acb | 196 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 197 | { |
30da5524 BH |
198 | BUG_ON(entry->dev->current_state != PCI_D0); |
199 | ||
200 | if (entry->msi_attrib.is_msix) { | |
201 | void __iomem *base = entry->mask_base + | |
202 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
203 | ||
204 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
205 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
206 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
207 | } else { | |
208 | struct pci_dev *dev = entry->dev; | |
209 | int pos = entry->msi_attrib.pos; | |
210 | u16 data; | |
211 | ||
212 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
213 | &msg->address_lo); | |
214 | if (entry->msi_attrib.is_64) { | |
215 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
216 | &msg->address_hi); | |
217 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
218 | } else { | |
219 | msg->address_hi = 0; | |
220 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
221 | } | |
222 | msg->data = data; | |
223 | } | |
224 | } | |
225 | ||
226 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
227 | { | |
39431acb | 228 | struct msi_desc *entry = get_irq_msi(irq); |
30da5524 | 229 | |
39431acb | 230 | __read_msi_msg(entry, msg); |
30da5524 BH |
231 | } |
232 | ||
39431acb | 233 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 234 | { |
30da5524 | 235 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
236 | * valid messages are not all-zeroes. */ |
237 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
238 | entry->msg.data)); | |
0366f8f7 | 239 | |
fcd097f3 | 240 | *msg = entry->msg; |
0366f8f7 | 241 | } |
1da177e4 | 242 | |
30da5524 | 243 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 244 | { |
39431acb | 245 | struct msi_desc *entry = get_irq_msi(irq); |
3145e941 | 246 | |
39431acb | 247 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
248 | } |
249 | ||
39431acb | 250 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 251 | { |
fcd097f3 BH |
252 | if (entry->dev->current_state != PCI_D0) { |
253 | /* Don't touch the hardware now */ | |
254 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
255 | void __iomem *base; |
256 | base = entry->mask_base + | |
257 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
258 | ||
2c21fd4b HS |
259 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
260 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
261 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 262 | } else { |
0366f8f7 EB |
263 | struct pci_dev *dev = entry->dev; |
264 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
265 | u16 msgctl; |
266 | ||
267 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
268 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
269 | msgctl |= entry->msi_attrib.multiple << 4; | |
270 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
271 | |
272 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
273 | msg->address_lo); | |
274 | if (entry->msi_attrib.is_64) { | |
275 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
276 | msg->address_hi); | |
277 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
278 | msg->data); | |
279 | } else { | |
280 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
281 | msg->data); | |
282 | } | |
1da177e4 | 283 | } |
392ee1e6 | 284 | entry->msg = *msg; |
1da177e4 | 285 | } |
0366f8f7 | 286 | |
3145e941 YL |
287 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
288 | { | |
39431acb | 289 | struct msi_desc *entry = get_irq_msi(irq); |
3145e941 | 290 | |
39431acb | 291 | __write_msi_msg(entry, msg); |
3145e941 YL |
292 | } |
293 | ||
f56e4481 HS |
294 | static void free_msi_irqs(struct pci_dev *dev) |
295 | { | |
296 | struct msi_desc *entry, *tmp; | |
297 | ||
298 | list_for_each_entry(entry, &dev->msi_list, list) { | |
299 | int i, nvec; | |
300 | if (!entry->irq) | |
301 | continue; | |
302 | nvec = 1 << entry->msi_attrib.multiple; | |
303 | for (i = 0; i < nvec; i++) | |
304 | BUG_ON(irq_has_action(entry->irq + i)); | |
305 | } | |
306 | ||
307 | arch_teardown_msi_irqs(dev); | |
308 | ||
309 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
310 | if (entry->msi_attrib.is_msix) { | |
311 | if (list_is_last(&entry->list, &dev->msi_list)) | |
312 | iounmap(entry->mask_base); | |
313 | } | |
314 | list_del(&entry->list); | |
315 | kfree(entry); | |
316 | } | |
317 | } | |
c54c1879 | 318 | |
379f5327 | 319 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 320 | { |
379f5327 MW |
321 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
322 | if (!desc) | |
1da177e4 LT |
323 | return NULL; |
324 | ||
379f5327 MW |
325 | INIT_LIST_HEAD(&desc->list); |
326 | desc->dev = dev; | |
1da177e4 | 327 | |
379f5327 | 328 | return desc; |
1da177e4 LT |
329 | } |
330 | ||
ba698ad4 DM |
331 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
332 | { | |
333 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
334 | pci_intx(dev, enable); | |
335 | } | |
336 | ||
8fed4b65 | 337 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 338 | { |
392ee1e6 | 339 | int pos; |
41017f0c | 340 | u16 control; |
392ee1e6 | 341 | struct msi_desc *entry; |
41017f0c | 342 | |
b1cbf4e4 EB |
343 | if (!dev->msi_enabled) |
344 | return; | |
345 | ||
392ee1e6 EB |
346 | entry = get_irq_msi(dev->irq); |
347 | pos = entry->msi_attrib.pos; | |
41017f0c | 348 | |
ba698ad4 | 349 | pci_intx_for_msi(dev, 0); |
110828c9 | 350 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 351 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
352 | |
353 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 354 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 355 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 356 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 357 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
358 | } |
359 | ||
360 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 361 | { |
41017f0c | 362 | int pos; |
41017f0c | 363 | struct msi_desc *entry; |
392ee1e6 | 364 | u16 control; |
41017f0c | 365 | |
ded86d8d EB |
366 | if (!dev->msix_enabled) |
367 | return; | |
f598282f | 368 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 369 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
370 | pos = entry->msi_attrib.pos; |
371 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 372 | |
41017f0c | 373 | /* route the table */ |
ba698ad4 | 374 | pci_intx_for_msi(dev, 0); |
f598282f MW |
375 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
376 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 377 | |
4aa9bc95 ME |
378 | list_for_each_entry(entry, &dev->msi_list, list) { |
379 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 380 | msix_mask_irq(entry, entry->masked); |
41017f0c | 381 | } |
41017f0c | 382 | |
392ee1e6 | 383 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 384 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 385 | } |
8fed4b65 ME |
386 | |
387 | void pci_restore_msi_state(struct pci_dev *dev) | |
388 | { | |
389 | __pci_restore_msi_state(dev); | |
390 | __pci_restore_msix_state(dev); | |
391 | } | |
94688cf2 | 392 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 393 | |
1da177e4 LT |
394 | /** |
395 | * msi_capability_init - configure device's MSI capability structure | |
396 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 397 | * @nvec: number of interrupts to allocate |
1da177e4 | 398 | * |
1c8d7b0a MW |
399 | * Setup the MSI capability structure of the device with the requested |
400 | * number of interrupts. A return value of zero indicates the successful | |
401 | * setup of an entry with the new MSI irq. A negative return value indicates | |
402 | * an error, and a positive return value indicates the number of interrupts | |
403 | * which could have been allocated. | |
404 | */ | |
405 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
406 | { |
407 | struct msi_desc *entry; | |
7fe3730d | 408 | int pos, ret; |
1da177e4 | 409 | u16 control; |
f2440d9a | 410 | unsigned mask; |
1da177e4 | 411 | |
500559a9 | 412 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
413 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
414 | ||
1da177e4 LT |
415 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
416 | /* MSI Entry Initialization */ | |
379f5327 | 417 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
418 | if (!entry) |
419 | return -ENOMEM; | |
1ce03373 | 420 | |
500559a9 HS |
421 | entry->msi_attrib.is_msix = 0; |
422 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
423 | entry->msi_attrib.entry_nr = 0; | |
424 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
425 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
426 | entry->msi_attrib.pos = pos; | |
f2440d9a | 427 | |
67b5db65 | 428 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
429 | /* All MSIs are unmasked by default, Mask them all */ |
430 | if (entry->msi_attrib.maskbit) | |
431 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
432 | mask = msi_capable_mask(control); | |
433 | msi_mask_irq(entry, mask, mask); | |
434 | ||
0dd11f9b | 435 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 436 | |
1da177e4 | 437 | /* Configure MSI capability structure */ |
1c8d7b0a | 438 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 439 | if (ret) { |
7ba1930d | 440 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 441 | free_msi_irqs(dev); |
7fe3730d | 442 | return ret; |
fd58e55f | 443 | } |
f7feaca7 | 444 | |
1da177e4 | 445 | /* Set MSI enabled bits */ |
ba698ad4 | 446 | pci_intx_for_msi(dev, 0); |
110828c9 | 447 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 448 | dev->msi_enabled = 1; |
1da177e4 | 449 | |
7fe3730d | 450 | dev->irq = entry->irq; |
1da177e4 LT |
451 | return 0; |
452 | } | |
453 | ||
5a05a9d8 HS |
454 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
455 | unsigned nr_entries) | |
456 | { | |
4302e0fb | 457 | resource_size_t phys_addr; |
5a05a9d8 HS |
458 | u32 table_offset; |
459 | u8 bir; | |
460 | ||
461 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
462 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
463 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
464 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
465 | ||
466 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
467 | } | |
468 | ||
d9d7070e HS |
469 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
470 | void __iomem *base, struct msix_entry *entries, | |
471 | int nvec) | |
472 | { | |
473 | struct msi_desc *entry; | |
474 | int i; | |
475 | ||
476 | for (i = 0; i < nvec; i++) { | |
477 | entry = alloc_msi_entry(dev); | |
478 | if (!entry) { | |
479 | if (!i) | |
480 | iounmap(base); | |
481 | else | |
482 | free_msi_irqs(dev); | |
483 | /* No enough memory. Don't try again */ | |
484 | return -ENOMEM; | |
485 | } | |
486 | ||
487 | entry->msi_attrib.is_msix = 1; | |
488 | entry->msi_attrib.is_64 = 1; | |
489 | entry->msi_attrib.entry_nr = entries[i].entry; | |
490 | entry->msi_attrib.default_irq = dev->irq; | |
491 | entry->msi_attrib.pos = pos; | |
492 | entry->mask_base = base; | |
493 | ||
494 | list_add_tail(&entry->list, &dev->msi_list); | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
75cb3426 HS |
500 | static void msix_program_entries(struct pci_dev *dev, |
501 | struct msix_entry *entries) | |
502 | { | |
503 | struct msi_desc *entry; | |
504 | int i = 0; | |
505 | ||
506 | list_for_each_entry(entry, &dev->msi_list, list) { | |
507 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
508 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
509 | ||
510 | entries[i].vector = entry->irq; | |
511 | set_irq_msi(entry->irq, entry); | |
512 | entry->masked = readl(entry->mask_base + offset); | |
513 | msix_mask_irq(entry, 1); | |
514 | i++; | |
515 | } | |
516 | } | |
517 | ||
1da177e4 LT |
518 | /** |
519 | * msix_capability_init - configure device's MSI-X capability | |
520 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
521 | * @entries: pointer to an array of struct msix_entry entries |
522 | * @nvec: number of @entries | |
1da177e4 | 523 | * |
eaae4b3a | 524 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
525 | * single MSI-X irq. A return of zero indicates the successful setup of |
526 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
527 | **/ |
528 | static int msix_capability_init(struct pci_dev *dev, | |
529 | struct msix_entry *entries, int nvec) | |
530 | { | |
d9d7070e | 531 | int pos, ret; |
5a05a9d8 | 532 | u16 control; |
1da177e4 LT |
533 | void __iomem *base; |
534 | ||
500559a9 | 535 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
536 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
537 | ||
538 | /* Ensure MSI-X is disabled while it is set up */ | |
539 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
540 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
541 | ||
1da177e4 | 542 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
543 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
544 | if (!base) | |
1da177e4 LT |
545 | return -ENOMEM; |
546 | ||
d9d7070e HS |
547 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
548 | if (ret) | |
549 | return ret; | |
9c831334 ME |
550 | |
551 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
552 | if (ret) |
553 | goto error; | |
9c831334 | 554 | |
f598282f MW |
555 | /* |
556 | * Some devices require MSI-X to be enabled before we can touch the | |
557 | * MSI-X registers. We need to mask all the vectors to prevent | |
558 | * interrupts coming in before they're fully set up. | |
559 | */ | |
560 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
561 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
562 | ||
75cb3426 | 563 | msix_program_entries(dev, entries); |
f598282f MW |
564 | |
565 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 566 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 567 | dev->msix_enabled = 1; |
1da177e4 | 568 | |
f598282f MW |
569 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
570 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 571 | |
1da177e4 | 572 | return 0; |
583871d4 HS |
573 | |
574 | error: | |
575 | if (ret < 0) { | |
576 | /* | |
577 | * If we had some success, report the number of irqs | |
578 | * we succeeded in setting up. | |
579 | */ | |
d9d7070e | 580 | struct msi_desc *entry; |
583871d4 HS |
581 | int avail = 0; |
582 | ||
583 | list_for_each_entry(entry, &dev->msi_list, list) { | |
584 | if (entry->irq != 0) | |
585 | avail++; | |
586 | } | |
587 | if (avail != 0) | |
588 | ret = avail; | |
589 | } | |
590 | ||
591 | free_msi_irqs(dev); | |
592 | ||
593 | return ret; | |
1da177e4 LT |
594 | } |
595 | ||
24334a12 | 596 | /** |
17bbc12a | 597 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 598 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 599 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 600 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 601 | * |
0306ebfa | 602 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
603 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
604 | * supported return 0, else return an error code. | |
24334a12 | 605 | **/ |
500559a9 | 606 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
607 | { |
608 | struct pci_bus *bus; | |
c9953a73 | 609 | int ret; |
24334a12 | 610 | |
0306ebfa | 611 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
612 | if (!pci_msi_enable || !dev || dev->no_msi) |
613 | return -EINVAL; | |
614 | ||
314e77b3 ME |
615 | /* |
616 | * You can't ask to have 0 or less MSIs configured. | |
617 | * a) it's stupid .. | |
618 | * b) the list manipulation code assumes nvec >= 1. | |
619 | */ | |
620 | if (nvec < 1) | |
621 | return -ERANGE; | |
622 | ||
500559a9 HS |
623 | /* |
624 | * Any bridge which does NOT route MSI transactions from its | |
625 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
626 | * the secondary pci_bus. |
627 | * We expect only arch-specific PCI host bus controller driver | |
628 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
629 | */ | |
24334a12 BG |
630 | for (bus = dev->bus; bus; bus = bus->parent) |
631 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
632 | return -EINVAL; | |
633 | ||
c9953a73 ME |
634 | ret = arch_msi_check_device(dev, nvec, type); |
635 | if (ret) | |
636 | return ret; | |
637 | ||
b1e2303d ME |
638 | if (!pci_find_capability(dev, type)) |
639 | return -EINVAL; | |
640 | ||
24334a12 BG |
641 | return 0; |
642 | } | |
643 | ||
1da177e4 | 644 | /** |
1c8d7b0a MW |
645 | * pci_enable_msi_block - configure device's MSI capability structure |
646 | * @dev: device to configure | |
647 | * @nvec: number of interrupts to configure | |
1da177e4 | 648 | * |
1c8d7b0a MW |
649 | * Allocate IRQs for a device with the MSI capability. |
650 | * This function returns a negative errno if an error occurs. If it | |
651 | * is unable to allocate the number of interrupts requested, it returns | |
652 | * the number of interrupts it might be able to allocate. If it successfully | |
653 | * allocates at least the number of interrupts requested, it returns 0 and | |
654 | * updates the @dev's irq member to the lowest new interrupt number; the | |
655 | * other interrupt numbers allocated to this device are consecutive. | |
656 | */ | |
657 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 658 | { |
1c8d7b0a MW |
659 | int status, pos, maxvec; |
660 | u16 msgctl; | |
661 | ||
662 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
663 | if (!pos) | |
664 | return -EINVAL; | |
665 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
666 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
667 | if (nvec > maxvec) | |
668 | return maxvec; | |
1da177e4 | 669 | |
1c8d7b0a | 670 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
671 | if (status) |
672 | return status; | |
1da177e4 | 673 | |
ded86d8d | 674 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 675 | |
1c8d7b0a | 676 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 677 | if (dev->msix_enabled) { |
80ccba11 BH |
678 | dev_info(&dev->dev, "can't enable MSI " |
679 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 680 | return -EINVAL; |
1da177e4 | 681 | } |
1c8d7b0a MW |
682 | |
683 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
684 | return status; |
685 | } | |
1c8d7b0a | 686 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 687 | |
f2440d9a | 688 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 689 | { |
f2440d9a MW |
690 | struct msi_desc *desc; |
691 | u32 mask; | |
692 | u16 ctrl; | |
110828c9 | 693 | unsigned pos; |
1da177e4 | 694 | |
128bc5fc | 695 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
696 | return; |
697 | ||
110828c9 MW |
698 | BUG_ON(list_empty(&dev->msi_list)); |
699 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
700 | pos = desc->msi_attrib.pos; | |
701 | ||
702 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 703 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 704 | dev->msi_enabled = 0; |
7bd007e4 | 705 | |
12abb8ba | 706 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 707 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 708 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
709 | /* Keep cached state to be restored */ |
710 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
711 | |
712 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 713 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 714 | } |
24d27553 | 715 | |
500559a9 | 716 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 717 | { |
d52877c7 YL |
718 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
719 | return; | |
720 | ||
721 | pci_msi_shutdown(dev); | |
f56e4481 | 722 | free_msi_irqs(dev); |
1da177e4 | 723 | } |
4cc086fa | 724 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 725 | |
a52e2e35 RW |
726 | /** |
727 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
728 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
729 | */ | |
730 | int pci_msix_table_size(struct pci_dev *dev) | |
731 | { | |
732 | int pos; | |
733 | u16 control; | |
734 | ||
735 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
736 | if (!pos) | |
737 | return 0; | |
738 | ||
739 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
740 | return multi_msix_capable(control); | |
741 | } | |
742 | ||
1da177e4 LT |
743 | /** |
744 | * pci_enable_msix - configure device's MSI-X capability structure | |
745 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 746 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 747 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
748 | * |
749 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 750 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
751 | * MSI-X mode enabled on its hardware device function. A return of zero |
752 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 753 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 754 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
755 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
756 | * re-send its request. | |
1da177e4 | 757 | **/ |
500559a9 | 758 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 759 | { |
a52e2e35 | 760 | int status, nr_entries; |
ded86d8d | 761 | int i, j; |
1da177e4 | 762 | |
c9953a73 | 763 | if (!entries) |
500559a9 | 764 | return -EINVAL; |
1da177e4 | 765 | |
c9953a73 ME |
766 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
767 | if (status) | |
768 | return status; | |
769 | ||
a52e2e35 | 770 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 771 | if (nvec > nr_entries) |
57fbf52c | 772 | return nr_entries; |
1da177e4 LT |
773 | |
774 | /* Check for any invalid entries */ | |
775 | for (i = 0; i < nvec; i++) { | |
776 | if (entries[i].entry >= nr_entries) | |
777 | return -EINVAL; /* invalid entry */ | |
778 | for (j = i + 1; j < nvec; j++) { | |
779 | if (entries[i].entry == entries[j].entry) | |
780 | return -EINVAL; /* duplicate entry */ | |
781 | } | |
782 | } | |
ded86d8d | 783 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 784 | |
1ce03373 | 785 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 786 | if (dev->msi_enabled) { |
80ccba11 BH |
787 | dev_info(&dev->dev, "can't enable MSI-X " |
788 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
789 | return -EINVAL; |
790 | } | |
1da177e4 | 791 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
792 | return status; |
793 | } | |
4cc086fa | 794 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 795 | |
500559a9 | 796 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 797 | { |
12abb8ba HS |
798 | struct msi_desc *entry; |
799 | ||
128bc5fc | 800 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
801 | return; |
802 | ||
12abb8ba HS |
803 | /* Return the device with MSI-X masked as initial states */ |
804 | list_for_each_entry(entry, &dev->msi_list, list) { | |
805 | /* Keep cached states to be restored */ | |
806 | __msix_mask_irq(entry, 1); | |
807 | } | |
808 | ||
b1cbf4e4 | 809 | msix_set_enable(dev, 0); |
ba698ad4 | 810 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 811 | dev->msix_enabled = 0; |
d52877c7 | 812 | } |
c901851f | 813 | |
500559a9 | 814 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
815 | { |
816 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
817 | return; | |
818 | ||
819 | pci_msix_shutdown(dev); | |
f56e4481 | 820 | free_msi_irqs(dev); |
1da177e4 | 821 | } |
4cc086fa | 822 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
823 | |
824 | /** | |
1ce03373 | 825 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
826 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
827 | * | |
eaae4b3a | 828 | * Being called during hotplug remove, from which the device function |
1ce03373 | 829 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
830 | * allocated for this device function, are reclaimed to unused state, |
831 | * which may be used later on. | |
832 | **/ | |
500559a9 | 833 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 834 | { |
1da177e4 | 835 | if (!pci_msi_enable || !dev) |
500559a9 | 836 | return; |
1da177e4 | 837 | |
f56e4481 HS |
838 | if (dev->msi_enabled || dev->msix_enabled) |
839 | free_msi_irqs(dev); | |
1da177e4 LT |
840 | } |
841 | ||
309e57df MW |
842 | void pci_no_msi(void) |
843 | { | |
844 | pci_msi_enable = 0; | |
845 | } | |
c9953a73 | 846 | |
07ae95f9 AP |
847 | /** |
848 | * pci_msi_enabled - is MSI enabled? | |
849 | * | |
850 | * Returns true if MSI has not been disabled by the command-line option | |
851 | * pci=nomsi. | |
852 | **/ | |
853 | int pci_msi_enabled(void) | |
d389fec6 | 854 | { |
07ae95f9 | 855 | return pci_msi_enable; |
d389fec6 | 856 | } |
07ae95f9 | 857 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 858 | |
07ae95f9 | 859 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 860 | { |
07ae95f9 | 861 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 862 | } |