Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
11df1f05 ME |
33 | #ifndef arch_msi_check_device |
34 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
35 | { |
36 | return 0; | |
37 | } | |
11df1f05 | 38 | #endif |
6a9e7f20 | 39 | |
11df1f05 | 40 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
41 | # define arch_setup_msi_irqs default_setup_msi_irqs |
42 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
43 | #endif | |
44 | ||
45 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
46 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
47 | { |
48 | struct msi_desc *entry; | |
49 | int ret; | |
50 | ||
1c8d7b0a MW |
51 | /* |
52 | * If an architecture wants to support multiple MSI, it needs to | |
53 | * override arch_setup_msi_irqs() | |
54 | */ | |
55 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
56 | return 1; | |
57 | ||
6a9e7f20 AB |
58 | list_for_each_entry(entry, &dev->msi_list, list) { |
59 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 60 | if (ret < 0) |
6a9e7f20 | 61 | return ret; |
b5fbf533 ME |
62 | if (ret > 0) |
63 | return -ENOSPC; | |
6a9e7f20 AB |
64 | } |
65 | ||
66 | return 0; | |
67 | } | |
11df1f05 | 68 | #endif |
6a9e7f20 | 69 | |
11df1f05 | 70 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
71 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
72 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
73 | #endif | |
74 | ||
75 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
76 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
77 | { |
78 | struct msi_desc *entry; | |
79 | ||
80 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
81 | int i, nvec; |
82 | if (entry->irq == 0) | |
83 | continue; | |
65f6ae66 AG |
84 | if (entry->nvec_used) |
85 | nvec = entry->nvec_used; | |
86 | else | |
87 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
88 | for (i = 0; i < nvec; i++) |
89 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
90 | } |
91 | } | |
11df1f05 | 92 | #endif |
6a9e7f20 | 93 | |
76ccc297 KRW |
94 | #ifndef arch_restore_msi_irqs |
95 | # define arch_restore_msi_irqs default_restore_msi_irqs | |
96 | # define HAVE_DEFAULT_MSI_RESTORE_IRQS | |
97 | #endif | |
98 | ||
99 | #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS | |
100 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) | |
101 | { | |
102 | struct msi_desc *entry; | |
103 | ||
104 | entry = NULL; | |
105 | if (dev->msix_enabled) { | |
106 | list_for_each_entry(entry, &dev->msi_list, list) { | |
107 | if (irq == entry->irq) | |
108 | break; | |
109 | } | |
110 | } else if (dev->msi_enabled) { | |
111 | entry = irq_get_msi_desc(irq); | |
112 | } | |
113 | ||
114 | if (entry) | |
115 | write_msi_msg(irq, &entry->msg); | |
116 | } | |
117 | #endif | |
118 | ||
e375b561 | 119 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 120 | { |
b1cbf4e4 EB |
121 | u16 control; |
122 | ||
e375b561 | 123 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
124 | control &= ~PCI_MSI_FLAGS_ENABLE; |
125 | if (enable) | |
126 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 127 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
128 | } |
129 | ||
b1cbf4e4 EB |
130 | static void msix_set_enable(struct pci_dev *dev, int enable) |
131 | { | |
b1cbf4e4 EB |
132 | u16 control; |
133 | ||
e375b561 GS |
134 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
135 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
136 | if (enable) | |
137 | control |= PCI_MSIX_FLAGS_ENABLE; | |
138 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
139 | } |
140 | ||
bffac3c5 MW |
141 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
142 | { | |
0b49ec37 MW |
143 | /* Don't shift by >= width of type */ |
144 | if (x >= 5) | |
145 | return 0xffffffff; | |
146 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
147 | } |
148 | ||
f2440d9a | 149 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 150 | { |
f2440d9a MW |
151 | return msi_mask((control >> 1) & 7); |
152 | } | |
988cbb15 | 153 | |
f2440d9a MW |
154 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
155 | { | |
156 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
157 | } |
158 | ||
ce6fce42 MW |
159 | /* |
160 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
161 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
162 | * reliably as devices without an INTx disable bit will then generate a | |
163 | * level IRQ which will never be cleared. | |
ce6fce42 | 164 | */ |
12abb8ba | 165 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 166 | { |
f2440d9a | 167 | u32 mask_bits = desc->masked; |
1da177e4 | 168 | |
f2440d9a | 169 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 170 | return 0; |
f2440d9a MW |
171 | |
172 | mask_bits &= ~mask; | |
173 | mask_bits |= flag; | |
174 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
175 | |
176 | return mask_bits; | |
177 | } | |
178 | ||
179 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
180 | { | |
181 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
182 | } |
183 | ||
184 | /* | |
185 | * This internal function does not flush PCI writes to the device. | |
186 | * All users must ensure that they read from the device before either | |
187 | * assuming that the device state is up to date, or returning out of this | |
188 | * file. This saves a few milliseconds when initialising devices with lots | |
189 | * of MSI-X interrupts. | |
190 | */ | |
12abb8ba | 191 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
192 | { |
193 | u32 mask_bits = desc->masked; | |
194 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 195 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
196 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
197 | if (flag) | |
198 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 199 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
200 | |
201 | return mask_bits; | |
202 | } | |
203 | ||
204 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
205 | { | |
206 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 207 | } |
24d27553 | 208 | |
9a4da8a5 JG |
209 | #ifdef CONFIG_GENERIC_HARDIRQS |
210 | ||
1c9db525 | 211 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 212 | { |
1c9db525 | 213 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 214 | |
f2440d9a MW |
215 | if (desc->msi_attrib.is_msix) { |
216 | msix_mask_irq(desc, flag); | |
217 | readl(desc->mask_base); /* Flush write to device */ | |
218 | } else { | |
1c9db525 | 219 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 220 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 221 | } |
f2440d9a MW |
222 | } |
223 | ||
1c9db525 | 224 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 225 | { |
1c9db525 | 226 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
227 | } |
228 | ||
1c9db525 | 229 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 230 | { |
1c9db525 | 231 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
232 | } |
233 | ||
9a4da8a5 JG |
234 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
235 | ||
39431acb | 236 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 237 | { |
30da5524 BH |
238 | BUG_ON(entry->dev->current_state != PCI_D0); |
239 | ||
240 | if (entry->msi_attrib.is_msix) { | |
241 | void __iomem *base = entry->mask_base + | |
242 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
243 | ||
244 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
245 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
246 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
247 | } else { | |
248 | struct pci_dev *dev = entry->dev; | |
f5322169 | 249 | int pos = dev->msi_cap; |
30da5524 BH |
250 | u16 data; |
251 | ||
9925ad0c BH |
252 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
253 | &msg->address_lo); | |
30da5524 | 254 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
255 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
256 | &msg->address_hi); | |
2f221349 | 257 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
258 | } else { |
259 | msg->address_hi = 0; | |
2f221349 | 260 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
261 | } |
262 | msg->data = data; | |
263 | } | |
264 | } | |
265 | ||
266 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
267 | { | |
dced35ae | 268 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 269 | |
39431acb | 270 | __read_msi_msg(entry, msg); |
30da5524 BH |
271 | } |
272 | ||
39431acb | 273 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 274 | { |
30da5524 | 275 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
276 | * valid messages are not all-zeroes. */ |
277 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
278 | entry->msg.data)); | |
0366f8f7 | 279 | |
fcd097f3 | 280 | *msg = entry->msg; |
0366f8f7 | 281 | } |
1da177e4 | 282 | |
30da5524 | 283 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 284 | { |
dced35ae | 285 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 286 | |
39431acb | 287 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
288 | } |
289 | ||
39431acb | 290 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 291 | { |
fcd097f3 BH |
292 | if (entry->dev->current_state != PCI_D0) { |
293 | /* Don't touch the hardware now */ | |
294 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
295 | void __iomem *base; |
296 | base = entry->mask_base + | |
297 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
298 | ||
2c21fd4b HS |
299 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
300 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
301 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 302 | } else { |
0366f8f7 | 303 | struct pci_dev *dev = entry->dev; |
f5322169 | 304 | int pos = dev->msi_cap; |
1c8d7b0a MW |
305 | u16 msgctl; |
306 | ||
f84ecd28 | 307 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
308 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
309 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 310 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 311 | |
9925ad0c BH |
312 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
313 | msg->address_lo); | |
0366f8f7 | 314 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
315 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
316 | msg->address_hi); | |
2f221349 BH |
317 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
318 | msg->data); | |
0366f8f7 | 319 | } else { |
2f221349 BH |
320 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
321 | msg->data); | |
0366f8f7 | 322 | } |
1da177e4 | 323 | } |
392ee1e6 | 324 | entry->msg = *msg; |
1da177e4 | 325 | } |
0366f8f7 | 326 | |
3145e941 YL |
327 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
328 | { | |
dced35ae | 329 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 330 | |
39431acb | 331 | __write_msi_msg(entry, msg); |
3145e941 YL |
332 | } |
333 | ||
f56e4481 HS |
334 | static void free_msi_irqs(struct pci_dev *dev) |
335 | { | |
336 | struct msi_desc *entry, *tmp; | |
337 | ||
338 | list_for_each_entry(entry, &dev->msi_list, list) { | |
339 | int i, nvec; | |
340 | if (!entry->irq) | |
341 | continue; | |
65f6ae66 AG |
342 | if (entry->nvec_used) |
343 | nvec = entry->nvec_used; | |
344 | else | |
345 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 346 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
347 | for (i = 0; i < nvec; i++) |
348 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 349 | #endif |
f56e4481 HS |
350 | } |
351 | ||
352 | arch_teardown_msi_irqs(dev); | |
353 | ||
354 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
355 | if (entry->msi_attrib.is_msix) { | |
356 | if (list_is_last(&entry->list, &dev->msi_list)) | |
357 | iounmap(entry->mask_base); | |
358 | } | |
424eb391 NH |
359 | |
360 | /* | |
361 | * Its possible that we get into this path | |
362 | * When populate_msi_sysfs fails, which means the entries | |
363 | * were not registered with sysfs. In that case don't | |
364 | * unregister them. | |
365 | */ | |
366 | if (entry->kobj.parent) { | |
367 | kobject_del(&entry->kobj); | |
368 | kobject_put(&entry->kobj); | |
369 | } | |
370 | ||
f56e4481 HS |
371 | list_del(&entry->list); |
372 | kfree(entry); | |
373 | } | |
374 | } | |
c54c1879 | 375 | |
379f5327 | 376 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 377 | { |
379f5327 MW |
378 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
379 | if (!desc) | |
1da177e4 LT |
380 | return NULL; |
381 | ||
379f5327 MW |
382 | INIT_LIST_HEAD(&desc->list); |
383 | desc->dev = dev; | |
1da177e4 | 384 | |
379f5327 | 385 | return desc; |
1da177e4 LT |
386 | } |
387 | ||
ba698ad4 DM |
388 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
389 | { | |
390 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
391 | pci_intx(dev, enable); | |
392 | } | |
393 | ||
8fed4b65 | 394 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 395 | { |
41017f0c | 396 | u16 control; |
392ee1e6 | 397 | struct msi_desc *entry; |
41017f0c | 398 | |
b1cbf4e4 EB |
399 | if (!dev->msi_enabled) |
400 | return; | |
401 | ||
dced35ae | 402 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 403 | |
ba698ad4 | 404 | pci_intx_for_msi(dev, 0); |
e375b561 | 405 | msi_set_enable(dev, 0); |
76ccc297 | 406 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 | 407 | |
f5322169 | 408 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 409 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 410 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 411 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 412 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
413 | } |
414 | ||
415 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 416 | { |
41017f0c | 417 | struct msi_desc *entry; |
392ee1e6 | 418 | u16 control; |
41017f0c | 419 | |
ded86d8d EB |
420 | if (!dev->msix_enabled) |
421 | return; | |
f598282f | 422 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 423 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 424 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 425 | |
41017f0c | 426 | /* route the table */ |
ba698ad4 | 427 | pci_intx_for_msi(dev, 0); |
f598282f | 428 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 429 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 430 | |
4aa9bc95 | 431 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 432 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 433 | msix_mask_irq(entry, entry->masked); |
41017f0c | 434 | } |
41017f0c | 435 | |
392ee1e6 | 436 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 437 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 438 | } |
8fed4b65 ME |
439 | |
440 | void pci_restore_msi_state(struct pci_dev *dev) | |
441 | { | |
442 | __pci_restore_msi_state(dev); | |
443 | __pci_restore_msix_state(dev); | |
444 | } | |
94688cf2 | 445 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 446 | |
da8d1c8b NH |
447 | |
448 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
449 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
450 | ||
451 | struct msi_attribute { | |
452 | struct attribute attr; | |
453 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
454 | char *buf); | |
455 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
456 | const char *buf, size_t count); | |
457 | }; | |
458 | ||
459 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
460 | char *buf) | |
461 | { | |
462 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
463 | } | |
464 | ||
465 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
466 | struct attribute *attr, char *buf) | |
467 | { | |
468 | struct msi_attribute *attribute = to_msi_attr(attr); | |
469 | struct msi_desc *entry = to_msi_desc(kobj); | |
470 | ||
471 | if (!attribute->show) | |
472 | return -EIO; | |
473 | ||
474 | return attribute->show(entry, attribute, buf); | |
475 | } | |
476 | ||
477 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
478 | .show = msi_irq_attr_show, | |
479 | }; | |
480 | ||
481 | static struct msi_attribute mode_attribute = | |
482 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
483 | ||
484 | ||
9738abed | 485 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
486 | &mode_attribute.attr, |
487 | NULL | |
488 | }; | |
489 | ||
9738abed | 490 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
491 | { |
492 | struct msi_desc *entry = to_msi_desc(kobj); | |
493 | ||
494 | pci_dev_put(entry->dev); | |
495 | } | |
496 | ||
497 | static struct kobj_type msi_irq_ktype = { | |
498 | .release = msi_kobj_release, | |
499 | .sysfs_ops = &msi_irq_sysfs_ops, | |
500 | .default_attrs = msi_irq_default_attrs, | |
501 | }; | |
502 | ||
503 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
504 | { | |
505 | struct msi_desc *entry; | |
506 | struct kobject *kobj; | |
507 | int ret; | |
508 | int count = 0; | |
509 | ||
510 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
511 | if (!pdev->msi_kset) | |
512 | return -ENOMEM; | |
513 | ||
514 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
515 | kobj = &entry->kobj; | |
516 | kobj->kset = pdev->msi_kset; | |
517 | pci_dev_get(pdev); | |
518 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
519 | "%u", entry->irq); | |
520 | if (ret) | |
521 | goto out_unroll; | |
522 | ||
523 | count++; | |
524 | } | |
525 | ||
526 | return 0; | |
527 | ||
528 | out_unroll: | |
529 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
530 | if (!count) | |
531 | break; | |
532 | kobject_del(&entry->kobj); | |
533 | kobject_put(&entry->kobj); | |
534 | count--; | |
535 | } | |
536 | return ret; | |
537 | } | |
538 | ||
1da177e4 LT |
539 | /** |
540 | * msi_capability_init - configure device's MSI capability structure | |
541 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 542 | * @nvec: number of interrupts to allocate |
1da177e4 | 543 | * |
1c8d7b0a MW |
544 | * Setup the MSI capability structure of the device with the requested |
545 | * number of interrupts. A return value of zero indicates the successful | |
546 | * setup of an entry with the new MSI irq. A negative return value indicates | |
547 | * an error, and a positive return value indicates the number of interrupts | |
548 | * which could have been allocated. | |
549 | */ | |
550 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
551 | { |
552 | struct msi_desc *entry; | |
f465136d | 553 | int ret; |
1da177e4 | 554 | u16 control; |
f2440d9a | 555 | unsigned mask; |
1da177e4 | 556 | |
e375b561 | 557 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 558 | |
f84ecd28 | 559 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 560 | /* MSI Entry Initialization */ |
379f5327 | 561 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
562 | if (!entry) |
563 | return -ENOMEM; | |
1ce03373 | 564 | |
500559a9 | 565 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 566 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 567 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 568 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 569 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 570 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 571 | |
e5f66eaf DC |
572 | if (control & PCI_MSI_FLAGS_64BIT) |
573 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
574 | else | |
575 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
576 | /* All MSIs are unmasked by default, Mask them all */ |
577 | if (entry->msi_attrib.maskbit) | |
578 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
579 | mask = msi_capable_mask(control); | |
580 | msi_mask_irq(entry, mask, mask); | |
581 | ||
0dd11f9b | 582 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 583 | |
1da177e4 | 584 | /* Configure MSI capability structure */ |
1c8d7b0a | 585 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 586 | if (ret) { |
7ba1930d | 587 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 588 | free_msi_irqs(dev); |
7fe3730d | 589 | return ret; |
fd58e55f | 590 | } |
f7feaca7 | 591 | |
da8d1c8b NH |
592 | ret = populate_msi_sysfs(dev); |
593 | if (ret) { | |
594 | msi_mask_irq(entry, mask, ~mask); | |
595 | free_msi_irqs(dev); | |
596 | return ret; | |
597 | } | |
598 | ||
1da177e4 | 599 | /* Set MSI enabled bits */ |
ba698ad4 | 600 | pci_intx_for_msi(dev, 0); |
e375b561 | 601 | msi_set_enable(dev, 1); |
b1cbf4e4 | 602 | dev->msi_enabled = 1; |
1da177e4 | 603 | |
7fe3730d | 604 | dev->irq = entry->irq; |
1da177e4 LT |
605 | return 0; |
606 | } | |
607 | ||
520fe9dc | 608 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 609 | { |
4302e0fb | 610 | resource_size_t phys_addr; |
5a05a9d8 HS |
611 | u32 table_offset; |
612 | u8 bir; | |
613 | ||
909094c6 BH |
614 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
615 | &table_offset); | |
4d18760c BH |
616 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
617 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
618 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
619 | ||
620 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
621 | } | |
622 | ||
520fe9dc GS |
623 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
624 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
625 | { |
626 | struct msi_desc *entry; | |
627 | int i; | |
628 | ||
629 | for (i = 0; i < nvec; i++) { | |
630 | entry = alloc_msi_entry(dev); | |
631 | if (!entry) { | |
632 | if (!i) | |
633 | iounmap(base); | |
634 | else | |
635 | free_msi_irqs(dev); | |
636 | /* No enough memory. Don't try again */ | |
637 | return -ENOMEM; | |
638 | } | |
639 | ||
640 | entry->msi_attrib.is_msix = 1; | |
641 | entry->msi_attrib.is_64 = 1; | |
642 | entry->msi_attrib.entry_nr = entries[i].entry; | |
643 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 644 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
645 | entry->mask_base = base; |
646 | ||
647 | list_add_tail(&entry->list, &dev->msi_list); | |
648 | } | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
75cb3426 | 653 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 654 | struct msix_entry *entries) |
75cb3426 HS |
655 | { |
656 | struct msi_desc *entry; | |
657 | int i = 0; | |
658 | ||
659 | list_for_each_entry(entry, &dev->msi_list, list) { | |
660 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
661 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
662 | ||
663 | entries[i].vector = entry->irq; | |
dced35ae | 664 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
665 | entry->masked = readl(entry->mask_base + offset); |
666 | msix_mask_irq(entry, 1); | |
667 | i++; | |
668 | } | |
669 | } | |
670 | ||
1da177e4 LT |
671 | /** |
672 | * msix_capability_init - configure device's MSI-X capability | |
673 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
674 | * @entries: pointer to an array of struct msix_entry entries |
675 | * @nvec: number of @entries | |
1da177e4 | 676 | * |
eaae4b3a | 677 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
678 | * single MSI-X irq. A return of zero indicates the successful setup of |
679 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
680 | **/ |
681 | static int msix_capability_init(struct pci_dev *dev, | |
682 | struct msix_entry *entries, int nvec) | |
683 | { | |
520fe9dc | 684 | int ret; |
5a05a9d8 | 685 | u16 control; |
1da177e4 LT |
686 | void __iomem *base; |
687 | ||
520fe9dc | 688 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
689 | |
690 | /* Ensure MSI-X is disabled while it is set up */ | |
691 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 692 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 693 | |
1da177e4 | 694 | /* Request & Map MSI-X table region */ |
527eee29 | 695 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 696 | if (!base) |
1da177e4 LT |
697 | return -ENOMEM; |
698 | ||
520fe9dc | 699 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
700 | if (ret) |
701 | return ret; | |
9c831334 ME |
702 | |
703 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
704 | if (ret) |
705 | goto error; | |
9c831334 | 706 | |
f598282f MW |
707 | /* |
708 | * Some devices require MSI-X to be enabled before we can touch the | |
709 | * MSI-X registers. We need to mask all the vectors to prevent | |
710 | * interrupts coming in before they're fully set up. | |
711 | */ | |
712 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 713 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 714 | |
75cb3426 | 715 | msix_program_entries(dev, entries); |
f598282f | 716 | |
da8d1c8b NH |
717 | ret = populate_msi_sysfs(dev); |
718 | if (ret) { | |
719 | ret = 0; | |
720 | goto error; | |
721 | } | |
722 | ||
f598282f | 723 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 724 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 725 | dev->msix_enabled = 1; |
1da177e4 | 726 | |
f598282f | 727 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 728 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 729 | |
1da177e4 | 730 | return 0; |
583871d4 HS |
731 | |
732 | error: | |
733 | if (ret < 0) { | |
734 | /* | |
735 | * If we had some success, report the number of irqs | |
736 | * we succeeded in setting up. | |
737 | */ | |
d9d7070e | 738 | struct msi_desc *entry; |
583871d4 HS |
739 | int avail = 0; |
740 | ||
741 | list_for_each_entry(entry, &dev->msi_list, list) { | |
742 | if (entry->irq != 0) | |
743 | avail++; | |
744 | } | |
745 | if (avail != 0) | |
746 | ret = avail; | |
747 | } | |
748 | ||
749 | free_msi_irqs(dev); | |
750 | ||
751 | return ret; | |
1da177e4 LT |
752 | } |
753 | ||
24334a12 | 754 | /** |
17bbc12a | 755 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 756 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 757 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 758 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 759 | * |
0306ebfa | 760 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
761 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
762 | * supported return 0, else return an error code. | |
24334a12 | 763 | **/ |
500559a9 | 764 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
765 | { |
766 | struct pci_bus *bus; | |
c9953a73 | 767 | int ret; |
24334a12 | 768 | |
0306ebfa | 769 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
770 | if (!pci_msi_enable || !dev || dev->no_msi) |
771 | return -EINVAL; | |
772 | ||
314e77b3 ME |
773 | /* |
774 | * You can't ask to have 0 or less MSIs configured. | |
775 | * a) it's stupid .. | |
776 | * b) the list manipulation code assumes nvec >= 1. | |
777 | */ | |
778 | if (nvec < 1) | |
779 | return -ERANGE; | |
780 | ||
500559a9 HS |
781 | /* |
782 | * Any bridge which does NOT route MSI transactions from its | |
783 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
784 | * the secondary pci_bus. |
785 | * We expect only arch-specific PCI host bus controller driver | |
786 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
787 | */ | |
24334a12 BG |
788 | for (bus = dev->bus; bus; bus = bus->parent) |
789 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
790 | return -EINVAL; | |
791 | ||
c9953a73 ME |
792 | ret = arch_msi_check_device(dev, nvec, type); |
793 | if (ret) | |
794 | return ret; | |
795 | ||
24334a12 BG |
796 | return 0; |
797 | } | |
798 | ||
1da177e4 | 799 | /** |
1c8d7b0a MW |
800 | * pci_enable_msi_block - configure device's MSI capability structure |
801 | * @dev: device to configure | |
802 | * @nvec: number of interrupts to configure | |
1da177e4 | 803 | * |
1c8d7b0a MW |
804 | * Allocate IRQs for a device with the MSI capability. |
805 | * This function returns a negative errno if an error occurs. If it | |
806 | * is unable to allocate the number of interrupts requested, it returns | |
807 | * the number of interrupts it might be able to allocate. If it successfully | |
808 | * allocates at least the number of interrupts requested, it returns 0 and | |
809 | * updates the @dev's irq member to the lowest new interrupt number; the | |
810 | * other interrupt numbers allocated to this device are consecutive. | |
811 | */ | |
812 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 813 | { |
f465136d | 814 | int status, maxvec; |
1c8d7b0a MW |
815 | u16 msgctl; |
816 | ||
f465136d | 817 | if (!dev->msi_cap) |
1c8d7b0a | 818 | return -EINVAL; |
f465136d GS |
819 | |
820 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
821 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
822 | if (nvec > maxvec) | |
823 | return maxvec; | |
1da177e4 | 824 | |
1c8d7b0a | 825 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
826 | if (status) |
827 | return status; | |
1da177e4 | 828 | |
ded86d8d | 829 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 830 | |
1c8d7b0a | 831 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 832 | if (dev->msix_enabled) { |
80ccba11 BH |
833 | dev_info(&dev->dev, "can't enable MSI " |
834 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 835 | return -EINVAL; |
1da177e4 | 836 | } |
1c8d7b0a MW |
837 | |
838 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
839 | return status; |
840 | } | |
1c8d7b0a | 841 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 842 | |
08261d87 AG |
843 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
844 | { | |
f465136d | 845 | int ret, nvec; |
08261d87 AG |
846 | u16 msgctl; |
847 | ||
f465136d | 848 | if (!dev->msi_cap) |
08261d87 AG |
849 | return -EINVAL; |
850 | ||
f465136d | 851 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
852 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
853 | ||
854 | if (maxvec) | |
855 | *maxvec = ret; | |
856 | ||
857 | do { | |
858 | nvec = ret; | |
859 | ret = pci_enable_msi_block(dev, nvec); | |
860 | } while (ret > 0); | |
861 | ||
862 | if (ret < 0) | |
863 | return ret; | |
864 | return nvec; | |
865 | } | |
866 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
867 | ||
f2440d9a | 868 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 869 | { |
f2440d9a MW |
870 | struct msi_desc *desc; |
871 | u32 mask; | |
872 | u16 ctrl; | |
1da177e4 | 873 | |
128bc5fc | 874 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
875 | return; |
876 | ||
110828c9 MW |
877 | BUG_ON(list_empty(&dev->msi_list)); |
878 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 879 | |
e375b561 | 880 | msi_set_enable(dev, 0); |
ba698ad4 | 881 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 882 | dev->msi_enabled = 0; |
7bd007e4 | 883 | |
12abb8ba | 884 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 885 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 886 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
887 | /* Keep cached state to be restored */ |
888 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
889 | |
890 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 891 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 892 | } |
24d27553 | 893 | |
500559a9 | 894 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 895 | { |
d52877c7 YL |
896 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
897 | return; | |
898 | ||
899 | pci_msi_shutdown(dev); | |
f56e4481 | 900 | free_msi_irqs(dev); |
da8d1c8b NH |
901 | kset_unregister(dev->msi_kset); |
902 | dev->msi_kset = NULL; | |
1da177e4 | 903 | } |
4cc086fa | 904 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 905 | |
a52e2e35 RW |
906 | /** |
907 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
908 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
909 | */ | |
910 | int pci_msix_table_size(struct pci_dev *dev) | |
911 | { | |
a52e2e35 RW |
912 | u16 control; |
913 | ||
520fe9dc | 914 | if (!dev->msix_cap) |
a52e2e35 RW |
915 | return 0; |
916 | ||
f84ecd28 | 917 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 918 | return msix_table_size(control); |
a52e2e35 RW |
919 | } |
920 | ||
1da177e4 LT |
921 | /** |
922 | * pci_enable_msix - configure device's MSI-X capability structure | |
923 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 924 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 925 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
926 | * |
927 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 928 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
929 | * MSI-X mode enabled on its hardware device function. A return of zero |
930 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 931 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 932 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
933 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
934 | * re-send its request. | |
1da177e4 | 935 | **/ |
500559a9 | 936 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 937 | { |
a52e2e35 | 938 | int status, nr_entries; |
ded86d8d | 939 | int i, j; |
1da177e4 | 940 | |
cdf1fd4d | 941 | if (!entries || !dev->msix_cap) |
500559a9 | 942 | return -EINVAL; |
1da177e4 | 943 | |
c9953a73 ME |
944 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
945 | if (status) | |
946 | return status; | |
947 | ||
a52e2e35 | 948 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 949 | if (nvec > nr_entries) |
57fbf52c | 950 | return nr_entries; |
1da177e4 LT |
951 | |
952 | /* Check for any invalid entries */ | |
953 | for (i = 0; i < nvec; i++) { | |
954 | if (entries[i].entry >= nr_entries) | |
955 | return -EINVAL; /* invalid entry */ | |
956 | for (j = i + 1; j < nvec; j++) { | |
957 | if (entries[i].entry == entries[j].entry) | |
958 | return -EINVAL; /* duplicate entry */ | |
959 | } | |
960 | } | |
ded86d8d | 961 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 962 | |
1ce03373 | 963 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 964 | if (dev->msi_enabled) { |
80ccba11 BH |
965 | dev_info(&dev->dev, "can't enable MSI-X " |
966 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
967 | return -EINVAL; |
968 | } | |
1da177e4 | 969 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
970 | return status; |
971 | } | |
4cc086fa | 972 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 973 | |
500559a9 | 974 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 975 | { |
12abb8ba HS |
976 | struct msi_desc *entry; |
977 | ||
128bc5fc | 978 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
979 | return; |
980 | ||
12abb8ba HS |
981 | /* Return the device with MSI-X masked as initial states */ |
982 | list_for_each_entry(entry, &dev->msi_list, list) { | |
983 | /* Keep cached states to be restored */ | |
984 | __msix_mask_irq(entry, 1); | |
985 | } | |
986 | ||
b1cbf4e4 | 987 | msix_set_enable(dev, 0); |
ba698ad4 | 988 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 989 | dev->msix_enabled = 0; |
d52877c7 | 990 | } |
c901851f | 991 | |
500559a9 | 992 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
993 | { |
994 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
995 | return; | |
996 | ||
997 | pci_msix_shutdown(dev); | |
f56e4481 | 998 | free_msi_irqs(dev); |
da8d1c8b NH |
999 | kset_unregister(dev->msi_kset); |
1000 | dev->msi_kset = NULL; | |
1da177e4 | 1001 | } |
4cc086fa | 1002 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1003 | |
1004 | /** | |
1ce03373 | 1005 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1006 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1007 | * | |
eaae4b3a | 1008 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1009 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1010 | * allocated for this device function, are reclaimed to unused state, |
1011 | * which may be used later on. | |
1012 | **/ | |
500559a9 | 1013 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1014 | { |
1da177e4 | 1015 | if (!pci_msi_enable || !dev) |
500559a9 | 1016 | return; |
1da177e4 | 1017 | |
f56e4481 HS |
1018 | if (dev->msi_enabled || dev->msix_enabled) |
1019 | free_msi_irqs(dev); | |
1da177e4 LT |
1020 | } |
1021 | ||
309e57df MW |
1022 | void pci_no_msi(void) |
1023 | { | |
1024 | pci_msi_enable = 0; | |
1025 | } | |
c9953a73 | 1026 | |
07ae95f9 AP |
1027 | /** |
1028 | * pci_msi_enabled - is MSI enabled? | |
1029 | * | |
1030 | * Returns true if MSI has not been disabled by the command-line option | |
1031 | * pci=nomsi. | |
1032 | **/ | |
1033 | int pci_msi_enabled(void) | |
d389fec6 | 1034 | { |
07ae95f9 | 1035 | return pci_msi_enable; |
d389fec6 | 1036 | } |
07ae95f9 | 1037 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1038 | |
07ae95f9 | 1039 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1040 | { |
07ae95f9 | 1041 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1042 | |
1043 | /* Disable the msi hardware to avoid screaming interrupts | |
1044 | * during boot. This is the power on reset default so | |
1045 | * usually this should be a noop. | |
1046 | */ | |
e375b561 GS |
1047 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1048 | if (dev->msi_cap) | |
1049 | msi_set_enable(dev, 0); | |
1050 | ||
1051 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1052 | if (dev->msix_cap) | |
1053 | msix_set_enable(dev, 0); | |
d389fec6 | 1054 | } |