Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
527eee29 BH |
27 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
28 | ||
29 | ||
6a9e7f20 AB |
30 | /* Arch hooks */ |
31 | ||
4287d824 TP |
32 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
33 | { | |
0cbdcfcf TR |
34 | struct msi_chip *chip = dev->bus->msi; |
35 | int err; | |
36 | ||
37 | if (!chip || !chip->setup_irq) | |
38 | return -EINVAL; | |
39 | ||
40 | err = chip->setup_irq(chip, dev, desc); | |
41 | if (err < 0) | |
42 | return err; | |
43 | ||
44 | irq_set_chip_data(desc->irq, chip); | |
45 | ||
46 | return 0; | |
4287d824 TP |
47 | } |
48 | ||
49 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 50 | { |
0cbdcfcf TR |
51 | struct msi_chip *chip = irq_get_chip_data(irq); |
52 | ||
53 | if (!chip || !chip->teardown_irq) | |
54 | return; | |
55 | ||
56 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
57 | } |
58 | ||
4287d824 | 59 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
60 | { |
61 | struct msi_desc *entry; | |
62 | int ret; | |
63 | ||
1c8d7b0a MW |
64 | /* |
65 | * If an architecture wants to support multiple MSI, it needs to | |
66 | * override arch_setup_msi_irqs() | |
67 | */ | |
68 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
69 | return 1; | |
70 | ||
6a9e7f20 AB |
71 | list_for_each_entry(entry, &dev->msi_list, list) { |
72 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 73 | if (ret < 0) |
6a9e7f20 | 74 | return ret; |
b5fbf533 ME |
75 | if (ret > 0) |
76 | return -ENOSPC; | |
6a9e7f20 AB |
77 | } |
78 | ||
79 | return 0; | |
80 | } | |
1525bf0d | 81 | |
4287d824 TP |
82 | /* |
83 | * We have a default implementation available as a separate non-weak | |
84 | * function, as it is used by the Xen x86 PCI code | |
85 | */ | |
1525bf0d | 86 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
87 | { |
88 | struct msi_desc *entry; | |
89 | ||
90 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
91 | int i, nvec; |
92 | if (entry->irq == 0) | |
93 | continue; | |
65f6ae66 AG |
94 | if (entry->nvec_used) |
95 | nvec = entry->nvec_used; | |
96 | else | |
97 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
98 | for (i = 0; i < nvec; i++) |
99 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
100 | } |
101 | } | |
102 | ||
4287d824 TP |
103 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
104 | { | |
105 | return default_teardown_msi_irqs(dev); | |
106 | } | |
76ccc297 | 107 | |
ac8344c4 | 108 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
109 | { |
110 | struct msi_desc *entry; | |
111 | ||
112 | entry = NULL; | |
113 | if (dev->msix_enabled) { | |
114 | list_for_each_entry(entry, &dev->msi_list, list) { | |
115 | if (irq == entry->irq) | |
116 | break; | |
117 | } | |
118 | } else if (dev->msi_enabled) { | |
119 | entry = irq_get_msi_desc(irq); | |
120 | } | |
121 | ||
122 | if (entry) | |
123 | write_msi_msg(irq, &entry->msg); | |
124 | } | |
4287d824 | 125 | |
ac8344c4 | 126 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 127 | { |
ac8344c4 | 128 | return default_restore_msi_irqs(dev); |
4287d824 | 129 | } |
76ccc297 | 130 | |
e375b561 | 131 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 132 | { |
b1cbf4e4 EB |
133 | u16 control; |
134 | ||
e375b561 | 135 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
136 | control &= ~PCI_MSI_FLAGS_ENABLE; |
137 | if (enable) | |
138 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 139 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
140 | } |
141 | ||
66f0d0c4 | 142 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 143 | { |
66f0d0c4 | 144 | u16 ctrl; |
b1cbf4e4 | 145 | |
66f0d0c4 YW |
146 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
147 | ctrl &= ~clear; | |
148 | ctrl |= set; | |
149 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
150 | } |
151 | ||
bffac3c5 MW |
152 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
153 | { | |
0b49ec37 MW |
154 | /* Don't shift by >= width of type */ |
155 | if (x >= 5) | |
156 | return 0xffffffff; | |
157 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
158 | } |
159 | ||
ce6fce42 MW |
160 | /* |
161 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
162 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
163 | * reliably as devices without an INTx disable bit will then generate a | |
164 | * level IRQ which will never be cleared. | |
ce6fce42 | 165 | */ |
0e4ccb15 | 166 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 167 | { |
f2440d9a | 168 | u32 mask_bits = desc->masked; |
1da177e4 | 169 | |
f2440d9a | 170 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 171 | return 0; |
f2440d9a MW |
172 | |
173 | mask_bits &= ~mask; | |
174 | mask_bits |= flag; | |
175 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
0e4ccb15 KRW |
180 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
181 | { | |
182 | return default_msi_mask_irq(desc, mask, flag); | |
183 | } | |
184 | ||
12abb8ba HS |
185 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
186 | { | |
0e4ccb15 | 187 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
188 | } |
189 | ||
190 | /* | |
191 | * This internal function does not flush PCI writes to the device. | |
192 | * All users must ensure that they read from the device before either | |
193 | * assuming that the device state is up to date, or returning out of this | |
194 | * file. This saves a few milliseconds when initialising devices with lots | |
195 | * of MSI-X interrupts. | |
196 | */ | |
0e4ccb15 | 197 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
198 | { |
199 | u32 mask_bits = desc->masked; | |
200 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 201 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
202 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
203 | if (flag) | |
204 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 205 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
206 | |
207 | return mask_bits; | |
208 | } | |
209 | ||
0e4ccb15 KRW |
210 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
211 | { | |
212 | return default_msix_mask_irq(desc, flag); | |
213 | } | |
214 | ||
12abb8ba HS |
215 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
216 | { | |
0e4ccb15 | 217 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 218 | } |
24d27553 | 219 | |
1c9db525 | 220 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 221 | { |
1c9db525 | 222 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 223 | |
f2440d9a MW |
224 | if (desc->msi_attrib.is_msix) { |
225 | msix_mask_irq(desc, flag); | |
226 | readl(desc->mask_base); /* Flush write to device */ | |
227 | } else { | |
a281b788 | 228 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 229 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 230 | } |
f2440d9a MW |
231 | } |
232 | ||
1c9db525 | 233 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 234 | { |
1c9db525 | 235 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
236 | } |
237 | ||
1c9db525 | 238 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 239 | { |
1c9db525 | 240 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
241 | } |
242 | ||
ac8344c4 D |
243 | void default_restore_msi_irqs(struct pci_dev *dev) |
244 | { | |
245 | struct msi_desc *entry; | |
246 | ||
247 | list_for_each_entry(entry, &dev->msi_list, list) { | |
248 | default_restore_msi_irq(dev, entry->irq); | |
249 | } | |
250 | } | |
251 | ||
39431acb | 252 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 253 | { |
30da5524 BH |
254 | BUG_ON(entry->dev->current_state != PCI_D0); |
255 | ||
256 | if (entry->msi_attrib.is_msix) { | |
257 | void __iomem *base = entry->mask_base + | |
258 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
259 | ||
260 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
261 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
262 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
263 | } else { | |
264 | struct pci_dev *dev = entry->dev; | |
f5322169 | 265 | int pos = dev->msi_cap; |
30da5524 BH |
266 | u16 data; |
267 | ||
9925ad0c BH |
268 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
269 | &msg->address_lo); | |
30da5524 | 270 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
271 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
272 | &msg->address_hi); | |
2f221349 | 273 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
274 | } else { |
275 | msg->address_hi = 0; | |
2f221349 | 276 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
277 | } |
278 | msg->data = data; | |
279 | } | |
280 | } | |
281 | ||
282 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
283 | { | |
dced35ae | 284 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 285 | |
39431acb | 286 | __read_msi_msg(entry, msg); |
30da5524 BH |
287 | } |
288 | ||
39431acb | 289 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 290 | { |
30da5524 | 291 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
292 | * valid messages are not all-zeroes. */ |
293 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
294 | entry->msg.data)); | |
0366f8f7 | 295 | |
fcd097f3 | 296 | *msg = entry->msg; |
0366f8f7 | 297 | } |
1da177e4 | 298 | |
30da5524 | 299 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 300 | { |
dced35ae | 301 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 302 | |
39431acb | 303 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
304 | } |
305 | ||
39431acb | 306 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 307 | { |
fcd097f3 BH |
308 | if (entry->dev->current_state != PCI_D0) { |
309 | /* Don't touch the hardware now */ | |
310 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
311 | void __iomem *base; |
312 | base = entry->mask_base + | |
313 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
314 | ||
2c21fd4b HS |
315 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
316 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
317 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 318 | } else { |
0366f8f7 | 319 | struct pci_dev *dev = entry->dev; |
f5322169 | 320 | int pos = dev->msi_cap; |
1c8d7b0a MW |
321 | u16 msgctl; |
322 | ||
f84ecd28 | 323 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
324 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
325 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 326 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 327 | |
9925ad0c BH |
328 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
329 | msg->address_lo); | |
0366f8f7 | 330 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
331 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
332 | msg->address_hi); | |
2f221349 BH |
333 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
334 | msg->data); | |
0366f8f7 | 335 | } else { |
2f221349 BH |
336 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
337 | msg->data); | |
0366f8f7 | 338 | } |
1da177e4 | 339 | } |
392ee1e6 | 340 | entry->msg = *msg; |
1da177e4 | 341 | } |
0366f8f7 | 342 | |
3145e941 YL |
343 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
344 | { | |
dced35ae | 345 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 346 | |
39431acb | 347 | __write_msi_msg(entry, msg); |
3145e941 YL |
348 | } |
349 | ||
f56e4481 HS |
350 | static void free_msi_irqs(struct pci_dev *dev) |
351 | { | |
352 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
353 | struct attribute **msi_attrs; |
354 | struct device_attribute *dev_attr; | |
355 | int count = 0; | |
f56e4481 HS |
356 | |
357 | list_for_each_entry(entry, &dev->msi_list, list) { | |
358 | int i, nvec; | |
359 | if (!entry->irq) | |
360 | continue; | |
65f6ae66 AG |
361 | if (entry->nvec_used) |
362 | nvec = entry->nvec_used; | |
363 | else | |
364 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
365 | for (i = 0; i < nvec; i++) |
366 | BUG_ON(irq_has_action(entry->irq + i)); | |
367 | } | |
368 | ||
369 | arch_teardown_msi_irqs(dev); | |
370 | ||
371 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
372 | if (entry->msi_attrib.is_msix) { | |
373 | if (list_is_last(&entry->list, &dev->msi_list)) | |
374 | iounmap(entry->mask_base); | |
375 | } | |
424eb391 NH |
376 | |
377 | /* | |
378 | * Its possible that we get into this path | |
379 | * When populate_msi_sysfs fails, which means the entries | |
380 | * were not registered with sysfs. In that case don't | |
381 | * unregister them. | |
382 | */ | |
383 | if (entry->kobj.parent) { | |
384 | kobject_del(&entry->kobj); | |
385 | kobject_put(&entry->kobj); | |
386 | } | |
387 | ||
f56e4481 HS |
388 | list_del(&entry->list); |
389 | kfree(entry); | |
390 | } | |
1c51b50c GKH |
391 | |
392 | if (dev->msi_irq_groups) { | |
393 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
394 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 395 | while (msi_attrs[count]) { |
1c51b50c GKH |
396 | dev_attr = container_of(msi_attrs[count], |
397 | struct device_attribute, attr); | |
398 | kfree(dev_attr->attr.name); | |
399 | kfree(dev_attr); | |
400 | ++count; | |
401 | } | |
402 | kfree(msi_attrs); | |
403 | kfree(dev->msi_irq_groups[0]); | |
404 | kfree(dev->msi_irq_groups); | |
405 | dev->msi_irq_groups = NULL; | |
406 | } | |
f56e4481 | 407 | } |
c54c1879 | 408 | |
379f5327 | 409 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 410 | { |
379f5327 MW |
411 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
412 | if (!desc) | |
1da177e4 LT |
413 | return NULL; |
414 | ||
379f5327 MW |
415 | INIT_LIST_HEAD(&desc->list); |
416 | desc->dev = dev; | |
1da177e4 | 417 | |
379f5327 | 418 | return desc; |
1da177e4 LT |
419 | } |
420 | ||
ba698ad4 DM |
421 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
422 | { | |
423 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
424 | pci_intx(dev, enable); | |
425 | } | |
426 | ||
8fed4b65 | 427 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 428 | { |
41017f0c | 429 | u16 control; |
392ee1e6 | 430 | struct msi_desc *entry; |
41017f0c | 431 | |
b1cbf4e4 EB |
432 | if (!dev->msi_enabled) |
433 | return; | |
434 | ||
dced35ae | 435 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 436 | |
ba698ad4 | 437 | pci_intx_for_msi(dev, 0); |
e375b561 | 438 | msi_set_enable(dev, 0); |
ac8344c4 | 439 | arch_restore_msi_irqs(dev); |
392ee1e6 | 440 | |
f5322169 | 441 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
442 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
443 | entry->masked); | |
abad2ec9 | 444 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 445 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 446 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
447 | } |
448 | ||
449 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 450 | { |
41017f0c | 451 | struct msi_desc *entry; |
41017f0c | 452 | |
ded86d8d EB |
453 | if (!dev->msix_enabled) |
454 | return; | |
f598282f | 455 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 456 | |
41017f0c | 457 | /* route the table */ |
ba698ad4 | 458 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
459 | msix_clear_and_set_ctrl(dev, 0, |
460 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 461 | |
ac8344c4 | 462 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 463 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 464 | msix_mask_irq(entry, entry->masked); |
41017f0c | 465 | } |
41017f0c | 466 | |
66f0d0c4 | 467 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 468 | } |
8fed4b65 ME |
469 | |
470 | void pci_restore_msi_state(struct pci_dev *dev) | |
471 | { | |
472 | __pci_restore_msi_state(dev); | |
473 | __pci_restore_msix_state(dev); | |
474 | } | |
94688cf2 | 475 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 476 | |
1c51b50c | 477 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
478 | char *buf) |
479 | { | |
1c51b50c GKH |
480 | struct msi_desc *entry; |
481 | unsigned long irq; | |
482 | int retval; | |
da8d1c8b | 483 | |
1c51b50c GKH |
484 | retval = kstrtoul(attr->attr.name, 10, &irq); |
485 | if (retval) | |
486 | return retval; | |
da8d1c8b | 487 | |
e11ece5a YW |
488 | entry = irq_get_msi_desc(irq); |
489 | if (entry) | |
490 | return sprintf(buf, "%s\n", | |
491 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
492 | ||
1c51b50c | 493 | return -ENODEV; |
da8d1c8b NH |
494 | } |
495 | ||
da8d1c8b NH |
496 | static int populate_msi_sysfs(struct pci_dev *pdev) |
497 | { | |
1c51b50c GKH |
498 | struct attribute **msi_attrs; |
499 | struct attribute *msi_attr; | |
500 | struct device_attribute *msi_dev_attr; | |
501 | struct attribute_group *msi_irq_group; | |
502 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 503 | struct msi_desc *entry; |
1c51b50c GKH |
504 | int ret = -ENOMEM; |
505 | int num_msi = 0; | |
da8d1c8b NH |
506 | int count = 0; |
507 | ||
1c51b50c GKH |
508 | /* Determine how many msi entries we have */ |
509 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
510 | ++num_msi; | |
511 | } | |
512 | if (!num_msi) | |
513 | return 0; | |
da8d1c8b | 514 | |
1c51b50c GKH |
515 | /* Dynamically create the MSI attributes for the PCI device */ |
516 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
517 | if (!msi_attrs) | |
518 | return -ENOMEM; | |
da8d1c8b | 519 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 520 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 521 | if (!msi_dev_attr) |
1c51b50c | 522 | goto error_attrs; |
1406276c | 523 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 524 | |
1c51b50c | 525 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
526 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
527 | entry->irq); | |
528 | if (!msi_dev_attr->attr.name) | |
529 | goto error_attrs; | |
1c51b50c GKH |
530 | msi_dev_attr->attr.mode = S_IRUGO; |
531 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 532 | ++count; |
da8d1c8b NH |
533 | } |
534 | ||
1c51b50c GKH |
535 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
536 | if (!msi_irq_group) | |
537 | goto error_attrs; | |
538 | msi_irq_group->name = "msi_irqs"; | |
539 | msi_irq_group->attrs = msi_attrs; | |
540 | ||
541 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
542 | if (!msi_irq_groups) | |
543 | goto error_irq_group; | |
544 | msi_irq_groups[0] = msi_irq_group; | |
545 | ||
546 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
547 | if (ret) | |
548 | goto error_irq_groups; | |
549 | pdev->msi_irq_groups = msi_irq_groups; | |
550 | ||
da8d1c8b NH |
551 | return 0; |
552 | ||
1c51b50c GKH |
553 | error_irq_groups: |
554 | kfree(msi_irq_groups); | |
555 | error_irq_group: | |
556 | kfree(msi_irq_group); | |
557 | error_attrs: | |
558 | count = 0; | |
559 | msi_attr = msi_attrs[count]; | |
560 | while (msi_attr) { | |
561 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
562 | kfree(msi_attr->name); | |
563 | kfree(msi_dev_attr); | |
564 | ++count; | |
565 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 566 | } |
29237756 | 567 | kfree(msi_attrs); |
da8d1c8b NH |
568 | return ret; |
569 | } | |
570 | ||
d873b4d4 YW |
571 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev) |
572 | { | |
573 | u16 control; | |
574 | struct msi_desc *entry; | |
575 | ||
576 | /* MSI Entry Initialization */ | |
577 | entry = alloc_msi_entry(dev); | |
578 | if (!entry) | |
579 | return NULL; | |
580 | ||
581 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
582 | ||
583 | entry->msi_attrib.is_msix = 0; | |
584 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
585 | entry->msi_attrib.entry_nr = 0; | |
586 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
587 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
588 | entry->msi_attrib.pos = dev->msi_cap; | |
589 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; | |
590 | ||
591 | if (control & PCI_MSI_FLAGS_64BIT) | |
592 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
593 | else | |
594 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
595 | ||
596 | /* Save the initial mask status */ | |
597 | if (entry->msi_attrib.maskbit) | |
598 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
599 | ||
600 | return entry; | |
601 | } | |
602 | ||
1da177e4 LT |
603 | /** |
604 | * msi_capability_init - configure device's MSI capability structure | |
605 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 606 | * @nvec: number of interrupts to allocate |
1da177e4 | 607 | * |
1c8d7b0a MW |
608 | * Setup the MSI capability structure of the device with the requested |
609 | * number of interrupts. A return value of zero indicates the successful | |
610 | * setup of an entry with the new MSI irq. A negative return value indicates | |
611 | * an error, and a positive return value indicates the number of interrupts | |
612 | * which could have been allocated. | |
613 | */ | |
614 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
615 | { |
616 | struct msi_desc *entry; | |
f465136d | 617 | int ret; |
f2440d9a | 618 | unsigned mask; |
1da177e4 | 619 | |
e375b561 | 620 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 621 | |
d873b4d4 | 622 | entry = msi_setup_entry(dev); |
f7feaca7 EB |
623 | if (!entry) |
624 | return -ENOMEM; | |
1ce03373 | 625 | |
f2440d9a | 626 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 627 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
628 | msi_mask_irq(entry, mask, mask); |
629 | ||
0dd11f9b | 630 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 631 | |
1da177e4 | 632 | /* Configure MSI capability structure */ |
1c8d7b0a | 633 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 634 | if (ret) { |
7ba1930d | 635 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 636 | free_msi_irqs(dev); |
7fe3730d | 637 | return ret; |
fd58e55f | 638 | } |
f7feaca7 | 639 | |
da8d1c8b NH |
640 | ret = populate_msi_sysfs(dev); |
641 | if (ret) { | |
642 | msi_mask_irq(entry, mask, ~mask); | |
643 | free_msi_irqs(dev); | |
644 | return ret; | |
645 | } | |
646 | ||
1da177e4 | 647 | /* Set MSI enabled bits */ |
ba698ad4 | 648 | pci_intx_for_msi(dev, 0); |
e375b561 | 649 | msi_set_enable(dev, 1); |
b1cbf4e4 | 650 | dev->msi_enabled = 1; |
1da177e4 | 651 | |
7fe3730d | 652 | dev->irq = entry->irq; |
1da177e4 LT |
653 | return 0; |
654 | } | |
655 | ||
520fe9dc | 656 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 657 | { |
4302e0fb | 658 | resource_size_t phys_addr; |
5a05a9d8 HS |
659 | u32 table_offset; |
660 | u8 bir; | |
661 | ||
909094c6 BH |
662 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
663 | &table_offset); | |
4d18760c BH |
664 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
665 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
666 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
667 | ||
668 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
669 | } | |
670 | ||
520fe9dc GS |
671 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
672 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
673 | { |
674 | struct msi_desc *entry; | |
675 | int i; | |
676 | ||
677 | for (i = 0; i < nvec; i++) { | |
678 | entry = alloc_msi_entry(dev); | |
679 | if (!entry) { | |
680 | if (!i) | |
681 | iounmap(base); | |
682 | else | |
683 | free_msi_irqs(dev); | |
684 | /* No enough memory. Don't try again */ | |
685 | return -ENOMEM; | |
686 | } | |
687 | ||
688 | entry->msi_attrib.is_msix = 1; | |
689 | entry->msi_attrib.is_64 = 1; | |
690 | entry->msi_attrib.entry_nr = entries[i].entry; | |
691 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 692 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
693 | entry->mask_base = base; |
694 | ||
695 | list_add_tail(&entry->list, &dev->msi_list); | |
696 | } | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
75cb3426 | 701 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 702 | struct msix_entry *entries) |
75cb3426 HS |
703 | { |
704 | struct msi_desc *entry; | |
705 | int i = 0; | |
706 | ||
707 | list_for_each_entry(entry, &dev->msi_list, list) { | |
708 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
709 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
710 | ||
711 | entries[i].vector = entry->irq; | |
dced35ae | 712 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
713 | entry->masked = readl(entry->mask_base + offset); |
714 | msix_mask_irq(entry, 1); | |
715 | i++; | |
716 | } | |
717 | } | |
718 | ||
1da177e4 LT |
719 | /** |
720 | * msix_capability_init - configure device's MSI-X capability | |
721 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
722 | * @entries: pointer to an array of struct msix_entry entries |
723 | * @nvec: number of @entries | |
1da177e4 | 724 | * |
eaae4b3a | 725 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
726 | * single MSI-X irq. A return of zero indicates the successful setup of |
727 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
728 | **/ |
729 | static int msix_capability_init(struct pci_dev *dev, | |
730 | struct msix_entry *entries, int nvec) | |
731 | { | |
520fe9dc | 732 | int ret; |
5a05a9d8 | 733 | u16 control; |
1da177e4 LT |
734 | void __iomem *base; |
735 | ||
f598282f | 736 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 737 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 738 | |
66f0d0c4 | 739 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 740 | /* Request & Map MSI-X table region */ |
527eee29 | 741 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 742 | if (!base) |
1da177e4 LT |
743 | return -ENOMEM; |
744 | ||
520fe9dc | 745 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
746 | if (ret) |
747 | return ret; | |
9c831334 ME |
748 | |
749 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 750 | if (ret) |
2adc7907 | 751 | goto out_avail; |
9c831334 | 752 | |
f598282f MW |
753 | /* |
754 | * Some devices require MSI-X to be enabled before we can touch the | |
755 | * MSI-X registers. We need to mask all the vectors to prevent | |
756 | * interrupts coming in before they're fully set up. | |
757 | */ | |
66f0d0c4 YW |
758 | msix_clear_and_set_ctrl(dev, 0, |
759 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 760 | |
75cb3426 | 761 | msix_program_entries(dev, entries); |
f598282f | 762 | |
da8d1c8b | 763 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
764 | if (ret) |
765 | goto out_free; | |
da8d1c8b | 766 | |
f598282f | 767 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 768 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 769 | dev->msix_enabled = 1; |
1da177e4 | 770 | |
66f0d0c4 | 771 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 772 | |
1da177e4 | 773 | return 0; |
583871d4 | 774 | |
2adc7907 | 775 | out_avail: |
583871d4 HS |
776 | if (ret < 0) { |
777 | /* | |
778 | * If we had some success, report the number of irqs | |
779 | * we succeeded in setting up. | |
780 | */ | |
d9d7070e | 781 | struct msi_desc *entry; |
583871d4 HS |
782 | int avail = 0; |
783 | ||
784 | list_for_each_entry(entry, &dev->msi_list, list) { | |
785 | if (entry->irq != 0) | |
786 | avail++; | |
787 | } | |
788 | if (avail != 0) | |
789 | ret = avail; | |
790 | } | |
791 | ||
2adc7907 | 792 | out_free: |
583871d4 HS |
793 | free_msi_irqs(dev); |
794 | ||
795 | return ret; | |
1da177e4 LT |
796 | } |
797 | ||
24334a12 | 798 | /** |
17bbc12a | 799 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 800 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 801 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 802 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 803 | * |
f7625980 | 804 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
805 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
806 | * supported return 0, else return an error code. | |
24334a12 | 807 | **/ |
ad975eba | 808 | static int pci_msi_check_device(struct pci_dev *dev, int nvec) |
24334a12 BG |
809 | { |
810 | struct pci_bus *bus; | |
811 | ||
0306ebfa | 812 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
813 | if (!pci_msi_enable || !dev || dev->no_msi) |
814 | return -EINVAL; | |
815 | ||
314e77b3 ME |
816 | /* |
817 | * You can't ask to have 0 or less MSIs configured. | |
818 | * a) it's stupid .. | |
819 | * b) the list manipulation code assumes nvec >= 1. | |
820 | */ | |
821 | if (nvec < 1) | |
822 | return -ERANGE; | |
823 | ||
500559a9 HS |
824 | /* |
825 | * Any bridge which does NOT route MSI transactions from its | |
826 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
827 | * the secondary pci_bus. |
828 | * We expect only arch-specific PCI host bus controller driver | |
829 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
830 | */ | |
24334a12 BG |
831 | for (bus = dev->bus; bus; bus = bus->parent) |
832 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
833 | return -EINVAL; | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
d1ac1d26 AG |
838 | /** |
839 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
840 | * @dev: device to report about | |
841 | * | |
842 | * This function returns the number of MSI vectors a device requested via | |
843 | * Multiple Message Capable register. It returns a negative errno if the | |
844 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
845 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
846 | * MSI specification. | |
847 | **/ | |
848 | int pci_msi_vec_count(struct pci_dev *dev) | |
849 | { | |
850 | int ret; | |
851 | u16 msgctl; | |
852 | ||
853 | if (!dev->msi_cap) | |
854 | return -EINVAL; | |
855 | ||
856 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
857 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
858 | ||
859 | return ret; | |
860 | } | |
861 | EXPORT_SYMBOL(pci_msi_vec_count); | |
862 | ||
f2440d9a | 863 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 864 | { |
f2440d9a MW |
865 | struct msi_desc *desc; |
866 | u32 mask; | |
1da177e4 | 867 | |
128bc5fc | 868 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
869 | return; |
870 | ||
110828c9 MW |
871 | BUG_ON(list_empty(&dev->msi_list)); |
872 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 873 | |
e375b561 | 874 | msi_set_enable(dev, 0); |
ba698ad4 | 875 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 876 | dev->msi_enabled = 0; |
7bd007e4 | 877 | |
12abb8ba | 878 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 879 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 880 | /* Keep cached state to be restored */ |
0e4ccb15 | 881 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
882 | |
883 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 884 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 885 | } |
24d27553 | 886 | |
500559a9 | 887 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 888 | { |
d52877c7 YL |
889 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
890 | return; | |
891 | ||
892 | pci_msi_shutdown(dev); | |
f56e4481 | 893 | free_msi_irqs(dev); |
1da177e4 | 894 | } |
4cc086fa | 895 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 896 | |
a52e2e35 | 897 | /** |
ff1aa430 | 898 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 899 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
900 | * This function returns the number of device's MSI-X table entries and |
901 | * therefore the number of MSI-X vectors device is capable of sending. | |
902 | * It returns a negative errno if the device is not capable of sending MSI-X | |
903 | * interrupts. | |
904 | **/ | |
905 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 906 | { |
a52e2e35 RW |
907 | u16 control; |
908 | ||
520fe9dc | 909 | if (!dev->msix_cap) |
ff1aa430 | 910 | return -EINVAL; |
a52e2e35 | 911 | |
f84ecd28 | 912 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 913 | return msix_table_size(control); |
a52e2e35 | 914 | } |
ff1aa430 | 915 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 916 | |
1da177e4 LT |
917 | /** |
918 | * pci_enable_msix - configure device's MSI-X capability structure | |
919 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 920 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 921 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
922 | * |
923 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 924 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
925 | * MSI-X mode enabled on its hardware device function. A return of zero |
926 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 927 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 928 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
929 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
930 | * re-send its request. | |
1da177e4 | 931 | **/ |
500559a9 | 932 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 933 | { |
a52e2e35 | 934 | int status, nr_entries; |
ded86d8d | 935 | int i, j; |
1da177e4 | 936 | |
869a1615 | 937 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 938 | return -EINVAL; |
1da177e4 | 939 | |
ad975eba | 940 | status = pci_msi_check_device(dev, nvec); |
c9953a73 ME |
941 | if (status) |
942 | return status; | |
943 | ||
ff1aa430 AG |
944 | nr_entries = pci_msix_vec_count(dev); |
945 | if (nr_entries < 0) | |
946 | return nr_entries; | |
1da177e4 | 947 | if (nvec > nr_entries) |
57fbf52c | 948 | return nr_entries; |
1da177e4 LT |
949 | |
950 | /* Check for any invalid entries */ | |
951 | for (i = 0; i < nvec; i++) { | |
952 | if (entries[i].entry >= nr_entries) | |
953 | return -EINVAL; /* invalid entry */ | |
954 | for (j = i + 1; j < nvec; j++) { | |
955 | if (entries[i].entry == entries[j].entry) | |
956 | return -EINVAL; /* duplicate entry */ | |
957 | } | |
958 | } | |
ded86d8d | 959 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 960 | |
1ce03373 | 961 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 962 | if (dev->msi_enabled) { |
227f0647 | 963 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
964 | return -EINVAL; |
965 | } | |
1da177e4 | 966 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
967 | return status; |
968 | } | |
4cc086fa | 969 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 970 | |
500559a9 | 971 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 972 | { |
12abb8ba HS |
973 | struct msi_desc *entry; |
974 | ||
128bc5fc | 975 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
976 | return; |
977 | ||
12abb8ba HS |
978 | /* Return the device with MSI-X masked as initial states */ |
979 | list_for_each_entry(entry, &dev->msi_list, list) { | |
980 | /* Keep cached states to be restored */ | |
0e4ccb15 | 981 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
982 | } |
983 | ||
66f0d0c4 | 984 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 985 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 986 | dev->msix_enabled = 0; |
d52877c7 | 987 | } |
c901851f | 988 | |
500559a9 | 989 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
990 | { |
991 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
992 | return; | |
993 | ||
994 | pci_msix_shutdown(dev); | |
f56e4481 | 995 | free_msi_irqs(dev); |
1da177e4 | 996 | } |
4cc086fa | 997 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 998 | |
309e57df MW |
999 | void pci_no_msi(void) |
1000 | { | |
1001 | pci_msi_enable = 0; | |
1002 | } | |
c9953a73 | 1003 | |
07ae95f9 AP |
1004 | /** |
1005 | * pci_msi_enabled - is MSI enabled? | |
1006 | * | |
1007 | * Returns true if MSI has not been disabled by the command-line option | |
1008 | * pci=nomsi. | |
1009 | **/ | |
1010 | int pci_msi_enabled(void) | |
d389fec6 | 1011 | { |
07ae95f9 | 1012 | return pci_msi_enable; |
d389fec6 | 1013 | } |
07ae95f9 | 1014 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1015 | |
07ae95f9 | 1016 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1017 | { |
07ae95f9 | 1018 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1019 | |
1020 | /* Disable the msi hardware to avoid screaming interrupts | |
1021 | * during boot. This is the power on reset default so | |
1022 | * usually this should be a noop. | |
1023 | */ | |
e375b561 GS |
1024 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1025 | if (dev->msi_cap) | |
1026 | msi_set_enable(dev, 0); | |
1027 | ||
1028 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1029 | if (dev->msix_cap) | |
66f0d0c4 | 1030 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1031 | } |
302a2523 AG |
1032 | |
1033 | /** | |
1034 | * pci_enable_msi_range - configure device's MSI capability structure | |
1035 | * @dev: device to configure | |
1036 | * @minvec: minimal number of interrupts to configure | |
1037 | * @maxvec: maximum number of interrupts to configure | |
1038 | * | |
1039 | * This function tries to allocate a maximum possible number of interrupts in a | |
1040 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1041 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1042 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1043 | * the other interrupt numbers allocated to this device are consecutive. | |
1044 | **/ | |
1045 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1046 | { | |
034cd97e | 1047 | int nvec; |
302a2523 AG |
1048 | int rc; |
1049 | ||
034cd97e AG |
1050 | if (dev->current_state != PCI_D0) |
1051 | return -EINVAL; | |
1052 | ||
1053 | WARN_ON(!!dev->msi_enabled); | |
1054 | ||
1055 | /* Check whether driver already requested MSI-X irqs */ | |
1056 | if (dev->msix_enabled) { | |
1057 | dev_info(&dev->dev, | |
1058 | "can't enable MSI (MSI-X already enabled)\n"); | |
1059 | return -EINVAL; | |
1060 | } | |
1061 | ||
302a2523 AG |
1062 | if (maxvec < minvec) |
1063 | return -ERANGE; | |
1064 | ||
034cd97e AG |
1065 | nvec = pci_msi_vec_count(dev); |
1066 | if (nvec < 0) | |
1067 | return nvec; | |
1068 | else if (nvec < minvec) | |
1069 | return -EINVAL; | |
1070 | else if (nvec > maxvec) | |
1071 | nvec = maxvec; | |
1072 | ||
1073 | do { | |
ad975eba | 1074 | rc = pci_msi_check_device(dev, nvec); |
034cd97e AG |
1075 | if (rc < 0) { |
1076 | return rc; | |
1077 | } else if (rc > 0) { | |
1078 | if (rc < minvec) | |
1079 | return -ENOSPC; | |
1080 | nvec = rc; | |
1081 | } | |
1082 | } while (rc); | |
1083 | ||
302a2523 | 1084 | do { |
034cd97e | 1085 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1086 | if (rc < 0) { |
1087 | return rc; | |
1088 | } else if (rc > 0) { | |
1089 | if (rc < minvec) | |
1090 | return -ENOSPC; | |
1091 | nvec = rc; | |
1092 | } | |
1093 | } while (rc); | |
1094 | ||
1095 | return nvec; | |
1096 | } | |
1097 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1098 | ||
1099 | /** | |
1100 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1101 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1102 | * @entries: pointer to an array of MSI-X entries | |
1103 | * @minvec: minimum number of MSI-X irqs requested | |
1104 | * @maxvec: maximum number of MSI-X irqs requested | |
1105 | * | |
1106 | * Setup the MSI-X capability structure of device function with a maximum | |
1107 | * possible number of interrupts in the range between @minvec and @maxvec | |
1108 | * upon its software driver call to request for MSI-X mode enabled on its | |
1109 | * hardware device function. It returns a negative errno if an error occurs. | |
1110 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1111 | * indicates the successful configuration of MSI-X capability structure | |
1112 | * with new allocated MSI-X interrupts. | |
1113 | **/ | |
1114 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1115 | int minvec, int maxvec) | |
1116 | { | |
1117 | int nvec = maxvec; | |
1118 | int rc; | |
1119 | ||
1120 | if (maxvec < minvec) | |
1121 | return -ERANGE; | |
1122 | ||
1123 | do { | |
1124 | rc = pci_enable_msix(dev, entries, nvec); | |
1125 | if (rc < 0) { | |
1126 | return rc; | |
1127 | } else if (rc > 0) { | |
1128 | if (rc < minvec) | |
1129 | return -ENOSPC; | |
1130 | nvec = rc; | |
1131 | } | |
1132 | } while (rc); | |
1133 | ||
1134 | return nvec; | |
1135 | } | |
1136 | EXPORT_SYMBOL(pci_enable_msix_range); |