Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
6a9e7f20 AB |
29 | /* Arch hooks */ |
30 | ||
11df1f05 ME |
31 | #ifndef arch_msi_check_device |
32 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
33 | { |
34 | return 0; | |
35 | } | |
11df1f05 | 36 | #endif |
6a9e7f20 | 37 | |
11df1f05 | 38 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
39 | # define arch_setup_msi_irqs default_setup_msi_irqs |
40 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
41 | #endif | |
42 | ||
43 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
44 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
45 | { |
46 | struct msi_desc *entry; | |
47 | int ret; | |
48 | ||
1c8d7b0a MW |
49 | /* |
50 | * If an architecture wants to support multiple MSI, it needs to | |
51 | * override arch_setup_msi_irqs() | |
52 | */ | |
53 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
54 | return 1; | |
55 | ||
6a9e7f20 AB |
56 | list_for_each_entry(entry, &dev->msi_list, list) { |
57 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 58 | if (ret < 0) |
6a9e7f20 | 59 | return ret; |
b5fbf533 ME |
60 | if (ret > 0) |
61 | return -ENOSPC; | |
6a9e7f20 AB |
62 | } |
63 | ||
64 | return 0; | |
65 | } | |
11df1f05 | 66 | #endif |
6a9e7f20 | 67 | |
11df1f05 | 68 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
69 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
70 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
71 | #endif | |
72 | ||
73 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
74 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | ||
78 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
79 | int i, nvec; |
80 | if (entry->irq == 0) | |
81 | continue; | |
82 | nvec = 1 << entry->msi_attrib.multiple; | |
83 | for (i = 0; i < nvec; i++) | |
84 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
85 | } |
86 | } | |
11df1f05 | 87 | #endif |
6a9e7f20 | 88 | |
76ccc297 KRW |
89 | #ifndef arch_restore_msi_irqs |
90 | # define arch_restore_msi_irqs default_restore_msi_irqs | |
91 | # define HAVE_DEFAULT_MSI_RESTORE_IRQS | |
92 | #endif | |
93 | ||
94 | #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS | |
95 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) | |
96 | { | |
97 | struct msi_desc *entry; | |
98 | ||
99 | entry = NULL; | |
100 | if (dev->msix_enabled) { | |
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
102 | if (irq == entry->irq) | |
103 | break; | |
104 | } | |
105 | } else if (dev->msi_enabled) { | |
106 | entry = irq_get_msi_desc(irq); | |
107 | } | |
108 | ||
109 | if (entry) | |
110 | write_msi_msg(irq, &entry->msg); | |
111 | } | |
112 | #endif | |
113 | ||
e375b561 | 114 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 115 | { |
b1cbf4e4 EB |
116 | u16 control; |
117 | ||
e375b561 | 118 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
119 | control &= ~PCI_MSI_FLAGS_ENABLE; |
120 | if (enable) | |
121 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 122 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
123 | } |
124 | ||
b1cbf4e4 EB |
125 | static void msix_set_enable(struct pci_dev *dev, int enable) |
126 | { | |
b1cbf4e4 EB |
127 | u16 control; |
128 | ||
e375b561 GS |
129 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
130 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
131 | if (enable) | |
132 | control |= PCI_MSIX_FLAGS_ENABLE; | |
133 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
134 | } |
135 | ||
bffac3c5 MW |
136 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
137 | { | |
0b49ec37 MW |
138 | /* Don't shift by >= width of type */ |
139 | if (x >= 5) | |
140 | return 0xffffffff; | |
141 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
142 | } |
143 | ||
f2440d9a | 144 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 145 | { |
f2440d9a MW |
146 | return msi_mask((control >> 1) & 7); |
147 | } | |
988cbb15 | 148 | |
f2440d9a MW |
149 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
150 | { | |
151 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
152 | } |
153 | ||
ce6fce42 MW |
154 | /* |
155 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
156 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
157 | * reliably as devices without an INTx disable bit will then generate a | |
158 | * level IRQ which will never be cleared. | |
ce6fce42 | 159 | */ |
12abb8ba | 160 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 161 | { |
f2440d9a | 162 | u32 mask_bits = desc->masked; |
1da177e4 | 163 | |
f2440d9a | 164 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 165 | return 0; |
f2440d9a MW |
166 | |
167 | mask_bits &= ~mask; | |
168 | mask_bits |= flag; | |
169 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
170 | |
171 | return mask_bits; | |
172 | } | |
173 | ||
174 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
175 | { | |
176 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
177 | } |
178 | ||
179 | /* | |
180 | * This internal function does not flush PCI writes to the device. | |
181 | * All users must ensure that they read from the device before either | |
182 | * assuming that the device state is up to date, or returning out of this | |
183 | * file. This saves a few milliseconds when initialising devices with lots | |
184 | * of MSI-X interrupts. | |
185 | */ | |
12abb8ba | 186 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
187 | { |
188 | u32 mask_bits = desc->masked; | |
189 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 190 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
191 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
192 | if (flag) | |
193 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 194 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
195 | |
196 | return mask_bits; | |
197 | } | |
198 | ||
199 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
200 | { | |
201 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 202 | } |
24d27553 | 203 | |
9a4da8a5 JG |
204 | #ifdef CONFIG_GENERIC_HARDIRQS |
205 | ||
1c9db525 | 206 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 207 | { |
1c9db525 | 208 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 209 | |
f2440d9a MW |
210 | if (desc->msi_attrib.is_msix) { |
211 | msix_mask_irq(desc, flag); | |
212 | readl(desc->mask_base); /* Flush write to device */ | |
213 | } else { | |
1c9db525 | 214 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 215 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 216 | } |
f2440d9a MW |
217 | } |
218 | ||
1c9db525 | 219 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 220 | { |
1c9db525 | 221 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
222 | } |
223 | ||
1c9db525 | 224 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 225 | { |
1c9db525 | 226 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
227 | } |
228 | ||
9a4da8a5 JG |
229 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
230 | ||
39431acb | 231 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 232 | { |
30da5524 BH |
233 | BUG_ON(entry->dev->current_state != PCI_D0); |
234 | ||
235 | if (entry->msi_attrib.is_msix) { | |
236 | void __iomem *base = entry->mask_base + | |
237 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
238 | ||
239 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
240 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
241 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
242 | } else { | |
243 | struct pci_dev *dev = entry->dev; | |
244 | int pos = entry->msi_attrib.pos; | |
245 | u16 data; | |
246 | ||
247 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
248 | &msg->address_lo); | |
249 | if (entry->msi_attrib.is_64) { | |
250 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
251 | &msg->address_hi); | |
252 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
253 | } else { | |
254 | msg->address_hi = 0; | |
255 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
256 | } | |
257 | msg->data = data; | |
258 | } | |
259 | } | |
260 | ||
261 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
262 | { | |
dced35ae | 263 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 264 | |
39431acb | 265 | __read_msi_msg(entry, msg); |
30da5524 BH |
266 | } |
267 | ||
39431acb | 268 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 269 | { |
30da5524 | 270 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
271 | * valid messages are not all-zeroes. */ |
272 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
273 | entry->msg.data)); | |
0366f8f7 | 274 | |
fcd097f3 | 275 | *msg = entry->msg; |
0366f8f7 | 276 | } |
1da177e4 | 277 | |
30da5524 | 278 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 279 | { |
dced35ae | 280 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 281 | |
39431acb | 282 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
283 | } |
284 | ||
39431acb | 285 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 286 | { |
fcd097f3 BH |
287 | if (entry->dev->current_state != PCI_D0) { |
288 | /* Don't touch the hardware now */ | |
289 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
290 | void __iomem *base; |
291 | base = entry->mask_base + | |
292 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
293 | ||
2c21fd4b HS |
294 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
295 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
296 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 297 | } else { |
0366f8f7 EB |
298 | struct pci_dev *dev = entry->dev; |
299 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
300 | u16 msgctl; |
301 | ||
302 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
303 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
304 | msgctl |= entry->msi_attrib.multiple << 4; | |
305 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
306 | |
307 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
308 | msg->address_lo); | |
309 | if (entry->msi_attrib.is_64) { | |
310 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
311 | msg->address_hi); | |
312 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
313 | msg->data); | |
314 | } else { | |
315 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
316 | msg->data); | |
317 | } | |
1da177e4 | 318 | } |
392ee1e6 | 319 | entry->msg = *msg; |
1da177e4 | 320 | } |
0366f8f7 | 321 | |
3145e941 YL |
322 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
323 | { | |
dced35ae | 324 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 325 | |
39431acb | 326 | __write_msi_msg(entry, msg); |
3145e941 YL |
327 | } |
328 | ||
f56e4481 HS |
329 | static void free_msi_irqs(struct pci_dev *dev) |
330 | { | |
331 | struct msi_desc *entry, *tmp; | |
332 | ||
333 | list_for_each_entry(entry, &dev->msi_list, list) { | |
334 | int i, nvec; | |
335 | if (!entry->irq) | |
336 | continue; | |
337 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 338 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
339 | for (i = 0; i < nvec; i++) |
340 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 341 | #endif |
f56e4481 HS |
342 | } |
343 | ||
344 | arch_teardown_msi_irqs(dev); | |
345 | ||
346 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
347 | if (entry->msi_attrib.is_msix) { | |
348 | if (list_is_last(&entry->list, &dev->msi_list)) | |
349 | iounmap(entry->mask_base); | |
350 | } | |
424eb391 NH |
351 | |
352 | /* | |
353 | * Its possible that we get into this path | |
354 | * When populate_msi_sysfs fails, which means the entries | |
355 | * were not registered with sysfs. In that case don't | |
356 | * unregister them. | |
357 | */ | |
358 | if (entry->kobj.parent) { | |
359 | kobject_del(&entry->kobj); | |
360 | kobject_put(&entry->kobj); | |
361 | } | |
362 | ||
f56e4481 HS |
363 | list_del(&entry->list); |
364 | kfree(entry); | |
365 | } | |
366 | } | |
c54c1879 | 367 | |
379f5327 | 368 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 369 | { |
379f5327 MW |
370 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
371 | if (!desc) | |
1da177e4 LT |
372 | return NULL; |
373 | ||
379f5327 MW |
374 | INIT_LIST_HEAD(&desc->list); |
375 | desc->dev = dev; | |
1da177e4 | 376 | |
379f5327 | 377 | return desc; |
1da177e4 LT |
378 | } |
379 | ||
ba698ad4 DM |
380 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
381 | { | |
382 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
383 | pci_intx(dev, enable); | |
384 | } | |
385 | ||
8fed4b65 | 386 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 387 | { |
392ee1e6 | 388 | int pos; |
41017f0c | 389 | u16 control; |
392ee1e6 | 390 | struct msi_desc *entry; |
41017f0c | 391 | |
b1cbf4e4 EB |
392 | if (!dev->msi_enabled) |
393 | return; | |
394 | ||
dced35ae | 395 | entry = irq_get_msi_desc(dev->irq); |
392ee1e6 | 396 | pos = entry->msi_attrib.pos; |
41017f0c | 397 | |
ba698ad4 | 398 | pci_intx_for_msi(dev, 0); |
e375b561 | 399 | msi_set_enable(dev, 0); |
76ccc297 | 400 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 EB |
401 | |
402 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 403 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 404 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 405 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 406 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
407 | } |
408 | ||
409 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 410 | { |
41017f0c | 411 | int pos; |
41017f0c | 412 | struct msi_desc *entry; |
392ee1e6 | 413 | u16 control; |
41017f0c | 414 | |
ded86d8d EB |
415 | if (!dev->msix_enabled) |
416 | return; | |
f598282f | 417 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 418 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
419 | pos = entry->msi_attrib.pos; |
420 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 421 | |
41017f0c | 422 | /* route the table */ |
ba698ad4 | 423 | pci_intx_for_msi(dev, 0); |
f598282f MW |
424 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
425 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 426 | |
4aa9bc95 | 427 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 428 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 429 | msix_mask_irq(entry, entry->masked); |
41017f0c | 430 | } |
41017f0c | 431 | |
392ee1e6 | 432 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 433 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 434 | } |
8fed4b65 ME |
435 | |
436 | void pci_restore_msi_state(struct pci_dev *dev) | |
437 | { | |
438 | __pci_restore_msi_state(dev); | |
439 | __pci_restore_msix_state(dev); | |
440 | } | |
94688cf2 | 441 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 442 | |
da8d1c8b NH |
443 | |
444 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
445 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
446 | ||
447 | struct msi_attribute { | |
448 | struct attribute attr; | |
449 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
450 | char *buf); | |
451 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
452 | const char *buf, size_t count); | |
453 | }; | |
454 | ||
455 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
456 | char *buf) | |
457 | { | |
458 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
459 | } | |
460 | ||
461 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
462 | struct attribute *attr, char *buf) | |
463 | { | |
464 | struct msi_attribute *attribute = to_msi_attr(attr); | |
465 | struct msi_desc *entry = to_msi_desc(kobj); | |
466 | ||
467 | if (!attribute->show) | |
468 | return -EIO; | |
469 | ||
470 | return attribute->show(entry, attribute, buf); | |
471 | } | |
472 | ||
473 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
474 | .show = msi_irq_attr_show, | |
475 | }; | |
476 | ||
477 | static struct msi_attribute mode_attribute = | |
478 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
479 | ||
480 | ||
481 | struct attribute *msi_irq_default_attrs[] = { | |
482 | &mode_attribute.attr, | |
483 | NULL | |
484 | }; | |
485 | ||
486 | void msi_kobj_release(struct kobject *kobj) | |
487 | { | |
488 | struct msi_desc *entry = to_msi_desc(kobj); | |
489 | ||
490 | pci_dev_put(entry->dev); | |
491 | } | |
492 | ||
493 | static struct kobj_type msi_irq_ktype = { | |
494 | .release = msi_kobj_release, | |
495 | .sysfs_ops = &msi_irq_sysfs_ops, | |
496 | .default_attrs = msi_irq_default_attrs, | |
497 | }; | |
498 | ||
499 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
500 | { | |
501 | struct msi_desc *entry; | |
502 | struct kobject *kobj; | |
503 | int ret; | |
504 | int count = 0; | |
505 | ||
506 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
507 | if (!pdev->msi_kset) | |
508 | return -ENOMEM; | |
509 | ||
510 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
511 | kobj = &entry->kobj; | |
512 | kobj->kset = pdev->msi_kset; | |
513 | pci_dev_get(pdev); | |
514 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
515 | "%u", entry->irq); | |
516 | if (ret) | |
517 | goto out_unroll; | |
518 | ||
519 | count++; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | ||
524 | out_unroll: | |
525 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
526 | if (!count) | |
527 | break; | |
528 | kobject_del(&entry->kobj); | |
529 | kobject_put(&entry->kobj); | |
530 | count--; | |
531 | } | |
532 | return ret; | |
533 | } | |
534 | ||
1da177e4 LT |
535 | /** |
536 | * msi_capability_init - configure device's MSI capability structure | |
537 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 538 | * @nvec: number of interrupts to allocate |
1da177e4 | 539 | * |
1c8d7b0a MW |
540 | * Setup the MSI capability structure of the device with the requested |
541 | * number of interrupts. A return value of zero indicates the successful | |
542 | * setup of an entry with the new MSI irq. A negative return value indicates | |
543 | * an error, and a positive return value indicates the number of interrupts | |
544 | * which could have been allocated. | |
545 | */ | |
546 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
547 | { |
548 | struct msi_desc *entry; | |
f465136d | 549 | int ret; |
1da177e4 | 550 | u16 control; |
f2440d9a | 551 | unsigned mask; |
1da177e4 | 552 | |
e375b561 | 553 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 554 | |
f465136d | 555 | pci_read_config_word(dev, msi_control_reg(dev->msi_cap), &control); |
1da177e4 | 556 | /* MSI Entry Initialization */ |
379f5327 | 557 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
558 | if (!entry) |
559 | return -ENOMEM; | |
1ce03373 | 560 | |
500559a9 HS |
561 | entry->msi_attrib.is_msix = 0; |
562 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
563 | entry->msi_attrib.entry_nr = 0; | |
564 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
565 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
f465136d | 566 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 567 | |
f465136d | 568 | entry->mask_pos = msi_mask_reg(dev->msi_cap, entry->msi_attrib.is_64); |
f2440d9a MW |
569 | /* All MSIs are unmasked by default, Mask them all */ |
570 | if (entry->msi_attrib.maskbit) | |
571 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
572 | mask = msi_capable_mask(control); | |
573 | msi_mask_irq(entry, mask, mask); | |
574 | ||
0dd11f9b | 575 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 576 | |
1da177e4 | 577 | /* Configure MSI capability structure */ |
1c8d7b0a | 578 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 579 | if (ret) { |
7ba1930d | 580 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 581 | free_msi_irqs(dev); |
7fe3730d | 582 | return ret; |
fd58e55f | 583 | } |
f7feaca7 | 584 | |
da8d1c8b NH |
585 | ret = populate_msi_sysfs(dev); |
586 | if (ret) { | |
587 | msi_mask_irq(entry, mask, ~mask); | |
588 | free_msi_irqs(dev); | |
589 | return ret; | |
590 | } | |
591 | ||
1da177e4 | 592 | /* Set MSI enabled bits */ |
ba698ad4 | 593 | pci_intx_for_msi(dev, 0); |
e375b561 | 594 | msi_set_enable(dev, 1); |
b1cbf4e4 | 595 | dev->msi_enabled = 1; |
1da177e4 | 596 | |
7fe3730d | 597 | dev->irq = entry->irq; |
1da177e4 LT |
598 | return 0; |
599 | } | |
600 | ||
5a05a9d8 HS |
601 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
602 | unsigned nr_entries) | |
603 | { | |
4302e0fb | 604 | resource_size_t phys_addr; |
5a05a9d8 HS |
605 | u32 table_offset; |
606 | u8 bir; | |
607 | ||
608 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
609 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
610 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
611 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
612 | ||
613 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
614 | } | |
615 | ||
d9d7070e HS |
616 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
617 | void __iomem *base, struct msix_entry *entries, | |
618 | int nvec) | |
619 | { | |
620 | struct msi_desc *entry; | |
621 | int i; | |
622 | ||
623 | for (i = 0; i < nvec; i++) { | |
624 | entry = alloc_msi_entry(dev); | |
625 | if (!entry) { | |
626 | if (!i) | |
627 | iounmap(base); | |
628 | else | |
629 | free_msi_irqs(dev); | |
630 | /* No enough memory. Don't try again */ | |
631 | return -ENOMEM; | |
632 | } | |
633 | ||
634 | entry->msi_attrib.is_msix = 1; | |
635 | entry->msi_attrib.is_64 = 1; | |
636 | entry->msi_attrib.entry_nr = entries[i].entry; | |
637 | entry->msi_attrib.default_irq = dev->irq; | |
638 | entry->msi_attrib.pos = pos; | |
639 | entry->mask_base = base; | |
640 | ||
641 | list_add_tail(&entry->list, &dev->msi_list); | |
642 | } | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
75cb3426 HS |
647 | static void msix_program_entries(struct pci_dev *dev, |
648 | struct msix_entry *entries) | |
649 | { | |
650 | struct msi_desc *entry; | |
651 | int i = 0; | |
652 | ||
653 | list_for_each_entry(entry, &dev->msi_list, list) { | |
654 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
655 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
656 | ||
657 | entries[i].vector = entry->irq; | |
dced35ae | 658 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
659 | entry->masked = readl(entry->mask_base + offset); |
660 | msix_mask_irq(entry, 1); | |
661 | i++; | |
662 | } | |
663 | } | |
664 | ||
1da177e4 LT |
665 | /** |
666 | * msix_capability_init - configure device's MSI-X capability | |
667 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
668 | * @entries: pointer to an array of struct msix_entry entries |
669 | * @nvec: number of @entries | |
1da177e4 | 670 | * |
eaae4b3a | 671 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
672 | * single MSI-X irq. A return of zero indicates the successful setup of |
673 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
674 | **/ |
675 | static int msix_capability_init(struct pci_dev *dev, | |
676 | struct msix_entry *entries, int nvec) | |
677 | { | |
d9d7070e | 678 | int pos, ret; |
5a05a9d8 | 679 | u16 control; |
1da177e4 LT |
680 | void __iomem *base; |
681 | ||
500559a9 | 682 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
683 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
684 | ||
685 | /* Ensure MSI-X is disabled while it is set up */ | |
686 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
687 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
688 | ||
1da177e4 | 689 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
690 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
691 | if (!base) | |
1da177e4 LT |
692 | return -ENOMEM; |
693 | ||
d9d7070e HS |
694 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
695 | if (ret) | |
696 | return ret; | |
9c831334 ME |
697 | |
698 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
699 | if (ret) |
700 | goto error; | |
9c831334 | 701 | |
f598282f MW |
702 | /* |
703 | * Some devices require MSI-X to be enabled before we can touch the | |
704 | * MSI-X registers. We need to mask all the vectors to prevent | |
705 | * interrupts coming in before they're fully set up. | |
706 | */ | |
707 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
708 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
709 | ||
75cb3426 | 710 | msix_program_entries(dev, entries); |
f598282f | 711 | |
da8d1c8b NH |
712 | ret = populate_msi_sysfs(dev); |
713 | if (ret) { | |
714 | ret = 0; | |
715 | goto error; | |
716 | } | |
717 | ||
f598282f | 718 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 719 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 720 | dev->msix_enabled = 1; |
1da177e4 | 721 | |
f598282f MW |
722 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
723 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 724 | |
1da177e4 | 725 | return 0; |
583871d4 HS |
726 | |
727 | error: | |
728 | if (ret < 0) { | |
729 | /* | |
730 | * If we had some success, report the number of irqs | |
731 | * we succeeded in setting up. | |
732 | */ | |
d9d7070e | 733 | struct msi_desc *entry; |
583871d4 HS |
734 | int avail = 0; |
735 | ||
736 | list_for_each_entry(entry, &dev->msi_list, list) { | |
737 | if (entry->irq != 0) | |
738 | avail++; | |
739 | } | |
740 | if (avail != 0) | |
741 | ret = avail; | |
742 | } | |
743 | ||
744 | free_msi_irqs(dev); | |
745 | ||
746 | return ret; | |
1da177e4 LT |
747 | } |
748 | ||
24334a12 | 749 | /** |
17bbc12a | 750 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 751 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 752 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 753 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 754 | * |
0306ebfa | 755 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
756 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
757 | * supported return 0, else return an error code. | |
24334a12 | 758 | **/ |
500559a9 | 759 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
760 | { |
761 | struct pci_bus *bus; | |
c9953a73 | 762 | int ret; |
24334a12 | 763 | |
0306ebfa | 764 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
765 | if (!pci_msi_enable || !dev || dev->no_msi) |
766 | return -EINVAL; | |
767 | ||
314e77b3 ME |
768 | /* |
769 | * You can't ask to have 0 or less MSIs configured. | |
770 | * a) it's stupid .. | |
771 | * b) the list manipulation code assumes nvec >= 1. | |
772 | */ | |
773 | if (nvec < 1) | |
774 | return -ERANGE; | |
775 | ||
500559a9 HS |
776 | /* |
777 | * Any bridge which does NOT route MSI transactions from its | |
778 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
779 | * the secondary pci_bus. |
780 | * We expect only arch-specific PCI host bus controller driver | |
781 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
782 | */ | |
24334a12 BG |
783 | for (bus = dev->bus; bus; bus = bus->parent) |
784 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
785 | return -EINVAL; | |
786 | ||
c9953a73 ME |
787 | ret = arch_msi_check_device(dev, nvec, type); |
788 | if (ret) | |
789 | return ret; | |
790 | ||
24334a12 BG |
791 | return 0; |
792 | } | |
793 | ||
1da177e4 | 794 | /** |
1c8d7b0a MW |
795 | * pci_enable_msi_block - configure device's MSI capability structure |
796 | * @dev: device to configure | |
797 | * @nvec: number of interrupts to configure | |
1da177e4 | 798 | * |
1c8d7b0a MW |
799 | * Allocate IRQs for a device with the MSI capability. |
800 | * This function returns a negative errno if an error occurs. If it | |
801 | * is unable to allocate the number of interrupts requested, it returns | |
802 | * the number of interrupts it might be able to allocate. If it successfully | |
803 | * allocates at least the number of interrupts requested, it returns 0 and | |
804 | * updates the @dev's irq member to the lowest new interrupt number; the | |
805 | * other interrupt numbers allocated to this device are consecutive. | |
806 | */ | |
807 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 808 | { |
f465136d | 809 | int status, maxvec; |
1c8d7b0a MW |
810 | u16 msgctl; |
811 | ||
f465136d | 812 | if (!dev->msi_cap) |
1c8d7b0a | 813 | return -EINVAL; |
f465136d GS |
814 | |
815 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
816 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
817 | if (nvec > maxvec) | |
818 | return maxvec; | |
1da177e4 | 819 | |
1c8d7b0a | 820 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
821 | if (status) |
822 | return status; | |
1da177e4 | 823 | |
ded86d8d | 824 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 825 | |
1c8d7b0a | 826 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 827 | if (dev->msix_enabled) { |
80ccba11 BH |
828 | dev_info(&dev->dev, "can't enable MSI " |
829 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 830 | return -EINVAL; |
1da177e4 | 831 | } |
1c8d7b0a MW |
832 | |
833 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
834 | return status; |
835 | } | |
1c8d7b0a | 836 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 837 | |
08261d87 AG |
838 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
839 | { | |
f465136d | 840 | int ret, nvec; |
08261d87 AG |
841 | u16 msgctl; |
842 | ||
f465136d | 843 | if (!dev->msi_cap) |
08261d87 AG |
844 | return -EINVAL; |
845 | ||
f465136d | 846 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
847 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
848 | ||
849 | if (maxvec) | |
850 | *maxvec = ret; | |
851 | ||
852 | do { | |
853 | nvec = ret; | |
854 | ret = pci_enable_msi_block(dev, nvec); | |
855 | } while (ret > 0); | |
856 | ||
857 | if (ret < 0) | |
858 | return ret; | |
859 | return nvec; | |
860 | } | |
861 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
862 | ||
f2440d9a | 863 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 864 | { |
f2440d9a MW |
865 | struct msi_desc *desc; |
866 | u32 mask; | |
867 | u16 ctrl; | |
110828c9 | 868 | unsigned pos; |
1da177e4 | 869 | |
128bc5fc | 870 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
871 | return; |
872 | ||
110828c9 MW |
873 | BUG_ON(list_empty(&dev->msi_list)); |
874 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
875 | pos = desc->msi_attrib.pos; | |
876 | ||
e375b561 | 877 | msi_set_enable(dev, 0); |
ba698ad4 | 878 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 879 | dev->msi_enabled = 0; |
7bd007e4 | 880 | |
12abb8ba | 881 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 882 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 883 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
884 | /* Keep cached state to be restored */ |
885 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
886 | |
887 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 888 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 889 | } |
24d27553 | 890 | |
500559a9 | 891 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 892 | { |
d52877c7 YL |
893 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
894 | return; | |
895 | ||
896 | pci_msi_shutdown(dev); | |
f56e4481 | 897 | free_msi_irqs(dev); |
da8d1c8b NH |
898 | kset_unregister(dev->msi_kset); |
899 | dev->msi_kset = NULL; | |
1da177e4 | 900 | } |
4cc086fa | 901 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 902 | |
a52e2e35 RW |
903 | /** |
904 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
905 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
906 | */ | |
907 | int pci_msix_table_size(struct pci_dev *dev) | |
908 | { | |
909 | int pos; | |
910 | u16 control; | |
911 | ||
912 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
913 | if (!pos) | |
914 | return 0; | |
915 | ||
916 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
917 | return multi_msix_capable(control); | |
918 | } | |
919 | ||
1da177e4 LT |
920 | /** |
921 | * pci_enable_msix - configure device's MSI-X capability structure | |
922 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 923 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 924 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
925 | * |
926 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 927 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
928 | * MSI-X mode enabled on its hardware device function. A return of zero |
929 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 930 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 931 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
932 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
933 | * re-send its request. | |
1da177e4 | 934 | **/ |
500559a9 | 935 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 936 | { |
a52e2e35 | 937 | int status, nr_entries; |
ded86d8d | 938 | int i, j; |
1da177e4 | 939 | |
cdf1fd4d | 940 | if (!entries || !dev->msix_cap) |
500559a9 | 941 | return -EINVAL; |
1da177e4 | 942 | |
c9953a73 ME |
943 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
944 | if (status) | |
945 | return status; | |
946 | ||
a52e2e35 | 947 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 948 | if (nvec > nr_entries) |
57fbf52c | 949 | return nr_entries; |
1da177e4 LT |
950 | |
951 | /* Check for any invalid entries */ | |
952 | for (i = 0; i < nvec; i++) { | |
953 | if (entries[i].entry >= nr_entries) | |
954 | return -EINVAL; /* invalid entry */ | |
955 | for (j = i + 1; j < nvec; j++) { | |
956 | if (entries[i].entry == entries[j].entry) | |
957 | return -EINVAL; /* duplicate entry */ | |
958 | } | |
959 | } | |
ded86d8d | 960 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 961 | |
1ce03373 | 962 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 963 | if (dev->msi_enabled) { |
80ccba11 BH |
964 | dev_info(&dev->dev, "can't enable MSI-X " |
965 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
966 | return -EINVAL; |
967 | } | |
1da177e4 | 968 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
969 | return status; |
970 | } | |
4cc086fa | 971 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 972 | |
500559a9 | 973 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 974 | { |
12abb8ba HS |
975 | struct msi_desc *entry; |
976 | ||
128bc5fc | 977 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
978 | return; |
979 | ||
12abb8ba HS |
980 | /* Return the device with MSI-X masked as initial states */ |
981 | list_for_each_entry(entry, &dev->msi_list, list) { | |
982 | /* Keep cached states to be restored */ | |
983 | __msix_mask_irq(entry, 1); | |
984 | } | |
985 | ||
b1cbf4e4 | 986 | msix_set_enable(dev, 0); |
ba698ad4 | 987 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 988 | dev->msix_enabled = 0; |
d52877c7 | 989 | } |
c901851f | 990 | |
500559a9 | 991 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
992 | { |
993 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
994 | return; | |
995 | ||
996 | pci_msix_shutdown(dev); | |
f56e4481 | 997 | free_msi_irqs(dev); |
da8d1c8b NH |
998 | kset_unregister(dev->msi_kset); |
999 | dev->msi_kset = NULL; | |
1da177e4 | 1000 | } |
4cc086fa | 1001 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1002 | |
1003 | /** | |
1ce03373 | 1004 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1005 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1006 | * | |
eaae4b3a | 1007 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1008 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1009 | * allocated for this device function, are reclaimed to unused state, |
1010 | * which may be used later on. | |
1011 | **/ | |
500559a9 | 1012 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1013 | { |
1da177e4 | 1014 | if (!pci_msi_enable || !dev) |
500559a9 | 1015 | return; |
1da177e4 | 1016 | |
f56e4481 HS |
1017 | if (dev->msi_enabled || dev->msix_enabled) |
1018 | free_msi_irqs(dev); | |
1da177e4 LT |
1019 | } |
1020 | ||
309e57df MW |
1021 | void pci_no_msi(void) |
1022 | { | |
1023 | pci_msi_enable = 0; | |
1024 | } | |
c9953a73 | 1025 | |
07ae95f9 AP |
1026 | /** |
1027 | * pci_msi_enabled - is MSI enabled? | |
1028 | * | |
1029 | * Returns true if MSI has not been disabled by the command-line option | |
1030 | * pci=nomsi. | |
1031 | **/ | |
1032 | int pci_msi_enabled(void) | |
d389fec6 | 1033 | { |
07ae95f9 | 1034 | return pci_msi_enable; |
d389fec6 | 1035 | } |
07ae95f9 | 1036 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1037 | |
07ae95f9 | 1038 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1039 | { |
07ae95f9 | 1040 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1041 | |
1042 | /* Disable the msi hardware to avoid screaming interrupts | |
1043 | * during boot. This is the power on reset default so | |
1044 | * usually this should be a noop. | |
1045 | */ | |
e375b561 GS |
1046 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1047 | if (dev->msi_cap) | |
1048 | msi_set_enable(dev, 0); | |
1049 | ||
1050 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1051 | if (dev->msix_cap) | |
1052 | msix_set_enable(dev, 0); | |
d389fec6 | 1053 | } |