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V4L/DVB (5101): Renamed video_mux to cx88_video_mux
[deliverable/linux.git] / drivers / pci / pci.c
CommitLineData
1da177e4
LT		 1/*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12#include <linux/kernel.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
1da177e4 19#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 20#include "pci.h"
1da177e4 21
ffadcc2f 22unsigned int pci_pm_d3_delay = 10;
1da177e4 23
4516a618
AN		 24#define DEFAULT_CARDBUS_IO_SIZE (256)
25#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
26/* pci=cbmemsize=nnM,cbiosize=nn can override this */
27unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
28unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
29
1da177e4
LT		 30/**
31 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
32 * @bus: pointer to PCI bus structure to search
33 *
34 * Given a PCI bus, returns the highest PCI bus number present in the set
35 * including the given PCI bus and its list of child PCI buses.
36 */
37unsigned char __devinit
38pci_bus_max_busnr(struct pci_bus* bus)
39{
40 struct list_head *tmp;
41 unsigned char max, n;
42
b82db5ce 43 max = bus->subordinate;
1da177e4
LT		 44 list_for_each(tmp, &bus->children) {
45 n = pci_bus_max_busnr(pci_bus_b(tmp));
46 if(n > max)
47 max = n;
48 }
49 return max;
50}
b82db5ce 51EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 52
b82db5ce 53#if 0
1da177e4
LT		 54/**
55 * pci_max_busnr - returns maximum PCI bus number
56 *
57 * Returns the highest PCI bus number present in the system global list of
58 * PCI buses.
59 */
60unsigned char __devinit
61pci_max_busnr(void)
62{
63 struct pci_bus *bus = NULL;
64 unsigned char max, n;
65
66 max = 0;
67 while ((bus = pci_find_next_bus(bus)) != NULL) {
68 n = pci_bus_max_busnr(bus);
69 if(n > max)
70 max = n;
71 }
72 return max;
73}
74
54c762fe
AB		 75#endif /* 0 */
76
687d5fe3
ME		 77#define PCI_FIND_CAP_TTL 48
78
79static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
80 u8 pos, int cap, int *ttl)
24a4e377
RD		 81{
82 u8 id;
24a4e377 83
687d5fe3 84 while ((*ttl)--) {
24a4e377
RD		 85 pci_bus_read_config_byte(bus, devfn, pos, &pos);
86 if (pos < 0x40)
87 break;
88 pos &= ~3;
89 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
90 &id);
91 if (id == 0xff)
92 break;
93 if (id == cap)
94 return pos;
95 pos += PCI_CAP_LIST_NEXT;
96 }
97 return 0;
98}
99
687d5fe3
ME		 100static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
101 u8 pos, int cap)
102{
103 int ttl = PCI_FIND_CAP_TTL;
104
105 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
106}
107
24a4e377
RD		 108int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
109{
110 return __pci_find_next_cap(dev->bus, dev->devfn,
111 pos + PCI_CAP_LIST_NEXT, cap);
112}
113EXPORT_SYMBOL_GPL(pci_find_next_capability);
114
d3bac118
ME		 115static int __pci_bus_find_cap_start(struct pci_bus *bus,
116 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 117{
118 u16 status;
1da177e4
LT		 119
120 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
121 if (!(status & PCI_STATUS_CAP_LIST))
122 return 0;
123
124 switch (hdr_type) {
125 case PCI_HEADER_TYPE_NORMAL:
126 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 127 return PCI_CAPABILITY_LIST;
1da177e4 128 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 129 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 130 default:
131 return 0;
132 }
d3bac118
ME		 133
134 return 0;
1da177e4
LT		 135}
136
137/**
138 * pci_find_capability - query for devices' capabilities
139 * @dev: PCI device to query
140 * @cap: capability code
141 *
142 * Tell if a device supports a given PCI capability.
143 * Returns the address of the requested capability structure within the
144 * device's PCI configuration space or 0 in case the device does not
145 * support it. Possible values for @cap:
146 *
147 * %PCI_CAP_ID_PM Power Management
148 * %PCI_CAP_ID_AGP Accelerated Graphics Port
149 * %PCI_CAP_ID_VPD Vital Product Data
150 * %PCI_CAP_ID_SLOTID Slot Identification
151 * %PCI_CAP_ID_MSI Message Signalled Interrupts
152 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
153 * %PCI_CAP_ID_PCIX PCI-X
154 * %PCI_CAP_ID_EXP PCI Express
155 */
156int pci_find_capability(struct pci_dev *dev, int cap)
157{
d3bac118
ME		 158 int pos;
159
160 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
161 if (pos)
162 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
163
164 return pos;
1da177e4
LT		 165}
166
167/**
168 * pci_bus_find_capability - query for devices' capabilities
169 * @bus: the PCI bus to query
170 * @devfn: PCI device to query
171 * @cap: capability code
172 *
173 * Like pci_find_capability() but works for pci devices that do not have a
174 * pci_dev structure set up yet.
175 *
176 * Returns the address of the requested capability structure within the
177 * device's PCI configuration space or 0 in case the device does not
178 * support it.
179 */
180int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
181{
d3bac118 182 int pos;
1da177e4
LT		 183 u8 hdr_type;
184
185 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
186
d3bac118
ME		 187 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
188 if (pos)
189 pos = __pci_find_next_cap(bus, devfn, pos, cap);
190
191 return pos;
1da177e4
LT		 192}
193
194/**
195 * pci_find_ext_capability - Find an extended capability
196 * @dev: PCI device to query
197 * @cap: capability code
198 *
199 * Returns the address of the requested extended capability structure
200 * within the device's PCI configuration space or 0 if the device does
201 * not support it. Possible values for @cap:
202 *
203 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
204 * %PCI_EXT_CAP_ID_VC Virtual Channel
205 * %PCI_EXT_CAP_ID_DSN Device Serial Number
206 * %PCI_EXT_CAP_ID_PWR Power Budgeting
207 */
208int pci_find_ext_capability(struct pci_dev *dev, int cap)
209{
210 u32 header;
211 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
212 int pos = 0x100;
213
214 if (dev->cfg_size <= 256)
215 return 0;
216
217 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
218 return 0;
219
220 /*
221 * If we have no capabilities, this is indicated by cap ID,
222 * cap version and next pointer all being 0.
223 */
224 if (header == 0)
225 return 0;
226
227 while (ttl-- > 0) {
228 if (PCI_EXT_CAP_ID(header) == cap)
229 return pos;
230
231 pos = PCI_EXT_CAP_NEXT(header);
232 if (pos < 0x100)
233 break;
234
235 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
236 break;
237 }
238
239 return 0;
240}
3a720d72 241EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 242
687d5fe3
ME		 243static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
244{
245 int rc, ttl = PCI_FIND_CAP_TTL;
246 u8 cap, mask;
247
248 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
249 mask = HT_3BIT_CAP_MASK;
250 else
251 mask = HT_5BIT_CAP_MASK;
252
253 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
254 PCI_CAP_ID_HT, &ttl);
255 while (pos) {
256 rc = pci_read_config_byte(dev, pos + 3, &cap);
257 if (rc != PCIBIOS_SUCCESSFUL)
258 return 0;
259
260 if ((cap & mask) == ht_cap)
261 return pos;
262
47a4d5be
BG		 263 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
264 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 265 PCI_CAP_ID_HT, &ttl);
266 }
267
268 return 0;
269}
270/**
271 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
272 * @dev: PCI device to query
273 * @pos: Position from which to continue searching
274 * @ht_cap: Hypertransport capability code
275 *
276 * To be used in conjunction with pci_find_ht_capability() to search for
277 * all capabilities matching @ht_cap. @pos should always be a value returned
278 * from pci_find_ht_capability().
279 *
280 * NB. To be 100% safe against broken PCI devices, the caller should take
281 * steps to avoid an infinite loop.
282 */
283int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
284{
285 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
286}
287EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
288
289/**
290 * pci_find_ht_capability - query a device's Hypertransport capabilities
291 * @dev: PCI device to query
292 * @ht_cap: Hypertransport capability code
293 *
294 * Tell if a device supports a given Hypertransport capability.
295 * Returns an address within the device's PCI configuration space
296 * or 0 in case the device does not support the request capability.
297 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
298 * which has a Hypertransport capability matching @ht_cap.
299 */
300int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
301{
302 int pos;
303
304 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
305 if (pos)
306 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
307
308 return pos;
309}
310EXPORT_SYMBOL_GPL(pci_find_ht_capability);
311
1da177e4
LT		 312/**
313 * pci_find_parent_resource - return resource region of parent bus of given region
314 * @dev: PCI device structure contains resources to be searched
315 * @res: child resource record for which parent is sought
316 *
317 * For given resource region of given device, return the resource
318 * region of parent bus the given region is contained in or where
319 * it should be allocated from.
320 */
321struct resource *
322pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
323{
324 const struct pci_bus *bus = dev->bus;
325 int i;
326 struct resource *best = NULL;
327
328 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
329 struct resource *r = bus->resource[i];
330 if (!r)
331 continue;
332 if (res->start && !(res->start >= r->start && res->end <= r->end))
333 continue; /* Not contained */
334 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
335 continue; /* Wrong type */
336 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
337 return r; /* Exact match */
338 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
339 best = r; /* Approximating prefetchable by non-prefetchable */
340 }
341 return best;
342}
343
064b53db
JL		 344/**
345 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
346 * @dev: PCI device to have its BARs restored
347 *
348 * Restore the BAR values for a given device, so as to make it
349 * accessible by its driver.
350 */
351void
352pci_restore_bars(struct pci_dev *dev)
353{
354 int i, numres;
355
356 switch (dev->hdr_type) {
357 case PCI_HEADER_TYPE_NORMAL:
358 numres = 6;
359 break;
360 case PCI_HEADER_TYPE_BRIDGE:
361 numres = 2;
362 break;
363 case PCI_HEADER_TYPE_CARDBUS:
364 numres = 1;
365 break;
366 default:
367 /* Should never get here, but just in case... */
368 return;
369 }
370
371 for (i = 0; i < numres; i ++)
372 pci_update_resource(dev, &dev->resource[i], i);
373}
374
8f7020d3
RD		 375int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
376
1da177e4
LT		 377/**
378 * pci_set_power_state - Set the power state of a PCI device
379 * @dev: PCI device to be suspended
380 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
381 *
382 * Transition a device to a new power state, using the Power Management
383 * Capabilities in the device's config space.
384 *
385 * RETURN VALUE:
386 * -EINVAL if trying to enter a lower state than we're already in.
387 * 0 if we're already in the requested state.
388 * -EIO if device does not support PCI PM.
389 * 0 if we can successfully change the power state.
390 */
1da177e4
LT		 391int
392pci_set_power_state(struct pci_dev *dev, pci_power_t state)
393{
064b53db 394 int pm, need_restore = 0;
1da177e4
LT		 395 u16 pmcsr, pmc;
396
397 /* bound the state we're entering */
398 if (state > PCI_D3hot)
399 state = PCI_D3hot;
400
e36c455c
PM		 401 /*
402 * If the device or the parent bridge can't support PCI PM, ignore
403 * the request if we're doing anything besides putting it into D0
404 * (which would only happen on boot).
405 */
406 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
407 return 0;
408
1da177e4
LT		 409 /* Validate current state:
410 * Can enter D0 from any state, but if we can only go deeper
411 * to sleep if we're already in a low power state
412 */
02669492
AM		 413 if (state != PCI_D0 && dev->current_state > state) {
414 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
415 __FUNCTION__, pci_name(dev), state, dev->current_state);
1da177e4 416 return -EINVAL;
02669492 417 } else if (dev->current_state == state)
1da177e4
LT		 418 return 0; /* we're already there */
419
ffadcc2f 420
1da177e4
LT		 421 /* find PCI PM capability in list */
422 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
423
424 /* abort if the device doesn't support PM capabilities */
425 if (!pm)
426 return -EIO;
427
428 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
3fe9d19f 429 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1da177e4
LT		 430 printk(KERN_DEBUG
431 "PCI: %s has unsupported PM cap regs version (%u)\n",
432 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
433 return -EIO;
434 }
435
436 /* check if this device supports the desired state */
3fe9d19f
DR		 437 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
438 return -EIO;
439 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
440 return -EIO;
1da177e4 441
064b53db
JL		 442 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
443
32a36585 444 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 445 * This doesn't affect PME_Status, disables PME_En, and
446 * sets PowerState to 0.
447 */
32a36585 448 switch (dev->current_state) {
d3535fbb
JL		 449 case PCI_D0:
450 case PCI_D1:
451 case PCI_D2:
452 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
453 pmcsr |= state;
454 break;
32a36585
JL		 455 case PCI_UNKNOWN: /* Boot-up */
456 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
457 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
064b53db 458 need_restore = 1;
32a36585 459 /* Fall-through: force to D0 */
32a36585 460 default:
d3535fbb 461 pmcsr = 0;
32a36585 462 break;
1da177e4
LT		 463 }
464
465 /* enter specified state */
466 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
467
468 /* Mandatory power management transition delays */
469 /* see PCI PM 1.1 5.6.1 table 18 */
470 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
ffadcc2f 471 msleep(pci_pm_d3_delay);
1da177e4
LT		 472 else if (state == PCI_D2 || dev->current_state == PCI_D2)
473 udelay(200);
1da177e4 474
b913100d
DSL		 475 /*
476 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
d6e05edc 477 * Firmware method after native method ?
b913100d
DSL		 478 */
479 if (platform_pci_set_power_state)
480 platform_pci_set_power_state(dev, state);
481
482 dev->current_state = state;
064b53db
JL		 483
484 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
485 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
486 * from D3hot to D0 _may_ perform an internal reset, thereby
487 * going to "D0 Uninitialized" rather than "D0 Initialized".
488 * For example, at least some versions of the 3c905B and the
489 * 3c556B exhibit this behaviour.
490 *
491 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
492 * devices in a D3hot state at boot. Consequently, we need to
493 * restore at least the BARs so that the device will be
494 * accessible to its driver.
495 */
496 if (need_restore)
497 pci_restore_bars(dev);
498
1da177e4
LT		 499 return 0;
500}
501
f165b10f 502int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
0f64474b 503
1da177e4
LT		 504/**
505 * pci_choose_state - Choose the power state of a PCI device
506 * @dev: PCI device to be suspended
507 * @state: target sleep state for the whole system. This is the value
508 * that is passed to suspend() function.
509 *
510 * Returns PCI power state suitable for given device and given system
511 * message.
512 */
513
514pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
515{
0f64474b
DSL		 516 int ret;
517
1da177e4
LT		 518 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
519 return PCI_D0;
520
0f64474b
DSL		 521 if (platform_pci_choose_state) {
522 ret = platform_pci_choose_state(dev, state);
523 if (ret >= 0)
ca078bae 524 state.event = ret;
0f64474b 525 }
ca078bae
PM		 526
527 switch (state.event) {
528 case PM_EVENT_ON:
529 return PCI_D0;
530 case PM_EVENT_FREEZE:
b887d2e6
DB		 531 case PM_EVENT_PRETHAW:
532 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae
PM		 533 case PM_EVENT_SUSPEND:
534 return PCI_D3hot;
1da177e4 535 default:
b887d2e6 536 printk("Unrecognized suspend event %d\n", state.event);
1da177e4
LT		 537 BUG();
538 }
539 return PCI_D0;
540}
541
542EXPORT_SYMBOL(pci_choose_state);
543
b56a5a23
MT		 544static int pci_save_pcie_state(struct pci_dev *dev)
545{
546 int pos, i = 0;
547 struct pci_cap_saved_state *save_state;
548 u16 *cap;
549
550 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
551 if (pos <= 0)
552 return 0;
553
554 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
555 if (!save_state) {
556 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
557 return -ENOMEM;
558 }
559 cap = (u16 *)&save_state->data[0];
560
561 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
562 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
563 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
564 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
565 pci_add_saved_cap(dev, save_state);
566 return 0;
567}
568
569static void pci_restore_pcie_state(struct pci_dev *dev)
570{
571 int i = 0, pos;
572 struct pci_cap_saved_state *save_state;
573 u16 *cap;
574
575 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
576 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
577 if (!save_state || pos <= 0)
578 return;
579 cap = (u16 *)&save_state->data[0];
580
581 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
582 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
583 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
584 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
585 pci_remove_saved_cap(save_state);
586 kfree(save_state);
587}
588
cc692a5f
SH		 589
590static int pci_save_pcix_state(struct pci_dev *dev)
591{
592 int pos, i = 0;
593 struct pci_cap_saved_state *save_state;
594 u16 *cap;
595
596 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
597 if (pos <= 0)
598 return 0;
599
600 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
601 if (!save_state) {
602 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
603 return -ENOMEM;
604 }
605 cap = (u16 *)&save_state->data[0];
606
607 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
608 pci_add_saved_cap(dev, save_state);
609 return 0;
610}
611
612static void pci_restore_pcix_state(struct pci_dev *dev)
613{
614 int i = 0, pos;
615 struct pci_cap_saved_state *save_state;
616 u16 *cap;
617
618 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
619 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
620 if (!save_state || pos <= 0)
621 return;
622 cap = (u16 *)&save_state->data[0];
623
624 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
625 pci_remove_saved_cap(save_state);
626 kfree(save_state);
627}
628
629
1da177e4
LT		 630/**
631 * pci_save_state - save the PCI configuration space of a device before suspending
632 * @dev: - PCI device that we're dealing with
1da177e4
LT		 633 */
634int
635pci_save_state(struct pci_dev *dev)
636{
637 int i;
638 /* XXX: 100% dword access ok here? */
639 for (i = 0; i < 16; i++)
640 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
41017f0c
SL		 641 if ((i = pci_save_msi_state(dev)) != 0)
642 return i;
b56a5a23
MT		 643 if ((i = pci_save_pcie_state(dev)) != 0)
644 return i;
cc692a5f
SH		 645 if ((i = pci_save_pcix_state(dev)) != 0)
646 return i;
1da177e4
LT		 647 return 0;
648}
649
650/**
651 * pci_restore_state - Restore the saved state of a PCI device
652 * @dev: - PCI device that we're dealing with
1da177e4
LT		 653 */
654int
655pci_restore_state(struct pci_dev *dev)
656{
657 int i;
04d9c1a1 658 int val;
1da177e4 659
b56a5a23
MT		 660 /* PCI Express register must be restored first */
661 pci_restore_pcie_state(dev);
662
8b8c8d28
YL		 663 /*
664 * The Base Address register should be programmed before the command
665 * register(s)
666 */
667 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 668 pci_read_config_dword(dev, i * 4, &val);
669 if (val != dev->saved_config_space[i]) {
670 printk(KERN_DEBUG "PM: Writing back config space on "
671 "device %s at offset %x (was %x, writing %x)\n",
672 pci_name(dev), i,
673 val, (int)dev->saved_config_space[i]);
674 pci_write_config_dword(dev,i * 4,
675 dev->saved_config_space[i]);
676 }
677 }
cc692a5f 678 pci_restore_pcix_state(dev);
41017f0c 679 pci_restore_msi_state(dev);
8fed4b65 680
1da177e4
LT		 681 return 0;
682}
683
38cc1302
HS		 684static int do_pci_enable_device(struct pci_dev *dev, int bars)
685{
686 int err;
687
688 err = pci_set_power_state(dev, PCI_D0);
689 if (err < 0 && err != -EIO)
690 return err;
691 err = pcibios_enable_device(dev, bars);
692 if (err < 0)
693 return err;
694 pci_fixup_device(pci_fixup_enable, dev);
695
696 return 0;
697}
698
699/**
700 * __pci_reenable_device - Resume abandoned device
701 * @dev: PCI device to be resumed
702 *
703 * Note this function is a backend of pci_default_resume and is not supposed
704 * to be called by normal code, write proper resume handler and use it instead.
705 */
706int
707__pci_reenable_device(struct pci_dev *dev)
708{
709 if (atomic_read(&dev->enable_cnt))
710 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
711 return 0;
712}
713
1da177e4
LT		 714/**
715 * pci_enable_device_bars - Initialize some of a device for use
716 * @dev: PCI device to be initialized
717 * @bars: bitmask of BAR's that must be configured
718 *
719 * Initialize device before it's used by a driver. Ask low-level code
9fb625c3 720 * to enable selected I/O and memory resources. Wake up the device if it
1da177e4
LT		 721 * was suspended. Beware, this function can fail.
722 */
1da177e4
LT		 723int
724pci_enable_device_bars(struct pci_dev *dev, int bars)
725{
726 int err;
727
9fb625c3
HS		 728 if (atomic_add_return(1, &dev->enable_cnt) > 1)
729 return 0; /* already enabled */
730
38cc1302 731 err = do_pci_enable_device(dev, bars);
95a62965 732 if (err < 0)
38cc1302 733 atomic_dec(&dev->enable_cnt);
9fb625c3 734 return err;
1da177e4
LT		 735}
736
bae94d02
IPG		 737/**
738 * pci_enable_device - Initialize device before it's used by a driver.
739 * @dev: PCI device to be initialized
740 *
741 * Initialize device before it's used by a driver. Ask low-level code
742 * to enable I/O and memory. Wake up the device if it was suspended.
743 * Beware, this function can fail.
744 *
745 * Note we don't actually enable the device many times if we call
746 * this function repeatedly (we just increment the count).
747 */
748int pci_enable_device(struct pci_dev *dev)
749{
9fb625c3 750 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
bae94d02
IPG		 751}
752
9ac7849e
TH		 753/*
754 * Managed PCI resources. This manages device on/off, intx/msi/msix
755 * on/off and BAR regions. pci_dev itself records msi/msix status, so
756 * there's no need to track it separately. pci_devres is initialized
757 * when a device is enabled using managed PCI device enable interface.
758 */
759struct pci_devres {
760 unsigned int disable:1;
761 unsigned int orig_intx:1;
762 unsigned int restore_intx:1;
763 u32 region_mask;
764};
765
766static void pcim_release(struct device *gendev, void *res)
767{
768 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
769 struct pci_devres *this = res;
770 int i;
771
772 if (dev->msi_enabled)
773 pci_disable_msi(dev);
774 if (dev->msix_enabled)
775 pci_disable_msix(dev);
776
777 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
778 if (this->region_mask & (1 << i))
779 pci_release_region(dev, i);
780
781 if (this->restore_intx)
782 pci_intx(dev, this->orig_intx);
783
784 if (this->disable)
785 pci_disable_device(dev);
786}
787
788static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
789{
790 struct pci_devres *dr, *new_dr;
791
792 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
793 if (dr)
794 return dr;
795
796 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
797 if (!new_dr)
798 return NULL;
799 return devres_get(&pdev->dev, new_dr, NULL, NULL);
800}
801
802static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
803{
804 if (pci_is_managed(pdev))
805 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
806 return NULL;
807}
808
809/**
810 * pcim_enable_device - Managed pci_enable_device()
811 * @pdev: PCI device to be initialized
812 *
813 * Managed pci_enable_device().
814 */
815int pcim_enable_device(struct pci_dev *pdev)
816{
817 struct pci_devres *dr;
818 int rc;
819
820 dr = get_pci_dr(pdev);
821 if (unlikely(!dr))
822 return -ENOMEM;
823 WARN_ON(!!dr->disable);
824
825 rc = pci_enable_device(pdev);
826 if (!rc) {
827 pdev->is_managed = 1;
828 dr->disable = 1;
829 }
830 return rc;
831}
832
833/**
834 * pcim_pin_device - Pin managed PCI device
835 * @pdev: PCI device to pin
836 *
837 * Pin managed PCI device @pdev. Pinned device won't be disabled on
838 * driver detach. @pdev must have been enabled with
839 * pcim_enable_device().
840 */
841void pcim_pin_device(struct pci_dev *pdev)
842{
843 struct pci_devres *dr;
844
845 dr = find_pci_dr(pdev);
846 WARN_ON(!dr || !dr->disable);
847 if (dr)
848 dr->disable = 0;
849}
850
1da177e4
LT		 851/**
852 * pcibios_disable_device - disable arch specific PCI resources for device dev
853 * @dev: the PCI device to disable
854 *
855 * Disables architecture specific PCI resources for the device. This
856 * is the default implementation. Architecture implementations can
857 * override this.
858 */
859void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
860
861/**
862 * pci_disable_device - Disable PCI device after use
863 * @dev: PCI device to be disabled
864 *
865 * Signal to the system that the PCI device is not in use by the system
866 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 867 *
868 * Note we don't actually disable the device until all callers of
869 * pci_device_enable() have called pci_device_disable().
1da177e4
LT		 870 */
871void
872pci_disable_device(struct pci_dev *dev)
873{
9ac7849e 874 struct pci_devres *dr;
1da177e4 875 u16 pci_command;
99dc804d 876
9ac7849e
TH		 877 dr = find_pci_dr(dev);
878 if (dr)
879 dr->disable = 0;
880
bae94d02
IPG		 881 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
882 return;
883
99dc804d
SL		 884 if (dev->msi_enabled)
885 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
886 PCI_CAP_ID_MSI);
887 if (dev->msix_enabled)
888 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
889 PCI_CAP_ID_MSIX);
890
1da177e4
LT		 891 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
892 if (pci_command & PCI_COMMAND_MASTER) {
893 pci_command &= ~PCI_COMMAND_MASTER;
894 pci_write_config_word(dev, PCI_COMMAND, pci_command);
895 }
ceb43744 896 dev->is_busmaster = 0;
1da177e4
LT		 897
898 pcibios_disable_device(dev);
899}
900
901/**
902 * pci_enable_wake - enable device to generate PME# when suspended
903 * @dev: - PCI device to operate on
904 * @state: - Current state of device.
905 * @enable: - Flag to enable or disable generation
906 *
907 * Set the bits in the device's PM Capabilities to generate PME# when
908 * the system is suspended.
909 *
910 * -EIO is returned if device doesn't have PM Capabilities.
911 * -EINVAL is returned if device supports it, but can't generate wake events.
912 * 0 if operation is successful.
913 *
914 */
915int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
916{
917 int pm;
918 u16 value;
919
920 /* find PCI PM capability in list */
921 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
922
923 /* If device doesn't support PM Capabilities, but request is to disable
924 * wake events, it's a nop; otherwise fail */
925 if (!pm)
926 return enable ? -EIO : 0;
927
928 /* Check device's ability to generate PME# */
929 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
930
931 value &= PCI_PM_CAP_PME_MASK;
932 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
933
934 /* Check if it can generate PME# from requested state. */
935 if (!value || !(value & (1 << state)))
936 return enable ? -EINVAL : 0;
937
938 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
939
940 /* Clear PME_Status by writing 1 to it and enable PME# */
941 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
942
943 if (!enable)
944 value &= ~PCI_PM_CTRL_PME_ENABLE;
945
946 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
947
948 return 0;
949}
950
951int
952pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
953{
954 u8 pin;
955
514d207d 956 pin = dev->pin;
1da177e4
LT		 957 if (!pin)
958 return -1;
959 pin--;
960 while (dev->bus->self) {
961 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
962 dev = dev->bus->self;
963 }
964 *bridge = dev;
965 return pin;
966}
967
968/**
969 * pci_release_region - Release a PCI bar
970 * @pdev: PCI device whose resources were previously reserved by pci_request_region
971 * @bar: BAR to release
972 *
973 * Releases the PCI I/O and memory resources previously reserved by a
974 * successful call to pci_request_region. Call this function only
975 * after all use of the PCI regions has ceased.
976 */
977void pci_release_region(struct pci_dev *pdev, int bar)
978{
9ac7849e
TH		 979 struct pci_devres *dr;
980
1da177e4
LT		 981 if (pci_resource_len(pdev, bar) == 0)
982 return;
983 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
984 release_region(pci_resource_start(pdev, bar),
985 pci_resource_len(pdev, bar));
986 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
987 release_mem_region(pci_resource_start(pdev, bar),
988 pci_resource_len(pdev, bar));
9ac7849e
TH		 989
990 dr = find_pci_dr(pdev);
991 if (dr)
992 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 993}
994
995/**
996 * pci_request_region - Reserved PCI I/O and memory resource
997 * @pdev: PCI device whose resources are to be reserved
998 * @bar: BAR to be reserved
999 * @res_name: Name to be associated with resource.
1000 *
1001 * Mark the PCI region associated with PCI device @pdev BR @bar as
1002 * being reserved by owner @res_name. Do not access any
1003 * address inside the PCI regions unless this call returns
1004 * successfully.
1005 *
1006 * Returns 0 on success, or %EBUSY on error. A warning
1007 * message is also printed on failure.
1008 */
3c990e92 1009int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1da177e4 1010{
9ac7849e
TH		 1011 struct pci_devres *dr;
1012
1da177e4
LT		 1013 if (pci_resource_len(pdev, bar) == 0)
1014 return 0;
1015
1016 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1017 if (!request_region(pci_resource_start(pdev, bar),
1018 pci_resource_len(pdev, bar), res_name))
1019 goto err_out;
1020 }
1021 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1022 if (!request_mem_region(pci_resource_start(pdev, bar),
1023 pci_resource_len(pdev, bar), res_name))
1024 goto err_out;
1025 }
9ac7849e
TH		 1026
1027 dr = find_pci_dr(pdev);
1028 if (dr)
1029 dr->region_mask |= 1 << bar;
1030
1da177e4
LT		 1031 return 0;
1032
1033err_out:
1396a8c3
GKH		 1034 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1035 "for device %s\n",
1da177e4
LT		 1036 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1037 bar + 1, /* PCI BAR # */
1396a8c3
GKH		 1038 (unsigned long long)pci_resource_len(pdev, bar),
1039 (unsigned long long)pci_resource_start(pdev, bar),
1da177e4
LT		 1040 pci_name(pdev));
1041 return -EBUSY;
1042}
1043
c87deff7
HS		 1044/**
1045 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1046 * @pdev: PCI device whose resources were previously reserved
1047 * @bars: Bitmask of BARs to be released
1048 *
1049 * Release selected PCI I/O and memory resources previously reserved.
1050 * Call this function only after all use of the PCI regions has ceased.
1051 */
1052void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1053{
1054 int i;
1055
1056 for (i = 0; i < 6; i++)
1057 if (bars & (1 << i))
1058 pci_release_region(pdev, i);
1059}
1060
1061/**
1062 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1063 * @pdev: PCI device whose resources are to be reserved
1064 * @bars: Bitmask of BARs to be requested
1065 * @res_name: Name to be associated with resource
1066 */
1067int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1068 const char *res_name)
1069{
1070 int i;
1071
1072 for (i = 0; i < 6; i++)
1073 if (bars & (1 << i))
1074 if(pci_request_region(pdev, i, res_name))
1075 goto err_out;
1076 return 0;
1077
1078err_out:
1079 while(--i >= 0)
1080 if (bars & (1 << i))
1081 pci_release_region(pdev, i);
1082
1083 return -EBUSY;
1084}
1da177e4
LT		 1085
1086/**
1087 * pci_release_regions - Release reserved PCI I/O and memory resources
1088 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1089 *
1090 * Releases all PCI I/O and memory resources previously reserved by a
1091 * successful call to pci_request_regions. Call this function only
1092 * after all use of the PCI regions has ceased.
1093 */
1094
1095void pci_release_regions(struct pci_dev *pdev)
1096{
c87deff7 1097 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 1098}
1099
1100/**
1101 * pci_request_regions - Reserved PCI I/O and memory resources
1102 * @pdev: PCI device whose resources are to be reserved
1103 * @res_name: Name to be associated with resource.
1104 *
1105 * Mark all PCI regions associated with PCI device @pdev as
1106 * being reserved by owner @res_name. Do not access any
1107 * address inside the PCI regions unless this call returns
1108 * successfully.
1109 *
1110 * Returns 0 on success, or %EBUSY on error. A warning
1111 * message is also printed on failure.
1112 */
3c990e92 1113int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 1114{
c87deff7 1115 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 1116}
1117
1118/**
1119 * pci_set_master - enables bus-mastering for device dev
1120 * @dev: the PCI device to enable
1121 *
1122 * Enables bus-mastering on the device and calls pcibios_set_master()
1123 * to do the needed arch specific settings.
1124 */
1125void
1126pci_set_master(struct pci_dev *dev)
1127{
1128 u16 cmd;
1129
1130 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1131 if (! (cmd & PCI_COMMAND_MASTER)) {
1132 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1133 cmd |= PCI_COMMAND_MASTER;
1134 pci_write_config_word(dev, PCI_COMMAND, cmd);
1135 }
1136 dev->is_busmaster = 1;
1137 pcibios_set_master(dev);
1138}
1139
edb2d97e
MW		 1140#ifdef PCI_DISABLE_MWI
1141int pci_set_mwi(struct pci_dev *dev)
1142{
1143 return 0;
1144}
1145
1146void pci_clear_mwi(struct pci_dev *dev)
1147{
1148}
1149
1150#else
ebf5a248
MW		 1151
1152#ifndef PCI_CACHE_LINE_BYTES
1153#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1154#endif
1155
1da177e4 1156/* This can be overridden by arch code. */
ebf5a248
MW		 1157/* Don't forget this is measured in 32-bit words, not bytes */
1158u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1da177e4
LT		 1159
1160/**
edb2d97e
MW		 1161 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1162 * @dev: the PCI device for which MWI is to be enabled
1da177e4 1163 *
edb2d97e
MW		 1164 * Helper function for pci_set_mwi.
1165 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 1166 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1167 *
1168 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1169 */
1170static int
edb2d97e 1171pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 1172{
1173 u8 cacheline_size;
1174
1175 if (!pci_cache_line_size)
1176 return -EINVAL; /* The system doesn't support MWI. */
1177
1178 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1179 equal to or multiple of the right value. */
1180 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1181 if (cacheline_size >= pci_cache_line_size &&
1182 (cacheline_size % pci_cache_line_size) == 0)
1183 return 0;
1184
1185 /* Write the correct value. */
1186 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1187 /* Read it back. */
1188 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1189 if (cacheline_size == pci_cache_line_size)
1190 return 0;
1191
1192 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1193 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1194
1195 return -EINVAL;
1196}
1da177e4
LT		 1197
1198/**
1199 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1200 * @dev: the PCI device for which MWI is enabled
1201 *
1202 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
1203 * and then calls @pcibios_set_mwi to do the needed arch specific
1204 * operations or a generic mwi-prep function.
1205 *
1206 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1207 */
1208int
1209pci_set_mwi(struct pci_dev *dev)
1210{
1211 int rc;
1212 u16 cmd;
1213
edb2d97e 1214 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 1215 if (rc)
1216 return rc;
1217
1218 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1219 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1220 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
1221 cmd |= PCI_COMMAND_INVALIDATE;
1222 pci_write_config_word(dev, PCI_COMMAND, cmd);
1223 }
1224
1225 return 0;
1226}
1227
1228/**
1229 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1230 * @dev: the PCI device to disable
1231 *
1232 * Disables PCI Memory-Write-Invalidate transaction on the device
1233 */
1234void
1235pci_clear_mwi(struct pci_dev *dev)
1236{
1237 u16 cmd;
1238
1239 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1240 if (cmd & PCI_COMMAND_INVALIDATE) {
1241 cmd &= ~PCI_COMMAND_INVALIDATE;
1242 pci_write_config_word(dev, PCI_COMMAND, cmd);
1243 }
1244}
edb2d97e 1245#endif /* ! PCI_DISABLE_MWI */
1da177e4 1246
a04ce0ff
BR		 1247/**
1248 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 1249 * @pdev: the PCI device to operate on
1250 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 1251 *
1252 * Enables/disables PCI INTx for device dev
1253 */
1254void
1255pci_intx(struct pci_dev *pdev, int enable)
1256{
1257 u16 pci_command, new;
1258
1259 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1260
1261 if (enable) {
1262 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1263 } else {
1264 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1265 }
1266
1267 if (new != pci_command) {
9ac7849e
TH		 1268 struct pci_devres *dr;
1269
2fd9d74b 1270 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 1271
1272 dr = find_pci_dr(pdev);
1273 if (dr && !dr->restore_intx) {
1274 dr->restore_intx = 1;
1275 dr->orig_intx = !enable;
1276 }
a04ce0ff
BR		 1277 }
1278}
1279
1da177e4
LT		 1280#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1281/*
1282 * These can be overridden by arch-specific implementations
1283 */
1284int
1285pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1286{
1287 if (!pci_dma_supported(dev, mask))
1288 return -EIO;
1289
1290 dev->dma_mask = mask;
1291
1292 return 0;
1293}
1294
1da177e4
LT		 1295int
1296pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1297{
1298 if (!pci_dma_supported(dev, mask))
1299 return -EIO;
1300
1301 dev->dev.coherent_dma_mask = mask;
1302
1303 return 0;
1304}
1305#endif
c87deff7
HS		 1306
1307/**
1308 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 1309 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 1310 * @flags: resource type mask to be selected
1311 *
1312 * This helper routine makes bar mask from the type of resource.
1313 */
1314int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1315{
1316 int i, bars = 0;
1317 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1318 if (pci_resource_flags(dev, i) & flags)
1319 bars |= (1 << i);
1320 return bars;
1321}
1322
1da177e4
LT		 1323static int __devinit pci_init(void)
1324{
1325 struct pci_dev *dev = NULL;
1326
1327 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1328 pci_fixup_device(pci_fixup_final, dev);
1329 }
1330 return 0;
1331}
1332
1333static int __devinit pci_setup(char *str)
1334{
1335 while (str) {
1336 char *k = strchr(str, ',');
1337 if (k)
1338 *k++ = 0;
1339 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 1340 if (!strcmp(str, "nomsi")) {
1341 pci_no_msi();
4516a618
AN		 1342 } else if (!strncmp(str, "cbiosize=", 9)) {
1343 pci_cardbus_io_size = memparse(str + 9, &str);
1344 } else if (!strncmp(str, "cbmemsize=", 10)) {
1345 pci_cardbus_mem_size = memparse(str + 10, &str);
309e57df
MW		 1346 } else {
1347 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1348 str);
1349 }
1da177e4
LT		 1350 }
1351 str = k;
1352 }
0637a70a 1353 return 0;
1da177e4 1354}
0637a70a 1355early_param("pci", pci_setup);
1da177e4
LT		 1356
1357device_initcall(pci_init);
1da177e4 1358
064b53db 1359EXPORT_SYMBOL_GPL(pci_restore_bars);
1da177e4
LT		 1360EXPORT_SYMBOL(pci_enable_device_bars);
1361EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 1362EXPORT_SYMBOL(pcim_enable_device);
1363EXPORT_SYMBOL(pcim_pin_device);
1da177e4 1364EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 1365EXPORT_SYMBOL(pci_find_capability);
1366EXPORT_SYMBOL(pci_bus_find_capability);
1367EXPORT_SYMBOL(pci_release_regions);
1368EXPORT_SYMBOL(pci_request_regions);
1369EXPORT_SYMBOL(pci_release_region);
1370EXPORT_SYMBOL(pci_request_region);
c87deff7
HS		 1371EXPORT_SYMBOL(pci_release_selected_regions);
1372EXPORT_SYMBOL(pci_request_selected_regions);
1da177e4
LT		 1373EXPORT_SYMBOL(pci_set_master);
1374EXPORT_SYMBOL(pci_set_mwi);
1375EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 1376EXPORT_SYMBOL_GPL(pci_intx);
1da177e4 1377EXPORT_SYMBOL(pci_set_dma_mask);
1da177e4
LT		 1378EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1379EXPORT_SYMBOL(pci_assign_resource);
1380EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 1381EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 1382
1383EXPORT_SYMBOL(pci_set_power_state);
1384EXPORT_SYMBOL(pci_save_state);
1385EXPORT_SYMBOL(pci_restore_state);
1386EXPORT_SYMBOL(pci_enable_wake);
1387
Linux kernel - Deliverables
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