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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
1da177e4 | 19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 | 21 | |
ffadcc2f | 22 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 LT |
23 | |
24 | /** | |
25 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
26 | * @bus: pointer to PCI bus structure to search | |
27 | * | |
28 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
29 | * including the given PCI bus and its list of child PCI buses. | |
30 | */ | |
31 | unsigned char __devinit | |
32 | pci_bus_max_busnr(struct pci_bus* bus) | |
33 | { | |
34 | struct list_head *tmp; | |
35 | unsigned char max, n; | |
36 | ||
b82db5ce | 37 | max = bus->subordinate; |
1da177e4 LT |
38 | list_for_each(tmp, &bus->children) { |
39 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
40 | if(n > max) | |
41 | max = n; | |
42 | } | |
43 | return max; | |
44 | } | |
b82db5ce | 45 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 46 | |
b82db5ce | 47 | #if 0 |
1da177e4 LT |
48 | /** |
49 | * pci_max_busnr - returns maximum PCI bus number | |
50 | * | |
51 | * Returns the highest PCI bus number present in the system global list of | |
52 | * PCI buses. | |
53 | */ | |
54 | unsigned char __devinit | |
55 | pci_max_busnr(void) | |
56 | { | |
57 | struct pci_bus *bus = NULL; | |
58 | unsigned char max, n; | |
59 | ||
60 | max = 0; | |
61 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
62 | n = pci_bus_max_busnr(bus); | |
63 | if(n > max) | |
64 | max = n; | |
65 | } | |
66 | return max; | |
67 | } | |
68 | ||
54c762fe AB |
69 | #endif /* 0 */ |
70 | ||
24a4e377 RD |
71 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) |
72 | { | |
73 | u8 id; | |
74 | int ttl = 48; | |
75 | ||
76 | while (ttl--) { | |
77 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
78 | if (pos < 0x40) | |
79 | break; | |
80 | pos &= ~3; | |
81 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
82 | &id); | |
83 | if (id == 0xff) | |
84 | break; | |
85 | if (id == cap) | |
86 | return pos; | |
87 | pos += PCI_CAP_LIST_NEXT; | |
88 | } | |
89 | return 0; | |
90 | } | |
91 | ||
92 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) | |
93 | { | |
94 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
95 | pos + PCI_CAP_LIST_NEXT, cap); | |
96 | } | |
97 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
98 | ||
1da177e4 LT |
99 | static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) |
100 | { | |
101 | u16 status; | |
24a4e377 | 102 | u8 pos; |
1da177e4 LT |
103 | |
104 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
105 | if (!(status & PCI_STATUS_CAP_LIST)) | |
106 | return 0; | |
107 | ||
108 | switch (hdr_type) { | |
109 | case PCI_HEADER_TYPE_NORMAL: | |
110 | case PCI_HEADER_TYPE_BRIDGE: | |
24a4e377 | 111 | pos = PCI_CAPABILITY_LIST; |
1da177e4 LT |
112 | break; |
113 | case PCI_HEADER_TYPE_CARDBUS: | |
24a4e377 | 114 | pos = PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
115 | break; |
116 | default: | |
117 | return 0; | |
118 | } | |
24a4e377 | 119 | return __pci_find_next_cap(bus, devfn, pos, cap); |
1da177e4 LT |
120 | } |
121 | ||
122 | /** | |
123 | * pci_find_capability - query for devices' capabilities | |
124 | * @dev: PCI device to query | |
125 | * @cap: capability code | |
126 | * | |
127 | * Tell if a device supports a given PCI capability. | |
128 | * Returns the address of the requested capability structure within the | |
129 | * device's PCI configuration space or 0 in case the device does not | |
130 | * support it. Possible values for @cap: | |
131 | * | |
132 | * %PCI_CAP_ID_PM Power Management | |
133 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
134 | * %PCI_CAP_ID_VPD Vital Product Data | |
135 | * %PCI_CAP_ID_SLOTID Slot Identification | |
136 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
137 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
138 | * %PCI_CAP_ID_PCIX PCI-X | |
139 | * %PCI_CAP_ID_EXP PCI Express | |
140 | */ | |
141 | int pci_find_capability(struct pci_dev *dev, int cap) | |
142 | { | |
143 | return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); | |
144 | } | |
145 | ||
146 | /** | |
147 | * pci_bus_find_capability - query for devices' capabilities | |
148 | * @bus: the PCI bus to query | |
149 | * @devfn: PCI device to query | |
150 | * @cap: capability code | |
151 | * | |
152 | * Like pci_find_capability() but works for pci devices that do not have a | |
153 | * pci_dev structure set up yet. | |
154 | * | |
155 | * Returns the address of the requested capability structure within the | |
156 | * device's PCI configuration space or 0 in case the device does not | |
157 | * support it. | |
158 | */ | |
159 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
160 | { | |
161 | u8 hdr_type; | |
162 | ||
163 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
164 | ||
165 | return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); | |
166 | } | |
167 | ||
168 | /** | |
169 | * pci_find_ext_capability - Find an extended capability | |
170 | * @dev: PCI device to query | |
171 | * @cap: capability code | |
172 | * | |
173 | * Returns the address of the requested extended capability structure | |
174 | * within the device's PCI configuration space or 0 if the device does | |
175 | * not support it. Possible values for @cap: | |
176 | * | |
177 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
178 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
179 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
180 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
181 | */ | |
182 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
183 | { | |
184 | u32 header; | |
185 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
186 | int pos = 0x100; | |
187 | ||
188 | if (dev->cfg_size <= 256) | |
189 | return 0; | |
190 | ||
191 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
192 | return 0; | |
193 | ||
194 | /* | |
195 | * If we have no capabilities, this is indicated by cap ID, | |
196 | * cap version and next pointer all being 0. | |
197 | */ | |
198 | if (header == 0) | |
199 | return 0; | |
200 | ||
201 | while (ttl-- > 0) { | |
202 | if (PCI_EXT_CAP_ID(header) == cap) | |
203 | return pos; | |
204 | ||
205 | pos = PCI_EXT_CAP_NEXT(header); | |
206 | if (pos < 0x100) | |
207 | break; | |
208 | ||
209 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
210 | break; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
3a720d72 | 215 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 LT |
216 | |
217 | /** | |
218 | * pci_find_parent_resource - return resource region of parent bus of given region | |
219 | * @dev: PCI device structure contains resources to be searched | |
220 | * @res: child resource record for which parent is sought | |
221 | * | |
222 | * For given resource region of given device, return the resource | |
223 | * region of parent bus the given region is contained in or where | |
224 | * it should be allocated from. | |
225 | */ | |
226 | struct resource * | |
227 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
228 | { | |
229 | const struct pci_bus *bus = dev->bus; | |
230 | int i; | |
231 | struct resource *best = NULL; | |
232 | ||
233 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
234 | struct resource *r = bus->resource[i]; | |
235 | if (!r) | |
236 | continue; | |
237 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
238 | continue; /* Not contained */ | |
239 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
240 | continue; /* Wrong type */ | |
241 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
242 | return r; /* Exact match */ | |
243 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
244 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
245 | } | |
246 | return best; | |
247 | } | |
248 | ||
064b53db JL |
249 | /** |
250 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
251 | * @dev: PCI device to have its BARs restored | |
252 | * | |
253 | * Restore the BAR values for a given device, so as to make it | |
254 | * accessible by its driver. | |
255 | */ | |
256 | void | |
257 | pci_restore_bars(struct pci_dev *dev) | |
258 | { | |
259 | int i, numres; | |
260 | ||
261 | switch (dev->hdr_type) { | |
262 | case PCI_HEADER_TYPE_NORMAL: | |
263 | numres = 6; | |
264 | break; | |
265 | case PCI_HEADER_TYPE_BRIDGE: | |
266 | numres = 2; | |
267 | break; | |
268 | case PCI_HEADER_TYPE_CARDBUS: | |
269 | numres = 1; | |
270 | break; | |
271 | default: | |
272 | /* Should never get here, but just in case... */ | |
273 | return; | |
274 | } | |
275 | ||
276 | for (i = 0; i < numres; i ++) | |
277 | pci_update_resource(dev, &dev->resource[i], i); | |
278 | } | |
279 | ||
8f7020d3 RD |
280 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
281 | ||
1da177e4 LT |
282 | /** |
283 | * pci_set_power_state - Set the power state of a PCI device | |
284 | * @dev: PCI device to be suspended | |
285 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
286 | * | |
287 | * Transition a device to a new power state, using the Power Management | |
288 | * Capabilities in the device's config space. | |
289 | * | |
290 | * RETURN VALUE: | |
291 | * -EINVAL if trying to enter a lower state than we're already in. | |
292 | * 0 if we're already in the requested state. | |
293 | * -EIO if device does not support PCI PM. | |
294 | * 0 if we can successfully change the power state. | |
295 | */ | |
1da177e4 LT |
296 | int |
297 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
298 | { | |
064b53db | 299 | int pm, need_restore = 0; |
1da177e4 LT |
300 | u16 pmcsr, pmc; |
301 | ||
302 | /* bound the state we're entering */ | |
303 | if (state > PCI_D3hot) | |
304 | state = PCI_D3hot; | |
305 | ||
306 | /* Validate current state: | |
307 | * Can enter D0 from any state, but if we can only go deeper | |
308 | * to sleep if we're already in a low power state | |
309 | */ | |
02669492 AM |
310 | if (state != PCI_D0 && dev->current_state > state) { |
311 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
312 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 313 | return -EINVAL; |
02669492 | 314 | } else if (dev->current_state == state) |
1da177e4 LT |
315 | return 0; /* we're already there */ |
316 | ||
ffadcc2f KCA |
317 | /* |
318 | * If the device or the parent bridge can't support PCI PM, ignore | |
319 | * the request if we're doing anything besides putting it into D0 | |
320 | * (which would only happen on boot). | |
321 | */ | |
322 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
323 | return 0; | |
324 | ||
1da177e4 LT |
325 | /* find PCI PM capability in list */ |
326 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
327 | ||
328 | /* abort if the device doesn't support PM capabilities */ | |
329 | if (!pm) | |
330 | return -EIO; | |
331 | ||
332 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); | |
3fe9d19f | 333 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
334 | printk(KERN_DEBUG |
335 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
336 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
337 | return -EIO; | |
338 | } | |
339 | ||
340 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
341 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
342 | return -EIO; | |
343 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
344 | return -EIO; | |
1da177e4 | 345 | |
064b53db JL |
346 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
347 | ||
32a36585 | 348 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
349 | * This doesn't affect PME_Status, disables PME_En, and |
350 | * sets PowerState to 0. | |
351 | */ | |
32a36585 | 352 | switch (dev->current_state) { |
d3535fbb JL |
353 | case PCI_D0: |
354 | case PCI_D1: | |
355 | case PCI_D2: | |
356 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
357 | pmcsr |= state; | |
358 | break; | |
32a36585 JL |
359 | case PCI_UNKNOWN: /* Boot-up */ |
360 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
361 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 362 | need_restore = 1; |
32a36585 | 363 | /* Fall-through: force to D0 */ |
32a36585 | 364 | default: |
d3535fbb | 365 | pmcsr = 0; |
32a36585 | 366 | break; |
1da177e4 LT |
367 | } |
368 | ||
369 | /* enter specified state */ | |
370 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
371 | ||
372 | /* Mandatory power management transition delays */ | |
373 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
374 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 375 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
376 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
377 | udelay(200); | |
1da177e4 | 378 | |
b913100d DSL |
379 | /* |
380 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 381 | * Firmware method after native method ? |
b913100d DSL |
382 | */ |
383 | if (platform_pci_set_power_state) | |
384 | platform_pci_set_power_state(dev, state); | |
385 | ||
386 | dev->current_state = state; | |
064b53db JL |
387 | |
388 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
389 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
390 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
391 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
392 | * For example, at least some versions of the 3c905B and the | |
393 | * 3c556B exhibit this behaviour. | |
394 | * | |
395 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
396 | * devices in a D3hot state at boot. Consequently, we need to | |
397 | * restore at least the BARs so that the device will be | |
398 | * accessible to its driver. | |
399 | */ | |
400 | if (need_restore) | |
401 | pci_restore_bars(dev); | |
402 | ||
1da177e4 LT |
403 | return 0; |
404 | } | |
405 | ||
f165b10f | 406 | int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 407 | |
1da177e4 LT |
408 | /** |
409 | * pci_choose_state - Choose the power state of a PCI device | |
410 | * @dev: PCI device to be suspended | |
411 | * @state: target sleep state for the whole system. This is the value | |
412 | * that is passed to suspend() function. | |
413 | * | |
414 | * Returns PCI power state suitable for given device and given system | |
415 | * message. | |
416 | */ | |
417 | ||
418 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
419 | { | |
0f64474b DSL |
420 | int ret; |
421 | ||
1da177e4 LT |
422 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
423 | return PCI_D0; | |
424 | ||
0f64474b DSL |
425 | if (platform_pci_choose_state) { |
426 | ret = platform_pci_choose_state(dev, state); | |
427 | if (ret >= 0) | |
ca078bae | 428 | state.event = ret; |
0f64474b | 429 | } |
ca078bae PM |
430 | |
431 | switch (state.event) { | |
432 | case PM_EVENT_ON: | |
433 | return PCI_D0; | |
434 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
435 | case PM_EVENT_PRETHAW: |
436 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae PM |
437 | case PM_EVENT_SUSPEND: |
438 | return PCI_D3hot; | |
1da177e4 | 439 | default: |
b887d2e6 | 440 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
441 | BUG(); |
442 | } | |
443 | return PCI_D0; | |
444 | } | |
445 | ||
446 | EXPORT_SYMBOL(pci_choose_state); | |
447 | ||
b56a5a23 MT |
448 | static int pci_save_pcie_state(struct pci_dev *dev) |
449 | { | |
450 | int pos, i = 0; | |
451 | struct pci_cap_saved_state *save_state; | |
452 | u16 *cap; | |
453 | ||
454 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
455 | if (pos <= 0) | |
456 | return 0; | |
457 | ||
458 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
459 | if (!save_state) { | |
460 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
461 | return -ENOMEM; | |
462 | } | |
463 | cap = (u16 *)&save_state->data[0]; | |
464 | ||
465 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
466 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
467 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
468 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
469 | pci_add_saved_cap(dev, save_state); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
474 | { | |
475 | int i = 0, pos; | |
476 | struct pci_cap_saved_state *save_state; | |
477 | u16 *cap; | |
478 | ||
479 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
480 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
481 | if (!save_state || pos <= 0) | |
482 | return; | |
483 | cap = (u16 *)&save_state->data[0]; | |
484 | ||
485 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
486 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
487 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
488 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
489 | pci_remove_saved_cap(save_state); | |
490 | kfree(save_state); | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /** |
494 | * pci_save_state - save the PCI configuration space of a device before suspending | |
495 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
496 | */ |
497 | int | |
498 | pci_save_state(struct pci_dev *dev) | |
499 | { | |
500 | int i; | |
501 | /* XXX: 100% dword access ok here? */ | |
502 | for (i = 0; i < 16; i++) | |
503 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
41017f0c SL |
504 | if ((i = pci_save_msi_state(dev)) != 0) |
505 | return i; | |
506 | if ((i = pci_save_msix_state(dev)) != 0) | |
507 | return i; | |
b56a5a23 MT |
508 | if ((i = pci_save_pcie_state(dev)) != 0) |
509 | return i; | |
1da177e4 LT |
510 | return 0; |
511 | } | |
512 | ||
513 | /** | |
514 | * pci_restore_state - Restore the saved state of a PCI device | |
515 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
516 | */ |
517 | int | |
518 | pci_restore_state(struct pci_dev *dev) | |
519 | { | |
520 | int i; | |
04d9c1a1 | 521 | int val; |
1da177e4 | 522 | |
b56a5a23 MT |
523 | /* PCI Express register must be restored first */ |
524 | pci_restore_pcie_state(dev); | |
525 | ||
8b8c8d28 YL |
526 | /* |
527 | * The Base Address register should be programmed before the command | |
528 | * register(s) | |
529 | */ | |
530 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
531 | pci_read_config_dword(dev, i * 4, &val); |
532 | if (val != dev->saved_config_space[i]) { | |
533 | printk(KERN_DEBUG "PM: Writing back config space on " | |
534 | "device %s at offset %x (was %x, writing %x)\n", | |
535 | pci_name(dev), i, | |
536 | val, (int)dev->saved_config_space[i]); | |
537 | pci_write_config_dword(dev,i * 4, | |
538 | dev->saved_config_space[i]); | |
539 | } | |
540 | } | |
41017f0c SL |
541 | pci_restore_msi_state(dev); |
542 | pci_restore_msix_state(dev); | |
1da177e4 LT |
543 | return 0; |
544 | } | |
545 | ||
546 | /** | |
547 | * pci_enable_device_bars - Initialize some of a device for use | |
548 | * @dev: PCI device to be initialized | |
549 | * @bars: bitmask of BAR's that must be configured | |
550 | * | |
551 | * Initialize device before it's used by a driver. Ask low-level code | |
552 | * to enable selected I/O and memory resources. Wake up the device if it | |
553 | * was suspended. Beware, this function can fail. | |
554 | */ | |
555 | ||
556 | int | |
557 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
558 | { | |
559 | int err; | |
560 | ||
95a62965 | 561 | err = pci_set_power_state(dev, PCI_D0); |
11f3859b | 562 | if (err < 0 && err != -EIO) |
95a62965 GKH |
563 | return err; |
564 | err = pcibios_enable_device(dev, bars); | |
565 | if (err < 0) | |
1da177e4 LT |
566 | return err; |
567 | return 0; | |
568 | } | |
569 | ||
570 | /** | |
571 | * pci_enable_device - Initialize device before it's used by a driver. | |
572 | * @dev: PCI device to be initialized | |
573 | * | |
574 | * Initialize device before it's used by a driver. Ask low-level code | |
575 | * to enable I/O and memory. Wake up the device if it was suspended. | |
576 | * Beware, this function can fail. | |
577 | */ | |
578 | int | |
579 | pci_enable_device(struct pci_dev *dev) | |
580 | { | |
a1e022b3 KA |
581 | int err; |
582 | ||
583 | if (dev->is_enabled) | |
584 | return 0; | |
585 | ||
586 | err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
b64c05e7 | 587 | if (err) |
1da177e4 LT |
588 | return err; |
589 | pci_fixup_device(pci_fixup_enable, dev); | |
ceb43744 | 590 | dev->is_enabled = 1; |
1da177e4 LT |
591 | return 0; |
592 | } | |
593 | ||
594 | /** | |
595 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
596 | * @dev: the PCI device to disable | |
597 | * | |
598 | * Disables architecture specific PCI resources for the device. This | |
599 | * is the default implementation. Architecture implementations can | |
600 | * override this. | |
601 | */ | |
602 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
603 | ||
604 | /** | |
605 | * pci_disable_device - Disable PCI device after use | |
606 | * @dev: PCI device to be disabled | |
607 | * | |
608 | * Signal to the system that the PCI device is not in use by the system | |
609 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
610 | */ | |
611 | void | |
612 | pci_disable_device(struct pci_dev *dev) | |
613 | { | |
614 | u16 pci_command; | |
99dc804d SL |
615 | |
616 | if (dev->msi_enabled) | |
617 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
618 | PCI_CAP_ID_MSI); | |
619 | if (dev->msix_enabled) | |
620 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
621 | PCI_CAP_ID_MSIX); | |
622 | ||
1da177e4 LT |
623 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
624 | if (pci_command & PCI_COMMAND_MASTER) { | |
625 | pci_command &= ~PCI_COMMAND_MASTER; | |
626 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
627 | } | |
ceb43744 | 628 | dev->is_busmaster = 0; |
1da177e4 LT |
629 | |
630 | pcibios_disable_device(dev); | |
ceb43744 | 631 | dev->is_enabled = 0; |
1da177e4 LT |
632 | } |
633 | ||
634 | /** | |
635 | * pci_enable_wake - enable device to generate PME# when suspended | |
636 | * @dev: - PCI device to operate on | |
637 | * @state: - Current state of device. | |
638 | * @enable: - Flag to enable or disable generation | |
639 | * | |
640 | * Set the bits in the device's PM Capabilities to generate PME# when | |
641 | * the system is suspended. | |
642 | * | |
643 | * -EIO is returned if device doesn't have PM Capabilities. | |
644 | * -EINVAL is returned if device supports it, but can't generate wake events. | |
645 | * 0 if operation is successful. | |
646 | * | |
647 | */ | |
648 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
649 | { | |
650 | int pm; | |
651 | u16 value; | |
652 | ||
653 | /* find PCI PM capability in list */ | |
654 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
655 | ||
656 | /* If device doesn't support PM Capabilities, but request is to disable | |
657 | * wake events, it's a nop; otherwise fail */ | |
658 | if (!pm) | |
659 | return enable ? -EIO : 0; | |
660 | ||
661 | /* Check device's ability to generate PME# */ | |
662 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
663 | ||
664 | value &= PCI_PM_CAP_PME_MASK; | |
665 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
666 | ||
667 | /* Check if it can generate PME# from requested state. */ | |
668 | if (!value || !(value & (1 << state))) | |
669 | return enable ? -EINVAL : 0; | |
670 | ||
671 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
672 | ||
673 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
674 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
675 | ||
676 | if (!enable) | |
677 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
678 | ||
679 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | int | |
685 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
686 | { | |
687 | u8 pin; | |
688 | ||
514d207d | 689 | pin = dev->pin; |
1da177e4 LT |
690 | if (!pin) |
691 | return -1; | |
692 | pin--; | |
693 | while (dev->bus->self) { | |
694 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
695 | dev = dev->bus->self; | |
696 | } | |
697 | *bridge = dev; | |
698 | return pin; | |
699 | } | |
700 | ||
701 | /** | |
702 | * pci_release_region - Release a PCI bar | |
703 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
704 | * @bar: BAR to release | |
705 | * | |
706 | * Releases the PCI I/O and memory resources previously reserved by a | |
707 | * successful call to pci_request_region. Call this function only | |
708 | * after all use of the PCI regions has ceased. | |
709 | */ | |
710 | void pci_release_region(struct pci_dev *pdev, int bar) | |
711 | { | |
712 | if (pci_resource_len(pdev, bar) == 0) | |
713 | return; | |
714 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
715 | release_region(pci_resource_start(pdev, bar), | |
716 | pci_resource_len(pdev, bar)); | |
717 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
718 | release_mem_region(pci_resource_start(pdev, bar), | |
719 | pci_resource_len(pdev, bar)); | |
720 | } | |
721 | ||
722 | /** | |
723 | * pci_request_region - Reserved PCI I/O and memory resource | |
724 | * @pdev: PCI device whose resources are to be reserved | |
725 | * @bar: BAR to be reserved | |
726 | * @res_name: Name to be associated with resource. | |
727 | * | |
728 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
729 | * being reserved by owner @res_name. Do not access any | |
730 | * address inside the PCI regions unless this call returns | |
731 | * successfully. | |
732 | * | |
733 | * Returns 0 on success, or %EBUSY on error. A warning | |
734 | * message is also printed on failure. | |
735 | */ | |
3c990e92 | 736 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 LT |
737 | { |
738 | if (pci_resource_len(pdev, bar) == 0) | |
739 | return 0; | |
740 | ||
741 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
742 | if (!request_region(pci_resource_start(pdev, bar), | |
743 | pci_resource_len(pdev, bar), res_name)) | |
744 | goto err_out; | |
745 | } | |
746 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
747 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
748 | pci_resource_len(pdev, bar), res_name)) | |
749 | goto err_out; | |
750 | } | |
751 | ||
752 | return 0; | |
753 | ||
754 | err_out: | |
1396a8c3 GKH |
755 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
756 | "for device %s\n", | |
1da177e4 LT |
757 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
758 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
759 | (unsigned long long)pci_resource_len(pdev, bar), |
760 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
761 | pci_name(pdev)); |
762 | return -EBUSY; | |
763 | } | |
764 | ||
765 | ||
766 | /** | |
767 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
768 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
769 | * | |
770 | * Releases all PCI I/O and memory resources previously reserved by a | |
771 | * successful call to pci_request_regions. Call this function only | |
772 | * after all use of the PCI regions has ceased. | |
773 | */ | |
774 | ||
775 | void pci_release_regions(struct pci_dev *pdev) | |
776 | { | |
777 | int i; | |
778 | ||
779 | for (i = 0; i < 6; i++) | |
780 | pci_release_region(pdev, i); | |
781 | } | |
782 | ||
783 | /** | |
784 | * pci_request_regions - Reserved PCI I/O and memory resources | |
785 | * @pdev: PCI device whose resources are to be reserved | |
786 | * @res_name: Name to be associated with resource. | |
787 | * | |
788 | * Mark all PCI regions associated with PCI device @pdev as | |
789 | * being reserved by owner @res_name. Do not access any | |
790 | * address inside the PCI regions unless this call returns | |
791 | * successfully. | |
792 | * | |
793 | * Returns 0 on success, or %EBUSY on error. A warning | |
794 | * message is also printed on failure. | |
795 | */ | |
3c990e92 | 796 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 LT |
797 | { |
798 | int i; | |
799 | ||
800 | for (i = 0; i < 6; i++) | |
801 | if(pci_request_region(pdev, i, res_name)) | |
802 | goto err_out; | |
803 | return 0; | |
804 | ||
805 | err_out: | |
806 | while(--i >= 0) | |
807 | pci_release_region(pdev, i); | |
808 | ||
809 | return -EBUSY; | |
810 | } | |
811 | ||
812 | /** | |
813 | * pci_set_master - enables bus-mastering for device dev | |
814 | * @dev: the PCI device to enable | |
815 | * | |
816 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
817 | * to do the needed arch specific settings. | |
818 | */ | |
819 | void | |
820 | pci_set_master(struct pci_dev *dev) | |
821 | { | |
822 | u16 cmd; | |
823 | ||
824 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
825 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
826 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
827 | cmd |= PCI_COMMAND_MASTER; | |
828 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
829 | } | |
830 | dev->is_busmaster = 1; | |
831 | pcibios_set_master(dev); | |
832 | } | |
833 | ||
834 | #ifndef HAVE_ARCH_PCI_MWI | |
835 | /* This can be overridden by arch code. */ | |
836 | u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; | |
837 | ||
838 | /** | |
839 | * pci_generic_prep_mwi - helper function for pci_set_mwi | |
840 | * @dev: the PCI device for which MWI is enabled | |
841 | * | |
842 | * Helper function for generic implementation of pcibios_prep_mwi | |
843 | * function. Originally copied from drivers/net/acenic.c. | |
844 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. | |
845 | * | |
846 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
847 | */ | |
848 | static int | |
849 | pci_generic_prep_mwi(struct pci_dev *dev) | |
850 | { | |
851 | u8 cacheline_size; | |
852 | ||
853 | if (!pci_cache_line_size) | |
854 | return -EINVAL; /* The system doesn't support MWI. */ | |
855 | ||
856 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
857 | equal to or multiple of the right value. */ | |
858 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
859 | if (cacheline_size >= pci_cache_line_size && | |
860 | (cacheline_size % pci_cache_line_size) == 0) | |
861 | return 0; | |
862 | ||
863 | /* Write the correct value. */ | |
864 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
865 | /* Read it back. */ | |
866 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
867 | if (cacheline_size == pci_cache_line_size) | |
868 | return 0; | |
869 | ||
870 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
871 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
872 | ||
873 | return -EINVAL; | |
874 | } | |
875 | #endif /* !HAVE_ARCH_PCI_MWI */ | |
876 | ||
877 | /** | |
878 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
879 | * @dev: the PCI device for which MWI is enabled | |
880 | * | |
881 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, | |
882 | * and then calls @pcibios_set_mwi to do the needed arch specific | |
883 | * operations or a generic mwi-prep function. | |
884 | * | |
885 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
886 | */ | |
887 | int | |
888 | pci_set_mwi(struct pci_dev *dev) | |
889 | { | |
890 | int rc; | |
891 | u16 cmd; | |
892 | ||
893 | #ifdef HAVE_ARCH_PCI_MWI | |
894 | rc = pcibios_prep_mwi(dev); | |
895 | #else | |
896 | rc = pci_generic_prep_mwi(dev); | |
897 | #endif | |
898 | ||
899 | if (rc) | |
900 | return rc; | |
901 | ||
902 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
903 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
904 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); | |
905 | cmd |= PCI_COMMAND_INVALIDATE; | |
906 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
907 | } | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | /** | |
913 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
914 | * @dev: the PCI device to disable | |
915 | * | |
916 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
917 | */ | |
918 | void | |
919 | pci_clear_mwi(struct pci_dev *dev) | |
920 | { | |
921 | u16 cmd; | |
922 | ||
923 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
924 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
925 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
926 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
927 | } | |
928 | } | |
929 | ||
a04ce0ff BR |
930 | /** |
931 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
932 | * @pdev: the PCI device to operate on |
933 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
934 | * |
935 | * Enables/disables PCI INTx for device dev | |
936 | */ | |
937 | void | |
938 | pci_intx(struct pci_dev *pdev, int enable) | |
939 | { | |
940 | u16 pci_command, new; | |
941 | ||
942 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
943 | ||
944 | if (enable) { | |
945 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
946 | } else { | |
947 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
948 | } | |
949 | ||
950 | if (new != pci_command) { | |
2fd9d74b | 951 | pci_write_config_word(pdev, PCI_COMMAND, new); |
a04ce0ff BR |
952 | } |
953 | } | |
954 | ||
1da177e4 LT |
955 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
956 | /* | |
957 | * These can be overridden by arch-specific implementations | |
958 | */ | |
959 | int | |
960 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
961 | { | |
962 | if (!pci_dma_supported(dev, mask)) | |
963 | return -EIO; | |
964 | ||
965 | dev->dma_mask = mask; | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
1da177e4 LT |
970 | int |
971 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
972 | { | |
973 | if (!pci_dma_supported(dev, mask)) | |
974 | return -EIO; | |
975 | ||
976 | dev->dev.coherent_dma_mask = mask; | |
977 | ||
978 | return 0; | |
979 | } | |
980 | #endif | |
981 | ||
982 | static int __devinit pci_init(void) | |
983 | { | |
984 | struct pci_dev *dev = NULL; | |
985 | ||
986 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
987 | pci_fixup_device(pci_fixup_final, dev); | |
988 | } | |
989 | return 0; | |
990 | } | |
991 | ||
992 | static int __devinit pci_setup(char *str) | |
993 | { | |
994 | while (str) { | |
995 | char *k = strchr(str, ','); | |
996 | if (k) | |
997 | *k++ = 0; | |
998 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
999 | if (!strcmp(str, "nomsi")) { |
1000 | pci_no_msi(); | |
1001 | } else { | |
1002 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1003 | str); | |
1004 | } | |
1da177e4 LT |
1005 | } |
1006 | str = k; | |
1007 | } | |
0637a70a | 1008 | return 0; |
1da177e4 | 1009 | } |
0637a70a | 1010 | early_param("pci", pci_setup); |
1da177e4 LT |
1011 | |
1012 | device_initcall(pci_init); | |
1da177e4 LT |
1013 | |
1014 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
1015 | /* FIXME: Some boxes have multiple ISA bridges! */ | |
1016 | struct pci_dev *isa_bridge; | |
1017 | EXPORT_SYMBOL(isa_bridge); | |
1018 | #endif | |
1019 | ||
064b53db | 1020 | EXPORT_SYMBOL_GPL(pci_restore_bars); |
1da177e4 LT |
1021 | EXPORT_SYMBOL(pci_enable_device_bars); |
1022 | EXPORT_SYMBOL(pci_enable_device); | |
1023 | EXPORT_SYMBOL(pci_disable_device); | |
1da177e4 LT |
1024 | EXPORT_SYMBOL(pci_find_capability); |
1025 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1026 | EXPORT_SYMBOL(pci_release_regions); | |
1027 | EXPORT_SYMBOL(pci_request_regions); | |
1028 | EXPORT_SYMBOL(pci_release_region); | |
1029 | EXPORT_SYMBOL(pci_request_region); | |
1030 | EXPORT_SYMBOL(pci_set_master); | |
1031 | EXPORT_SYMBOL(pci_set_mwi); | |
1032 | EXPORT_SYMBOL(pci_clear_mwi); | |
a04ce0ff | 1033 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1034 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1035 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1036 | EXPORT_SYMBOL(pci_assign_resource); | |
1037 | EXPORT_SYMBOL(pci_find_parent_resource); | |
1038 | ||
1039 | EXPORT_SYMBOL(pci_set_power_state); | |
1040 | EXPORT_SYMBOL(pci_save_state); | |
1041 | EXPORT_SYMBOL(pci_restore_state); | |
1042 | EXPORT_SYMBOL(pci_enable_wake); | |
1043 | ||
1044 | /* Quirk info */ | |
1045 | ||
1046 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
1047 | EXPORT_SYMBOL(pci_pci_problems); |