Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
2ab51dde | 10 | #include <linux/acpi.h> |
1da177e4 LT |
11 | #include <linux/kernel.h> |
12 | #include <linux/delay.h> | |
9d26d3a8 | 13 | #include <linux/dmi.h> |
1da177e4 | 14 | #include <linux/init.h> |
7c674700 LP |
15 | #include <linux/of.h> |
16 | #include <linux/of_pci.h> | |
1da177e4 | 17 | #include <linux/pci.h> |
075c1771 | 18 | #include <linux/pm.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1da177e4 LT |
20 | #include <linux/module.h> |
21 | #include <linux/spinlock.h> | |
4e57b681 | 22 | #include <linux/string.h> |
229f5afd | 23 | #include <linux/log2.h> |
7d715a6c | 24 | #include <linux/pci-aspm.h> |
c300bd2f | 25 | #include <linux/pm_wakeup.h> |
8dd7f803 | 26 | #include <linux/interrupt.h> |
32a9a682 | 27 | #include <linux/device.h> |
b67ea761 | 28 | #include <linux/pm_runtime.h> |
608c3881 | 29 | #include <linux/pci_hotplug.h> |
4d3f1384 | 30 | #include <linux/vmalloc.h> |
32a9a682 | 31 | #include <asm/setup.h> |
2a2aca31 | 32 | #include <asm/dma.h> |
b07461a8 | 33 | #include <linux/aer.h> |
bc56b9e0 | 34 | #include "pci.h" |
1da177e4 | 35 | |
00240c38 AS |
36 | const char *pci_power_names[] = { |
37 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
38 | }; | |
39 | EXPORT_SYMBOL_GPL(pci_power_names); | |
40 | ||
93177a74 RW |
41 | int isa_dma_bridge_buggy; |
42 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
43 | ||
44 | int pci_pci_problems; | |
45 | EXPORT_SYMBOL(pci_pci_problems); | |
46 | ||
1ae861e6 RW |
47 | unsigned int pci_pm_d3_delay; |
48 | ||
df17e62e MG |
49 | static void pci_pme_list_scan(struct work_struct *work); |
50 | ||
51 | static LIST_HEAD(pci_pme_list); | |
52 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
53 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
54 | ||
55 | struct pci_pme_device { | |
56 | struct list_head list; | |
57 | struct pci_dev *dev; | |
58 | }; | |
59 | ||
60 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
61 | ||
1ae861e6 RW |
62 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
63 | { | |
64 | unsigned int delay = dev->d3_delay; | |
65 | ||
66 | if (delay < pci_pm_d3_delay) | |
67 | delay = pci_pm_d3_delay; | |
68 | ||
69 | msleep(delay); | |
70 | } | |
1da177e4 | 71 | |
32a2eea7 JG |
72 | #ifdef CONFIG_PCI_DOMAINS |
73 | int pci_domains_supported = 1; | |
74 | #endif | |
75 | ||
4516a618 AN |
76 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
77 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
78 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
79 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
80 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
81 | ||
28760489 EB |
82 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
83 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
84 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
85 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
86 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
87 | ||
e16b4660 KB |
88 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
89 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
90 | ||
27d868b5 | 91 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 92 | |
ac1aa47b JB |
93 | /* |
94 | * The default CLS is used if arch didn't set CLS explicitly and not | |
95 | * all pci devices agree on the same value. Arch can override either | |
96 | * the dfl or actual value as it sees fit. Don't forget this is | |
97 | * measured in 32-bit words, not bytes. | |
98 | */ | |
15856ad5 | 99 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
100 | u8 pci_cache_line_size; |
101 | ||
96c55900 MS |
102 | /* |
103 | * If we set up a device for bus mastering, we need to check the latency | |
104 | * timer as certain BIOSes forget to set it properly. | |
105 | */ | |
106 | unsigned int pcibios_max_latency = 255; | |
107 | ||
6748dcc2 RW |
108 | /* If set, the PCIe ARI capability will not be used. */ |
109 | static bool pcie_ari_disabled; | |
110 | ||
9d26d3a8 MW |
111 | /* Disable bridge_d3 for all PCIe ports */ |
112 | static bool pci_bridge_d3_disable; | |
113 | /* Force bridge_d3 for all PCIe ports */ | |
114 | static bool pci_bridge_d3_force; | |
115 | ||
116 | static int __init pcie_port_pm_setup(char *str) | |
117 | { | |
118 | if (!strcmp(str, "off")) | |
119 | pci_bridge_d3_disable = true; | |
120 | else if (!strcmp(str, "force")) | |
121 | pci_bridge_d3_force = true; | |
122 | return 1; | |
123 | } | |
124 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
125 | ||
1da177e4 LT |
126 | /** |
127 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
128 | * @bus: pointer to PCI bus structure to search | |
129 | * | |
130 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
131 | * including the given PCI bus and its list of child PCI buses. | |
132 | */ | |
07656d83 | 133 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 134 | { |
94e6a9b9 | 135 | struct pci_bus *tmp; |
1da177e4 LT |
136 | unsigned char max, n; |
137 | ||
b918c62e | 138 | max = bus->busn_res.end; |
94e6a9b9 YW |
139 | list_for_each_entry(tmp, &bus->children, node) { |
140 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 141 | if (n > max) |
1da177e4 LT |
142 | max = n; |
143 | } | |
144 | return max; | |
145 | } | |
b82db5ce | 146 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 147 | |
1684f5dd AM |
148 | #ifdef CONFIG_HAS_IOMEM |
149 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
150 | { | |
1f7bf3bf BH |
151 | struct resource *res = &pdev->resource[bar]; |
152 | ||
1684f5dd AM |
153 | /* |
154 | * Make sure the BAR is actually a memory resource, not an IO resource | |
155 | */ | |
646c0282 | 156 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
1f7bf3bf | 157 | dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
158 | return NULL; |
159 | } | |
1f7bf3bf | 160 | return ioremap_nocache(res->start, resource_size(res)); |
1684f5dd AM |
161 | } |
162 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
163 | |
164 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
165 | { | |
166 | /* | |
167 | * Make sure the BAR is actually a memory resource, not an IO resource | |
168 | */ | |
169 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
170 | WARN_ON(1); | |
171 | return NULL; | |
172 | } | |
173 | return ioremap_wc(pci_resource_start(pdev, bar), | |
174 | pci_resource_len(pdev, bar)); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
177 | #endif |
178 | ||
687d5fe3 ME |
179 | |
180 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
181 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
182 | { |
183 | u8 id; | |
55db3208 SS |
184 | u16 ent; |
185 | ||
186 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 187 | |
687d5fe3 | 188 | while ((*ttl)--) { |
24a4e377 RD |
189 | if (pos < 0x40) |
190 | break; | |
191 | pos &= ~3; | |
55db3208 SS |
192 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
193 | ||
194 | id = ent & 0xff; | |
24a4e377 RD |
195 | if (id == 0xff) |
196 | break; | |
197 | if (id == cap) | |
198 | return pos; | |
55db3208 | 199 | pos = (ent >> 8); |
24a4e377 RD |
200 | } |
201 | return 0; | |
202 | } | |
203 | ||
687d5fe3 ME |
204 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
205 | u8 pos, int cap) | |
206 | { | |
207 | int ttl = PCI_FIND_CAP_TTL; | |
208 | ||
209 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
210 | } | |
211 | ||
24a4e377 RD |
212 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
213 | { | |
214 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
215 | pos + PCI_CAP_LIST_NEXT, cap); | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
218 | ||
d3bac118 ME |
219 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
220 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
221 | { |
222 | u16 status; | |
1da177e4 LT |
223 | |
224 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
225 | if (!(status & PCI_STATUS_CAP_LIST)) | |
226 | return 0; | |
227 | ||
228 | switch (hdr_type) { | |
229 | case PCI_HEADER_TYPE_NORMAL: | |
230 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 231 | return PCI_CAPABILITY_LIST; |
1da177e4 | 232 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 233 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 234 | } |
d3bac118 ME |
235 | |
236 | return 0; | |
1da177e4 LT |
237 | } |
238 | ||
239 | /** | |
f7625980 | 240 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
241 | * @dev: PCI device to query |
242 | * @cap: capability code | |
243 | * | |
244 | * Tell if a device supports a given PCI capability. | |
245 | * Returns the address of the requested capability structure within the | |
246 | * device's PCI configuration space or 0 in case the device does not | |
247 | * support it. Possible values for @cap: | |
248 | * | |
f7625980 BH |
249 | * %PCI_CAP_ID_PM Power Management |
250 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
251 | * %PCI_CAP_ID_VPD Vital Product Data | |
252 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 253 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 254 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
255 | * %PCI_CAP_ID_PCIX PCI-X |
256 | * %PCI_CAP_ID_EXP PCI Express | |
257 | */ | |
258 | int pci_find_capability(struct pci_dev *dev, int cap) | |
259 | { | |
d3bac118 ME |
260 | int pos; |
261 | ||
262 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
263 | if (pos) | |
264 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
265 | ||
266 | return pos; | |
1da177e4 | 267 | } |
b7fe9434 | 268 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
269 | |
270 | /** | |
f7625980 | 271 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
272 | * @bus: the PCI bus to query |
273 | * @devfn: PCI device to query | |
274 | * @cap: capability code | |
275 | * | |
276 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 277 | * pci_dev structure set up yet. |
1da177e4 LT |
278 | * |
279 | * Returns the address of the requested capability structure within the | |
280 | * device's PCI configuration space or 0 in case the device does not | |
281 | * support it. | |
282 | */ | |
283 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
284 | { | |
d3bac118 | 285 | int pos; |
1da177e4 LT |
286 | u8 hdr_type; |
287 | ||
288 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
289 | ||
d3bac118 ME |
290 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
291 | if (pos) | |
292 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
293 | ||
294 | return pos; | |
1da177e4 | 295 | } |
b7fe9434 | 296 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
297 | |
298 | /** | |
44a9a36f | 299 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 300 | * @dev: PCI device to query |
44a9a36f | 301 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
302 | * @cap: capability code |
303 | * | |
44a9a36f | 304 | * Returns the address of the next matching extended capability structure |
1da177e4 | 305 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
306 | * not support it. Some capabilities can occur several times, e.g., the |
307 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 308 | */ |
44a9a36f | 309 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
310 | { |
311 | u32 header; | |
557848c3 ZY |
312 | int ttl; |
313 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 314 | |
557848c3 ZY |
315 | /* minimum 8 bytes per capability */ |
316 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
317 | ||
318 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
319 | return 0; |
320 | ||
44a9a36f BH |
321 | if (start) |
322 | pos = start; | |
323 | ||
1da177e4 LT |
324 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
325 | return 0; | |
326 | ||
327 | /* | |
328 | * If we have no capabilities, this is indicated by cap ID, | |
329 | * cap version and next pointer all being 0. | |
330 | */ | |
331 | if (header == 0) | |
332 | return 0; | |
333 | ||
334 | while (ttl-- > 0) { | |
44a9a36f | 335 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
336 | return pos; |
337 | ||
338 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 339 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
340 | break; |
341 | ||
342 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
343 | break; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
44a9a36f BH |
348 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
349 | ||
350 | /** | |
351 | * pci_find_ext_capability - Find an extended capability | |
352 | * @dev: PCI device to query | |
353 | * @cap: capability code | |
354 | * | |
355 | * Returns the address of the requested extended capability structure | |
356 | * within the device's PCI configuration space or 0 if the device does | |
357 | * not support it. Possible values for @cap: | |
358 | * | |
359 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
360 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
361 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
362 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
363 | */ | |
364 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
365 | { | |
366 | return pci_find_next_ext_capability(dev, 0, cap); | |
367 | } | |
3a720d72 | 368 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 369 | |
687d5fe3 ME |
370 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
371 | { | |
372 | int rc, ttl = PCI_FIND_CAP_TTL; | |
373 | u8 cap, mask; | |
374 | ||
375 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
376 | mask = HT_3BIT_CAP_MASK; | |
377 | else | |
378 | mask = HT_5BIT_CAP_MASK; | |
379 | ||
380 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
381 | PCI_CAP_ID_HT, &ttl); | |
382 | while (pos) { | |
383 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
384 | if (rc != PCIBIOS_SUCCESSFUL) | |
385 | return 0; | |
386 | ||
387 | if ((cap & mask) == ht_cap) | |
388 | return pos; | |
389 | ||
47a4d5be BG |
390 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
391 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
392 | PCI_CAP_ID_HT, &ttl); |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | /** | |
398 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
399 | * @dev: PCI device to query | |
400 | * @pos: Position from which to continue searching | |
401 | * @ht_cap: Hypertransport capability code | |
402 | * | |
403 | * To be used in conjunction with pci_find_ht_capability() to search for | |
404 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
405 | * from pci_find_ht_capability(). | |
406 | * | |
407 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
408 | * steps to avoid an infinite loop. | |
409 | */ | |
410 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
411 | { | |
412 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
415 | ||
416 | /** | |
417 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
418 | * @dev: PCI device to query | |
419 | * @ht_cap: Hypertransport capability code | |
420 | * | |
421 | * Tell if a device supports a given Hypertransport capability. | |
422 | * Returns an address within the device's PCI configuration space | |
423 | * or 0 in case the device does not support the request capability. | |
424 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
425 | * which has a Hypertransport capability matching @ht_cap. | |
426 | */ | |
427 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
428 | { | |
429 | int pos; | |
430 | ||
431 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
432 | if (pos) | |
433 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
434 | ||
435 | return pos; | |
436 | } | |
437 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
438 | ||
1da177e4 LT |
439 | /** |
440 | * pci_find_parent_resource - return resource region of parent bus of given region | |
441 | * @dev: PCI device structure contains resources to be searched | |
442 | * @res: child resource record for which parent is sought | |
443 | * | |
444 | * For given resource region of given device, return the resource | |
f44116ae | 445 | * region of parent bus the given region is contained in. |
1da177e4 | 446 | */ |
3c78bc61 RD |
447 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
448 | struct resource *res) | |
1da177e4 LT |
449 | { |
450 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 451 | struct resource *r; |
1da177e4 | 452 | int i; |
1da177e4 | 453 | |
89a74ecc | 454 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
455 | if (!r) |
456 | continue; | |
f44116ae BH |
457 | if (res->start && resource_contains(r, res)) { |
458 | ||
459 | /* | |
460 | * If the window is prefetchable but the BAR is | |
461 | * not, the allocator made a mistake. | |
462 | */ | |
463 | if (r->flags & IORESOURCE_PREFETCH && | |
464 | !(res->flags & IORESOURCE_PREFETCH)) | |
465 | return NULL; | |
466 | ||
467 | /* | |
468 | * If we're below a transparent bridge, there may | |
469 | * be both a positively-decoded aperture and a | |
470 | * subtractively-decoded region that contain the BAR. | |
471 | * We want the positively-decoded one, so this depends | |
472 | * on pci_bus_for_each_resource() giving us those | |
473 | * first. | |
474 | */ | |
475 | return r; | |
476 | } | |
1da177e4 | 477 | } |
f44116ae | 478 | return NULL; |
1da177e4 | 479 | } |
b7fe9434 | 480 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 481 | |
c56d4450 HS |
482 | /** |
483 | * pci_find_pcie_root_port - return PCIe Root Port | |
484 | * @dev: PCI device to query | |
485 | * | |
486 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
487 | * for a given PCI Device. | |
488 | */ | |
489 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
490 | { | |
491 | struct pci_dev *bridge, *highest_pcie_bridge = NULL; | |
492 | ||
493 | bridge = pci_upstream_bridge(dev); | |
494 | while (bridge && pci_is_pcie(bridge)) { | |
495 | highest_pcie_bridge = bridge; | |
496 | bridge = pci_upstream_bridge(bridge); | |
497 | } | |
498 | ||
499 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) | |
500 | return NULL; | |
501 | ||
502 | return highest_pcie_bridge; | |
503 | } | |
504 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
505 | ||
157e876f AW |
506 | /** |
507 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
508 | * @dev: the PCI device to operate on | |
509 | * @pos: config space offset of status word | |
510 | * @mask: mask of bit(s) to care about in status word | |
511 | * | |
512 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
513 | */ | |
514 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
515 | { | |
516 | int i; | |
517 | ||
518 | /* Wait for Transaction Pending bit clean */ | |
519 | for (i = 0; i < 4; i++) { | |
520 | u16 status; | |
521 | if (i) | |
522 | msleep((1 << (i - 1)) * 100); | |
523 | ||
524 | pci_read_config_word(dev, pos, &status); | |
525 | if (!(status & mask)) | |
526 | return 1; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
064b53db | 532 | /** |
70675e0b | 533 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
534 | * @dev: PCI device to have its BARs restored |
535 | * | |
536 | * Restore the BAR values for a given device, so as to make it | |
537 | * accessible by its driver. | |
538 | */ | |
3c78bc61 | 539 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 540 | { |
bc5f5a82 | 541 | int i; |
064b53db | 542 | |
70675e0b WY |
543 | /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ |
544 | if (dev->is_virtfn) | |
545 | return; | |
546 | ||
bc5f5a82 | 547 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 548 | pci_update_resource(dev, i); |
064b53db JL |
549 | } |
550 | ||
299f2ffe | 551 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 552 | |
299f2ffe | 553 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 554 | { |
6ec39cf5 AS |
555 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state || |
556 | !ops->sleep_wake || !ops->run_wake || !ops->need_resume) | |
961d9120 RW |
557 | return -EINVAL; |
558 | pci_platform_pm = ops; | |
559 | return 0; | |
560 | } | |
561 | ||
562 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
563 | { | |
564 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
565 | } | |
566 | ||
567 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 568 | pci_power_t t) |
961d9120 RW |
569 | { |
570 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
571 | } | |
572 | ||
573 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
574 | { | |
575 | return pci_platform_pm ? | |
576 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
577 | } | |
8f7020d3 | 578 | |
eb9d0fe4 RW |
579 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
580 | { | |
581 | return pci_platform_pm ? | |
582 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
583 | } | |
584 | ||
b67ea761 RW |
585 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
586 | { | |
587 | return pci_platform_pm ? | |
588 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
589 | } | |
590 | ||
bac2a909 RW |
591 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
592 | { | |
593 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
594 | } | |
595 | ||
1da177e4 | 596 | /** |
44e4e66e RW |
597 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
598 | * given PCI device | |
599 | * @dev: PCI device to handle. | |
44e4e66e | 600 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 601 | * |
44e4e66e RW |
602 | * RETURN VALUE: |
603 | * -EINVAL if the requested state is invalid. | |
604 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
605 | * wrong version, or device doesn't support the requested state. | |
606 | * 0 if device already is in the requested state. | |
607 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 608 | */ |
f00a20ef | 609 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 610 | { |
337001b6 | 611 | u16 pmcsr; |
44e4e66e | 612 | bool need_restore = false; |
1da177e4 | 613 | |
4a865905 RW |
614 | /* Check if we're already there */ |
615 | if (dev->current_state == state) | |
616 | return 0; | |
617 | ||
337001b6 | 618 | if (!dev->pm_cap) |
cca03dec AL |
619 | return -EIO; |
620 | ||
44e4e66e RW |
621 | if (state < PCI_D0 || state > PCI_D3hot) |
622 | return -EINVAL; | |
623 | ||
1da177e4 | 624 | /* Validate current state: |
f7625980 | 625 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
626 | * to sleep if we're already in a low power state |
627 | */ | |
4a865905 | 628 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 629 | && dev->current_state > state) { |
227f0647 RD |
630 | dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", |
631 | dev->current_state, state); | |
1da177e4 | 632 | return -EINVAL; |
44e4e66e | 633 | } |
1da177e4 | 634 | |
1da177e4 | 635 | /* check if this device supports the desired state */ |
337001b6 RW |
636 | if ((state == PCI_D1 && !dev->d1_support) |
637 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 638 | return -EIO; |
1da177e4 | 639 | |
337001b6 | 640 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 641 | |
32a36585 | 642 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
643 | * This doesn't affect PME_Status, disables PME_En, and |
644 | * sets PowerState to 0. | |
645 | */ | |
32a36585 | 646 | switch (dev->current_state) { |
d3535fbb JL |
647 | case PCI_D0: |
648 | case PCI_D1: | |
649 | case PCI_D2: | |
650 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
651 | pmcsr |= state; | |
652 | break; | |
f62795f1 RW |
653 | case PCI_D3hot: |
654 | case PCI_D3cold: | |
32a36585 JL |
655 | case PCI_UNKNOWN: /* Boot-up */ |
656 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 657 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 658 | need_restore = true; |
32a36585 | 659 | /* Fall-through: force to D0 */ |
32a36585 | 660 | default: |
d3535fbb | 661 | pmcsr = 0; |
32a36585 | 662 | break; |
1da177e4 LT |
663 | } |
664 | ||
665 | /* enter specified state */ | |
337001b6 | 666 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
667 | |
668 | /* Mandatory power management transition delays */ | |
669 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
670 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 671 | pci_dev_d3_sleep(dev); |
1da177e4 | 672 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 673 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 674 | |
e13cdbd7 RW |
675 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
676 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
677 | if (dev->current_state != state && printk_ratelimit()) | |
227f0647 RD |
678 | dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", |
679 | dev->current_state); | |
064b53db | 680 | |
448bd857 HY |
681 | /* |
682 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
683 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
684 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
685 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
686 | * For example, at least some versions of the 3c905B and the | |
687 | * 3c556B exhibit this behaviour. | |
688 | * | |
689 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
690 | * devices in a D3hot state at boot. Consequently, we need to | |
691 | * restore at least the BARs so that the device will be | |
692 | * accessible to its driver. | |
693 | */ | |
694 | if (need_restore) | |
695 | pci_restore_bars(dev); | |
696 | ||
f00a20ef | 697 | if (dev->bus->self) |
7d715a6c SL |
698 | pcie_aspm_pm_state_change(dev->bus->self); |
699 | ||
1da177e4 LT |
700 | return 0; |
701 | } | |
702 | ||
44e4e66e RW |
703 | /** |
704 | * pci_update_current_state - Read PCI power state of given device from its | |
705 | * PCI PM registers and cache it | |
706 | * @dev: PCI device to handle. | |
f06fc0b6 | 707 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 708 | */ |
73410429 | 709 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 710 | { |
337001b6 | 711 | if (dev->pm_cap) { |
44e4e66e RW |
712 | u16 pmcsr; |
713 | ||
448bd857 HY |
714 | /* |
715 | * Configuration space is not accessible for device in | |
716 | * D3cold, so just keep or set D3cold for safety | |
717 | */ | |
718 | if (dev->current_state == PCI_D3cold) | |
719 | return; | |
720 | if (state == PCI_D3cold) { | |
721 | dev->current_state = PCI_D3cold; | |
722 | return; | |
723 | } | |
337001b6 | 724 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 725 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
726 | } else { |
727 | dev->current_state = state; | |
44e4e66e RW |
728 | } |
729 | } | |
730 | ||
db288c9c RW |
731 | /** |
732 | * pci_power_up - Put the given device into D0 forcibly | |
733 | * @dev: PCI device to power up | |
734 | */ | |
735 | void pci_power_up(struct pci_dev *dev) | |
736 | { | |
737 | if (platform_pci_power_manageable(dev)) | |
738 | platform_pci_set_power_state(dev, PCI_D0); | |
739 | ||
740 | pci_raw_set_power_state(dev, PCI_D0); | |
741 | pci_update_current_state(dev, PCI_D0); | |
742 | } | |
743 | ||
0e5dd46b RW |
744 | /** |
745 | * pci_platform_power_transition - Use platform to change device power state | |
746 | * @dev: PCI device to handle. | |
747 | * @state: State to put the device into. | |
748 | */ | |
749 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
750 | { | |
751 | int error; | |
752 | ||
753 | if (platform_pci_power_manageable(dev)) { | |
754 | error = platform_pci_set_power_state(dev, state); | |
755 | if (!error) | |
756 | pci_update_current_state(dev, state); | |
769ba721 | 757 | } else |
0e5dd46b | 758 | error = -ENODEV; |
769ba721 RW |
759 | |
760 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
761 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
762 | |
763 | return error; | |
764 | } | |
765 | ||
0b950f0f SH |
766 | /** |
767 | * pci_wakeup - Wake up a PCI device | |
768 | * @pci_dev: Device to handle. | |
769 | * @ign: ignored parameter | |
770 | */ | |
771 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
772 | { | |
773 | pci_wakeup_event(pci_dev); | |
774 | pm_request_resume(&pci_dev->dev); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /** | |
779 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
780 | * @bus: Top bus of the subtree to walk. | |
781 | */ | |
782 | static void pci_wakeup_bus(struct pci_bus *bus) | |
783 | { | |
784 | if (bus) | |
785 | pci_walk_bus(bus, pci_wakeup, NULL); | |
786 | } | |
787 | ||
0e5dd46b RW |
788 | /** |
789 | * __pci_start_power_transition - Start power transition of a PCI device | |
790 | * @dev: PCI device to handle. | |
791 | * @state: State to put the device into. | |
792 | */ | |
793 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
794 | { | |
448bd857 | 795 | if (state == PCI_D0) { |
0e5dd46b | 796 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
797 | /* |
798 | * Mandatory power management transition delays, see | |
799 | * PCI Express Base Specification Revision 2.0 Section | |
800 | * 6.6.1: Conventional Reset. Do not delay for | |
801 | * devices powered on/off by corresponding bridge, | |
802 | * because have already delayed for the bridge. | |
803 | */ | |
804 | if (dev->runtime_d3cold) { | |
805 | msleep(dev->d3cold_delay); | |
806 | /* | |
807 | * When powering on a bridge from D3cold, the | |
808 | * whole hierarchy may be powered on into | |
809 | * D0uninitialized state, resume them to give | |
810 | * them a chance to suspend again | |
811 | */ | |
812 | pci_wakeup_bus(dev->subordinate); | |
813 | } | |
814 | } | |
815 | } | |
816 | ||
817 | /** | |
818 | * __pci_dev_set_current_state - Set current state of a PCI device | |
819 | * @dev: Device to handle | |
820 | * @data: pointer to state to be set | |
821 | */ | |
822 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
823 | { | |
824 | pci_power_t state = *(pci_power_t *)data; | |
825 | ||
826 | dev->current_state = state; | |
827 | return 0; | |
828 | } | |
829 | ||
830 | /** | |
831 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
832 | * @bus: Top bus of the subtree to walk. | |
833 | * @state: state to be set | |
834 | */ | |
835 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
836 | { | |
837 | if (bus) | |
838 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
839 | } |
840 | ||
841 | /** | |
842 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
843 | * @dev: PCI device to handle. | |
844 | * @state: State to put the device into. | |
845 | * | |
846 | * This function should not be called directly by device drivers. | |
847 | */ | |
848 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
849 | { | |
448bd857 HY |
850 | int ret; |
851 | ||
db288c9c | 852 | if (state <= PCI_D0) |
448bd857 HY |
853 | return -EINVAL; |
854 | ret = pci_platform_power_transition(dev, state); | |
855 | /* Power off the bridge may power off the whole hierarchy */ | |
856 | if (!ret && state == PCI_D3cold) | |
857 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
858 | return ret; | |
0e5dd46b RW |
859 | } |
860 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
861 | ||
44e4e66e RW |
862 | /** |
863 | * pci_set_power_state - Set the power state of a PCI device | |
864 | * @dev: PCI device to handle. | |
865 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
866 | * | |
877d0310 | 867 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
868 | * the device's PCI PM registers. |
869 | * | |
870 | * RETURN VALUE: | |
871 | * -EINVAL if the requested state is invalid. | |
872 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
873 | * wrong version, or device doesn't support the requested state. | |
874 | * 0 if device already is in the requested state. | |
875 | * 0 if device's power state has been successfully changed. | |
876 | */ | |
877 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
878 | { | |
337001b6 | 879 | int error; |
44e4e66e RW |
880 | |
881 | /* bound the state we're entering */ | |
448bd857 HY |
882 | if (state > PCI_D3cold) |
883 | state = PCI_D3cold; | |
44e4e66e RW |
884 | else if (state < PCI_D0) |
885 | state = PCI_D0; | |
886 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
887 | /* | |
888 | * If the device or the parent bridge do not support PCI PM, | |
889 | * ignore the request if we're doing anything other than putting | |
890 | * it into D0 (which would only happen on boot). | |
891 | */ | |
892 | return 0; | |
893 | ||
db288c9c RW |
894 | /* Check if we're already there */ |
895 | if (dev->current_state == state) | |
896 | return 0; | |
897 | ||
0e5dd46b RW |
898 | __pci_start_power_transition(dev, state); |
899 | ||
979b1791 AC |
900 | /* This device is quirked not to be put into D3, so |
901 | don't put it in D3 */ | |
448bd857 | 902 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 903 | return 0; |
44e4e66e | 904 | |
448bd857 HY |
905 | /* |
906 | * To put device in D3cold, we put device into D3hot in native | |
907 | * way, then put device into D3cold with platform ops | |
908 | */ | |
909 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
910 | PCI_D3hot : state); | |
44e4e66e | 911 | |
0e5dd46b RW |
912 | if (!__pci_complete_power_transition(dev, state)) |
913 | error = 0; | |
44e4e66e RW |
914 | |
915 | return error; | |
916 | } | |
b7fe9434 | 917 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 918 | |
1da177e4 LT |
919 | /** |
920 | * pci_choose_state - Choose the power state of a PCI device | |
921 | * @dev: PCI device to be suspended | |
922 | * @state: target sleep state for the whole system. This is the value | |
923 | * that is passed to suspend() function. | |
924 | * | |
925 | * Returns PCI power state suitable for given device and given system | |
926 | * message. | |
927 | */ | |
928 | ||
929 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
930 | { | |
ab826ca4 | 931 | pci_power_t ret; |
0f64474b | 932 | |
728cdb75 | 933 | if (!dev->pm_cap) |
1da177e4 LT |
934 | return PCI_D0; |
935 | ||
961d9120 RW |
936 | ret = platform_pci_choose_state(dev); |
937 | if (ret != PCI_POWER_ERROR) | |
938 | return ret; | |
ca078bae PM |
939 | |
940 | switch (state.event) { | |
941 | case PM_EVENT_ON: | |
942 | return PCI_D0; | |
943 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
944 | case PM_EVENT_PRETHAW: |
945 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 946 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 947 | case PM_EVENT_HIBERNATE: |
ca078bae | 948 | return PCI_D3hot; |
1da177e4 | 949 | default: |
80ccba11 BH |
950 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
951 | state.event); | |
1da177e4 LT |
952 | BUG(); |
953 | } | |
954 | return PCI_D0; | |
955 | } | |
1da177e4 LT |
956 | EXPORT_SYMBOL(pci_choose_state); |
957 | ||
89858517 YZ |
958 | #define PCI_EXP_SAVE_REGS 7 |
959 | ||
fd0f7f73 AW |
960 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
961 | u16 cap, bool extended) | |
34a4876e YL |
962 | { |
963 | struct pci_cap_saved_state *tmp; | |
34a4876e | 964 | |
b67bfe0d | 965 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 966 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
967 | return tmp; |
968 | } | |
969 | return NULL; | |
970 | } | |
971 | ||
fd0f7f73 AW |
972 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
973 | { | |
974 | return _pci_find_saved_cap(dev, cap, false); | |
975 | } | |
976 | ||
977 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
978 | { | |
979 | return _pci_find_saved_cap(dev, cap, true); | |
980 | } | |
981 | ||
b56a5a23 MT |
982 | static int pci_save_pcie_state(struct pci_dev *dev) |
983 | { | |
59875ae4 | 984 | int i = 0; |
b56a5a23 MT |
985 | struct pci_cap_saved_state *save_state; |
986 | u16 *cap; | |
987 | ||
59875ae4 | 988 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
989 | return 0; |
990 | ||
9f35575d | 991 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 992 | if (!save_state) { |
e496b617 | 993 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
994 | return -ENOMEM; |
995 | } | |
63f4898a | 996 | |
59875ae4 JL |
997 | cap = (u16 *)&save_state->cap.data[0]; |
998 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
999 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1000 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1001 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1002 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1003 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1004 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1005 | |
b56a5a23 MT |
1006 | return 0; |
1007 | } | |
1008 | ||
1009 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1010 | { | |
59875ae4 | 1011 | int i = 0; |
b56a5a23 MT |
1012 | struct pci_cap_saved_state *save_state; |
1013 | u16 *cap; | |
1014 | ||
1015 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1016 | if (!save_state) |
9cb604ed MS |
1017 | return; |
1018 | ||
59875ae4 JL |
1019 | cap = (u16 *)&save_state->cap.data[0]; |
1020 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1021 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1022 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1023 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1024 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1025 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1026 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1027 | } |
1028 | ||
cc692a5f SH |
1029 | |
1030 | static int pci_save_pcix_state(struct pci_dev *dev) | |
1031 | { | |
63f4898a | 1032 | int pos; |
cc692a5f | 1033 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1034 | |
1035 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1036 | if (!pos) |
cc692a5f SH |
1037 | return 0; |
1038 | ||
f34303de | 1039 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1040 | if (!save_state) { |
e496b617 | 1041 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1042 | return -ENOMEM; |
1043 | } | |
cc692a5f | 1044 | |
24a4742f AW |
1045 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1046 | (u16 *)save_state->cap.data); | |
63f4898a | 1047 | |
cc692a5f SH |
1048 | return 0; |
1049 | } | |
1050 | ||
1051 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1052 | { | |
1053 | int i = 0, pos; | |
1054 | struct pci_cap_saved_state *save_state; | |
1055 | u16 *cap; | |
1056 | ||
1057 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1058 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1059 | if (!save_state || !pos) |
cc692a5f | 1060 | return; |
24a4742f | 1061 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1062 | |
1063 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1064 | } |
1065 | ||
1066 | ||
1da177e4 LT |
1067 | /** |
1068 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1069 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1070 | */ |
3c78bc61 | 1071 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1072 | { |
1073 | int i; | |
1074 | /* XXX: 100% dword access ok here? */ | |
1075 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1076 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1077 | dev->state_saved = true; |
79e50e72 QL |
1078 | |
1079 | i = pci_save_pcie_state(dev); | |
1080 | if (i != 0) | |
b56a5a23 | 1081 | return i; |
79e50e72 QL |
1082 | |
1083 | i = pci_save_pcix_state(dev); | |
1084 | if (i != 0) | |
cc692a5f | 1085 | return i; |
79e50e72 | 1086 | |
754834b9 | 1087 | return pci_save_vc_state(dev); |
1da177e4 | 1088 | } |
b7fe9434 | 1089 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1090 | |
ebfc5b80 RW |
1091 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1092 | u32 saved_val, int retry) | |
1093 | { | |
1094 | u32 val; | |
1095 | ||
1096 | pci_read_config_dword(pdev, offset, &val); | |
1097 | if (val == saved_val) | |
1098 | return; | |
1099 | ||
1100 | for (;;) { | |
227f0647 RD |
1101 | dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
1102 | offset, val, saved_val); | |
ebfc5b80 RW |
1103 | pci_write_config_dword(pdev, offset, saved_val); |
1104 | if (retry-- <= 0) | |
1105 | return; | |
1106 | ||
1107 | pci_read_config_dword(pdev, offset, &val); | |
1108 | if (val == saved_val) | |
1109 | return; | |
1110 | ||
1111 | mdelay(1); | |
1112 | } | |
1113 | } | |
1114 | ||
a6cb9ee7 RW |
1115 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1116 | int start, int end, int retry) | |
ebfc5b80 RW |
1117 | { |
1118 | int index; | |
1119 | ||
1120 | for (index = end; index >= start; index--) | |
1121 | pci_restore_config_dword(pdev, 4 * index, | |
1122 | pdev->saved_config_space[index], | |
1123 | retry); | |
1124 | } | |
1125 | ||
a6cb9ee7 RW |
1126 | static void pci_restore_config_space(struct pci_dev *pdev) |
1127 | { | |
1128 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1129 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1130 | /* Restore BARs before the command register. */ | |
1131 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1132 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1133 | } else { | |
1134 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1135 | } | |
1136 | } | |
1137 | ||
f7625980 | 1138 | /** |
1da177e4 LT |
1139 | * pci_restore_state - Restore the saved state of a PCI device |
1140 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1141 | */ |
1d3c16a8 | 1142 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1143 | { |
c82f63e4 | 1144 | if (!dev->state_saved) |
1d3c16a8 | 1145 | return; |
4b77b0a2 | 1146 | |
b56a5a23 MT |
1147 | /* PCI Express register must be restored first */ |
1148 | pci_restore_pcie_state(dev); | |
1900ca13 | 1149 | pci_restore_ats_state(dev); |
425c1b22 | 1150 | pci_restore_vc_state(dev); |
b56a5a23 | 1151 | |
b07461a8 TI |
1152 | pci_cleanup_aer_error_status_regs(dev); |
1153 | ||
a6cb9ee7 | 1154 | pci_restore_config_space(dev); |
ebfc5b80 | 1155 | |
cc692a5f | 1156 | pci_restore_pcix_state(dev); |
41017f0c | 1157 | pci_restore_msi_state(dev); |
ccbc175a AD |
1158 | |
1159 | /* Restore ACS and IOV configuration state */ | |
1160 | pci_enable_acs(dev); | |
8c5cdb6a | 1161 | pci_restore_iov_state(dev); |
8fed4b65 | 1162 | |
4b77b0a2 | 1163 | dev->state_saved = false; |
1da177e4 | 1164 | } |
b7fe9434 | 1165 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1166 | |
ffbdd3f7 AW |
1167 | struct pci_saved_state { |
1168 | u32 config_space[16]; | |
1169 | struct pci_cap_saved_data cap[0]; | |
1170 | }; | |
1171 | ||
1172 | /** | |
1173 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1174 | * the device saved state. | |
1175 | * @dev: PCI device that we're dealing with | |
1176 | * | |
f7625980 | 1177 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1178 | */ |
1179 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1180 | { | |
1181 | struct pci_saved_state *state; | |
1182 | struct pci_cap_saved_state *tmp; | |
1183 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1184 | size_t size; |
1185 | ||
1186 | if (!dev->state_saved) | |
1187 | return NULL; | |
1188 | ||
1189 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1190 | ||
b67bfe0d | 1191 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1192 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1193 | ||
1194 | state = kzalloc(size, GFP_KERNEL); | |
1195 | if (!state) | |
1196 | return NULL; | |
1197 | ||
1198 | memcpy(state->config_space, dev->saved_config_space, | |
1199 | sizeof(state->config_space)); | |
1200 | ||
1201 | cap = state->cap; | |
b67bfe0d | 1202 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1203 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1204 | memcpy(cap, &tmp->cap, len); | |
1205 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1206 | } | |
1207 | /* Empty cap_save terminates list */ | |
1208 | ||
1209 | return state; | |
1210 | } | |
1211 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1212 | ||
1213 | /** | |
1214 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1215 | * @dev: PCI device that we're dealing with | |
1216 | * @state: Saved state returned from pci_store_saved_state() | |
1217 | */ | |
98d9b271 KRW |
1218 | int pci_load_saved_state(struct pci_dev *dev, |
1219 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1220 | { |
1221 | struct pci_cap_saved_data *cap; | |
1222 | ||
1223 | dev->state_saved = false; | |
1224 | ||
1225 | if (!state) | |
1226 | return 0; | |
1227 | ||
1228 | memcpy(dev->saved_config_space, state->config_space, | |
1229 | sizeof(state->config_space)); | |
1230 | ||
1231 | cap = state->cap; | |
1232 | while (cap->size) { | |
1233 | struct pci_cap_saved_state *tmp; | |
1234 | ||
fd0f7f73 | 1235 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1236 | if (!tmp || tmp->cap.size != cap->size) |
1237 | return -EINVAL; | |
1238 | ||
1239 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1240 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1241 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1242 | } | |
1243 | ||
1244 | dev->state_saved = true; | |
1245 | return 0; | |
1246 | } | |
98d9b271 | 1247 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1248 | |
1249 | /** | |
1250 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1251 | * and free the memory allocated for it. | |
1252 | * @dev: PCI device that we're dealing with | |
1253 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1254 | */ | |
1255 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1256 | struct pci_saved_state **state) | |
1257 | { | |
1258 | int ret = pci_load_saved_state(dev, *state); | |
1259 | kfree(*state); | |
1260 | *state = NULL; | |
1261 | return ret; | |
1262 | } | |
1263 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1264 | ||
8a9d5609 BH |
1265 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1266 | { | |
1267 | return pci_enable_resources(dev, bars); | |
1268 | } | |
1269 | ||
38cc1302 HS |
1270 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1271 | { | |
1272 | int err; | |
1f6ae47e | 1273 | struct pci_dev *bridge; |
1e2571a7 BH |
1274 | u16 cmd; |
1275 | u8 pin; | |
38cc1302 HS |
1276 | |
1277 | err = pci_set_power_state(dev, PCI_D0); | |
1278 | if (err < 0 && err != -EIO) | |
1279 | return err; | |
1f6ae47e VS |
1280 | |
1281 | bridge = pci_upstream_bridge(dev); | |
1282 | if (bridge) | |
1283 | pcie_aspm_powersave_config_link(bridge); | |
1284 | ||
38cc1302 HS |
1285 | err = pcibios_enable_device(dev, bars); |
1286 | if (err < 0) | |
1287 | return err; | |
1288 | pci_fixup_device(pci_fixup_enable, dev); | |
1289 | ||
866d5417 BH |
1290 | if (dev->msi_enabled || dev->msix_enabled) |
1291 | return 0; | |
1292 | ||
1e2571a7 BH |
1293 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1294 | if (pin) { | |
1295 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1296 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1297 | pci_write_config_word(dev, PCI_COMMAND, | |
1298 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1299 | } | |
1300 | ||
38cc1302 HS |
1301 | return 0; |
1302 | } | |
1303 | ||
1304 | /** | |
0b62e13b | 1305 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1306 | * @dev: PCI device to be resumed |
1307 | * | |
1308 | * Note this function is a backend of pci_default_resume and is not supposed | |
1309 | * to be called by normal code, write proper resume handler and use it instead. | |
1310 | */ | |
0b62e13b | 1311 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1312 | { |
296ccb08 | 1313 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1314 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1315 | return 0; | |
1316 | } | |
b7fe9434 | 1317 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1318 | |
928bea96 YL |
1319 | static void pci_enable_bridge(struct pci_dev *dev) |
1320 | { | |
79272138 | 1321 | struct pci_dev *bridge; |
928bea96 YL |
1322 | int retval; |
1323 | ||
79272138 BH |
1324 | bridge = pci_upstream_bridge(dev); |
1325 | if (bridge) | |
1326 | pci_enable_bridge(bridge); | |
928bea96 | 1327 | |
cf3e1feb | 1328 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1329 | if (!dev->is_busmaster) |
cf3e1feb | 1330 | pci_set_master(dev); |
928bea96 | 1331 | return; |
cf3e1feb YL |
1332 | } |
1333 | ||
928bea96 YL |
1334 | retval = pci_enable_device(dev); |
1335 | if (retval) | |
1336 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1337 | retval); | |
1338 | pci_set_master(dev); | |
1339 | } | |
1340 | ||
b4b4fbba | 1341 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1342 | { |
79272138 | 1343 | struct pci_dev *bridge; |
1da177e4 | 1344 | int err; |
b718989d | 1345 | int i, bars = 0; |
1da177e4 | 1346 | |
97c145f7 JB |
1347 | /* |
1348 | * Power state could be unknown at this point, either due to a fresh | |
1349 | * boot or a device removal call. So get the current power state | |
1350 | * so that things like MSI message writing will behave as expected | |
1351 | * (e.g. if the device really is in D0 at enable time). | |
1352 | */ | |
1353 | if (dev->pm_cap) { | |
1354 | u16 pmcsr; | |
1355 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1356 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1357 | } | |
1358 | ||
cc7ba39b | 1359 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1360 | return 0; /* already enabled */ |
1361 | ||
79272138 BH |
1362 | bridge = pci_upstream_bridge(dev); |
1363 | if (bridge) | |
1364 | pci_enable_bridge(bridge); | |
928bea96 | 1365 | |
497f16f2 YL |
1366 | /* only skip sriov related */ |
1367 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1368 | if (dev->resource[i].flags & flags) | |
1369 | bars |= (1 << i); | |
1370 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1371 | if (dev->resource[i].flags & flags) |
1372 | bars |= (1 << i); | |
1373 | ||
38cc1302 | 1374 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1375 | if (err < 0) |
38cc1302 | 1376 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1377 | return err; |
1da177e4 LT |
1378 | } |
1379 | ||
b718989d BH |
1380 | /** |
1381 | * pci_enable_device_io - Initialize a device for use with IO space | |
1382 | * @dev: PCI device to be initialized | |
1383 | * | |
1384 | * Initialize device before it's used by a driver. Ask low-level code | |
1385 | * to enable I/O resources. Wake up the device if it was suspended. | |
1386 | * Beware, this function can fail. | |
1387 | */ | |
1388 | int pci_enable_device_io(struct pci_dev *dev) | |
1389 | { | |
b4b4fbba | 1390 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1391 | } |
b7fe9434 | 1392 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1393 | |
1394 | /** | |
1395 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1396 | * @dev: PCI device to be initialized | |
1397 | * | |
1398 | * Initialize device before it's used by a driver. Ask low-level code | |
1399 | * to enable Memory resources. Wake up the device if it was suspended. | |
1400 | * Beware, this function can fail. | |
1401 | */ | |
1402 | int pci_enable_device_mem(struct pci_dev *dev) | |
1403 | { | |
b4b4fbba | 1404 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1405 | } |
b7fe9434 | 1406 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1407 | |
bae94d02 IPG |
1408 | /** |
1409 | * pci_enable_device - Initialize device before it's used by a driver. | |
1410 | * @dev: PCI device to be initialized | |
1411 | * | |
1412 | * Initialize device before it's used by a driver. Ask low-level code | |
1413 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1414 | * Beware, this function can fail. | |
1415 | * | |
1416 | * Note we don't actually enable the device many times if we call | |
1417 | * this function repeatedly (we just increment the count). | |
1418 | */ | |
1419 | int pci_enable_device(struct pci_dev *dev) | |
1420 | { | |
b4b4fbba | 1421 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1422 | } |
b7fe9434 | 1423 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1424 | |
9ac7849e TH |
1425 | /* |
1426 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1427 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1428 | * there's no need to track it separately. pci_devres is initialized | |
1429 | * when a device is enabled using managed PCI device enable interface. | |
1430 | */ | |
1431 | struct pci_devres { | |
7f375f32 TH |
1432 | unsigned int enabled:1; |
1433 | unsigned int pinned:1; | |
9ac7849e TH |
1434 | unsigned int orig_intx:1; |
1435 | unsigned int restore_intx:1; | |
1436 | u32 region_mask; | |
1437 | }; | |
1438 | ||
1439 | static void pcim_release(struct device *gendev, void *res) | |
1440 | { | |
f3d2f165 | 1441 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1442 | struct pci_devres *this = res; |
1443 | int i; | |
1444 | ||
1445 | if (dev->msi_enabled) | |
1446 | pci_disable_msi(dev); | |
1447 | if (dev->msix_enabled) | |
1448 | pci_disable_msix(dev); | |
1449 | ||
1450 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1451 | if (this->region_mask & (1 << i)) | |
1452 | pci_release_region(dev, i); | |
1453 | ||
1454 | if (this->restore_intx) | |
1455 | pci_intx(dev, this->orig_intx); | |
1456 | ||
7f375f32 | 1457 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1458 | pci_disable_device(dev); |
1459 | } | |
1460 | ||
07656d83 | 1461 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1462 | { |
1463 | struct pci_devres *dr, *new_dr; | |
1464 | ||
1465 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1466 | if (dr) | |
1467 | return dr; | |
1468 | ||
1469 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1470 | if (!new_dr) | |
1471 | return NULL; | |
1472 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1473 | } | |
1474 | ||
07656d83 | 1475 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1476 | { |
1477 | if (pci_is_managed(pdev)) | |
1478 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1479 | return NULL; | |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * pcim_enable_device - Managed pci_enable_device() | |
1484 | * @pdev: PCI device to be initialized | |
1485 | * | |
1486 | * Managed pci_enable_device(). | |
1487 | */ | |
1488 | int pcim_enable_device(struct pci_dev *pdev) | |
1489 | { | |
1490 | struct pci_devres *dr; | |
1491 | int rc; | |
1492 | ||
1493 | dr = get_pci_dr(pdev); | |
1494 | if (unlikely(!dr)) | |
1495 | return -ENOMEM; | |
b95d58ea TH |
1496 | if (dr->enabled) |
1497 | return 0; | |
9ac7849e TH |
1498 | |
1499 | rc = pci_enable_device(pdev); | |
1500 | if (!rc) { | |
1501 | pdev->is_managed = 1; | |
7f375f32 | 1502 | dr->enabled = 1; |
9ac7849e TH |
1503 | } |
1504 | return rc; | |
1505 | } | |
b7fe9434 | 1506 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1507 | |
1508 | /** | |
1509 | * pcim_pin_device - Pin managed PCI device | |
1510 | * @pdev: PCI device to pin | |
1511 | * | |
1512 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1513 | * driver detach. @pdev must have been enabled with | |
1514 | * pcim_enable_device(). | |
1515 | */ | |
1516 | void pcim_pin_device(struct pci_dev *pdev) | |
1517 | { | |
1518 | struct pci_devres *dr; | |
1519 | ||
1520 | dr = find_pci_dr(pdev); | |
7f375f32 | 1521 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1522 | if (dr) |
7f375f32 | 1523 | dr->pinned = 1; |
9ac7849e | 1524 | } |
b7fe9434 | 1525 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1526 | |
eca0d467 MG |
1527 | /* |
1528 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1529 | * @dev: the PCI device being added | |
1530 | * | |
1531 | * Permits the platform to provide architecture specific functionality when | |
1532 | * devices are added. This is the default implementation. Architecture | |
1533 | * implementations can override this. | |
1534 | */ | |
3c78bc61 | 1535 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1536 | { |
1537 | return 0; | |
1538 | } | |
1539 | ||
6ae32c53 SO |
1540 | /** |
1541 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1542 | * @dev: the PCI device being released | |
1543 | * | |
1544 | * Permits the platform to provide architecture specific functionality when | |
1545 | * devices are released. This is the default implementation. Architecture | |
1546 | * implementations can override this. | |
1547 | */ | |
1548 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1549 | ||
1da177e4 LT |
1550 | /** |
1551 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1552 | * @dev: the PCI device to disable | |
1553 | * | |
1554 | * Disables architecture specific PCI resources for the device. This | |
1555 | * is the default implementation. Architecture implementations can | |
1556 | * override this. | |
1557 | */ | |
ff3ce480 | 1558 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1559 | |
a43ae58c HG |
1560 | /** |
1561 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1562 | * @irq: ISA IRQ to penalize | |
1563 | * @active: IRQ active or not | |
1564 | * | |
1565 | * Permits the platform to provide architecture-specific functionality when | |
1566 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1567 | * implementations can override this. | |
1568 | */ | |
1569 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1570 | ||
fa58d305 RW |
1571 | static void do_pci_disable_device(struct pci_dev *dev) |
1572 | { | |
1573 | u16 pci_command; | |
1574 | ||
1575 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1576 | if (pci_command & PCI_COMMAND_MASTER) { | |
1577 | pci_command &= ~PCI_COMMAND_MASTER; | |
1578 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1579 | } | |
1580 | ||
1581 | pcibios_disable_device(dev); | |
1582 | } | |
1583 | ||
1584 | /** | |
1585 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1586 | * @dev: PCI device to disable | |
1587 | * | |
1588 | * NOTE: This function is a backend of PCI power management routines and is | |
1589 | * not supposed to be called drivers. | |
1590 | */ | |
1591 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1592 | { | |
296ccb08 | 1593 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1594 | do_pci_disable_device(dev); |
1595 | } | |
1596 | ||
1da177e4 LT |
1597 | /** |
1598 | * pci_disable_device - Disable PCI device after use | |
1599 | * @dev: PCI device to be disabled | |
1600 | * | |
1601 | * Signal to the system that the PCI device is not in use by the system | |
1602 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1603 | * |
1604 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1605 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1606 | */ |
3c78bc61 | 1607 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1608 | { |
9ac7849e | 1609 | struct pci_devres *dr; |
99dc804d | 1610 | |
9ac7849e TH |
1611 | dr = find_pci_dr(dev); |
1612 | if (dr) | |
7f375f32 | 1613 | dr->enabled = 0; |
9ac7849e | 1614 | |
fd6dceab KK |
1615 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1616 | "disabling already-disabled device"); | |
1617 | ||
cc7ba39b | 1618 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1619 | return; |
1620 | ||
fa58d305 | 1621 | do_pci_disable_device(dev); |
1da177e4 | 1622 | |
fa58d305 | 1623 | dev->is_busmaster = 0; |
1da177e4 | 1624 | } |
b7fe9434 | 1625 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1626 | |
f7bdd12d BK |
1627 | /** |
1628 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1629 | * @dev: the PCIe device reset |
f7bdd12d BK |
1630 | * @state: Reset state to enter into |
1631 | * | |
1632 | * | |
45e829ea | 1633 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1634 | * implementation. Architecture implementations can override this. |
1635 | */ | |
d6d88c83 BH |
1636 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1637 | enum pcie_reset_state state) | |
f7bdd12d BK |
1638 | { |
1639 | return -EINVAL; | |
1640 | } | |
1641 | ||
1642 | /** | |
1643 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1644 | * @dev: the PCIe device reset |
f7bdd12d BK |
1645 | * @state: Reset state to enter into |
1646 | * | |
1647 | * | |
1648 | * Sets the PCI reset state for the device. | |
1649 | */ | |
1650 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1651 | { | |
1652 | return pcibios_set_pcie_reset_state(dev, state); | |
1653 | } | |
b7fe9434 | 1654 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1655 | |
58ff4633 RW |
1656 | /** |
1657 | * pci_check_pme_status - Check if given device has generated PME. | |
1658 | * @dev: Device to check. | |
1659 | * | |
1660 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1661 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1662 | * 'false' otherwise. | |
1663 | */ | |
1664 | bool pci_check_pme_status(struct pci_dev *dev) | |
1665 | { | |
1666 | int pmcsr_pos; | |
1667 | u16 pmcsr; | |
1668 | bool ret = false; | |
1669 | ||
1670 | if (!dev->pm_cap) | |
1671 | return false; | |
1672 | ||
1673 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1674 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1675 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1676 | return false; | |
1677 | ||
1678 | /* Clear PME status. */ | |
1679 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1680 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1681 | /* Disable PME to avoid interrupt flood. */ | |
1682 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1683 | ret = true; | |
1684 | } | |
1685 | ||
1686 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1687 | ||
1688 | return ret; | |
1689 | } | |
1690 | ||
b67ea761 RW |
1691 | /** |
1692 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1693 | * @dev: Device to handle. | |
379021d5 | 1694 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1695 | * |
1696 | * Check if @dev has generated PME and queue a resume request for it in that | |
1697 | * case. | |
1698 | */ | |
379021d5 | 1699 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1700 | { |
379021d5 RW |
1701 | if (pme_poll_reset && dev->pme_poll) |
1702 | dev->pme_poll = false; | |
1703 | ||
c125e96f | 1704 | if (pci_check_pme_status(dev)) { |
c125e96f | 1705 | pci_wakeup_event(dev); |
0f953bf6 | 1706 | pm_request_resume(&dev->dev); |
c125e96f | 1707 | } |
b67ea761 RW |
1708 | return 0; |
1709 | } | |
1710 | ||
1711 | /** | |
1712 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1713 | * @bus: Top bus of the subtree to walk. | |
1714 | */ | |
1715 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1716 | { | |
1717 | if (bus) | |
379021d5 | 1718 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1719 | } |
1720 | ||
448bd857 | 1721 | |
eb9d0fe4 RW |
1722 | /** |
1723 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1724 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1725 | * @state: PCI state from which device will issue PME#. |
1726 | */ | |
e5899e1b | 1727 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1728 | { |
337001b6 | 1729 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1730 | return false; |
1731 | ||
337001b6 | 1732 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1733 | } |
b7fe9434 | 1734 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1735 | |
df17e62e MG |
1736 | static void pci_pme_list_scan(struct work_struct *work) |
1737 | { | |
379021d5 | 1738 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1739 | |
1740 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1741 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1742 | if (pme_dev->dev->pme_poll) { | |
1743 | struct pci_dev *bridge; | |
1744 | ||
1745 | bridge = pme_dev->dev->bus->self; | |
1746 | /* | |
1747 | * If bridge is in low power state, the | |
1748 | * configuration space of subordinate devices | |
1749 | * may be not accessible | |
1750 | */ | |
1751 | if (bridge && bridge->current_state != PCI_D0) | |
1752 | continue; | |
1753 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1754 | } else { | |
1755 | list_del(&pme_dev->list); | |
1756 | kfree(pme_dev); | |
379021d5 | 1757 | } |
df17e62e | 1758 | } |
ce300008 BH |
1759 | if (!list_empty(&pci_pme_list)) |
1760 | schedule_delayed_work(&pci_pme_work, | |
1761 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1762 | mutex_unlock(&pci_pme_list_mutex); |
1763 | } | |
1764 | ||
2cef548a | 1765 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1766 | { |
1767 | u16 pmcsr; | |
1768 | ||
ffaddbe8 | 1769 | if (!dev->pme_support) |
eb9d0fe4 RW |
1770 | return; |
1771 | ||
337001b6 | 1772 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1773 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1774 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1775 | if (!enable) | |
1776 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1777 | ||
337001b6 | 1778 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
1779 | } |
1780 | ||
1781 | /** | |
1782 | * pci_pme_active - enable or disable PCI device's PME# function | |
1783 | * @dev: PCI device to handle. | |
1784 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
1785 | * | |
1786 | * The caller must verify that the device is capable of generating PME# before | |
1787 | * calling this function with @enable equal to 'true'. | |
1788 | */ | |
1789 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
1790 | { | |
1791 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 1792 | |
6e965e0d HY |
1793 | /* |
1794 | * PCI (as opposed to PCIe) PME requires that the device have | |
1795 | * its PME# line hooked up correctly. Not all hardware vendors | |
1796 | * do this, so the PME never gets delivered and the device | |
1797 | * remains asleep. The easiest way around this is to | |
1798 | * periodically walk the list of suspended devices and check | |
1799 | * whether any have their PME flag set. The assumption is that | |
1800 | * we'll wake up often enough anyway that this won't be a huge | |
1801 | * hit, and the power savings from the devices will still be a | |
1802 | * win. | |
1803 | * | |
1804 | * Although PCIe uses in-band PME message instead of PME# line | |
1805 | * to report PME, PME does not work for some PCIe devices in | |
1806 | * reality. For example, there are devices that set their PME | |
1807 | * status bits, but don't really bother to send a PME message; | |
1808 | * there are PCI Express Root Ports that don't bother to | |
1809 | * trigger interrupts when they receive PME messages from the | |
1810 | * devices below. So PME poll is used for PCIe devices too. | |
1811 | */ | |
df17e62e | 1812 | |
379021d5 | 1813 | if (dev->pme_poll) { |
df17e62e MG |
1814 | struct pci_pme_device *pme_dev; |
1815 | if (enable) { | |
1816 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1817 | GFP_KERNEL); | |
0394cb19 BH |
1818 | if (!pme_dev) { |
1819 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1820 | return; | |
1821 | } | |
df17e62e MG |
1822 | pme_dev->dev = dev; |
1823 | mutex_lock(&pci_pme_list_mutex); | |
1824 | list_add(&pme_dev->list, &pci_pme_list); | |
1825 | if (list_is_singular(&pci_pme_list)) | |
1826 | schedule_delayed_work(&pci_pme_work, | |
1827 | msecs_to_jiffies(PME_TIMEOUT)); | |
1828 | mutex_unlock(&pci_pme_list_mutex); | |
1829 | } else { | |
1830 | mutex_lock(&pci_pme_list_mutex); | |
1831 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1832 | if (pme_dev->dev == dev) { | |
1833 | list_del(&pme_dev->list); | |
1834 | kfree(pme_dev); | |
1835 | break; | |
1836 | } | |
1837 | } | |
1838 | mutex_unlock(&pci_pme_list_mutex); | |
1839 | } | |
1840 | } | |
1841 | ||
85b8582d | 1842 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1843 | } |
b7fe9434 | 1844 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1845 | |
1da177e4 | 1846 | /** |
6cbf8214 | 1847 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1848 | * @dev: PCI device affected |
1849 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1850 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1851 | * @enable: True to enable event generation; false to disable |
1852 | * | |
1853 | * This enables the device as a wakeup event source, or disables it. | |
1854 | * When such events involves platform-specific hooks, those hooks are | |
1855 | * called automatically by this routine. | |
1856 | * | |
1857 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1858 | * always require such platform hooks. |
075c1771 | 1859 | * |
eb9d0fe4 RW |
1860 | * RETURN VALUE: |
1861 | * 0 is returned on success | |
1862 | * -EINVAL is returned if device is not supposed to wake up the system | |
1863 | * Error code depending on the platform is returned if both the platform and | |
1864 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1865 | */ |
6cbf8214 RW |
1866 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1867 | bool runtime, bool enable) | |
1da177e4 | 1868 | { |
5bcc2fb4 | 1869 | int ret = 0; |
075c1771 | 1870 | |
6cbf8214 | 1871 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1872 | return -EINVAL; |
1da177e4 | 1873 | |
e80bb09d RW |
1874 | /* Don't do the same thing twice in a row for one device. */ |
1875 | if (!!enable == !!dev->wakeup_prepared) | |
1876 | return 0; | |
1877 | ||
eb9d0fe4 RW |
1878 | /* |
1879 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1880 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1881 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1882 | */ |
1da177e4 | 1883 | |
5bcc2fb4 RW |
1884 | if (enable) { |
1885 | int error; | |
1da177e4 | 1886 | |
5bcc2fb4 RW |
1887 | if (pci_pme_capable(dev, state)) |
1888 | pci_pme_active(dev, true); | |
1889 | else | |
1890 | ret = 1; | |
6cbf8214 RW |
1891 | error = runtime ? platform_pci_run_wake(dev, true) : |
1892 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1893 | if (ret) |
1894 | ret = error; | |
e80bb09d RW |
1895 | if (!ret) |
1896 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1897 | } else { |
6cbf8214 RW |
1898 | if (runtime) |
1899 | platform_pci_run_wake(dev, false); | |
1900 | else | |
1901 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1902 | pci_pme_active(dev, false); |
e80bb09d | 1903 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1904 | } |
1da177e4 | 1905 | |
5bcc2fb4 | 1906 | return ret; |
eb9d0fe4 | 1907 | } |
6cbf8214 | 1908 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1909 | |
0235c4fc RW |
1910 | /** |
1911 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1912 | * @dev: PCI device to prepare | |
1913 | * @enable: True to enable wake-up event generation; false to disable | |
1914 | * | |
1915 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1916 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1917 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1918 | * ordering constraints. | |
1919 | * | |
1920 | * This function only returns error code if the device is not capable of | |
1921 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1922 | * enable wake-up power for it. | |
1923 | */ | |
1924 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1925 | { | |
1926 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1927 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1928 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1929 | } | |
b7fe9434 | 1930 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1931 | |
404cc2d8 | 1932 | /** |
37139074 JB |
1933 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1934 | * @dev: PCI device | |
1935 | * | |
1936 | * Use underlying platform code to find a supported low power state for @dev. | |
1937 | * If the platform can't manage @dev, return the deepest state from which it | |
1938 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1939 | */ |
0b950f0f | 1940 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1941 | { |
1942 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1943 | |
1944 | if (platform_pci_power_manageable(dev)) { | |
1945 | /* | |
1946 | * Call the platform to choose the target state of the device | |
1947 | * and enable wake-up from this state if supported. | |
1948 | */ | |
1949 | pci_power_t state = platform_pci_choose_state(dev); | |
1950 | ||
1951 | switch (state) { | |
1952 | case PCI_POWER_ERROR: | |
1953 | case PCI_UNKNOWN: | |
1954 | break; | |
1955 | case PCI_D1: | |
1956 | case PCI_D2: | |
1957 | if (pci_no_d1d2(dev)) | |
1958 | break; | |
1959 | default: | |
1960 | target_state = state; | |
404cc2d8 | 1961 | } |
d2abdf62 RW |
1962 | } else if (!dev->pm_cap) { |
1963 | target_state = PCI_D0; | |
404cc2d8 RW |
1964 | } else if (device_may_wakeup(&dev->dev)) { |
1965 | /* | |
1966 | * Find the deepest state from which the device can generate | |
1967 | * wake-up events, make it the target state and enable device | |
1968 | * to generate PME#. | |
1969 | */ | |
337001b6 RW |
1970 | if (dev->pme_support) { |
1971 | while (target_state | |
1972 | && !(dev->pme_support & (1 << target_state))) | |
1973 | target_state--; | |
404cc2d8 RW |
1974 | } |
1975 | } | |
1976 | ||
e5899e1b RW |
1977 | return target_state; |
1978 | } | |
1979 | ||
1980 | /** | |
1981 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1982 | * @dev: Device to handle. | |
1983 | * | |
1984 | * Choose the power state appropriate for the device depending on whether | |
1985 | * it can wake up the system and/or is power manageable by the platform | |
1986 | * (PCI_D3hot is the default) and put the device into that state. | |
1987 | */ | |
1988 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1989 | { | |
1990 | pci_power_t target_state = pci_target_state(dev); | |
1991 | int error; | |
1992 | ||
1993 | if (target_state == PCI_POWER_ERROR) | |
1994 | return -EIO; | |
1995 | ||
8efb8c76 | 1996 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1997 | |
404cc2d8 RW |
1998 | error = pci_set_power_state(dev, target_state); |
1999 | ||
2000 | if (error) | |
2001 | pci_enable_wake(dev, target_state, false); | |
2002 | ||
2003 | return error; | |
2004 | } | |
b7fe9434 | 2005 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2006 | |
2007 | /** | |
443bd1c4 | 2008 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
2009 | * @dev: Device to handle. |
2010 | * | |
88393161 | 2011 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2012 | */ |
2013 | int pci_back_from_sleep(struct pci_dev *dev) | |
2014 | { | |
2015 | pci_enable_wake(dev, PCI_D0, false); | |
2016 | return pci_set_power_state(dev, PCI_D0); | |
2017 | } | |
b7fe9434 | 2018 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2019 | |
6cbf8214 RW |
2020 | /** |
2021 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2022 | * @dev: PCI device being suspended. | |
2023 | * | |
2024 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2025 | * power state. | |
2026 | */ | |
2027 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2028 | { | |
2029 | pci_power_t target_state = pci_target_state(dev); | |
2030 | int error; | |
2031 | ||
2032 | if (target_state == PCI_POWER_ERROR) | |
2033 | return -EIO; | |
2034 | ||
448bd857 HY |
2035 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2036 | ||
6cbf8214 RW |
2037 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
2038 | ||
2039 | error = pci_set_power_state(dev, target_state); | |
2040 | ||
448bd857 | 2041 | if (error) { |
6cbf8214 | 2042 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
2043 | dev->runtime_d3cold = false; |
2044 | } | |
6cbf8214 RW |
2045 | |
2046 | return error; | |
2047 | } | |
2048 | ||
b67ea761 RW |
2049 | /** |
2050 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2051 | * @dev: Device to check. | |
2052 | * | |
f7625980 | 2053 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2054 | * (through the platform or using the native PCIe PME) or if the device supports |
2055 | * PME and one of its upstream bridges can generate wake-up events. | |
2056 | */ | |
2057 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2058 | { | |
2059 | struct pci_bus *bus = dev->bus; | |
2060 | ||
2061 | if (device_run_wake(&dev->dev)) | |
2062 | return true; | |
2063 | ||
2064 | if (!dev->pme_support) | |
2065 | return false; | |
2066 | ||
2067 | while (bus->parent) { | |
2068 | struct pci_dev *bridge = bus->self; | |
2069 | ||
2070 | if (device_run_wake(&bridge->dev)) | |
2071 | return true; | |
2072 | ||
2073 | bus = bus->parent; | |
2074 | } | |
2075 | ||
2076 | /* We have reached the root bus. */ | |
2077 | if (bus->bridge) | |
2078 | return device_run_wake(bus->bridge); | |
2079 | ||
2080 | return false; | |
2081 | } | |
2082 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2083 | ||
bac2a909 RW |
2084 | /** |
2085 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2086 | * @pci_dev: Device to check. | |
2087 | * | |
2088 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2089 | * reconfigured due to wakeup settings difference between system and runtime | |
2090 | * suspend and the current power state of it is suitable for the upcoming | |
2091 | * (system) transition. | |
2cef548a RW |
2092 | * |
2093 | * If the device is not configured for system wakeup, disable PME for it before | |
2094 | * returning 'true' to prevent it from waking up the system unnecessarily. | |
bac2a909 RW |
2095 | */ |
2096 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2097 | { | |
2098 | struct device *dev = &pci_dev->dev; | |
2099 | ||
2100 | if (!pm_runtime_suspended(dev) | |
2cef548a | 2101 | || pci_target_state(pci_dev) != pci_dev->current_state |
bac2a909 RW |
2102 | || platform_pci_need_resume(pci_dev)) |
2103 | return false; | |
2104 | ||
2cef548a RW |
2105 | /* |
2106 | * At this point the device is good to go unless it's been configured | |
2107 | * to generate PME at the runtime suspend time, but it is not supposed | |
2108 | * to wake up the system. In that case, simply disable PME for it | |
2109 | * (it will have to be re-enabled on exit from system resume). | |
2110 | * | |
2111 | * If the device's power state is D3cold and the platform check above | |
2112 | * hasn't triggered, the device's configuration is suitable and we don't | |
2113 | * need to manipulate it at all. | |
2114 | */ | |
2115 | spin_lock_irq(&dev->power.lock); | |
2116 | ||
2117 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && | |
2118 | !device_may_wakeup(dev)) | |
2119 | __pci_pme_active(pci_dev, false); | |
2120 | ||
2121 | spin_unlock_irq(&dev->power.lock); | |
2122 | return true; | |
2123 | } | |
2124 | ||
2125 | /** | |
2126 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2127 | * @pci_dev: Device to handle. | |
2128 | * | |
2129 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2130 | * it might have been disabled during the prepare phase of system suspend if | |
2131 | * the device was not configured for system wakeup. | |
2132 | */ | |
2133 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2134 | { | |
2135 | struct device *dev = &pci_dev->dev; | |
2136 | ||
2137 | if (!pci_dev_run_wake(pci_dev)) | |
2138 | return; | |
2139 | ||
2140 | spin_lock_irq(&dev->power.lock); | |
2141 | ||
2142 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2143 | __pci_pme_active(pci_dev, true); | |
2144 | ||
2145 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2146 | } |
2147 | ||
b3c32c4f HY |
2148 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2149 | { | |
2150 | struct device *dev = &pdev->dev; | |
2151 | struct device *parent = dev->parent; | |
2152 | ||
2153 | if (parent) | |
2154 | pm_runtime_get_sync(parent); | |
2155 | pm_runtime_get_noresume(dev); | |
2156 | /* | |
2157 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2158 | * so wait until suspending completes | |
2159 | */ | |
2160 | pm_runtime_barrier(dev); | |
2161 | /* | |
2162 | * Only need to resume devices in D3cold, because config | |
2163 | * registers are still accessible for devices suspended but | |
2164 | * not in D3cold. | |
2165 | */ | |
2166 | if (pdev->current_state == PCI_D3cold) | |
2167 | pm_runtime_resume(dev); | |
2168 | } | |
2169 | ||
2170 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2171 | { | |
2172 | struct device *dev = &pdev->dev; | |
2173 | struct device *parent = dev->parent; | |
2174 | ||
2175 | pm_runtime_put(dev); | |
2176 | if (parent) | |
2177 | pm_runtime_put_sync(parent); | |
2178 | } | |
2179 | ||
9d26d3a8 MW |
2180 | /** |
2181 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2182 | * @bridge: Bridge to check | |
2183 | * | |
2184 | * This function checks if it is possible to move the bridge to D3. | |
2185 | * Currently we only allow D3 for recent enough PCIe ports. | |
2186 | */ | |
2187 | static bool pci_bridge_d3_possible(struct pci_dev *bridge) | |
2188 | { | |
2189 | unsigned int year; | |
2190 | ||
2191 | if (!pci_is_pcie(bridge)) | |
2192 | return false; | |
2193 | ||
2194 | switch (pci_pcie_type(bridge)) { | |
2195 | case PCI_EXP_TYPE_ROOT_PORT: | |
2196 | case PCI_EXP_TYPE_UPSTREAM: | |
2197 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2198 | if (pci_bridge_d3_disable) | |
2199 | return false; | |
2200 | if (pci_bridge_d3_force) | |
2201 | return true; | |
2202 | ||
2203 | /* | |
2204 | * It should be safe to put PCIe ports from 2015 or newer | |
2205 | * to D3. | |
2206 | */ | |
2207 | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && | |
2208 | year >= 2015) { | |
2209 | return true; | |
2210 | } | |
2211 | break; | |
2212 | } | |
2213 | ||
2214 | return false; | |
2215 | } | |
2216 | ||
2217 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2218 | { | |
2219 | bool *d3cold_ok = data; | |
2220 | bool no_d3cold; | |
2221 | ||
2222 | /* | |
2223 | * The device needs to be allowed to go D3cold and if it is wake | |
2224 | * capable to do so from D3cold. | |
2225 | */ | |
2226 | no_d3cold = dev->no_d3cold || !dev->d3cold_allowed || | |
2227 | (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) || | |
2228 | !pci_power_manageable(dev); | |
2229 | ||
2230 | *d3cold_ok = !no_d3cold; | |
2231 | ||
2232 | return no_d3cold; | |
2233 | } | |
2234 | ||
2235 | /* | |
2236 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2237 | * @dev: PCI device which is changed | |
2238 | * @remove: Is the device being removed | |
2239 | * | |
2240 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2241 | * device PM configuration was changed or the device is being removed. The | |
2242 | * change is also propagated upstream. | |
2243 | */ | |
2244 | static void pci_bridge_d3_update(struct pci_dev *dev, bool remove) | |
2245 | { | |
2246 | struct pci_dev *bridge; | |
2247 | bool d3cold_ok = true; | |
2248 | ||
2249 | bridge = pci_upstream_bridge(dev); | |
2250 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2251 | return; | |
2252 | ||
2253 | pci_dev_get(bridge); | |
2254 | /* | |
2255 | * If the device is removed we do not care about its D3cold | |
2256 | * capabilities. | |
2257 | */ | |
2258 | if (!remove) | |
2259 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2260 | ||
2261 | if (d3cold_ok) { | |
2262 | /* | |
2263 | * We need to go through all children to find out if all of | |
2264 | * them can still go to D3cold. | |
2265 | */ | |
2266 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, | |
2267 | &d3cold_ok); | |
2268 | } | |
2269 | ||
2270 | if (bridge->bridge_d3 != d3cold_ok) { | |
2271 | bridge->bridge_d3 = d3cold_ok; | |
2272 | /* Propagate change to upstream bridges */ | |
2273 | pci_bridge_d3_update(bridge, false); | |
2274 | } | |
2275 | ||
2276 | pci_dev_put(bridge); | |
2277 | } | |
2278 | ||
2279 | /** | |
2280 | * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change | |
2281 | * @dev: PCI device that was changed | |
2282 | * | |
2283 | * If a device is added or its PM configuration, such as is it allowed to | |
2284 | * enter D3cold, is changed this function updates upstream bridge PM | |
2285 | * capabilities accordingly. | |
2286 | */ | |
2287 | void pci_bridge_d3_device_changed(struct pci_dev *dev) | |
2288 | { | |
2289 | pci_bridge_d3_update(dev, false); | |
2290 | } | |
2291 | ||
2292 | /** | |
2293 | * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove | |
2294 | * @dev: PCI device being removed | |
2295 | * | |
2296 | * Function updates upstream bridge PM capabilities based on other devices | |
2297 | * still left on the bus. | |
2298 | */ | |
2299 | void pci_bridge_d3_device_removed(struct pci_dev *dev) | |
2300 | { | |
2301 | pci_bridge_d3_update(dev, true); | |
2302 | } | |
2303 | ||
2304 | /** | |
2305 | * pci_d3cold_enable - Enable D3cold for device | |
2306 | * @dev: PCI device to handle | |
2307 | * | |
2308 | * This function can be used in drivers to enable D3cold from the device | |
2309 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2310 | * accordingly. | |
2311 | */ | |
2312 | void pci_d3cold_enable(struct pci_dev *dev) | |
2313 | { | |
2314 | if (dev->no_d3cold) { | |
2315 | dev->no_d3cold = false; | |
2316 | pci_bridge_d3_device_changed(dev); | |
2317 | } | |
2318 | } | |
2319 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2320 | ||
2321 | /** | |
2322 | * pci_d3cold_disable - Disable D3cold for device | |
2323 | * @dev: PCI device to handle | |
2324 | * | |
2325 | * This function can be used in drivers to disable D3cold from the device | |
2326 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2327 | * accordingly. | |
2328 | */ | |
2329 | void pci_d3cold_disable(struct pci_dev *dev) | |
2330 | { | |
2331 | if (!dev->no_d3cold) { | |
2332 | dev->no_d3cold = true; | |
2333 | pci_bridge_d3_device_changed(dev); | |
2334 | } | |
2335 | } | |
2336 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2337 | ||
eb9d0fe4 RW |
2338 | /** |
2339 | * pci_pm_init - Initialize PM functions of given PCI device | |
2340 | * @dev: PCI device to handle. | |
2341 | */ | |
2342 | void pci_pm_init(struct pci_dev *dev) | |
2343 | { | |
2344 | int pm; | |
2345 | u16 pmc; | |
1da177e4 | 2346 | |
bb910a70 | 2347 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2348 | pm_runtime_set_active(&dev->dev); |
2349 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2350 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2351 | dev->wakeup_prepared = false; |
bb910a70 | 2352 | |
337001b6 | 2353 | dev->pm_cap = 0; |
ffaddbe8 | 2354 | dev->pme_support = 0; |
337001b6 | 2355 | |
eb9d0fe4 RW |
2356 | /* find PCI PM capability in list */ |
2357 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2358 | if (!pm) | |
50246dd4 | 2359 | return; |
eb9d0fe4 RW |
2360 | /* Check device's ability to generate PME# */ |
2361 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2362 | |
eb9d0fe4 RW |
2363 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2364 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2365 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2366 | return; |
eb9d0fe4 RW |
2367 | } |
2368 | ||
337001b6 | 2369 | dev->pm_cap = pm; |
1ae861e6 | 2370 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2371 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2372 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2373 | dev->d3cold_allowed = true; |
337001b6 RW |
2374 | |
2375 | dev->d1_support = false; | |
2376 | dev->d2_support = false; | |
2377 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2378 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2379 | dev->d1_support = true; |
c9ed77ee | 2380 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2381 | dev->d2_support = true; |
c9ed77ee BH |
2382 | |
2383 | if (dev->d1_support || dev->d2_support) | |
2384 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2385 | dev->d1_support ? " D1" : "", |
2386 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2387 | } |
2388 | ||
2389 | pmc &= PCI_PM_CAP_PME_MASK; | |
2390 | if (pmc) { | |
10c3d71d BH |
2391 | dev_printk(KERN_DEBUG, &dev->dev, |
2392 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2393 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2394 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2395 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2396 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2397 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2398 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2399 | dev->pme_poll = true; |
eb9d0fe4 RW |
2400 | /* |
2401 | * Make device's PM flags reflect the wake-up capability, but | |
2402 | * let the user space enable it to wake up the system as needed. | |
2403 | */ | |
2404 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2405 | /* Disable the PME# generation functionality */ |
337001b6 | 2406 | pci_pme_active(dev, false); |
eb9d0fe4 | 2407 | } |
1da177e4 LT |
2408 | } |
2409 | ||
938174e5 SS |
2410 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2411 | { | |
92efb1bd | 2412 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2413 | |
2414 | switch (prop) { | |
2415 | case PCI_EA_P_MEM: | |
2416 | case PCI_EA_P_VF_MEM: | |
2417 | flags |= IORESOURCE_MEM; | |
2418 | break; | |
2419 | case PCI_EA_P_MEM_PREFETCH: | |
2420 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2421 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2422 | break; | |
2423 | case PCI_EA_P_IO: | |
2424 | flags |= IORESOURCE_IO; | |
2425 | break; | |
2426 | default: | |
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | return flags; | |
2431 | } | |
2432 | ||
2433 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2434 | u8 prop) | |
2435 | { | |
2436 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2437 | return &dev->resource[bei]; | |
11183991 DD |
2438 | #ifdef CONFIG_PCI_IOV |
2439 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2440 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2441 | return &dev->resource[PCI_IOV_RESOURCES + | |
2442 | bei - PCI_EA_BEI_VF_BAR0]; | |
2443 | #endif | |
938174e5 SS |
2444 | else if (bei == PCI_EA_BEI_ROM) |
2445 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2446 | else | |
2447 | return NULL; | |
2448 | } | |
2449 | ||
2450 | /* Read an Enhanced Allocation (EA) entry */ | |
2451 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2452 | { | |
2453 | struct resource *res; | |
2454 | int ent_size, ent_offset = offset; | |
2455 | resource_size_t start, end; | |
2456 | unsigned long flags; | |
26635112 | 2457 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2458 | u8 prop; |
2459 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2460 | ||
2461 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2462 | ent_offset += 4; | |
2463 | ||
2464 | /* Entry size field indicates DWORDs after 1st */ | |
2465 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2466 | ||
2467 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2468 | goto out; | |
2469 | ||
26635112 BH |
2470 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2471 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2472 | ||
938174e5 SS |
2473 | /* |
2474 | * If the Property is in the reserved range, try the Secondary | |
2475 | * Property instead. | |
2476 | */ | |
2477 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2478 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2479 | if (prop > PCI_EA_P_BRIDGE_IO) |
2480 | goto out; | |
2481 | ||
26635112 | 2482 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2483 | if (!res) { |
26635112 | 2484 | dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2485 | goto out; |
2486 | } | |
2487 | ||
2488 | flags = pci_ea_flags(dev, prop); | |
2489 | if (!flags) { | |
2490 | dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); | |
2491 | goto out; | |
2492 | } | |
2493 | ||
2494 | /* Read Base */ | |
2495 | pci_read_config_dword(dev, ent_offset, &base); | |
2496 | start = (base & PCI_EA_FIELD_MASK); | |
2497 | ent_offset += 4; | |
2498 | ||
2499 | /* Read MaxOffset */ | |
2500 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2501 | ent_offset += 4; | |
2502 | ||
2503 | /* Read Base MSBs (if 64-bit entry) */ | |
2504 | if (base & PCI_EA_IS_64) { | |
2505 | u32 base_upper; | |
2506 | ||
2507 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2508 | ent_offset += 4; | |
2509 | ||
2510 | flags |= IORESOURCE_MEM_64; | |
2511 | ||
2512 | /* entry starts above 32-bit boundary, can't use */ | |
2513 | if (!support_64 && base_upper) | |
2514 | goto out; | |
2515 | ||
2516 | if (support_64) | |
2517 | start |= ((u64)base_upper << 32); | |
2518 | } | |
2519 | ||
2520 | end = start + (max_offset | 0x03); | |
2521 | ||
2522 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
2523 | if (max_offset & PCI_EA_IS_64) { | |
2524 | u32 max_offset_upper; | |
2525 | ||
2526 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
2527 | ent_offset += 4; | |
2528 | ||
2529 | flags |= IORESOURCE_MEM_64; | |
2530 | ||
2531 | /* entry too big, can't use */ | |
2532 | if (!support_64 && max_offset_upper) | |
2533 | goto out; | |
2534 | ||
2535 | if (support_64) | |
2536 | end += ((u64)max_offset_upper << 32); | |
2537 | } | |
2538 | ||
2539 | if (end < start) { | |
2540 | dev_err(&dev->dev, "EA Entry crosses address boundary\n"); | |
2541 | goto out; | |
2542 | } | |
2543 | ||
2544 | if (ent_size != ent_offset - offset) { | |
2545 | dev_err(&dev->dev, | |
2546 | "EA Entry Size (%d) does not match length read (%d)\n", | |
2547 | ent_size, ent_offset - offset); | |
2548 | goto out; | |
2549 | } | |
2550 | ||
2551 | res->name = pci_name(dev); | |
2552 | res->start = start; | |
2553 | res->end = end; | |
2554 | res->flags = flags; | |
597becb4 BH |
2555 | |
2556 | if (bei <= PCI_EA_BEI_BAR5) | |
2557 | dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2558 | bei, res, prop); | |
2559 | else if (bei == PCI_EA_BEI_ROM) | |
2560 | dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2561 | res, prop); | |
2562 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
2563 | dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2564 | bei - PCI_EA_BEI_VF_BAR0, res, prop); | |
2565 | else | |
2566 | dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2567 | bei, res, prop); | |
2568 | ||
938174e5 SS |
2569 | out: |
2570 | return offset + ent_size; | |
2571 | } | |
2572 | ||
dcbb408a | 2573 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
2574 | void pci_ea_init(struct pci_dev *dev) |
2575 | { | |
2576 | int ea; | |
2577 | u8 num_ent; | |
2578 | int offset; | |
2579 | int i; | |
2580 | ||
2581 | /* find PCI EA capability in list */ | |
2582 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
2583 | if (!ea) | |
2584 | return; | |
2585 | ||
2586 | /* determine the number of entries */ | |
2587 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
2588 | &num_ent); | |
2589 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
2590 | ||
2591 | offset = ea + PCI_EA_FIRST_ENT; | |
2592 | ||
2593 | /* Skip DWORD 2 for type 1 functions */ | |
2594 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2595 | offset += 4; | |
2596 | ||
2597 | /* parse each EA entry */ | |
2598 | for (i = 0; i < num_ent; ++i) | |
2599 | offset = pci_ea_read(dev, offset); | |
2600 | } | |
2601 | ||
34a4876e YL |
2602 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2603 | struct pci_cap_saved_state *new_cap) | |
2604 | { | |
2605 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2606 | } | |
2607 | ||
63f4898a | 2608 | /** |
fd0f7f73 AW |
2609 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2610 | * capability registers | |
63f4898a RW |
2611 | * @dev: the PCI device |
2612 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2613 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2614 | * @size: requested size of the buffer |
2615 | */ | |
fd0f7f73 AW |
2616 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2617 | bool extended, unsigned int size) | |
63f4898a RW |
2618 | { |
2619 | int pos; | |
2620 | struct pci_cap_saved_state *save_state; | |
2621 | ||
fd0f7f73 AW |
2622 | if (extended) |
2623 | pos = pci_find_ext_capability(dev, cap); | |
2624 | else | |
2625 | pos = pci_find_capability(dev, cap); | |
2626 | ||
0a1a9b49 | 2627 | if (!pos) |
63f4898a RW |
2628 | return 0; |
2629 | ||
2630 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2631 | if (!save_state) | |
2632 | return -ENOMEM; | |
2633 | ||
24a4742f | 2634 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2635 | save_state->cap.cap_extended = extended; |
24a4742f | 2636 | save_state->cap.size = size; |
63f4898a RW |
2637 | pci_add_saved_cap(dev, save_state); |
2638 | ||
2639 | return 0; | |
2640 | } | |
2641 | ||
fd0f7f73 AW |
2642 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2643 | { | |
2644 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2645 | } | |
2646 | ||
2647 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2648 | { | |
2649 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2650 | } | |
2651 | ||
63f4898a RW |
2652 | /** |
2653 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2654 | * @dev: the PCI device | |
2655 | */ | |
2656 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2657 | { | |
2658 | int error; | |
2659 | ||
89858517 YZ |
2660 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2661 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2662 | if (error) |
2663 | dev_err(&dev->dev, | |
2664 | "unable to preallocate PCI Express save buffer\n"); | |
2665 | ||
2666 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2667 | if (error) | |
2668 | dev_err(&dev->dev, | |
2669 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2670 | |
2671 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2672 | } |
2673 | ||
f796841e YL |
2674 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2675 | { | |
2676 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2677 | struct hlist_node *n; |
f796841e | 2678 | |
b67bfe0d | 2679 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2680 | kfree(tmp); |
2681 | } | |
2682 | ||
58c3a727 | 2683 | /** |
31ab2476 | 2684 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2685 | * @dev: the PCI device |
b0cc6020 YW |
2686 | * |
2687 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2688 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2689 | */ |
31ab2476 | 2690 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2691 | { |
58c3a727 | 2692 | u32 cap; |
8113587c | 2693 | struct pci_dev *bridge; |
58c3a727 | 2694 | |
6748dcc2 | 2695 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2696 | return; |
2697 | ||
8113587c | 2698 | bridge = dev->bus->self; |
cb97ae34 | 2699 | if (!bridge) |
8113587c ZY |
2700 | return; |
2701 | ||
59875ae4 | 2702 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2703 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2704 | return; | |
2705 | ||
b0cc6020 YW |
2706 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2707 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2708 | PCI_EXP_DEVCTL2_ARI); | |
2709 | bridge->ari_enabled = 1; | |
2710 | } else { | |
2711 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2712 | PCI_EXP_DEVCTL2_ARI); | |
2713 | bridge->ari_enabled = 0; | |
2714 | } | |
58c3a727 YZ |
2715 | } |
2716 | ||
5d990b62 CW |
2717 | static int pci_acs_enable; |
2718 | ||
2719 | /** | |
2720 | * pci_request_acs - ask for ACS to be enabled if supported | |
2721 | */ | |
2722 | void pci_request_acs(void) | |
2723 | { | |
2724 | pci_acs_enable = 1; | |
2725 | } | |
2726 | ||
ae21ee65 | 2727 | /** |
2c744244 | 2728 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2729 | * @dev: the PCI device |
2730 | */ | |
c1d61c9b | 2731 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2732 | { |
2733 | int pos; | |
2734 | u16 cap; | |
2735 | u16 ctrl; | |
2736 | ||
ae21ee65 AK |
2737 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2738 | if (!pos) | |
c1d61c9b | 2739 | return; |
ae21ee65 AK |
2740 | |
2741 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2742 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2743 | ||
2744 | /* Source Validation */ | |
2745 | ctrl |= (cap & PCI_ACS_SV); | |
2746 | ||
2747 | /* P2P Request Redirect */ | |
2748 | ctrl |= (cap & PCI_ACS_RR); | |
2749 | ||
2750 | /* P2P Completion Redirect */ | |
2751 | ctrl |= (cap & PCI_ACS_CR); | |
2752 | ||
2753 | /* Upstream Forwarding */ | |
2754 | ctrl |= (cap & PCI_ACS_UF); | |
2755 | ||
2756 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2757 | } |
2758 | ||
2759 | /** | |
2760 | * pci_enable_acs - enable ACS if hardware support it | |
2761 | * @dev: the PCI device | |
2762 | */ | |
2763 | void pci_enable_acs(struct pci_dev *dev) | |
2764 | { | |
2765 | if (!pci_acs_enable) | |
2766 | return; | |
2767 | ||
c1d61c9b | 2768 | if (!pci_dev_specific_enable_acs(dev)) |
2c744244 AW |
2769 | return; |
2770 | ||
c1d61c9b | 2771 | pci_std_enable_acs(dev); |
ae21ee65 AK |
2772 | } |
2773 | ||
0a67119f AW |
2774 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2775 | { | |
2776 | int pos; | |
83db7e0b | 2777 | u16 cap, ctrl; |
0a67119f AW |
2778 | |
2779 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2780 | if (!pos) | |
2781 | return false; | |
2782 | ||
83db7e0b AW |
2783 | /* |
2784 | * Except for egress control, capabilities are either required | |
2785 | * or only required if controllable. Features missing from the | |
2786 | * capability field can therefore be assumed as hard-wired enabled. | |
2787 | */ | |
2788 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2789 | acs_flags &= (cap | PCI_ACS_EC); | |
2790 | ||
0a67119f AW |
2791 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2792 | return (ctrl & acs_flags) == acs_flags; | |
2793 | } | |
2794 | ||
ad805758 AW |
2795 | /** |
2796 | * pci_acs_enabled - test ACS against required flags for a given device | |
2797 | * @pdev: device to test | |
2798 | * @acs_flags: required PCI ACS flags | |
2799 | * | |
2800 | * Return true if the device supports the provided flags. Automatically | |
2801 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2802 | * |
2803 | * Note that this interface checks the effective ACS capabilities of the | |
2804 | * device rather than the actual capabilities. For instance, most single | |
2805 | * function endpoints are not required to support ACS because they have no | |
2806 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2807 | * regardless of whether the device exposes an ACS capability. This makes | |
2808 | * it much easier for callers of this function to ignore the actual type | |
2809 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2810 | */ |
2811 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2812 | { | |
0a67119f | 2813 | int ret; |
ad805758 AW |
2814 | |
2815 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2816 | if (ret >= 0) | |
2817 | return ret > 0; | |
2818 | ||
0a67119f AW |
2819 | /* |
2820 | * Conventional PCI and PCI-X devices never support ACS, either | |
2821 | * effectively or actually. The shared bus topology implies that | |
2822 | * any device on the bus can receive or snoop DMA. | |
2823 | */ | |
ad805758 AW |
2824 | if (!pci_is_pcie(pdev)) |
2825 | return false; | |
2826 | ||
0a67119f AW |
2827 | switch (pci_pcie_type(pdev)) { |
2828 | /* | |
2829 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2830 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2831 | * handle them as we would a non-PCIe device. |
2832 | */ | |
2833 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2834 | /* | |
2835 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2836 | * applicable... must never implement an ACS Extended Capability...". | |
2837 | * This seems arbitrary, but we take a conservative interpretation | |
2838 | * of this statement. | |
2839 | */ | |
2840 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2841 | case PCI_EXP_TYPE_RC_EC: | |
2842 | return false; | |
2843 | /* | |
2844 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2845 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2846 | * regardless of whether they are single- or multi-function devices. | |
2847 | */ | |
2848 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2849 | case PCI_EXP_TYPE_ROOT_PORT: | |
2850 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2851 | /* | |
2852 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2853 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2854 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2855 | * device. The footnote for section 6.12 indicates the specific |
2856 | * PCIe types included here. | |
2857 | */ | |
2858 | case PCI_EXP_TYPE_ENDPOINT: | |
2859 | case PCI_EXP_TYPE_UPSTREAM: | |
2860 | case PCI_EXP_TYPE_LEG_END: | |
2861 | case PCI_EXP_TYPE_RC_END: | |
2862 | if (!pdev->multifunction) | |
2863 | break; | |
2864 | ||
0a67119f | 2865 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2866 | } |
2867 | ||
0a67119f | 2868 | /* |
f7625980 | 2869 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2870 | * to single function devices with the exception of downstream ports. |
2871 | */ | |
ad805758 AW |
2872 | return true; |
2873 | } | |
2874 | ||
2875 | /** | |
2876 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2877 | * @start: starting downstream device | |
2878 | * @end: ending upstream device or NULL to search to the root bus | |
2879 | * @acs_flags: required flags | |
2880 | * | |
2881 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2882 | * any step along the way does not support the required flags, return false. | |
2883 | */ | |
2884 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2885 | struct pci_dev *end, u16 acs_flags) | |
2886 | { | |
2887 | struct pci_dev *pdev, *parent = start; | |
2888 | ||
2889 | do { | |
2890 | pdev = parent; | |
2891 | ||
2892 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2893 | return false; | |
2894 | ||
2895 | if (pci_is_root_bus(pdev->bus)) | |
2896 | return (end == NULL); | |
2897 | ||
2898 | parent = pdev->bus->self; | |
2899 | } while (pdev != end); | |
2900 | ||
2901 | return true; | |
2902 | } | |
2903 | ||
57c2cf71 BH |
2904 | /** |
2905 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2906 | * @dev: the PCI device | |
bb5c2de2 | 2907 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2908 | * |
2909 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2910 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2911 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2912 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2913 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2914 | */ |
3df425f3 | 2915 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2916 | { |
46b952a3 MW |
2917 | int slot; |
2918 | ||
2919 | if (pci_ari_enabled(dev->bus)) | |
2920 | slot = 0; | |
2921 | else | |
2922 | slot = PCI_SLOT(dev->devfn); | |
2923 | ||
2924 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2925 | } |
2926 | ||
3c78bc61 | 2927 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
2928 | { |
2929 | u8 pin; | |
2930 | ||
514d207d | 2931 | pin = dev->pin; |
1da177e4 LT |
2932 | if (!pin) |
2933 | return -1; | |
878f2e50 | 2934 | |
8784fd4d | 2935 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2936 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2937 | dev = dev->bus->self; |
2938 | } | |
2939 | *bridge = dev; | |
2940 | return pin; | |
2941 | } | |
2942 | ||
68feac87 BH |
2943 | /** |
2944 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2945 | * @dev: the PCI device | |
2946 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2947 | * | |
2948 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2949 | * bridges all the way up to a PCI root bus. | |
2950 | */ | |
2951 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2952 | { | |
2953 | u8 pin = *pinp; | |
2954 | ||
1eb39487 | 2955 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2956 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2957 | dev = dev->bus->self; | |
2958 | } | |
2959 | *pinp = pin; | |
2960 | return PCI_SLOT(dev->devfn); | |
2961 | } | |
e6b29dea | 2962 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 2963 | |
1da177e4 LT |
2964 | /** |
2965 | * pci_release_region - Release a PCI bar | |
2966 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2967 | * @bar: BAR to release | |
2968 | * | |
2969 | * Releases the PCI I/O and memory resources previously reserved by a | |
2970 | * successful call to pci_request_region. Call this function only | |
2971 | * after all use of the PCI regions has ceased. | |
2972 | */ | |
2973 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2974 | { | |
9ac7849e TH |
2975 | struct pci_devres *dr; |
2976 | ||
1da177e4 LT |
2977 | if (pci_resource_len(pdev, bar) == 0) |
2978 | return; | |
2979 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2980 | release_region(pci_resource_start(pdev, bar), | |
2981 | pci_resource_len(pdev, bar)); | |
2982 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2983 | release_mem_region(pci_resource_start(pdev, bar), | |
2984 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2985 | |
2986 | dr = find_pci_dr(pdev); | |
2987 | if (dr) | |
2988 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 2989 | } |
b7fe9434 | 2990 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
2991 | |
2992 | /** | |
f5ddcac4 | 2993 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2994 | * @pdev: PCI device whose resources are to be reserved |
2995 | * @bar: BAR to be reserved | |
2996 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2997 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2998 | * |
2999 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3000 | * being reserved by owner @res_name. Do not access any | |
3001 | * address inside the PCI regions unless this call returns | |
3002 | * successfully. | |
3003 | * | |
f5ddcac4 RD |
3004 | * If @exclusive is set, then the region is marked so that userspace |
3005 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3006 | * sysfs MMIO access. |
f5ddcac4 | 3007 | * |
1da177e4 LT |
3008 | * Returns 0 on success, or %EBUSY on error. A warning |
3009 | * message is also printed on failure. | |
3010 | */ | |
3c78bc61 RD |
3011 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3012 | const char *res_name, int exclusive) | |
1da177e4 | 3013 | { |
9ac7849e TH |
3014 | struct pci_devres *dr; |
3015 | ||
1da177e4 LT |
3016 | if (pci_resource_len(pdev, bar) == 0) |
3017 | return 0; | |
f7625980 | 3018 | |
1da177e4 LT |
3019 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3020 | if (!request_region(pci_resource_start(pdev, bar), | |
3021 | pci_resource_len(pdev, bar), res_name)) | |
3022 | goto err_out; | |
3c78bc61 | 3023 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3024 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3025 | pci_resource_len(pdev, bar), res_name, | |
3026 | exclusive)) | |
1da177e4 LT |
3027 | goto err_out; |
3028 | } | |
9ac7849e TH |
3029 | |
3030 | dr = find_pci_dr(pdev); | |
3031 | if (dr) | |
3032 | dr->region_mask |= 1 << bar; | |
3033 | ||
1da177e4 LT |
3034 | return 0; |
3035 | ||
3036 | err_out: | |
c7dabef8 | 3037 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3038 | &pdev->resource[bar]); |
1da177e4 LT |
3039 | return -EBUSY; |
3040 | } | |
3041 | ||
e8de1481 | 3042 | /** |
f5ddcac4 | 3043 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
3044 | * @pdev: PCI device whose resources are to be reserved |
3045 | * @bar: BAR to be reserved | |
f5ddcac4 | 3046 | * @res_name: Name to be associated with resource |
e8de1481 | 3047 | * |
f5ddcac4 | 3048 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
3049 | * being reserved by owner @res_name. Do not access any |
3050 | * address inside the PCI regions unless this call returns | |
3051 | * successfully. | |
3052 | * | |
3053 | * Returns 0 on success, or %EBUSY on error. A warning | |
3054 | * message is also printed on failure. | |
3055 | */ | |
3056 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3057 | { | |
3058 | return __pci_request_region(pdev, bar, res_name, 0); | |
3059 | } | |
b7fe9434 | 3060 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
3061 | |
3062 | /** | |
3063 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
3064 | * @pdev: PCI device whose resources are to be reserved | |
3065 | * @bar: BAR to be reserved | |
3066 | * @res_name: Name to be associated with resource. | |
3067 | * | |
3068 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3069 | * being reserved by owner @res_name. Do not access any | |
3070 | * address inside the PCI regions unless this call returns | |
3071 | * successfully. | |
3072 | * | |
3073 | * Returns 0 on success, or %EBUSY on error. A warning | |
3074 | * message is also printed on failure. | |
3075 | * | |
3076 | * The key difference that _exclusive makes it that userspace is | |
3077 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3078 | * sysfs. |
e8de1481 | 3079 | */ |
3c78bc61 RD |
3080 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
3081 | const char *res_name) | |
e8de1481 AV |
3082 | { |
3083 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
3084 | } | |
b7fe9434 RD |
3085 | EXPORT_SYMBOL(pci_request_region_exclusive); |
3086 | ||
c87deff7 HS |
3087 | /** |
3088 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3089 | * @pdev: PCI device whose resources were previously reserved | |
3090 | * @bars: Bitmask of BARs to be released | |
3091 | * | |
3092 | * Release selected PCI I/O and memory resources previously reserved. | |
3093 | * Call this function only after all use of the PCI regions has ceased. | |
3094 | */ | |
3095 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3096 | { | |
3097 | int i; | |
3098 | ||
3099 | for (i = 0; i < 6; i++) | |
3100 | if (bars & (1 << i)) | |
3101 | pci_release_region(pdev, i); | |
3102 | } | |
b7fe9434 | 3103 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3104 | |
9738abed | 3105 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3106 | const char *res_name, int excl) |
c87deff7 HS |
3107 | { |
3108 | int i; | |
3109 | ||
3110 | for (i = 0; i < 6; i++) | |
3111 | if (bars & (1 << i)) | |
e8de1481 | 3112 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3113 | goto err_out; |
3114 | return 0; | |
3115 | ||
3116 | err_out: | |
3c78bc61 | 3117 | while (--i >= 0) |
c87deff7 HS |
3118 | if (bars & (1 << i)) |
3119 | pci_release_region(pdev, i); | |
3120 | ||
3121 | return -EBUSY; | |
3122 | } | |
1da177e4 | 3123 | |
e8de1481 AV |
3124 | |
3125 | /** | |
3126 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3127 | * @pdev: PCI device whose resources are to be reserved | |
3128 | * @bars: Bitmask of BARs to be requested | |
3129 | * @res_name: Name to be associated with resource | |
3130 | */ | |
3131 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3132 | const char *res_name) | |
3133 | { | |
3134 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3135 | } | |
b7fe9434 | 3136 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3137 | |
3c78bc61 RD |
3138 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3139 | const char *res_name) | |
e8de1481 AV |
3140 | { |
3141 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3142 | IORESOURCE_EXCLUSIVE); | |
3143 | } | |
b7fe9434 | 3144 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3145 | |
1da177e4 LT |
3146 | /** |
3147 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
3148 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
3149 | * | |
3150 | * Releases all PCI I/O and memory resources previously reserved by a | |
3151 | * successful call to pci_request_regions. Call this function only | |
3152 | * after all use of the PCI regions has ceased. | |
3153 | */ | |
3154 | ||
3155 | void pci_release_regions(struct pci_dev *pdev) | |
3156 | { | |
c87deff7 | 3157 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 3158 | } |
b7fe9434 | 3159 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3160 | |
3161 | /** | |
3162 | * pci_request_regions - Reserved PCI I/O and memory resources | |
3163 | * @pdev: PCI device whose resources are to be reserved | |
3164 | * @res_name: Name to be associated with resource. | |
3165 | * | |
3166 | * Mark all PCI regions associated with PCI device @pdev as | |
3167 | * being reserved by owner @res_name. Do not access any | |
3168 | * address inside the PCI regions unless this call returns | |
3169 | * successfully. | |
3170 | * | |
3171 | * Returns 0 on success, or %EBUSY on error. A warning | |
3172 | * message is also printed on failure. | |
3173 | */ | |
3c990e92 | 3174 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3175 | { |
c87deff7 | 3176 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 3177 | } |
b7fe9434 | 3178 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3179 | |
e8de1481 AV |
3180 | /** |
3181 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
3182 | * @pdev: PCI device whose resources are to be reserved | |
3183 | * @res_name: Name to be associated with resource. | |
3184 | * | |
3185 | * Mark all PCI regions associated with PCI device @pdev as | |
3186 | * being reserved by owner @res_name. Do not access any | |
3187 | * address inside the PCI regions unless this call returns | |
3188 | * successfully. | |
3189 | * | |
3190 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 3191 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
3192 | * |
3193 | * Returns 0 on success, or %EBUSY on error. A warning | |
3194 | * message is also printed on failure. | |
3195 | */ | |
3196 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3197 | { | |
3198 | return pci_request_selected_regions_exclusive(pdev, | |
3199 | ((1 << 6) - 1), res_name); | |
3200 | } | |
b7fe9434 | 3201 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3202 | |
c5076cfe TN |
3203 | #ifdef PCI_IOBASE |
3204 | struct io_range { | |
3205 | struct list_head list; | |
3206 | phys_addr_t start; | |
3207 | resource_size_t size; | |
3208 | }; | |
3209 | ||
3210 | static LIST_HEAD(io_range_list); | |
3211 | static DEFINE_SPINLOCK(io_range_lock); | |
3212 | #endif | |
3213 | ||
3214 | /* | |
3215 | * Record the PCI IO range (expressed as CPU physical address + size). | |
3216 | * Return a negative value if an error has occured, zero otherwise | |
3217 | */ | |
3218 | int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) | |
3219 | { | |
3220 | int err = 0; | |
3221 | ||
3222 | #ifdef PCI_IOBASE | |
3223 | struct io_range *range; | |
3224 | resource_size_t allocated_size = 0; | |
3225 | ||
3226 | /* check if the range hasn't been previously recorded */ | |
3227 | spin_lock(&io_range_lock); | |
3228 | list_for_each_entry(range, &io_range_list, list) { | |
3229 | if (addr >= range->start && addr + size <= range->start + size) { | |
3230 | /* range already registered, bail out */ | |
3231 | goto end_register; | |
3232 | } | |
3233 | allocated_size += range->size; | |
3234 | } | |
3235 | ||
3236 | /* range not registed yet, check for available space */ | |
3237 | if (allocated_size + size - 1 > IO_SPACE_LIMIT) { | |
3238 | /* if it's too big check if 64K space can be reserved */ | |
3239 | if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { | |
3240 | err = -E2BIG; | |
3241 | goto end_register; | |
3242 | } | |
3243 | ||
3244 | size = SZ_64K; | |
3245 | pr_warn("Requested IO range too big, new size set to 64K\n"); | |
3246 | } | |
3247 | ||
3248 | /* add the range to the list */ | |
3249 | range = kzalloc(sizeof(*range), GFP_ATOMIC); | |
3250 | if (!range) { | |
3251 | err = -ENOMEM; | |
3252 | goto end_register; | |
3253 | } | |
3254 | ||
3255 | range->start = addr; | |
3256 | range->size = size; | |
3257 | ||
3258 | list_add_tail(&range->list, &io_range_list); | |
3259 | ||
3260 | end_register: | |
3261 | spin_unlock(&io_range_lock); | |
3262 | #endif | |
3263 | ||
3264 | return err; | |
3265 | } | |
3266 | ||
3267 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3268 | { | |
3269 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3270 | ||
3271 | #ifdef PCI_IOBASE | |
3272 | struct io_range *range; | |
3273 | resource_size_t allocated_size = 0; | |
3274 | ||
3275 | if (pio > IO_SPACE_LIMIT) | |
3276 | return address; | |
3277 | ||
3278 | spin_lock(&io_range_lock); | |
3279 | list_for_each_entry(range, &io_range_list, list) { | |
3280 | if (pio >= allocated_size && pio < allocated_size + range->size) { | |
3281 | address = range->start + pio - allocated_size; | |
3282 | break; | |
3283 | } | |
3284 | allocated_size += range->size; | |
3285 | } | |
3286 | spin_unlock(&io_range_lock); | |
3287 | #endif | |
3288 | ||
3289 | return address; | |
3290 | } | |
3291 | ||
3292 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3293 | { | |
3294 | #ifdef PCI_IOBASE | |
3295 | struct io_range *res; | |
3296 | resource_size_t offset = 0; | |
3297 | unsigned long addr = -1; | |
3298 | ||
3299 | spin_lock(&io_range_lock); | |
3300 | list_for_each_entry(res, &io_range_list, list) { | |
3301 | if (address >= res->start && address < res->start + res->size) { | |
3302 | addr = address - res->start + offset; | |
3303 | break; | |
3304 | } | |
3305 | offset += res->size; | |
3306 | } | |
3307 | spin_unlock(&io_range_lock); | |
3308 | ||
3309 | return addr; | |
3310 | #else | |
3311 | if (address > IO_SPACE_LIMIT) | |
3312 | return (unsigned long)-1; | |
3313 | ||
3314 | return (unsigned long) address; | |
3315 | #endif | |
3316 | } | |
3317 | ||
8b921acf LD |
3318 | /** |
3319 | * pci_remap_iospace - Remap the memory mapped I/O space | |
3320 | * @res: Resource describing the I/O space | |
3321 | * @phys_addr: physical address of range to be mapped | |
3322 | * | |
3323 | * Remap the memory mapped I/O space described by the @res | |
3324 | * and the CPU physical address @phys_addr into virtual address space. | |
3325 | * Only architectures that have memory mapped IO functions defined | |
3326 | * (and the PCI_IOBASE value defined) should call this function. | |
3327 | */ | |
3328 | int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) | |
3329 | { | |
3330 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3331 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3332 | ||
3333 | if (!(res->flags & IORESOURCE_IO)) | |
3334 | return -EINVAL; | |
3335 | ||
3336 | if (res->end > IO_SPACE_LIMIT) | |
3337 | return -EINVAL; | |
3338 | ||
3339 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3340 | pgprot_device(PAGE_KERNEL)); | |
3341 | #else | |
3342 | /* this architecture does not have memory mapped I/O space, | |
3343 | so this function should never be called */ | |
3344 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
3345 | return -ENODEV; | |
3346 | #endif | |
3347 | } | |
3348 | ||
4d3f1384 SK |
3349 | /** |
3350 | * pci_unmap_iospace - Unmap the memory mapped I/O space | |
3351 | * @res: resource to be unmapped | |
3352 | * | |
3353 | * Unmap the CPU virtual address @res from virtual address space. | |
3354 | * Only architectures that have memory mapped IO functions defined | |
3355 | * (and the PCI_IOBASE value defined) should call this function. | |
3356 | */ | |
3357 | void pci_unmap_iospace(struct resource *res) | |
3358 | { | |
3359 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3360 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3361 | ||
3362 | unmap_kernel_range(vaddr, resource_size(res)); | |
3363 | #endif | |
3364 | } | |
3365 | ||
6a479079 BH |
3366 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
3367 | { | |
3368 | u16 old_cmd, cmd; | |
3369 | ||
3370 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
3371 | if (enable) | |
3372 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
3373 | else | |
3374 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
3375 | if (cmd != old_cmd) { | |
3376 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
3377 | enable ? "enabling" : "disabling"); | |
3378 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3379 | } | |
3380 | dev->is_busmaster = enable; | |
3381 | } | |
e8de1481 | 3382 | |
2b6f2c35 MS |
3383 | /** |
3384 | * pcibios_setup - process "pci=" kernel boot arguments | |
3385 | * @str: string used to pass in "pci=" kernel boot arguments | |
3386 | * | |
3387 | * Process kernel boot arguments. This is the default implementation. | |
3388 | * Architecture specific implementations can override this as necessary. | |
3389 | */ | |
3390 | char * __weak __init pcibios_setup(char *str) | |
3391 | { | |
3392 | return str; | |
3393 | } | |
3394 | ||
96c55900 MS |
3395 | /** |
3396 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
3397 | * @dev: the PCI device to enable | |
3398 | * | |
3399 | * Enables PCI bus-mastering for the device. This is the default | |
3400 | * implementation. Architecture specific implementations can override | |
3401 | * this if necessary. | |
3402 | */ | |
3403 | void __weak pcibios_set_master(struct pci_dev *dev) | |
3404 | { | |
3405 | u8 lat; | |
3406 | ||
f676678f MS |
3407 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
3408 | if (pci_is_pcie(dev)) | |
3409 | return; | |
3410 | ||
96c55900 MS |
3411 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
3412 | if (lat < 16) | |
3413 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
3414 | else if (lat > pcibios_max_latency) | |
3415 | lat = pcibios_max_latency; | |
3416 | else | |
3417 | return; | |
a006482b | 3418 | |
96c55900 MS |
3419 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
3420 | } | |
3421 | ||
1da177e4 LT |
3422 | /** |
3423 | * pci_set_master - enables bus-mastering for device dev | |
3424 | * @dev: the PCI device to enable | |
3425 | * | |
3426 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
3427 | * to do the needed arch specific settings. | |
3428 | */ | |
6a479079 | 3429 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 3430 | { |
6a479079 | 3431 | __pci_set_master(dev, true); |
1da177e4 LT |
3432 | pcibios_set_master(dev); |
3433 | } | |
b7fe9434 | 3434 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 3435 | |
6a479079 BH |
3436 | /** |
3437 | * pci_clear_master - disables bus-mastering for device dev | |
3438 | * @dev: the PCI device to disable | |
3439 | */ | |
3440 | void pci_clear_master(struct pci_dev *dev) | |
3441 | { | |
3442 | __pci_set_master(dev, false); | |
3443 | } | |
b7fe9434 | 3444 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 3445 | |
1da177e4 | 3446 | /** |
edb2d97e MW |
3447 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
3448 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 3449 | * |
edb2d97e MW |
3450 | * Helper function for pci_set_mwi. |
3451 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
3452 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
3453 | * | |
3454 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3455 | */ | |
15ea76d4 | 3456 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
3457 | { |
3458 | u8 cacheline_size; | |
3459 | ||
3460 | if (!pci_cache_line_size) | |
15ea76d4 | 3461 | return -EINVAL; |
1da177e4 LT |
3462 | |
3463 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
3464 | equal to or multiple of the right value. */ | |
3465 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3466 | if (cacheline_size >= pci_cache_line_size && | |
3467 | (cacheline_size % pci_cache_line_size) == 0) | |
3468 | return 0; | |
3469 | ||
3470 | /* Write the correct value. */ | |
3471 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
3472 | /* Read it back. */ | |
3473 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3474 | if (cacheline_size == pci_cache_line_size) | |
3475 | return 0; | |
3476 | ||
227f0647 RD |
3477 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", |
3478 | pci_cache_line_size << 2); | |
1da177e4 LT |
3479 | |
3480 | return -EINVAL; | |
3481 | } | |
15ea76d4 TH |
3482 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
3483 | ||
1da177e4 LT |
3484 | /** |
3485 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
3486 | * @dev: the PCI device for which MWI is enabled | |
3487 | * | |
694625c0 | 3488 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
3489 | * |
3490 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3491 | */ | |
3c78bc61 | 3492 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 3493 | { |
b7fe9434 RD |
3494 | #ifdef PCI_DISABLE_MWI |
3495 | return 0; | |
3496 | #else | |
1da177e4 LT |
3497 | int rc; |
3498 | u16 cmd; | |
3499 | ||
edb2d97e | 3500 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
3501 | if (rc) |
3502 | return rc; | |
3503 | ||
3504 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 3505 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
80ccba11 | 3506 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
3507 | cmd |= PCI_COMMAND_INVALIDATE; |
3508 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3509 | } | |
1da177e4 | 3510 | return 0; |
b7fe9434 | 3511 | #endif |
1da177e4 | 3512 | } |
b7fe9434 | 3513 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 3514 | |
694625c0 RD |
3515 | /** |
3516 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
3517 | * @dev: the PCI device for which MWI is enabled | |
3518 | * | |
3519 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
3520 | * Callers are not required to check the return value. | |
3521 | * | |
3522 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3523 | */ | |
3524 | int pci_try_set_mwi(struct pci_dev *dev) | |
3525 | { | |
b7fe9434 RD |
3526 | #ifdef PCI_DISABLE_MWI |
3527 | return 0; | |
3528 | #else | |
3529 | return pci_set_mwi(dev); | |
3530 | #endif | |
694625c0 | 3531 | } |
b7fe9434 | 3532 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 3533 | |
1da177e4 LT |
3534 | /** |
3535 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
3536 | * @dev: the PCI device to disable | |
3537 | * | |
3538 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
3539 | */ | |
3c78bc61 | 3540 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 3541 | { |
b7fe9434 | 3542 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
3543 | u16 cmd; |
3544 | ||
3545 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3546 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
3547 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
3548 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3549 | } | |
b7fe9434 | 3550 | #endif |
1da177e4 | 3551 | } |
b7fe9434 | 3552 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 3553 | |
a04ce0ff BR |
3554 | /** |
3555 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
3556 | * @pdev: the PCI device to operate on |
3557 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
3558 | * |
3559 | * Enables/disables PCI INTx for device dev | |
3560 | */ | |
3c78bc61 | 3561 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
3562 | { |
3563 | u16 pci_command, new; | |
3564 | ||
3565 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
3566 | ||
3c78bc61 | 3567 | if (enable) |
a04ce0ff | 3568 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 3569 | else |
a04ce0ff | 3570 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
3571 | |
3572 | if (new != pci_command) { | |
9ac7849e TH |
3573 | struct pci_devres *dr; |
3574 | ||
2fd9d74b | 3575 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
3576 | |
3577 | dr = find_pci_dr(pdev); | |
3578 | if (dr && !dr->restore_intx) { | |
3579 | dr->restore_intx = 1; | |
3580 | dr->orig_intx = !enable; | |
3581 | } | |
a04ce0ff BR |
3582 | } |
3583 | } | |
b7fe9434 | 3584 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 3585 | |
a2e27787 JK |
3586 | /** |
3587 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 3588 | * @dev: the PCI device to operate on |
a2e27787 JK |
3589 | * |
3590 | * Check if the device dev support INTx masking via the config space | |
3591 | * command word. | |
3592 | */ | |
3593 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
3594 | { | |
3595 | bool mask_supported = false; | |
3596 | u16 orig, new; | |
3597 | ||
fbebb9fd BH |
3598 | if (dev->broken_intx_masking) |
3599 | return false; | |
3600 | ||
a2e27787 JK |
3601 | pci_cfg_access_lock(dev); |
3602 | ||
3603 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
3604 | pci_write_config_word(dev, PCI_COMMAND, | |
3605 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
3606 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
3607 | ||
3608 | /* | |
3609 | * There's no way to protect against hardware bugs or detect them | |
3610 | * reliably, but as long as we know what the value should be, let's | |
3611 | * go ahead and check it. | |
3612 | */ | |
3613 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
227f0647 RD |
3614 | dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", |
3615 | orig, new); | |
a2e27787 JK |
3616 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { |
3617 | mask_supported = true; | |
3618 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
3619 | } | |
3620 | ||
3621 | pci_cfg_access_unlock(dev); | |
3622 | return mask_supported; | |
3623 | } | |
3624 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
3625 | ||
3626 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
3627 | { | |
3628 | struct pci_bus *bus = dev->bus; | |
3629 | bool mask_updated = true; | |
3630 | u32 cmd_status_dword; | |
3631 | u16 origcmd, newcmd; | |
3632 | unsigned long flags; | |
3633 | bool irq_pending; | |
3634 | ||
3635 | /* | |
3636 | * We do a single dword read to retrieve both command and status. | |
3637 | * Document assumptions that make this possible. | |
3638 | */ | |
3639 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3640 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3641 | ||
3642 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3643 | ||
3644 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3645 | ||
3646 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3647 | ||
3648 | /* | |
3649 | * Check interrupt status register to see whether our device | |
3650 | * triggered the interrupt (when masking) or the next IRQ is | |
3651 | * already pending (when unmasking). | |
3652 | */ | |
3653 | if (mask != irq_pending) { | |
3654 | mask_updated = false; | |
3655 | goto done; | |
3656 | } | |
3657 | ||
3658 | origcmd = cmd_status_dword; | |
3659 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3660 | if (mask) | |
3661 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3662 | if (newcmd != origcmd) | |
3663 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3664 | ||
3665 | done: | |
3666 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3667 | ||
3668 | return mask_updated; | |
3669 | } | |
3670 | ||
3671 | /** | |
3672 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3673 | * @dev: the PCI device to operate on |
a2e27787 JK |
3674 | * |
3675 | * Check if the device dev has its INTx line asserted, mask it and | |
3676 | * return true in that case. False is returned if not interrupt was | |
3677 | * pending. | |
3678 | */ | |
3679 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3680 | { | |
3681 | return pci_check_and_set_intx_mask(dev, true); | |
3682 | } | |
3683 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3684 | ||
3685 | /** | |
ebd50b93 | 3686 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3687 | * @dev: the PCI device to operate on |
a2e27787 JK |
3688 | * |
3689 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3690 | * and return true. False is returned and the mask remains active if | |
3691 | * there was still an interrupt pending. | |
3692 | */ | |
3693 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3694 | { | |
3695 | return pci_check_and_set_intx_mask(dev, false); | |
3696 | } | |
3697 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3698 | ||
3775a209 CL |
3699 | /** |
3700 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3701 | * @dev: the PCI device to operate on | |
3702 | * | |
3703 | * Return 0 if transaction is pending 1 otherwise. | |
3704 | */ | |
3705 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3706 | { |
157e876f AW |
3707 | if (!pci_is_pcie(dev)) |
3708 | return 1; | |
8c1c699f | 3709 | |
d0b4cc4e GS |
3710 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
3711 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
3712 | } |
3713 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3714 | ||
5adecf81 AW |
3715 | /* |
3716 | * We should only need to wait 100ms after FLR, but some devices take longer. | |
3717 | * Wait for up to 1000ms for config space to return something other than -1. | |
3718 | * Intel IGD requires this when an LCD panel is attached. We read the 2nd | |
3719 | * dword because VFs don't implement the 1st dword. | |
3720 | */ | |
3721 | static void pci_flr_wait(struct pci_dev *dev) | |
3722 | { | |
3723 | int i = 0; | |
3724 | u32 id; | |
3725 | ||
3726 | do { | |
3727 | msleep(100); | |
3728 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
3729 | } while (i++ < 10 && id == ~0); | |
3730 | ||
3731 | if (id == ~0) | |
3732 | dev_warn(&dev->dev, "Failed to return from FLR\n"); | |
3733 | else if (i > 1) | |
3734 | dev_info(&dev->dev, "Required additional %dms to return from FLR\n", | |
3735 | (i - 1) * 100); | |
3736 | } | |
3737 | ||
3775a209 CL |
3738 | static int pcie_flr(struct pci_dev *dev, int probe) |
3739 | { | |
3740 | u32 cap; | |
3741 | ||
3742 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3743 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3744 | return -ENOTTY; | |
3745 | ||
3746 | if (probe) | |
3747 | return 0; | |
3748 | ||
3749 | if (!pci_wait_for_pending_transaction(dev)) | |
bb383e28 | 3750 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 3751 | |
59875ae4 | 3752 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
5adecf81 | 3753 | pci_flr_wait(dev); |
8dd7f803 SY |
3754 | return 0; |
3755 | } | |
d91cdc74 | 3756 | |
8c1c699f | 3757 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3758 | { |
8c1c699f | 3759 | int pos; |
1ca88797 SY |
3760 | u8 cap; |
3761 | ||
8c1c699f YZ |
3762 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3763 | if (!pos) | |
1ca88797 | 3764 | return -ENOTTY; |
8c1c699f YZ |
3765 | |
3766 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3767 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3768 | return -ENOTTY; | |
3769 | ||
3770 | if (probe) | |
3771 | return 0; | |
3772 | ||
d066c946 AW |
3773 | /* |
3774 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
3775 | * is used, so we use the conrol offset rather than status and shift | |
3776 | * the test bit to match. | |
3777 | */ | |
bb383e28 | 3778 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 3779 | PCI_AF_STATUS_TP << 8)) |
bb383e28 | 3780 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 3781 | |
8c1c699f | 3782 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
5adecf81 | 3783 | pci_flr_wait(dev); |
1ca88797 SY |
3784 | return 0; |
3785 | } | |
3786 | ||
83d74e03 RW |
3787 | /** |
3788 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3789 | * @dev: Device to reset. | |
3790 | * @probe: If set, only check if the device can be reset this way. | |
3791 | * | |
3792 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3793 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3794 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3795 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3796 | * | |
3797 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3798 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3799 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3800 | * Moreover, only devices in D0 can be reset by this function. |
3801 | */ | |
f85876ba | 3802 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3803 | { |
f85876ba YZ |
3804 | u16 csr; |
3805 | ||
51e53738 | 3806 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 3807 | return -ENOTTY; |
d91cdc74 | 3808 | |
f85876ba YZ |
3809 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3810 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3811 | return -ENOTTY; | |
d91cdc74 | 3812 | |
f85876ba YZ |
3813 | if (probe) |
3814 | return 0; | |
1ca88797 | 3815 | |
f85876ba YZ |
3816 | if (dev->current_state != PCI_D0) |
3817 | return -EINVAL; | |
3818 | ||
3819 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3820 | csr |= PCI_D3hot; | |
3821 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3822 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3823 | |
3824 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3825 | csr |= PCI_D0; | |
3826 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3827 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3828 | |
3829 | return 0; | |
3830 | } | |
3831 | ||
9e33002f | 3832 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
3833 | { |
3834 | u16 ctrl; | |
64e8674f AW |
3835 | |
3836 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3837 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3838 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3839 | /* |
3840 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3841 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3842 | */ |
3843 | msleep(2); | |
64e8674f AW |
3844 | |
3845 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3846 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3847 | |
3848 | /* | |
3849 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3850 | * Assuming a minimum 33MHz clock this results in a 1s | |
3851 | * delay before we can consider subordinate devices to | |
3852 | * be re-initialized. PCIe has some ways to shorten this, | |
3853 | * but we don't make use of them yet. | |
3854 | */ | |
3855 | ssleep(1); | |
64e8674f | 3856 | } |
d92a208d | 3857 | |
9e33002f GS |
3858 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
3859 | { | |
3860 | pci_reset_secondary_bus(dev); | |
3861 | } | |
3862 | ||
d92a208d GS |
3863 | /** |
3864 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3865 | * @dev: Bridge device | |
3866 | * | |
3867 | * Use the bridge control register to assert reset on the secondary bus. | |
3868 | * Devices on the secondary bus are left in power-on state. | |
3869 | */ | |
3870 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
3871 | { | |
3872 | pcibios_reset_secondary_bus(dev); | |
3873 | } | |
64e8674f AW |
3874 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |
3875 | ||
3876 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3877 | { | |
c12ff1df YZ |
3878 | struct pci_dev *pdev; |
3879 | ||
f331a859 AW |
3880 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
3881 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
3882 | return -ENOTTY; |
3883 | ||
3884 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3885 | if (pdev != dev) | |
3886 | return -ENOTTY; | |
3887 | ||
3888 | if (probe) | |
3889 | return 0; | |
3890 | ||
64e8674f | 3891 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3892 | |
3893 | return 0; | |
3894 | } | |
3895 | ||
608c3881 AW |
3896 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3897 | { | |
3898 | int rc = -ENOTTY; | |
3899 | ||
3900 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3901 | return rc; | |
3902 | ||
3903 | if (hotplug->ops->reset_slot) | |
3904 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3905 | ||
3906 | module_put(hotplug->ops->owner); | |
3907 | ||
3908 | return rc; | |
3909 | } | |
3910 | ||
3911 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3912 | { | |
3913 | struct pci_dev *pdev; | |
3914 | ||
f331a859 AW |
3915 | if (dev->subordinate || !dev->slot || |
3916 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
3917 | return -ENOTTY; |
3918 | ||
3919 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3920 | if (pdev != dev && pdev->slot == dev->slot) | |
3921 | return -ENOTTY; | |
3922 | ||
3923 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3924 | } | |
3925 | ||
977f857c | 3926 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3927 | { |
8c1c699f YZ |
3928 | int rc; |
3929 | ||
3930 | might_sleep(); | |
3931 | ||
b9c3b266 DC |
3932 | rc = pci_dev_specific_reset(dev, probe); |
3933 | if (rc != -ENOTTY) | |
3934 | goto done; | |
3935 | ||
8c1c699f YZ |
3936 | rc = pcie_flr(dev, probe); |
3937 | if (rc != -ENOTTY) | |
3938 | goto done; | |
d91cdc74 | 3939 | |
8c1c699f | 3940 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3941 | if (rc != -ENOTTY) |
3942 | goto done; | |
3943 | ||
3944 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3945 | if (rc != -ENOTTY) |
3946 | goto done; | |
3947 | ||
608c3881 AW |
3948 | rc = pci_dev_reset_slot_function(dev, probe); |
3949 | if (rc != -ENOTTY) | |
3950 | goto done; | |
3951 | ||
c12ff1df | 3952 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3953 | done: |
977f857c KRW |
3954 | return rc; |
3955 | } | |
3956 | ||
77cb985a AW |
3957 | static void pci_dev_lock(struct pci_dev *dev) |
3958 | { | |
3959 | pci_cfg_access_lock(dev); | |
3960 | /* block PM suspend, driver probe, etc. */ | |
3961 | device_lock(&dev->dev); | |
3962 | } | |
3963 | ||
61cf16d8 AW |
3964 | /* Return 1 on successful lock, 0 on contention */ |
3965 | static int pci_dev_trylock(struct pci_dev *dev) | |
3966 | { | |
3967 | if (pci_cfg_access_trylock(dev)) { | |
3968 | if (device_trylock(&dev->dev)) | |
3969 | return 1; | |
3970 | pci_cfg_access_unlock(dev); | |
3971 | } | |
3972 | ||
3973 | return 0; | |
3974 | } | |
3975 | ||
77cb985a AW |
3976 | static void pci_dev_unlock(struct pci_dev *dev) |
3977 | { | |
3978 | device_unlock(&dev->dev); | |
3979 | pci_cfg_access_unlock(dev); | |
3980 | } | |
3981 | ||
3ebe7f9f KB |
3982 | /** |
3983 | * pci_reset_notify - notify device driver of reset | |
3984 | * @dev: device to be notified of reset | |
3985 | * @prepare: 'true' if device is about to be reset; 'false' if reset attempt | |
3986 | * completed | |
3987 | * | |
3988 | * Must be called prior to device access being disabled and after device | |
3989 | * access is restored. | |
3990 | */ | |
3991 | static void pci_reset_notify(struct pci_dev *dev, bool prepare) | |
3992 | { | |
3993 | const struct pci_error_handlers *err_handler = | |
3994 | dev->driver ? dev->driver->err_handler : NULL; | |
3995 | if (err_handler && err_handler->reset_notify) | |
3996 | err_handler->reset_notify(dev, prepare); | |
3997 | } | |
3998 | ||
77cb985a AW |
3999 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
4000 | { | |
3ebe7f9f KB |
4001 | pci_reset_notify(dev, true); |
4002 | ||
a6cbaade AW |
4003 | /* |
4004 | * Wake-up device prior to save. PM registers default to D0 after | |
4005 | * reset and a simple register restore doesn't reliably return | |
4006 | * to a non-D0 state anyway. | |
4007 | */ | |
4008 | pci_set_power_state(dev, PCI_D0); | |
4009 | ||
77cb985a AW |
4010 | pci_save_state(dev); |
4011 | /* | |
4012 | * Disable the device by clearing the Command register, except for | |
4013 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4014 | * BARs, but also prevents the device from being Bus Master, preventing | |
4015 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4016 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4017 | */ | |
4018 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4019 | } | |
4020 | ||
4021 | static void pci_dev_restore(struct pci_dev *dev) | |
4022 | { | |
4023 | pci_restore_state(dev); | |
3ebe7f9f | 4024 | pci_reset_notify(dev, false); |
77cb985a AW |
4025 | } |
4026 | ||
977f857c KRW |
4027 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
4028 | { | |
4029 | int rc; | |
4030 | ||
77cb985a AW |
4031 | if (!probe) |
4032 | pci_dev_lock(dev); | |
977f857c KRW |
4033 | |
4034 | rc = __pci_dev_reset(dev, probe); | |
4035 | ||
77cb985a AW |
4036 | if (!probe) |
4037 | pci_dev_unlock(dev); | |
4038 | ||
8c1c699f | 4039 | return rc; |
d91cdc74 | 4040 | } |
3ebe7f9f | 4041 | |
d91cdc74 | 4042 | /** |
8c1c699f YZ |
4043 | * __pci_reset_function - reset a PCI device function |
4044 | * @dev: PCI device to reset | |
d91cdc74 SY |
4045 | * |
4046 | * Some devices allow an individual function to be reset without affecting | |
4047 | * other functions in the same device. The PCI device must be responsive | |
4048 | * to PCI config space in order to use this function. | |
4049 | * | |
4050 | * The device function is presumed to be unused when this function is called. | |
4051 | * Resetting the device will make the contents of PCI configuration space | |
4052 | * random, so any caller of this must be prepared to reinitialise the | |
4053 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4054 | * etc. | |
4055 | * | |
8c1c699f | 4056 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
4057 | * device doesn't support resetting a single function. |
4058 | */ | |
8c1c699f | 4059 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 4060 | { |
8c1c699f | 4061 | return pci_dev_reset(dev, 0); |
d91cdc74 | 4062 | } |
8c1c699f | 4063 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 4064 | |
6fbf9e7a KRW |
4065 | /** |
4066 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4067 | * the @dev mutex lock. | |
4068 | * @dev: PCI device to reset | |
4069 | * | |
4070 | * Some devices allow an individual function to be reset without affecting | |
4071 | * other functions in the same device. The PCI device must be responsive | |
4072 | * to PCI config space in order to use this function. | |
4073 | * | |
4074 | * The device function is presumed to be unused and the caller is holding | |
4075 | * the device mutex lock when this function is called. | |
4076 | * Resetting the device will make the contents of PCI configuration space | |
4077 | * random, so any caller of this must be prepared to reinitialise the | |
4078 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4079 | * etc. | |
4080 | * | |
4081 | * Returns 0 if the device function was successfully reset or negative if the | |
4082 | * device doesn't support resetting a single function. | |
4083 | */ | |
4084 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4085 | { | |
977f857c | 4086 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
4087 | } |
4088 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
4089 | ||
711d5779 MT |
4090 | /** |
4091 | * pci_probe_reset_function - check whether the device can be safely reset | |
4092 | * @dev: PCI device to reset | |
4093 | * | |
4094 | * Some devices allow an individual function to be reset without affecting | |
4095 | * other functions in the same device. The PCI device must be responsive | |
4096 | * to PCI config space in order to use this function. | |
4097 | * | |
4098 | * Returns 0 if the device function can be reset or negative if the | |
4099 | * device doesn't support resetting a single function. | |
4100 | */ | |
4101 | int pci_probe_reset_function(struct pci_dev *dev) | |
4102 | { | |
4103 | return pci_dev_reset(dev, 1); | |
4104 | } | |
4105 | ||
8dd7f803 | 4106 | /** |
8c1c699f YZ |
4107 | * pci_reset_function - quiesce and reset a PCI device function |
4108 | * @dev: PCI device to reset | |
8dd7f803 SY |
4109 | * |
4110 | * Some devices allow an individual function to be reset without affecting | |
4111 | * other functions in the same device. The PCI device must be responsive | |
4112 | * to PCI config space in order to use this function. | |
4113 | * | |
4114 | * This function does not just reset the PCI portion of a device, but | |
4115 | * clears all the state associated with the device. This function differs | |
8c1c699f | 4116 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
4117 | * over the reset. |
4118 | * | |
8c1c699f | 4119 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
4120 | * device doesn't support resetting a single function. |
4121 | */ | |
4122 | int pci_reset_function(struct pci_dev *dev) | |
4123 | { | |
8c1c699f | 4124 | int rc; |
8dd7f803 | 4125 | |
8c1c699f YZ |
4126 | rc = pci_dev_reset(dev, 1); |
4127 | if (rc) | |
4128 | return rc; | |
8dd7f803 | 4129 | |
77cb985a | 4130 | pci_dev_save_and_disable(dev); |
8dd7f803 | 4131 | |
8c1c699f | 4132 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 4133 | |
77cb985a | 4134 | pci_dev_restore(dev); |
8dd7f803 | 4135 | |
8c1c699f | 4136 | return rc; |
8dd7f803 SY |
4137 | } |
4138 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
4139 | ||
61cf16d8 AW |
4140 | /** |
4141 | * pci_try_reset_function - quiesce and reset a PCI device function | |
4142 | * @dev: PCI device to reset | |
4143 | * | |
4144 | * Same as above, except return -EAGAIN if unable to lock device. | |
4145 | */ | |
4146 | int pci_try_reset_function(struct pci_dev *dev) | |
4147 | { | |
4148 | int rc; | |
4149 | ||
4150 | rc = pci_dev_reset(dev, 1); | |
4151 | if (rc) | |
4152 | return rc; | |
4153 | ||
4154 | pci_dev_save_and_disable(dev); | |
4155 | ||
4156 | if (pci_dev_trylock(dev)) { | |
4157 | rc = __pci_dev_reset(dev, 0); | |
4158 | pci_dev_unlock(dev); | |
4159 | } else | |
4160 | rc = -EAGAIN; | |
4161 | ||
4162 | pci_dev_restore(dev); | |
4163 | ||
4164 | return rc; | |
4165 | } | |
4166 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
4167 | ||
f331a859 AW |
4168 | /* Do any devices on or below this bus prevent a bus reset? */ |
4169 | static bool pci_bus_resetable(struct pci_bus *bus) | |
4170 | { | |
4171 | struct pci_dev *dev; | |
4172 | ||
4173 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4174 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4175 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4176 | return false; | |
4177 | } | |
4178 | ||
4179 | return true; | |
4180 | } | |
4181 | ||
090a3c53 AW |
4182 | /* Lock devices from the top of the tree down */ |
4183 | static void pci_bus_lock(struct pci_bus *bus) | |
4184 | { | |
4185 | struct pci_dev *dev; | |
4186 | ||
4187 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4188 | pci_dev_lock(dev); | |
4189 | if (dev->subordinate) | |
4190 | pci_bus_lock(dev->subordinate); | |
4191 | } | |
4192 | } | |
4193 | ||
4194 | /* Unlock devices from the bottom of the tree up */ | |
4195 | static void pci_bus_unlock(struct pci_bus *bus) | |
4196 | { | |
4197 | struct pci_dev *dev; | |
4198 | ||
4199 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4200 | if (dev->subordinate) | |
4201 | pci_bus_unlock(dev->subordinate); | |
4202 | pci_dev_unlock(dev); | |
4203 | } | |
4204 | } | |
4205 | ||
61cf16d8 AW |
4206 | /* Return 1 on successful lock, 0 on contention */ |
4207 | static int pci_bus_trylock(struct pci_bus *bus) | |
4208 | { | |
4209 | struct pci_dev *dev; | |
4210 | ||
4211 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4212 | if (!pci_dev_trylock(dev)) | |
4213 | goto unlock; | |
4214 | if (dev->subordinate) { | |
4215 | if (!pci_bus_trylock(dev->subordinate)) { | |
4216 | pci_dev_unlock(dev); | |
4217 | goto unlock; | |
4218 | } | |
4219 | } | |
4220 | } | |
4221 | return 1; | |
4222 | ||
4223 | unlock: | |
4224 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
4225 | if (dev->subordinate) | |
4226 | pci_bus_unlock(dev->subordinate); | |
4227 | pci_dev_unlock(dev); | |
4228 | } | |
4229 | return 0; | |
4230 | } | |
4231 | ||
f331a859 AW |
4232 | /* Do any devices on or below this slot prevent a bus reset? */ |
4233 | static bool pci_slot_resetable(struct pci_slot *slot) | |
4234 | { | |
4235 | struct pci_dev *dev; | |
4236 | ||
4237 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4238 | if (!dev->slot || dev->slot != slot) | |
4239 | continue; | |
4240 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4241 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4242 | return false; | |
4243 | } | |
4244 | ||
4245 | return true; | |
4246 | } | |
4247 | ||
090a3c53 AW |
4248 | /* Lock devices from the top of the tree down */ |
4249 | static void pci_slot_lock(struct pci_slot *slot) | |
4250 | { | |
4251 | struct pci_dev *dev; | |
4252 | ||
4253 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4254 | if (!dev->slot || dev->slot != slot) | |
4255 | continue; | |
4256 | pci_dev_lock(dev); | |
4257 | if (dev->subordinate) | |
4258 | pci_bus_lock(dev->subordinate); | |
4259 | } | |
4260 | } | |
4261 | ||
4262 | /* Unlock devices from the bottom of the tree up */ | |
4263 | static void pci_slot_unlock(struct pci_slot *slot) | |
4264 | { | |
4265 | struct pci_dev *dev; | |
4266 | ||
4267 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4268 | if (!dev->slot || dev->slot != slot) | |
4269 | continue; | |
4270 | if (dev->subordinate) | |
4271 | pci_bus_unlock(dev->subordinate); | |
4272 | pci_dev_unlock(dev); | |
4273 | } | |
4274 | } | |
4275 | ||
61cf16d8 AW |
4276 | /* Return 1 on successful lock, 0 on contention */ |
4277 | static int pci_slot_trylock(struct pci_slot *slot) | |
4278 | { | |
4279 | struct pci_dev *dev; | |
4280 | ||
4281 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4282 | if (!dev->slot || dev->slot != slot) | |
4283 | continue; | |
4284 | if (!pci_dev_trylock(dev)) | |
4285 | goto unlock; | |
4286 | if (dev->subordinate) { | |
4287 | if (!pci_bus_trylock(dev->subordinate)) { | |
4288 | pci_dev_unlock(dev); | |
4289 | goto unlock; | |
4290 | } | |
4291 | } | |
4292 | } | |
4293 | return 1; | |
4294 | ||
4295 | unlock: | |
4296 | list_for_each_entry_continue_reverse(dev, | |
4297 | &slot->bus->devices, bus_list) { | |
4298 | if (!dev->slot || dev->slot != slot) | |
4299 | continue; | |
4300 | if (dev->subordinate) | |
4301 | pci_bus_unlock(dev->subordinate); | |
4302 | pci_dev_unlock(dev); | |
4303 | } | |
4304 | return 0; | |
4305 | } | |
4306 | ||
090a3c53 AW |
4307 | /* Save and disable devices from the top of the tree down */ |
4308 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
4309 | { | |
4310 | struct pci_dev *dev; | |
4311 | ||
4312 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4313 | pci_dev_save_and_disable(dev); | |
4314 | if (dev->subordinate) | |
4315 | pci_bus_save_and_disable(dev->subordinate); | |
4316 | } | |
4317 | } | |
4318 | ||
4319 | /* | |
4320 | * Restore devices from top of the tree down - parent bridges need to be | |
4321 | * restored before we can get to subordinate devices. | |
4322 | */ | |
4323 | static void pci_bus_restore(struct pci_bus *bus) | |
4324 | { | |
4325 | struct pci_dev *dev; | |
4326 | ||
4327 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4328 | pci_dev_restore(dev); | |
4329 | if (dev->subordinate) | |
4330 | pci_bus_restore(dev->subordinate); | |
4331 | } | |
4332 | } | |
4333 | ||
4334 | /* Save and disable devices from the top of the tree down */ | |
4335 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
4336 | { | |
4337 | struct pci_dev *dev; | |
4338 | ||
4339 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4340 | if (!dev->slot || dev->slot != slot) | |
4341 | continue; | |
4342 | pci_dev_save_and_disable(dev); | |
4343 | if (dev->subordinate) | |
4344 | pci_bus_save_and_disable(dev->subordinate); | |
4345 | } | |
4346 | } | |
4347 | ||
4348 | /* | |
4349 | * Restore devices from top of the tree down - parent bridges need to be | |
4350 | * restored before we can get to subordinate devices. | |
4351 | */ | |
4352 | static void pci_slot_restore(struct pci_slot *slot) | |
4353 | { | |
4354 | struct pci_dev *dev; | |
4355 | ||
4356 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4357 | if (!dev->slot || dev->slot != slot) | |
4358 | continue; | |
4359 | pci_dev_restore(dev); | |
4360 | if (dev->subordinate) | |
4361 | pci_bus_restore(dev->subordinate); | |
4362 | } | |
4363 | } | |
4364 | ||
4365 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
4366 | { | |
4367 | int rc; | |
4368 | ||
f331a859 | 4369 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
4370 | return -ENOTTY; |
4371 | ||
4372 | if (!probe) | |
4373 | pci_slot_lock(slot); | |
4374 | ||
4375 | might_sleep(); | |
4376 | ||
4377 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
4378 | ||
4379 | if (!probe) | |
4380 | pci_slot_unlock(slot); | |
4381 | ||
4382 | return rc; | |
4383 | } | |
4384 | ||
9a3d2b9b AW |
4385 | /** |
4386 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
4387 | * @slot: PCI slot to probe | |
4388 | * | |
4389 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
4390 | */ | |
4391 | int pci_probe_reset_slot(struct pci_slot *slot) | |
4392 | { | |
4393 | return pci_slot_reset(slot, 1); | |
4394 | } | |
4395 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
4396 | ||
090a3c53 AW |
4397 | /** |
4398 | * pci_reset_slot - reset a PCI slot | |
4399 | * @slot: PCI slot to reset | |
4400 | * | |
4401 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
4402 | * independent of other slots. For instance, some slots may support slot power | |
4403 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
4404 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
4405 | * Generally a slot reset should be attempted before a bus reset. All of the | |
4406 | * function of the slot and any subordinate buses behind the slot are reset | |
4407 | * through this function. PCI config space of all devices in the slot and | |
4408 | * behind the slot is saved before and restored after reset. | |
4409 | * | |
4410 | * Return 0 on success, non-zero on error. | |
4411 | */ | |
4412 | int pci_reset_slot(struct pci_slot *slot) | |
4413 | { | |
4414 | int rc; | |
4415 | ||
4416 | rc = pci_slot_reset(slot, 1); | |
4417 | if (rc) | |
4418 | return rc; | |
4419 | ||
4420 | pci_slot_save_and_disable(slot); | |
4421 | ||
4422 | rc = pci_slot_reset(slot, 0); | |
4423 | ||
4424 | pci_slot_restore(slot); | |
4425 | ||
4426 | return rc; | |
4427 | } | |
4428 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
4429 | ||
61cf16d8 AW |
4430 | /** |
4431 | * pci_try_reset_slot - Try to reset a PCI slot | |
4432 | * @slot: PCI slot to reset | |
4433 | * | |
4434 | * Same as above except return -EAGAIN if the slot cannot be locked | |
4435 | */ | |
4436 | int pci_try_reset_slot(struct pci_slot *slot) | |
4437 | { | |
4438 | int rc; | |
4439 | ||
4440 | rc = pci_slot_reset(slot, 1); | |
4441 | if (rc) | |
4442 | return rc; | |
4443 | ||
4444 | pci_slot_save_and_disable(slot); | |
4445 | ||
4446 | if (pci_slot_trylock(slot)) { | |
4447 | might_sleep(); | |
4448 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
4449 | pci_slot_unlock(slot); | |
4450 | } else | |
4451 | rc = -EAGAIN; | |
4452 | ||
4453 | pci_slot_restore(slot); | |
4454 | ||
4455 | return rc; | |
4456 | } | |
4457 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
4458 | ||
090a3c53 AW |
4459 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
4460 | { | |
f331a859 | 4461 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
4462 | return -ENOTTY; |
4463 | ||
4464 | if (probe) | |
4465 | return 0; | |
4466 | ||
4467 | pci_bus_lock(bus); | |
4468 | ||
4469 | might_sleep(); | |
4470 | ||
4471 | pci_reset_bridge_secondary_bus(bus->self); | |
4472 | ||
4473 | pci_bus_unlock(bus); | |
4474 | ||
4475 | return 0; | |
4476 | } | |
4477 | ||
9a3d2b9b AW |
4478 | /** |
4479 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
4480 | * @bus: PCI bus to probe | |
4481 | * | |
4482 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
4483 | */ | |
4484 | int pci_probe_reset_bus(struct pci_bus *bus) | |
4485 | { | |
4486 | return pci_bus_reset(bus, 1); | |
4487 | } | |
4488 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
4489 | ||
090a3c53 AW |
4490 | /** |
4491 | * pci_reset_bus - reset a PCI bus | |
4492 | * @bus: top level PCI bus to reset | |
4493 | * | |
4494 | * Do a bus reset on the given bus and any subordinate buses, saving | |
4495 | * and restoring state of all devices. | |
4496 | * | |
4497 | * Return 0 on success, non-zero on error. | |
4498 | */ | |
4499 | int pci_reset_bus(struct pci_bus *bus) | |
4500 | { | |
4501 | int rc; | |
4502 | ||
4503 | rc = pci_bus_reset(bus, 1); | |
4504 | if (rc) | |
4505 | return rc; | |
4506 | ||
4507 | pci_bus_save_and_disable(bus); | |
4508 | ||
4509 | rc = pci_bus_reset(bus, 0); | |
4510 | ||
4511 | pci_bus_restore(bus); | |
4512 | ||
4513 | return rc; | |
4514 | } | |
4515 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
4516 | ||
61cf16d8 AW |
4517 | /** |
4518 | * pci_try_reset_bus - Try to reset a PCI bus | |
4519 | * @bus: top level PCI bus to reset | |
4520 | * | |
4521 | * Same as above except return -EAGAIN if the bus cannot be locked | |
4522 | */ | |
4523 | int pci_try_reset_bus(struct pci_bus *bus) | |
4524 | { | |
4525 | int rc; | |
4526 | ||
4527 | rc = pci_bus_reset(bus, 1); | |
4528 | if (rc) | |
4529 | return rc; | |
4530 | ||
4531 | pci_bus_save_and_disable(bus); | |
4532 | ||
4533 | if (pci_bus_trylock(bus)) { | |
4534 | might_sleep(); | |
4535 | pci_reset_bridge_secondary_bus(bus->self); | |
4536 | pci_bus_unlock(bus); | |
4537 | } else | |
4538 | rc = -EAGAIN; | |
4539 | ||
4540 | pci_bus_restore(bus); | |
4541 | ||
4542 | return rc; | |
4543 | } | |
4544 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
4545 | ||
d556ad4b PO |
4546 | /** |
4547 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
4548 | * @dev: PCI device to query | |
4549 | * | |
4550 | * Returns mmrbc: maximum designed memory read count in bytes | |
4551 | * or appropriate error value. | |
4552 | */ | |
4553 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
4554 | { | |
7c9e2b1c | 4555 | int cap; |
d556ad4b PO |
4556 | u32 stat; |
4557 | ||
4558 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4559 | if (!cap) | |
4560 | return -EINVAL; | |
4561 | ||
7c9e2b1c | 4562 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
4563 | return -EINVAL; |
4564 | ||
25daeb55 | 4565 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
4566 | } |
4567 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
4568 | ||
4569 | /** | |
4570 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
4571 | * @dev: PCI device to query | |
4572 | * | |
4573 | * Returns mmrbc: maximum memory read count in bytes | |
4574 | * or appropriate error value. | |
4575 | */ | |
4576 | int pcix_get_mmrbc(struct pci_dev *dev) | |
4577 | { | |
7c9e2b1c | 4578 | int cap; |
bdc2bda7 | 4579 | u16 cmd; |
d556ad4b PO |
4580 | |
4581 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4582 | if (!cap) | |
4583 | return -EINVAL; | |
4584 | ||
7c9e2b1c DN |
4585 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4586 | return -EINVAL; | |
d556ad4b | 4587 | |
7c9e2b1c | 4588 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
4589 | } |
4590 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
4591 | ||
4592 | /** | |
4593 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
4594 | * @dev: PCI device to query | |
4595 | * @mmrbc: maximum memory read count in bytes | |
4596 | * valid values are 512, 1024, 2048, 4096 | |
4597 | * | |
4598 | * If possible sets maximum memory read byte count, some bridges have erratas | |
4599 | * that prevent this. | |
4600 | */ | |
4601 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
4602 | { | |
7c9e2b1c | 4603 | int cap; |
bdc2bda7 DN |
4604 | u32 stat, v, o; |
4605 | u16 cmd; | |
d556ad4b | 4606 | |
229f5afd | 4607 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 4608 | return -EINVAL; |
d556ad4b PO |
4609 | |
4610 | v = ffs(mmrbc) - 10; | |
4611 | ||
4612 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4613 | if (!cap) | |
7c9e2b1c | 4614 | return -EINVAL; |
d556ad4b | 4615 | |
7c9e2b1c DN |
4616 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
4617 | return -EINVAL; | |
d556ad4b PO |
4618 | |
4619 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
4620 | return -E2BIG; | |
4621 | ||
7c9e2b1c DN |
4622 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4623 | return -EINVAL; | |
d556ad4b PO |
4624 | |
4625 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
4626 | if (o != v) { | |
809a3bf9 | 4627 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
4628 | return -EIO; |
4629 | ||
4630 | cmd &= ~PCI_X_CMD_MAX_READ; | |
4631 | cmd |= v << 2; | |
7c9e2b1c DN |
4632 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
4633 | return -EIO; | |
d556ad4b | 4634 | } |
7c9e2b1c | 4635 | return 0; |
d556ad4b PO |
4636 | } |
4637 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
4638 | ||
4639 | /** | |
4640 | * pcie_get_readrq - get PCI Express read request size | |
4641 | * @dev: PCI device to query | |
4642 | * | |
4643 | * Returns maximum memory read request in bytes | |
4644 | * or appropriate error value. | |
4645 | */ | |
4646 | int pcie_get_readrq(struct pci_dev *dev) | |
4647 | { | |
d556ad4b PO |
4648 | u16 ctl; |
4649 | ||
59875ae4 | 4650 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 4651 | |
59875ae4 | 4652 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
4653 | } |
4654 | EXPORT_SYMBOL(pcie_get_readrq); | |
4655 | ||
4656 | /** | |
4657 | * pcie_set_readrq - set PCI Express maximum memory read request | |
4658 | * @dev: PCI device to query | |
42e61f4a | 4659 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
4660 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4661 | * | |
c9b378c7 | 4662 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
4663 | */ |
4664 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
4665 | { | |
59875ae4 | 4666 | u16 v; |
d556ad4b | 4667 | |
229f5afd | 4668 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4669 | return -EINVAL; |
d556ad4b | 4670 | |
a1c473aa BH |
4671 | /* |
4672 | * If using the "performance" PCIe config, we clamp the | |
4673 | * read rq size to the max packet size to prevent the | |
4674 | * host bridge generating requests larger than we can | |
4675 | * cope with | |
4676 | */ | |
4677 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4678 | int mps = pcie_get_mps(dev); | |
4679 | ||
a1c473aa BH |
4680 | if (mps < rq) |
4681 | rq = mps; | |
4682 | } | |
4683 | ||
4684 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4685 | |
59875ae4 JL |
4686 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4687 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4688 | } |
4689 | EXPORT_SYMBOL(pcie_set_readrq); | |
4690 | ||
b03e7495 JM |
4691 | /** |
4692 | * pcie_get_mps - get PCI Express maximum payload size | |
4693 | * @dev: PCI device to query | |
4694 | * | |
4695 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4696 | */ |
4697 | int pcie_get_mps(struct pci_dev *dev) | |
4698 | { | |
b03e7495 JM |
4699 | u16 ctl; |
4700 | ||
59875ae4 | 4701 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4702 | |
59875ae4 | 4703 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4704 | } |
f1c66c46 | 4705 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4706 | |
4707 | /** | |
4708 | * pcie_set_mps - set PCI Express maximum payload size | |
4709 | * @dev: PCI device to query | |
47c08f31 | 4710 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4711 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4712 | * | |
4713 | * If possible sets maximum payload size | |
4714 | */ | |
4715 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4716 | { | |
59875ae4 | 4717 | u16 v; |
b03e7495 JM |
4718 | |
4719 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4720 | return -EINVAL; |
b03e7495 JM |
4721 | |
4722 | v = ffs(mps) - 8; | |
f7625980 | 4723 | if (v > dev->pcie_mpss) |
59875ae4 | 4724 | return -EINVAL; |
b03e7495 JM |
4725 | v <<= 5; |
4726 | ||
59875ae4 JL |
4727 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4728 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4729 | } |
f1c66c46 | 4730 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4731 | |
81377c8d JK |
4732 | /** |
4733 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4734 | * @dev: PCI device to query | |
4735 | * @speed: storage for minimum speed | |
4736 | * @width: storage for minimum width | |
4737 | * | |
4738 | * This function will walk up the PCI device chain and determine the minimum | |
4739 | * link width and speed of the device. | |
4740 | */ | |
4741 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4742 | enum pcie_link_width *width) | |
4743 | { | |
4744 | int ret; | |
4745 | ||
4746 | *speed = PCI_SPEED_UNKNOWN; | |
4747 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4748 | ||
4749 | while (dev) { | |
4750 | u16 lnksta; | |
4751 | enum pci_bus_speed next_speed; | |
4752 | enum pcie_link_width next_width; | |
4753 | ||
4754 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4755 | if (ret) | |
4756 | return ret; | |
4757 | ||
4758 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4759 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4760 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4761 | ||
4762 | if (next_speed < *speed) | |
4763 | *speed = next_speed; | |
4764 | ||
4765 | if (next_width < *width) | |
4766 | *width = next_width; | |
4767 | ||
4768 | dev = dev->bus->self; | |
4769 | } | |
4770 | ||
4771 | return 0; | |
4772 | } | |
4773 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4774 | ||
c87deff7 HS |
4775 | /** |
4776 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4777 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4778 | * @flags: resource type mask to be selected |
4779 | * | |
4780 | * This helper routine makes bar mask from the type of resource. | |
4781 | */ | |
4782 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4783 | { | |
4784 | int i, bars = 0; | |
4785 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4786 | if (pci_resource_flags(dev, i) & flags) | |
4787 | bars |= (1 << i); | |
4788 | return bars; | |
4789 | } | |
b7fe9434 | 4790 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 4791 | |
613e7ed6 YZ |
4792 | /** |
4793 | * pci_resource_bar - get position of the BAR associated with a resource | |
4794 | * @dev: the PCI device | |
4795 | * @resno: the resource number | |
4796 | * @type: the BAR type to be filled in | |
4797 | * | |
4798 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4799 | */ | |
4800 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4801 | { | |
d1b054da YZ |
4802 | int reg; |
4803 | ||
613e7ed6 YZ |
4804 | if (resno < PCI_ROM_RESOURCE) { |
4805 | *type = pci_bar_unknown; | |
4806 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4807 | } else if (resno == PCI_ROM_RESOURCE) { | |
4808 | *type = pci_bar_mem32; | |
4809 | return dev->rom_base_reg; | |
d1b054da YZ |
4810 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4811 | /* device specific resource */ | |
26ff46c6 MS |
4812 | *type = pci_bar_unknown; |
4813 | reg = pci_iov_resource_bar(dev, resno); | |
d1b054da YZ |
4814 | if (reg) |
4815 | return reg; | |
613e7ed6 YZ |
4816 | } |
4817 | ||
865df576 | 4818 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4819 | return 0; |
4820 | } | |
4821 | ||
95a8b6ef MT |
4822 | /* Some architectures require additional programming to enable VGA */ |
4823 | static arch_set_vga_state_t arch_set_vga_state; | |
4824 | ||
4825 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4826 | { | |
4827 | arch_set_vga_state = func; /* NULL disables */ | |
4828 | } | |
4829 | ||
4830 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 4831 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4832 | { |
4833 | if (arch_set_vga_state) | |
4834 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4835 | flags); |
95a8b6ef MT |
4836 | return 0; |
4837 | } | |
4838 | ||
deb2d2ec BH |
4839 | /** |
4840 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4841 | * @dev: the PCI device |
4842 | * @decode: true = enable decoding, false = disable decoding | |
4843 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4844 | * @flags: traverse ancestors and change bridges |
3448a19d | 4845 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4846 | */ |
4847 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4848 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4849 | { |
4850 | struct pci_bus *bus; | |
4851 | struct pci_dev *bridge; | |
4852 | u16 cmd; | |
95a8b6ef | 4853 | int rc; |
deb2d2ec | 4854 | |
67ebd814 | 4855 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4856 | |
95a8b6ef | 4857 | /* ARCH specific VGA enables */ |
3448a19d | 4858 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4859 | if (rc) |
4860 | return rc; | |
4861 | ||
3448a19d DA |
4862 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4863 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4864 | if (decode == true) | |
4865 | cmd |= command_bits; | |
4866 | else | |
4867 | cmd &= ~command_bits; | |
4868 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4869 | } | |
deb2d2ec | 4870 | |
3448a19d | 4871 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4872 | return 0; |
4873 | ||
4874 | bus = dev->bus; | |
4875 | while (bus) { | |
4876 | bridge = bus->self; | |
4877 | if (bridge) { | |
4878 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4879 | &cmd); | |
4880 | if (decode == true) | |
4881 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4882 | else | |
4883 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4884 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4885 | cmd); | |
4886 | } | |
4887 | bus = bus->parent; | |
4888 | } | |
4889 | return 0; | |
4890 | } | |
4891 | ||
f0af9593 BH |
4892 | /** |
4893 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
4894 | * @dev: the PCI device for which alias is added | |
4895 | * @devfn: alias slot and function | |
4896 | * | |
4897 | * This helper encodes 8-bit devfn as bit number in dma_alias_mask. | |
4898 | * It should be called early, preferably as PCI fixup header quirk. | |
4899 | */ | |
4900 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) | |
4901 | { | |
338c3149 JL |
4902 | if (!dev->dma_alias_mask) |
4903 | dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), | |
4904 | sizeof(long), GFP_KERNEL); | |
4905 | if (!dev->dma_alias_mask) { | |
4906 | dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); | |
4907 | return; | |
4908 | } | |
4909 | ||
4910 | set_bit(devfn, dev->dma_alias_mask); | |
48c83080 BH |
4911 | dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", |
4912 | PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
f0af9593 BH |
4913 | } |
4914 | ||
338c3149 JL |
4915 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
4916 | { | |
4917 | return (dev1->dma_alias_mask && | |
4918 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
4919 | (dev2->dma_alias_mask && | |
4920 | test_bit(dev1->devfn, dev2->dma_alias_mask)); | |
4921 | } | |
4922 | ||
8496e85c RW |
4923 | bool pci_device_is_present(struct pci_dev *pdev) |
4924 | { | |
4925 | u32 v; | |
4926 | ||
4927 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4928 | } | |
4929 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4930 | ||
08249651 RW |
4931 | void pci_ignore_hotplug(struct pci_dev *dev) |
4932 | { | |
4933 | struct pci_dev *bridge = dev->bus->self; | |
4934 | ||
4935 | dev->ignore_hotplug = 1; | |
4936 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
4937 | if (bridge) | |
4938 | bridge->ignore_hotplug = 1; | |
4939 | } | |
4940 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
4941 | ||
32a9a682 YS |
4942 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4943 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4944 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4945 | |
4946 | /** | |
4947 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4948 | * @dev: the PCI device to get | |
4949 | * | |
4950 | * RETURNS: Resource alignment if it is specified. | |
4951 | * Zero if it is not specified. | |
4952 | */ | |
9738abed | 4953 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4954 | { |
4955 | int seg, bus, slot, func, align_order, count; | |
644a544f | 4956 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
32a9a682 YS |
4957 | resource_size_t align = 0; |
4958 | char *p; | |
4959 | ||
4960 | spin_lock(&resource_alignment_lock); | |
4961 | p = resource_alignment_param; | |
4962 | while (*p) { | |
4963 | count = 0; | |
4964 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4965 | p[count] == '@') { | |
4966 | p += count + 1; | |
4967 | } else { | |
4968 | align_order = -1; | |
4969 | } | |
644a544f KMEE |
4970 | if (strncmp(p, "pci:", 4) == 0) { |
4971 | /* PCI vendor/device (subvendor/subdevice) ids are specified */ | |
4972 | p += 4; | |
4973 | if (sscanf(p, "%hx:%hx:%hx:%hx%n", | |
4974 | &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) { | |
4975 | if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) { | |
4976 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n", | |
4977 | p); | |
4978 | break; | |
4979 | } | |
4980 | subsystem_vendor = subsystem_device = 0; | |
4981 | } | |
4982 | p += count; | |
4983 | if ((!vendor || (vendor == dev->vendor)) && | |
4984 | (!device || (device == dev->device)) && | |
4985 | (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) && | |
4986 | (!subsystem_device || (subsystem_device == dev->subsystem_device))) { | |
4987 | if (align_order == -1) | |
4988 | align = PAGE_SIZE; | |
4989 | else | |
4990 | align = 1 << align_order; | |
4991 | /* Found */ | |
32a9a682 YS |
4992 | break; |
4993 | } | |
4994 | } | |
644a544f KMEE |
4995 | else { |
4996 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4997 | &seg, &bus, &slot, &func, &count) != 4) { | |
4998 | seg = 0; | |
4999 | if (sscanf(p, "%x:%x.%x%n", | |
5000 | &bus, &slot, &func, &count) != 3) { | |
5001 | /* Invalid format */ | |
5002 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
5003 | p); | |
5004 | break; | |
5005 | } | |
5006 | } | |
5007 | p += count; | |
5008 | if (seg == pci_domain_nr(dev->bus) && | |
5009 | bus == dev->bus->number && | |
5010 | slot == PCI_SLOT(dev->devfn) && | |
5011 | func == PCI_FUNC(dev->devfn)) { | |
5012 | if (align_order == -1) | |
5013 | align = PAGE_SIZE; | |
5014 | else | |
5015 | align = 1 << align_order; | |
5016 | /* Found */ | |
5017 | break; | |
5018 | } | |
32a9a682 YS |
5019 | } |
5020 | if (*p != ';' && *p != ',') { | |
5021 | /* End of param or invalid format */ | |
5022 | break; | |
5023 | } | |
5024 | p++; | |
5025 | } | |
5026 | spin_unlock(&resource_alignment_lock); | |
5027 | return align; | |
5028 | } | |
5029 | ||
2069ecfb YL |
5030 | /* |
5031 | * This function disables memory decoding and releases memory resources | |
5032 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
5033 | * It also rounds up size to specified alignment. | |
5034 | * Later on, the kernel will assign page-aligned memory resource back | |
5035 | * to the device. | |
5036 | */ | |
5037 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
5038 | { | |
5039 | int i; | |
5040 | struct resource *r; | |
5041 | resource_size_t align, size; | |
5042 | u16 command; | |
5043 | ||
10c463a7 YL |
5044 | /* check if specified PCI is target device to reassign */ |
5045 | align = pci_specified_resource_alignment(dev); | |
5046 | if (!align) | |
2069ecfb YL |
5047 | return; |
5048 | ||
5049 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
5050 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
5051 | dev_warn(&dev->dev, | |
5052 | "Can't reassign resources to host bridge.\n"); | |
5053 | return; | |
5054 | } | |
5055 | ||
5056 | dev_info(&dev->dev, | |
5057 | "Disabling memory decoding and releasing memory resources.\n"); | |
5058 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
5059 | command &= ~PCI_COMMAND_MEMORY; | |
5060 | pci_write_config_word(dev, PCI_COMMAND, command); | |
5061 | ||
2069ecfb YL |
5062 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
5063 | r = &dev->resource[i]; | |
5064 | if (!(r->flags & IORESOURCE_MEM)) | |
5065 | continue; | |
5066 | size = resource_size(r); | |
5067 | if (size < align) { | |
5068 | size = align; | |
5069 | dev_info(&dev->dev, | |
5070 | "Rounding up size of resource #%d to %#llx.\n", | |
5071 | i, (unsigned long long)size); | |
5072 | } | |
bd064f0a | 5073 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
5074 | r->end = size - 1; |
5075 | r->start = 0; | |
5076 | } | |
5077 | /* Need to disable bridge's resource window, | |
5078 | * to enable the kernel to reassign new resource | |
5079 | * window later on. | |
5080 | */ | |
5081 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
5082 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
5083 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
5084 | r = &dev->resource[i]; | |
5085 | if (!(r->flags & IORESOURCE_MEM)) | |
5086 | continue; | |
bd064f0a | 5087 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
5088 | r->end = resource_size(r) - 1; |
5089 | r->start = 0; | |
5090 | } | |
5091 | pci_disable_bridge_window(dev); | |
5092 | } | |
5093 | } | |
5094 | ||
9738abed | 5095 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
5096 | { |
5097 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
5098 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
5099 | spin_lock(&resource_alignment_lock); | |
5100 | strncpy(resource_alignment_param, buf, count); | |
5101 | resource_alignment_param[count] = '\0'; | |
5102 | spin_unlock(&resource_alignment_lock); | |
5103 | return count; | |
5104 | } | |
5105 | ||
9738abed | 5106 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
5107 | { |
5108 | size_t count; | |
5109 | spin_lock(&resource_alignment_lock); | |
5110 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
5111 | spin_unlock(&resource_alignment_lock); | |
5112 | return count; | |
5113 | } | |
5114 | ||
5115 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
5116 | { | |
5117 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
5118 | } | |
5119 | ||
5120 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
5121 | const char *buf, size_t count) | |
5122 | { | |
5123 | return pci_set_resource_alignment_param(buf, count); | |
5124 | } | |
5125 | ||
21751a9a | 5126 | static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, |
32a9a682 YS |
5127 | pci_resource_alignment_store); |
5128 | ||
5129 | static int __init pci_resource_alignment_sysfs_init(void) | |
5130 | { | |
5131 | return bus_create_file(&pci_bus_type, | |
5132 | &bus_attr_resource_alignment); | |
5133 | } | |
32a9a682 YS |
5134 | late_initcall(pci_resource_alignment_sysfs_init); |
5135 | ||
15856ad5 | 5136 | static void pci_no_domains(void) |
32a2eea7 JG |
5137 | { |
5138 | #ifdef CONFIG_PCI_DOMAINS | |
5139 | pci_domains_supported = 0; | |
5140 | #endif | |
5141 | } | |
5142 | ||
41e5c0f8 LD |
5143 | #ifdef CONFIG_PCI_DOMAINS |
5144 | static atomic_t __domain_nr = ATOMIC_INIT(-1); | |
5145 | ||
5146 | int pci_get_new_domain_nr(void) | |
5147 | { | |
5148 | return atomic_inc_return(&__domain_nr); | |
5149 | } | |
7c674700 LP |
5150 | |
5151 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1a4f93f7 | 5152 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
5153 | { |
5154 | static int use_dt_domains = -1; | |
54c6e2dd | 5155 | int domain = -1; |
7c674700 | 5156 | |
54c6e2dd KHC |
5157 | if (parent) |
5158 | domain = of_get_pci_domain_nr(parent->of_node); | |
7c674700 LP |
5159 | /* |
5160 | * Check DT domain and use_dt_domains values. | |
5161 | * | |
5162 | * If DT domain property is valid (domain >= 0) and | |
5163 | * use_dt_domains != 0, the DT assignment is valid since this means | |
5164 | * we have not previously allocated a domain number by using | |
5165 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
5166 | * 1, to indicate that we have just assigned a domain number from | |
5167 | * DT. | |
5168 | * | |
5169 | * If DT domain property value is not valid (ie domain < 0), and we | |
5170 | * have not previously assigned a domain number from DT | |
5171 | * (use_dt_domains != 1) we should assign a domain number by | |
5172 | * using the: | |
5173 | * | |
5174 | * pci_get_new_domain_nr() | |
5175 | * | |
5176 | * API and update the use_dt_domains value to keep track of method we | |
5177 | * are using to assign domain numbers (use_dt_domains = 0). | |
5178 | * | |
5179 | * All other combinations imply we have a platform that is trying | |
5180 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
5181 | * which is a recipe for domain mishandling and it is prevented by | |
5182 | * invalidating the domain value (domain = -1) and printing a | |
5183 | * corresponding error. | |
5184 | */ | |
5185 | if (domain >= 0 && use_dt_domains) { | |
5186 | use_dt_domains = 1; | |
5187 | } else if (domain < 0 && use_dt_domains != 1) { | |
5188 | use_dt_domains = 0; | |
5189 | domain = pci_get_new_domain_nr(); | |
5190 | } else { | |
5191 | dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", | |
5192 | parent->of_node->full_name); | |
5193 | domain = -1; | |
5194 | } | |
5195 | ||
9c7cb891 | 5196 | return domain; |
7c674700 | 5197 | } |
1a4f93f7 TN |
5198 | |
5199 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
5200 | { | |
2ab51dde TN |
5201 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
5202 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
5203 | } |
5204 | #endif | |
41e5c0f8 LD |
5205 | #endif |
5206 | ||
0ef5f8f6 | 5207 | /** |
642c92da | 5208 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
5209 | * |
5210 | * Returns 1 if we can access PCI extended config space (offsets | |
5211 | * greater than 0xff). This is the default implementation. Architecture | |
5212 | * implementations can override this. | |
5213 | */ | |
642c92da | 5214 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
5215 | { |
5216 | return 1; | |
5217 | } | |
5218 | ||
2d1c8618 BH |
5219 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
5220 | { | |
5221 | } | |
5222 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
5223 | ||
ad04d31e | 5224 | static int __init pci_setup(char *str) |
1da177e4 LT |
5225 | { |
5226 | while (str) { | |
5227 | char *k = strchr(str, ','); | |
5228 | if (k) | |
5229 | *k++ = 0; | |
5230 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
5231 | if (!strcmp(str, "nomsi")) { |
5232 | pci_no_msi(); | |
7f785763 RD |
5233 | } else if (!strcmp(str, "noaer")) { |
5234 | pci_no_aer(); | |
b55438fd YL |
5235 | } else if (!strncmp(str, "realloc=", 8)) { |
5236 | pci_realloc_get_opt(str + 8); | |
f483d392 | 5237 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 5238 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
5239 | } else if (!strcmp(str, "nodomains")) { |
5240 | pci_no_domains(); | |
6748dcc2 RW |
5241 | } else if (!strncmp(str, "noari", 5)) { |
5242 | pcie_ari_disabled = true; | |
4516a618 AN |
5243 | } else if (!strncmp(str, "cbiosize=", 9)) { |
5244 | pci_cardbus_io_size = memparse(str + 9, &str); | |
5245 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
5246 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
5247 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
5248 | pci_set_resource_alignment_param(str + 19, | |
5249 | strlen(str + 19)); | |
43c16408 AP |
5250 | } else if (!strncmp(str, "ecrc=", 5)) { |
5251 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
5252 | } else if (!strncmp(str, "hpiosize=", 9)) { |
5253 | pci_hotplug_io_size = memparse(str + 9, &str); | |
5254 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
5255 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
e16b4660 KB |
5256 | } else if (!strncmp(str, "hpbussize=", 10)) { |
5257 | pci_hotplug_bus_size = | |
5258 | simple_strtoul(str + 10, &str, 0); | |
5259 | if (pci_hotplug_bus_size > 0xff) | |
5260 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
5261 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
5262 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
5263 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
5264 | pcie_bus_config = PCIE_BUS_SAFE; | |
5265 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
5266 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
5267 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
5268 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
5269 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
5270 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
5271 | } else { |
5272 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
5273 | str); | |
5274 | } | |
1da177e4 LT |
5275 | } |
5276 | str = k; | |
5277 | } | |
0637a70a | 5278 | return 0; |
1da177e4 | 5279 | } |
0637a70a | 5280 | early_param("pci", pci_setup); |