Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
075c1771 | 16 | #include <linux/pm.h> |
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> | |
4e57b681 | 19 | #include <linux/string.h> |
229f5afd | 20 | #include <linux/log2.h> |
7d715a6c | 21 | #include <linux/pci-aspm.h> |
1da177e4 | 22 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 23 | #include "pci.h" |
1da177e4 | 24 | |
ffadcc2f | 25 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 26 | |
32a2eea7 JG |
27 | #ifdef CONFIG_PCI_DOMAINS |
28 | int pci_domains_supported = 1; | |
29 | #endif | |
30 | ||
4516a618 AN |
31 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
32 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
33 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
34 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
35 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
36 | ||
1da177e4 LT |
37 | /** |
38 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
39 | * @bus: pointer to PCI bus structure to search | |
40 | * | |
41 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
42 | * including the given PCI bus and its list of child PCI buses. | |
43 | */ | |
96bde06a | 44 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
45 | { |
46 | struct list_head *tmp; | |
47 | unsigned char max, n; | |
48 | ||
b82db5ce | 49 | max = bus->subordinate; |
1da177e4 LT |
50 | list_for_each(tmp, &bus->children) { |
51 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
52 | if(n > max) | |
53 | max = n; | |
54 | } | |
55 | return max; | |
56 | } | |
b82db5ce | 57 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 58 | |
b82db5ce | 59 | #if 0 |
1da177e4 LT |
60 | /** |
61 | * pci_max_busnr - returns maximum PCI bus number | |
62 | * | |
63 | * Returns the highest PCI bus number present in the system global list of | |
64 | * PCI buses. | |
65 | */ | |
66 | unsigned char __devinit | |
67 | pci_max_busnr(void) | |
68 | { | |
69 | struct pci_bus *bus = NULL; | |
70 | unsigned char max, n; | |
71 | ||
72 | max = 0; | |
73 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
74 | n = pci_bus_max_busnr(bus); | |
75 | if(n > max) | |
76 | max = n; | |
77 | } | |
78 | return max; | |
79 | } | |
80 | ||
54c762fe AB |
81 | #endif /* 0 */ |
82 | ||
687d5fe3 ME |
83 | #define PCI_FIND_CAP_TTL 48 |
84 | ||
85 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
86 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
87 | { |
88 | u8 id; | |
24a4e377 | 89 | |
687d5fe3 | 90 | while ((*ttl)--) { |
24a4e377 RD |
91 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
92 | if (pos < 0x40) | |
93 | break; | |
94 | pos &= ~3; | |
95 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
96 | &id); | |
97 | if (id == 0xff) | |
98 | break; | |
99 | if (id == cap) | |
100 | return pos; | |
101 | pos += PCI_CAP_LIST_NEXT; | |
102 | } | |
103 | return 0; | |
104 | } | |
105 | ||
687d5fe3 ME |
106 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
107 | u8 pos, int cap) | |
108 | { | |
109 | int ttl = PCI_FIND_CAP_TTL; | |
110 | ||
111 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
112 | } | |
113 | ||
24a4e377 RD |
114 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
115 | { | |
116 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
117 | pos + PCI_CAP_LIST_NEXT, cap); | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
120 | ||
d3bac118 ME |
121 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
122 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
123 | { |
124 | u16 status; | |
1da177e4 LT |
125 | |
126 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
127 | if (!(status & PCI_STATUS_CAP_LIST)) | |
128 | return 0; | |
129 | ||
130 | switch (hdr_type) { | |
131 | case PCI_HEADER_TYPE_NORMAL: | |
132 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 133 | return PCI_CAPABILITY_LIST; |
1da177e4 | 134 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 135 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
136 | default: |
137 | return 0; | |
138 | } | |
d3bac118 ME |
139 | |
140 | return 0; | |
1da177e4 LT |
141 | } |
142 | ||
143 | /** | |
144 | * pci_find_capability - query for devices' capabilities | |
145 | * @dev: PCI device to query | |
146 | * @cap: capability code | |
147 | * | |
148 | * Tell if a device supports a given PCI capability. | |
149 | * Returns the address of the requested capability structure within the | |
150 | * device's PCI configuration space or 0 in case the device does not | |
151 | * support it. Possible values for @cap: | |
152 | * | |
153 | * %PCI_CAP_ID_PM Power Management | |
154 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
155 | * %PCI_CAP_ID_VPD Vital Product Data | |
156 | * %PCI_CAP_ID_SLOTID Slot Identification | |
157 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
158 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
159 | * %PCI_CAP_ID_PCIX PCI-X | |
160 | * %PCI_CAP_ID_EXP PCI Express | |
161 | */ | |
162 | int pci_find_capability(struct pci_dev *dev, int cap) | |
163 | { | |
d3bac118 ME |
164 | int pos; |
165 | ||
166 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
167 | if (pos) | |
168 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
169 | ||
170 | return pos; | |
1da177e4 LT |
171 | } |
172 | ||
173 | /** | |
174 | * pci_bus_find_capability - query for devices' capabilities | |
175 | * @bus: the PCI bus to query | |
176 | * @devfn: PCI device to query | |
177 | * @cap: capability code | |
178 | * | |
179 | * Like pci_find_capability() but works for pci devices that do not have a | |
180 | * pci_dev structure set up yet. | |
181 | * | |
182 | * Returns the address of the requested capability structure within the | |
183 | * device's PCI configuration space or 0 in case the device does not | |
184 | * support it. | |
185 | */ | |
186 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
187 | { | |
d3bac118 | 188 | int pos; |
1da177e4 LT |
189 | u8 hdr_type; |
190 | ||
191 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
192 | ||
d3bac118 ME |
193 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
194 | if (pos) | |
195 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
196 | ||
197 | return pos; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
201 | * pci_find_ext_capability - Find an extended capability | |
202 | * @dev: PCI device to query | |
203 | * @cap: capability code | |
204 | * | |
205 | * Returns the address of the requested extended capability structure | |
206 | * within the device's PCI configuration space or 0 if the device does | |
207 | * not support it. Possible values for @cap: | |
208 | * | |
209 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
210 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
211 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
212 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
213 | */ | |
214 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
215 | { | |
216 | u32 header; | |
217 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
218 | int pos = 0x100; | |
219 | ||
220 | if (dev->cfg_size <= 256) | |
221 | return 0; | |
222 | ||
223 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
224 | return 0; | |
225 | ||
226 | /* | |
227 | * If we have no capabilities, this is indicated by cap ID, | |
228 | * cap version and next pointer all being 0. | |
229 | */ | |
230 | if (header == 0) | |
231 | return 0; | |
232 | ||
233 | while (ttl-- > 0) { | |
234 | if (PCI_EXT_CAP_ID(header) == cap) | |
235 | return pos; | |
236 | ||
237 | pos = PCI_EXT_CAP_NEXT(header); | |
238 | if (pos < 0x100) | |
239 | break; | |
240 | ||
241 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
242 | break; | |
243 | } | |
244 | ||
245 | return 0; | |
246 | } | |
3a720d72 | 247 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 248 | |
687d5fe3 ME |
249 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
250 | { | |
251 | int rc, ttl = PCI_FIND_CAP_TTL; | |
252 | u8 cap, mask; | |
253 | ||
254 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
255 | mask = HT_3BIT_CAP_MASK; | |
256 | else | |
257 | mask = HT_5BIT_CAP_MASK; | |
258 | ||
259 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
260 | PCI_CAP_ID_HT, &ttl); | |
261 | while (pos) { | |
262 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
263 | if (rc != PCIBIOS_SUCCESSFUL) | |
264 | return 0; | |
265 | ||
266 | if ((cap & mask) == ht_cap) | |
267 | return pos; | |
268 | ||
47a4d5be BG |
269 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
270 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
271 | PCI_CAP_ID_HT, &ttl); |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | /** | |
277 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
278 | * @dev: PCI device to query | |
279 | * @pos: Position from which to continue searching | |
280 | * @ht_cap: Hypertransport capability code | |
281 | * | |
282 | * To be used in conjunction with pci_find_ht_capability() to search for | |
283 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
284 | * from pci_find_ht_capability(). | |
285 | * | |
286 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
287 | * steps to avoid an infinite loop. | |
288 | */ | |
289 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
290 | { | |
291 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
292 | } | |
293 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
294 | ||
295 | /** | |
296 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
297 | * @dev: PCI device to query | |
298 | * @ht_cap: Hypertransport capability code | |
299 | * | |
300 | * Tell if a device supports a given Hypertransport capability. | |
301 | * Returns an address within the device's PCI configuration space | |
302 | * or 0 in case the device does not support the request capability. | |
303 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
304 | * which has a Hypertransport capability matching @ht_cap. | |
305 | */ | |
306 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
307 | { | |
308 | int pos; | |
309 | ||
310 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
311 | if (pos) | |
312 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
313 | ||
314 | return pos; | |
315 | } | |
316 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
317 | ||
1da177e4 LT |
318 | /** |
319 | * pci_find_parent_resource - return resource region of parent bus of given region | |
320 | * @dev: PCI device structure contains resources to be searched | |
321 | * @res: child resource record for which parent is sought | |
322 | * | |
323 | * For given resource region of given device, return the resource | |
324 | * region of parent bus the given region is contained in or where | |
325 | * it should be allocated from. | |
326 | */ | |
327 | struct resource * | |
328 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
329 | { | |
330 | const struct pci_bus *bus = dev->bus; | |
331 | int i; | |
332 | struct resource *best = NULL; | |
333 | ||
334 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
335 | struct resource *r = bus->resource[i]; | |
336 | if (!r) | |
337 | continue; | |
338 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
339 | continue; /* Not contained */ | |
340 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
341 | continue; /* Wrong type */ | |
342 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
343 | return r; /* Exact match */ | |
344 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
345 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
346 | } | |
347 | return best; | |
348 | } | |
349 | ||
064b53db JL |
350 | /** |
351 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
352 | * @dev: PCI device to have its BARs restored | |
353 | * | |
354 | * Restore the BAR values for a given device, so as to make it | |
355 | * accessible by its driver. | |
356 | */ | |
ad668599 | 357 | static void |
064b53db JL |
358 | pci_restore_bars(struct pci_dev *dev) |
359 | { | |
360 | int i, numres; | |
361 | ||
362 | switch (dev->hdr_type) { | |
363 | case PCI_HEADER_TYPE_NORMAL: | |
364 | numres = 6; | |
365 | break; | |
366 | case PCI_HEADER_TYPE_BRIDGE: | |
367 | numres = 2; | |
368 | break; | |
369 | case PCI_HEADER_TYPE_CARDBUS: | |
370 | numres = 1; | |
371 | break; | |
372 | default: | |
373 | /* Should never get here, but just in case... */ | |
374 | return; | |
375 | } | |
376 | ||
377 | for (i = 0; i < numres; i ++) | |
378 | pci_update_resource(dev, &dev->resource[i], i); | |
379 | } | |
380 | ||
8f7020d3 RD |
381 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
382 | ||
1da177e4 LT |
383 | /** |
384 | * pci_set_power_state - Set the power state of a PCI device | |
385 | * @dev: PCI device to be suspended | |
386 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
387 | * | |
388 | * Transition a device to a new power state, using the Power Management | |
389 | * Capabilities in the device's config space. | |
390 | * | |
391 | * RETURN VALUE: | |
392 | * -EINVAL if trying to enter a lower state than we're already in. | |
393 | * 0 if we're already in the requested state. | |
394 | * -EIO if device does not support PCI PM. | |
395 | * 0 if we can successfully change the power state. | |
396 | */ | |
1da177e4 LT |
397 | int |
398 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
399 | { | |
064b53db | 400 | int pm, need_restore = 0; |
1da177e4 LT |
401 | u16 pmcsr, pmc; |
402 | ||
403 | /* bound the state we're entering */ | |
404 | if (state > PCI_D3hot) | |
405 | state = PCI_D3hot; | |
406 | ||
e36c455c PM |
407 | /* |
408 | * If the device or the parent bridge can't support PCI PM, ignore | |
409 | * the request if we're doing anything besides putting it into D0 | |
410 | * (which would only happen on boot). | |
411 | */ | |
412 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
413 | return 0; | |
414 | ||
cca03dec AL |
415 | /* find PCI PM capability in list */ |
416 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
417 | ||
418 | /* abort if the device doesn't support PM capabilities */ | |
419 | if (!pm) | |
420 | return -EIO; | |
421 | ||
1da177e4 LT |
422 | /* Validate current state: |
423 | * Can enter D0 from any state, but if we can only go deeper | |
424 | * to sleep if we're already in a low power state | |
425 | */ | |
02669492 AM |
426 | if (state != PCI_D0 && dev->current_state > state) { |
427 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
66bef8c0 | 428 | __func__, pci_name(dev), state, dev->current_state); |
1da177e4 | 429 | return -EINVAL; |
02669492 | 430 | } else if (dev->current_state == state) |
1da177e4 LT |
431 | return 0; /* we're already there */ |
432 | ||
ffadcc2f | 433 | |
1da177e4 | 434 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); |
3fe9d19f | 435 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
436 | printk(KERN_DEBUG |
437 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
438 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
439 | return -EIO; | |
440 | } | |
441 | ||
442 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
443 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
444 | return -EIO; | |
445 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
446 | return -EIO; | |
1da177e4 | 447 | |
064b53db JL |
448 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
449 | ||
32a36585 | 450 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
451 | * This doesn't affect PME_Status, disables PME_En, and |
452 | * sets PowerState to 0. | |
453 | */ | |
32a36585 | 454 | switch (dev->current_state) { |
d3535fbb JL |
455 | case PCI_D0: |
456 | case PCI_D1: | |
457 | case PCI_D2: | |
458 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
459 | pmcsr |= state; | |
460 | break; | |
32a36585 JL |
461 | case PCI_UNKNOWN: /* Boot-up */ |
462 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
463 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 464 | need_restore = 1; |
32a36585 | 465 | /* Fall-through: force to D0 */ |
32a36585 | 466 | default: |
d3535fbb | 467 | pmcsr = 0; |
32a36585 | 468 | break; |
1da177e4 LT |
469 | } |
470 | ||
471 | /* enter specified state */ | |
472 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
473 | ||
474 | /* Mandatory power management transition delays */ | |
475 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
476 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 477 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
478 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
479 | udelay(200); | |
1da177e4 | 480 | |
b913100d DSL |
481 | /* |
482 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 483 | * Firmware method after native method ? |
b913100d DSL |
484 | */ |
485 | if (platform_pci_set_power_state) | |
486 | platform_pci_set_power_state(dev, state); | |
487 | ||
488 | dev->current_state = state; | |
064b53db JL |
489 | |
490 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
491 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
492 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
493 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
494 | * For example, at least some versions of the 3c905B and the | |
495 | * 3c556B exhibit this behaviour. | |
496 | * | |
497 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
498 | * devices in a D3hot state at boot. Consequently, we need to | |
499 | * restore at least the BARs so that the device will be | |
500 | * accessible to its driver. | |
501 | */ | |
502 | if (need_restore) | |
503 | pci_restore_bars(dev); | |
504 | ||
7d715a6c SL |
505 | if (dev->bus->self) |
506 | pcie_aspm_pm_state_change(dev->bus->self); | |
507 | ||
1da177e4 LT |
508 | return 0; |
509 | } | |
510 | ||
ab826ca4 | 511 | pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 512 | |
1da177e4 LT |
513 | /** |
514 | * pci_choose_state - Choose the power state of a PCI device | |
515 | * @dev: PCI device to be suspended | |
516 | * @state: target sleep state for the whole system. This is the value | |
517 | * that is passed to suspend() function. | |
518 | * | |
519 | * Returns PCI power state suitable for given device and given system | |
520 | * message. | |
521 | */ | |
522 | ||
523 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
524 | { | |
ab826ca4 | 525 | pci_power_t ret; |
0f64474b | 526 | |
1da177e4 LT |
527 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
528 | return PCI_D0; | |
529 | ||
0f64474b DSL |
530 | if (platform_pci_choose_state) { |
531 | ret = platform_pci_choose_state(dev, state); | |
ab826ca4 SL |
532 | if (ret != PCI_POWER_ERROR) |
533 | return ret; | |
0f64474b | 534 | } |
ca078bae PM |
535 | |
536 | switch (state.event) { | |
537 | case PM_EVENT_ON: | |
538 | return PCI_D0; | |
539 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
540 | case PM_EVENT_PRETHAW: |
541 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 542 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 543 | case PM_EVENT_HIBERNATE: |
ca078bae | 544 | return PCI_D3hot; |
1da177e4 | 545 | default: |
b887d2e6 | 546 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
547 | BUG(); |
548 | } | |
549 | return PCI_D0; | |
550 | } | |
551 | ||
552 | EXPORT_SYMBOL(pci_choose_state); | |
553 | ||
b56a5a23 MT |
554 | static int pci_save_pcie_state(struct pci_dev *dev) |
555 | { | |
556 | int pos, i = 0; | |
557 | struct pci_cap_saved_state *save_state; | |
558 | u16 *cap; | |
017fc480 | 559 | int found = 0; |
b56a5a23 MT |
560 | |
561 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
562 | if (pos <= 0) | |
563 | return 0; | |
564 | ||
9f35575d EB |
565 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
566 | if (!save_state) | |
567 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
568 | else |
569 | found = 1; | |
b56a5a23 MT |
570 | if (!save_state) { |
571 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
572 | return -ENOMEM; | |
573 | } | |
574 | cap = (u16 *)&save_state->data[0]; | |
575 | ||
576 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
577 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
578 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
579 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 580 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
581 | if (!found) |
582 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
583 | return 0; |
584 | } | |
585 | ||
586 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
587 | { | |
588 | int i = 0, pos; | |
589 | struct pci_cap_saved_state *save_state; | |
590 | u16 *cap; | |
591 | ||
592 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
593 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
594 | if (!save_state || pos <= 0) | |
595 | return; | |
596 | cap = (u16 *)&save_state->data[0]; | |
597 | ||
598 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
599 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
600 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
601 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
602 | } |
603 | ||
cc692a5f SH |
604 | |
605 | static int pci_save_pcix_state(struct pci_dev *dev) | |
606 | { | |
607 | int pos, i = 0; | |
608 | struct pci_cap_saved_state *save_state; | |
609 | u16 *cap; | |
017fc480 | 610 | int found = 0; |
cc692a5f SH |
611 | |
612 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
613 | if (pos <= 0) | |
614 | return 0; | |
615 | ||
f34303de | 616 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
617 | if (!save_state) |
618 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
619 | else |
620 | found = 1; | |
cc692a5f SH |
621 | if (!save_state) { |
622 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
623 | return -ENOMEM; | |
624 | } | |
625 | cap = (u16 *)&save_state->data[0]; | |
626 | ||
627 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 628 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
629 | if (!found) |
630 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
631 | return 0; |
632 | } | |
633 | ||
634 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
635 | { | |
636 | int i = 0, pos; | |
637 | struct pci_cap_saved_state *save_state; | |
638 | u16 *cap; | |
639 | ||
640 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
641 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
642 | if (!save_state || pos <= 0) | |
643 | return; | |
644 | cap = (u16 *)&save_state->data[0]; | |
645 | ||
646 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
647 | } |
648 | ||
649 | ||
1da177e4 LT |
650 | /** |
651 | * pci_save_state - save the PCI configuration space of a device before suspending | |
652 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
653 | */ |
654 | int | |
655 | pci_save_state(struct pci_dev *dev) | |
656 | { | |
657 | int i; | |
658 | /* XXX: 100% dword access ok here? */ | |
659 | for (i = 0; i < 16; i++) | |
660 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
661 | if ((i = pci_save_pcie_state(dev)) != 0) |
662 | return i; | |
cc692a5f SH |
663 | if ((i = pci_save_pcix_state(dev)) != 0) |
664 | return i; | |
1da177e4 LT |
665 | return 0; |
666 | } | |
667 | ||
668 | /** | |
669 | * pci_restore_state - Restore the saved state of a PCI device | |
670 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
671 | */ |
672 | int | |
673 | pci_restore_state(struct pci_dev *dev) | |
674 | { | |
675 | int i; | |
b4482a4b | 676 | u32 val; |
1da177e4 | 677 | |
b56a5a23 MT |
678 | /* PCI Express register must be restored first */ |
679 | pci_restore_pcie_state(dev); | |
680 | ||
8b8c8d28 YL |
681 | /* |
682 | * The Base Address register should be programmed before the command | |
683 | * register(s) | |
684 | */ | |
685 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
686 | pci_read_config_dword(dev, i * 4, &val); |
687 | if (val != dev->saved_config_space[i]) { | |
688 | printk(KERN_DEBUG "PM: Writing back config space on " | |
689 | "device %s at offset %x (was %x, writing %x)\n", | |
690 | pci_name(dev), i, | |
691 | val, (int)dev->saved_config_space[i]); | |
692 | pci_write_config_dword(dev,i * 4, | |
693 | dev->saved_config_space[i]); | |
694 | } | |
695 | } | |
cc692a5f | 696 | pci_restore_pcix_state(dev); |
41017f0c | 697 | pci_restore_msi_state(dev); |
8fed4b65 | 698 | |
1da177e4 LT |
699 | return 0; |
700 | } | |
701 | ||
38cc1302 HS |
702 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
703 | { | |
704 | int err; | |
705 | ||
706 | err = pci_set_power_state(dev, PCI_D0); | |
707 | if (err < 0 && err != -EIO) | |
708 | return err; | |
709 | err = pcibios_enable_device(dev, bars); | |
710 | if (err < 0) | |
711 | return err; | |
712 | pci_fixup_device(pci_fixup_enable, dev); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | /** | |
0b62e13b | 718 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
719 | * @dev: PCI device to be resumed |
720 | * | |
721 | * Note this function is a backend of pci_default_resume and is not supposed | |
722 | * to be called by normal code, write proper resume handler and use it instead. | |
723 | */ | |
0b62e13b | 724 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
725 | { |
726 | if (atomic_read(&dev->enable_cnt)) | |
727 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
728 | return 0; | |
729 | } | |
730 | ||
b718989d BH |
731 | static int __pci_enable_device_flags(struct pci_dev *dev, |
732 | resource_size_t flags) | |
1da177e4 LT |
733 | { |
734 | int err; | |
b718989d | 735 | int i, bars = 0; |
1da177e4 | 736 | |
9fb625c3 HS |
737 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
738 | return 0; /* already enabled */ | |
739 | ||
b718989d BH |
740 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
741 | if (dev->resource[i].flags & flags) | |
742 | bars |= (1 << i); | |
743 | ||
38cc1302 | 744 | err = do_pci_enable_device(dev, bars); |
95a62965 | 745 | if (err < 0) |
38cc1302 | 746 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 747 | return err; |
1da177e4 LT |
748 | } |
749 | ||
b718989d BH |
750 | /** |
751 | * pci_enable_device_io - Initialize a device for use with IO space | |
752 | * @dev: PCI device to be initialized | |
753 | * | |
754 | * Initialize device before it's used by a driver. Ask low-level code | |
755 | * to enable I/O resources. Wake up the device if it was suspended. | |
756 | * Beware, this function can fail. | |
757 | */ | |
758 | int pci_enable_device_io(struct pci_dev *dev) | |
759 | { | |
760 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
761 | } | |
762 | ||
763 | /** | |
764 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
765 | * @dev: PCI device to be initialized | |
766 | * | |
767 | * Initialize device before it's used by a driver. Ask low-level code | |
768 | * to enable Memory resources. Wake up the device if it was suspended. | |
769 | * Beware, this function can fail. | |
770 | */ | |
771 | int pci_enable_device_mem(struct pci_dev *dev) | |
772 | { | |
773 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
774 | } | |
775 | ||
bae94d02 IPG |
776 | /** |
777 | * pci_enable_device - Initialize device before it's used by a driver. | |
778 | * @dev: PCI device to be initialized | |
779 | * | |
780 | * Initialize device before it's used by a driver. Ask low-level code | |
781 | * to enable I/O and memory. Wake up the device if it was suspended. | |
782 | * Beware, this function can fail. | |
783 | * | |
784 | * Note we don't actually enable the device many times if we call | |
785 | * this function repeatedly (we just increment the count). | |
786 | */ | |
787 | int pci_enable_device(struct pci_dev *dev) | |
788 | { | |
b718989d | 789 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
790 | } |
791 | ||
9ac7849e TH |
792 | /* |
793 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
794 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
795 | * there's no need to track it separately. pci_devres is initialized | |
796 | * when a device is enabled using managed PCI device enable interface. | |
797 | */ | |
798 | struct pci_devres { | |
7f375f32 TH |
799 | unsigned int enabled:1; |
800 | unsigned int pinned:1; | |
9ac7849e TH |
801 | unsigned int orig_intx:1; |
802 | unsigned int restore_intx:1; | |
803 | u32 region_mask; | |
804 | }; | |
805 | ||
806 | static void pcim_release(struct device *gendev, void *res) | |
807 | { | |
808 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
809 | struct pci_devres *this = res; | |
810 | int i; | |
811 | ||
812 | if (dev->msi_enabled) | |
813 | pci_disable_msi(dev); | |
814 | if (dev->msix_enabled) | |
815 | pci_disable_msix(dev); | |
816 | ||
817 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
818 | if (this->region_mask & (1 << i)) | |
819 | pci_release_region(dev, i); | |
820 | ||
821 | if (this->restore_intx) | |
822 | pci_intx(dev, this->orig_intx); | |
823 | ||
7f375f32 | 824 | if (this->enabled && !this->pinned) |
9ac7849e TH |
825 | pci_disable_device(dev); |
826 | } | |
827 | ||
828 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
829 | { | |
830 | struct pci_devres *dr, *new_dr; | |
831 | ||
832 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
833 | if (dr) | |
834 | return dr; | |
835 | ||
836 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
837 | if (!new_dr) | |
838 | return NULL; | |
839 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
840 | } | |
841 | ||
842 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
843 | { | |
844 | if (pci_is_managed(pdev)) | |
845 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
846 | return NULL; | |
847 | } | |
848 | ||
849 | /** | |
850 | * pcim_enable_device - Managed pci_enable_device() | |
851 | * @pdev: PCI device to be initialized | |
852 | * | |
853 | * Managed pci_enable_device(). | |
854 | */ | |
855 | int pcim_enable_device(struct pci_dev *pdev) | |
856 | { | |
857 | struct pci_devres *dr; | |
858 | int rc; | |
859 | ||
860 | dr = get_pci_dr(pdev); | |
861 | if (unlikely(!dr)) | |
862 | return -ENOMEM; | |
b95d58ea TH |
863 | if (dr->enabled) |
864 | return 0; | |
9ac7849e TH |
865 | |
866 | rc = pci_enable_device(pdev); | |
867 | if (!rc) { | |
868 | pdev->is_managed = 1; | |
7f375f32 | 869 | dr->enabled = 1; |
9ac7849e TH |
870 | } |
871 | return rc; | |
872 | } | |
873 | ||
874 | /** | |
875 | * pcim_pin_device - Pin managed PCI device | |
876 | * @pdev: PCI device to pin | |
877 | * | |
878 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
879 | * driver detach. @pdev must have been enabled with | |
880 | * pcim_enable_device(). | |
881 | */ | |
882 | void pcim_pin_device(struct pci_dev *pdev) | |
883 | { | |
884 | struct pci_devres *dr; | |
885 | ||
886 | dr = find_pci_dr(pdev); | |
7f375f32 | 887 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 888 | if (dr) |
7f375f32 | 889 | dr->pinned = 1; |
9ac7849e TH |
890 | } |
891 | ||
1da177e4 LT |
892 | /** |
893 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
894 | * @dev: the PCI device to disable | |
895 | * | |
896 | * Disables architecture specific PCI resources for the device. This | |
897 | * is the default implementation. Architecture implementations can | |
898 | * override this. | |
899 | */ | |
900 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
901 | ||
902 | /** | |
903 | * pci_disable_device - Disable PCI device after use | |
904 | * @dev: PCI device to be disabled | |
905 | * | |
906 | * Signal to the system that the PCI device is not in use by the system | |
907 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
908 | * |
909 | * Note we don't actually disable the device until all callers of | |
910 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
911 | */ |
912 | void | |
913 | pci_disable_device(struct pci_dev *dev) | |
914 | { | |
9ac7849e | 915 | struct pci_devres *dr; |
1da177e4 | 916 | u16 pci_command; |
99dc804d | 917 | |
9ac7849e TH |
918 | dr = find_pci_dr(dev); |
919 | if (dr) | |
7f375f32 | 920 | dr->enabled = 0; |
9ac7849e | 921 | |
bae94d02 IPG |
922 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
923 | return; | |
924 | ||
1da177e4 LT |
925 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
926 | if (pci_command & PCI_COMMAND_MASTER) { | |
927 | pci_command &= ~PCI_COMMAND_MASTER; | |
928 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
929 | } | |
ceb43744 | 930 | dev->is_busmaster = 0; |
1da177e4 LT |
931 | |
932 | pcibios_disable_device(dev); | |
933 | } | |
934 | ||
f7bdd12d BK |
935 | /** |
936 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
937 | * @dev: the PCI-E device reset | |
938 | * @state: Reset state to enter into | |
939 | * | |
940 | * | |
941 | * Sets the PCI-E reset state for the device. This is the default | |
942 | * implementation. Architecture implementations can override this. | |
943 | */ | |
944 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
945 | enum pcie_reset_state state) | |
946 | { | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
950 | /** | |
951 | * pci_set_pcie_reset_state - set reset state for device dev | |
952 | * @dev: the PCI-E device reset | |
953 | * @state: Reset state to enter into | |
954 | * | |
955 | * | |
956 | * Sets the PCI reset state for the device. | |
957 | */ | |
958 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
959 | { | |
960 | return pcibios_set_pcie_reset_state(dev, state); | |
961 | } | |
962 | ||
1da177e4 | 963 | /** |
075c1771 DB |
964 | * pci_enable_wake - enable PCI device as wakeup event source |
965 | * @dev: PCI device affected | |
966 | * @state: PCI state from which device will issue wakeup events | |
967 | * @enable: True to enable event generation; false to disable | |
968 | * | |
969 | * This enables the device as a wakeup event source, or disables it. | |
970 | * When such events involves platform-specific hooks, those hooks are | |
971 | * called automatically by this routine. | |
972 | * | |
973 | * Devices with legacy power management (no standard PCI PM capabilities) | |
974 | * always require such platform hooks. Depending on the platform, devices | |
975 | * supporting the standard PCI PME# signal may require such platform hooks; | |
976 | * they always update bits in config space to allow PME# generation. | |
977 | * | |
978 | * -EIO is returned if the device can't ever be a wakeup event source. | |
979 | * -EINVAL is returned if the device can't generate wakeup events from | |
980 | * the specified PCI state. Returns zero if the operation is successful. | |
1da177e4 LT |
981 | */ |
982 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
983 | { | |
984 | int pm; | |
075c1771 | 985 | int status; |
1da177e4 LT |
986 | u16 value; |
987 | ||
075c1771 DB |
988 | /* Note that drivers should verify device_may_wakeup(&dev->dev) |
989 | * before calling this function. Platform code should report | |
990 | * errors when drivers try to enable wakeup on devices that | |
991 | * can't issue wakeups, or on which wakeups were disabled by | |
992 | * userspace updating the /sys/devices.../power/wakeup file. | |
993 | */ | |
994 | ||
995 | status = call_platform_enable_wakeup(&dev->dev, enable); | |
996 | ||
1da177e4 LT |
997 | /* find PCI PM capability in list */ |
998 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
999 | ||
075c1771 DB |
1000 | /* If device doesn't support PM Capabilities, but caller wants to |
1001 | * disable wake events, it's a NOP. Otherwise fail unless the | |
1002 | * platform hooks handled this legacy device already. | |
1003 | */ | |
1004 | if (!pm) | |
1005 | return enable ? status : 0; | |
1da177e4 LT |
1006 | |
1007 | /* Check device's ability to generate PME# */ | |
1008 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
1009 | ||
1010 | value &= PCI_PM_CAP_PME_MASK; | |
1011 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
1012 | ||
1013 | /* Check if it can generate PME# from requested state. */ | |
075c1771 DB |
1014 | if (!value || !(value & (1 << state))) { |
1015 | /* if it can't, revert what the platform hook changed, | |
1016 | * always reporting the base "EINVAL, can't PME#" error | |
1017 | */ | |
1018 | if (enable) | |
1019 | call_platform_enable_wakeup(&dev->dev, 0); | |
1da177e4 | 1020 | return enable ? -EINVAL : 0; |
075c1771 | 1021 | } |
1da177e4 LT |
1022 | |
1023 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
1024 | ||
1025 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
1026 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1027 | ||
1028 | if (!enable) | |
1029 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
1030 | ||
1031 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
075c1771 | 1032 | |
1da177e4 LT |
1033 | return 0; |
1034 | } | |
1035 | ||
1036 | int | |
1037 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1038 | { | |
1039 | u8 pin; | |
1040 | ||
514d207d | 1041 | pin = dev->pin; |
1da177e4 LT |
1042 | if (!pin) |
1043 | return -1; | |
1044 | pin--; | |
1045 | while (dev->bus->self) { | |
1046 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1047 | dev = dev->bus->self; | |
1048 | } | |
1049 | *bridge = dev; | |
1050 | return pin; | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * pci_release_region - Release a PCI bar | |
1055 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1056 | * @bar: BAR to release | |
1057 | * | |
1058 | * Releases the PCI I/O and memory resources previously reserved by a | |
1059 | * successful call to pci_request_region. Call this function only | |
1060 | * after all use of the PCI regions has ceased. | |
1061 | */ | |
1062 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1063 | { | |
9ac7849e TH |
1064 | struct pci_devres *dr; |
1065 | ||
1da177e4 LT |
1066 | if (pci_resource_len(pdev, bar) == 0) |
1067 | return; | |
1068 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1069 | release_region(pci_resource_start(pdev, bar), | |
1070 | pci_resource_len(pdev, bar)); | |
1071 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1072 | release_mem_region(pci_resource_start(pdev, bar), | |
1073 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1074 | |
1075 | dr = find_pci_dr(pdev); | |
1076 | if (dr) | |
1077 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1078 | } |
1079 | ||
1080 | /** | |
1081 | * pci_request_region - Reserved PCI I/O and memory resource | |
1082 | * @pdev: PCI device whose resources are to be reserved | |
1083 | * @bar: BAR to be reserved | |
1084 | * @res_name: Name to be associated with resource. | |
1085 | * | |
1086 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1087 | * being reserved by owner @res_name. Do not access any | |
1088 | * address inside the PCI regions unless this call returns | |
1089 | * successfully. | |
1090 | * | |
1091 | * Returns 0 on success, or %EBUSY on error. A warning | |
1092 | * message is also printed on failure. | |
1093 | */ | |
3c990e92 | 1094 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1095 | { |
9ac7849e TH |
1096 | struct pci_devres *dr; |
1097 | ||
1da177e4 LT |
1098 | if (pci_resource_len(pdev, bar) == 0) |
1099 | return 0; | |
1100 | ||
1101 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1102 | if (!request_region(pci_resource_start(pdev, bar), | |
1103 | pci_resource_len(pdev, bar), res_name)) | |
1104 | goto err_out; | |
1105 | } | |
1106 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1107 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1108 | pci_resource_len(pdev, bar), res_name)) | |
1109 | goto err_out; | |
1110 | } | |
9ac7849e TH |
1111 | |
1112 | dr = find_pci_dr(pdev); | |
1113 | if (dr) | |
1114 | dr->region_mask |= 1 << bar; | |
1115 | ||
1da177e4 LT |
1116 | return 0; |
1117 | ||
1118 | err_out: | |
1396a8c3 GKH |
1119 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
1120 | "for device %s\n", | |
1da177e4 LT |
1121 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
1122 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
1123 | (unsigned long long)pci_resource_len(pdev, bar), |
1124 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
1125 | pci_name(pdev)); |
1126 | return -EBUSY; | |
1127 | } | |
1128 | ||
c87deff7 HS |
1129 | /** |
1130 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1131 | * @pdev: PCI device whose resources were previously reserved | |
1132 | * @bars: Bitmask of BARs to be released | |
1133 | * | |
1134 | * Release selected PCI I/O and memory resources previously reserved. | |
1135 | * Call this function only after all use of the PCI regions has ceased. | |
1136 | */ | |
1137 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1138 | { | |
1139 | int i; | |
1140 | ||
1141 | for (i = 0; i < 6; i++) | |
1142 | if (bars & (1 << i)) | |
1143 | pci_release_region(pdev, i); | |
1144 | } | |
1145 | ||
1146 | /** | |
1147 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1148 | * @pdev: PCI device whose resources are to be reserved | |
1149 | * @bars: Bitmask of BARs to be requested | |
1150 | * @res_name: Name to be associated with resource | |
1151 | */ | |
1152 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1153 | const char *res_name) | |
1154 | { | |
1155 | int i; | |
1156 | ||
1157 | for (i = 0; i < 6; i++) | |
1158 | if (bars & (1 << i)) | |
1159 | if(pci_request_region(pdev, i, res_name)) | |
1160 | goto err_out; | |
1161 | return 0; | |
1162 | ||
1163 | err_out: | |
1164 | while(--i >= 0) | |
1165 | if (bars & (1 << i)) | |
1166 | pci_release_region(pdev, i); | |
1167 | ||
1168 | return -EBUSY; | |
1169 | } | |
1da177e4 LT |
1170 | |
1171 | /** | |
1172 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1173 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1174 | * | |
1175 | * Releases all PCI I/O and memory resources previously reserved by a | |
1176 | * successful call to pci_request_regions. Call this function only | |
1177 | * after all use of the PCI regions has ceased. | |
1178 | */ | |
1179 | ||
1180 | void pci_release_regions(struct pci_dev *pdev) | |
1181 | { | |
c87deff7 | 1182 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1183 | } |
1184 | ||
1185 | /** | |
1186 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1187 | * @pdev: PCI device whose resources are to be reserved | |
1188 | * @res_name: Name to be associated with resource. | |
1189 | * | |
1190 | * Mark all PCI regions associated with PCI device @pdev as | |
1191 | * being reserved by owner @res_name. Do not access any | |
1192 | * address inside the PCI regions unless this call returns | |
1193 | * successfully. | |
1194 | * | |
1195 | * Returns 0 on success, or %EBUSY on error. A warning | |
1196 | * message is also printed on failure. | |
1197 | */ | |
3c990e92 | 1198 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1199 | { |
c87deff7 | 1200 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1201 | } |
1202 | ||
1203 | /** | |
1204 | * pci_set_master - enables bus-mastering for device dev | |
1205 | * @dev: the PCI device to enable | |
1206 | * | |
1207 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1208 | * to do the needed arch specific settings. | |
1209 | */ | |
1210 | void | |
1211 | pci_set_master(struct pci_dev *dev) | |
1212 | { | |
1213 | u16 cmd; | |
1214 | ||
1215 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1216 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
1217 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
1218 | cmd |= PCI_COMMAND_MASTER; | |
1219 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1220 | } | |
1221 | dev->is_busmaster = 1; | |
1222 | pcibios_set_master(dev); | |
1223 | } | |
1224 | ||
edb2d97e MW |
1225 | #ifdef PCI_DISABLE_MWI |
1226 | int pci_set_mwi(struct pci_dev *dev) | |
1227 | { | |
1228 | return 0; | |
1229 | } | |
1230 | ||
694625c0 RD |
1231 | int pci_try_set_mwi(struct pci_dev *dev) |
1232 | { | |
1233 | return 0; | |
1234 | } | |
1235 | ||
edb2d97e MW |
1236 | void pci_clear_mwi(struct pci_dev *dev) |
1237 | { | |
1238 | } | |
1239 | ||
1240 | #else | |
ebf5a248 MW |
1241 | |
1242 | #ifndef PCI_CACHE_LINE_BYTES | |
1243 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1244 | #endif | |
1245 | ||
1da177e4 | 1246 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1247 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1248 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1249 | |
1250 | /** | |
edb2d97e MW |
1251 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1252 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1253 | * |
edb2d97e MW |
1254 | * Helper function for pci_set_mwi. |
1255 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1256 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1257 | * | |
1258 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1259 | */ | |
1260 | static int | |
edb2d97e | 1261 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1262 | { |
1263 | u8 cacheline_size; | |
1264 | ||
1265 | if (!pci_cache_line_size) | |
1266 | return -EINVAL; /* The system doesn't support MWI. */ | |
1267 | ||
1268 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1269 | equal to or multiple of the right value. */ | |
1270 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1271 | if (cacheline_size >= pci_cache_line_size && | |
1272 | (cacheline_size % pci_cache_line_size) == 0) | |
1273 | return 0; | |
1274 | ||
1275 | /* Write the correct value. */ | |
1276 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1277 | /* Read it back. */ | |
1278 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1279 | if (cacheline_size == pci_cache_line_size) | |
1280 | return 0; | |
1281 | ||
1282 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
1283 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
1284 | ||
1285 | return -EINVAL; | |
1286 | } | |
1da177e4 LT |
1287 | |
1288 | /** | |
1289 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1290 | * @dev: the PCI device for which MWI is enabled | |
1291 | * | |
694625c0 | 1292 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1293 | * |
1294 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1295 | */ | |
1296 | int | |
1297 | pci_set_mwi(struct pci_dev *dev) | |
1298 | { | |
1299 | int rc; | |
1300 | u16 cmd; | |
1301 | ||
edb2d97e | 1302 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1303 | if (rc) |
1304 | return rc; | |
1305 | ||
1306 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1307 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
694625c0 RD |
1308 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", |
1309 | pci_name(dev)); | |
1da177e4 LT |
1310 | cmd |= PCI_COMMAND_INVALIDATE; |
1311 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1312 | } | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
694625c0 RD |
1317 | /** |
1318 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1319 | * @dev: the PCI device for which MWI is enabled | |
1320 | * | |
1321 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1322 | * Callers are not required to check the return value. | |
1323 | * | |
1324 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1325 | */ | |
1326 | int pci_try_set_mwi(struct pci_dev *dev) | |
1327 | { | |
1328 | int rc = pci_set_mwi(dev); | |
1329 | return rc; | |
1330 | } | |
1331 | ||
1da177e4 LT |
1332 | /** |
1333 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1334 | * @dev: the PCI device to disable | |
1335 | * | |
1336 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1337 | */ | |
1338 | void | |
1339 | pci_clear_mwi(struct pci_dev *dev) | |
1340 | { | |
1341 | u16 cmd; | |
1342 | ||
1343 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1344 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1345 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1346 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1347 | } | |
1348 | } | |
edb2d97e | 1349 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1350 | |
a04ce0ff BR |
1351 | /** |
1352 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1353 | * @pdev: the PCI device to operate on |
1354 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1355 | * |
1356 | * Enables/disables PCI INTx for device dev | |
1357 | */ | |
1358 | void | |
1359 | pci_intx(struct pci_dev *pdev, int enable) | |
1360 | { | |
1361 | u16 pci_command, new; | |
1362 | ||
1363 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1364 | ||
1365 | if (enable) { | |
1366 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1367 | } else { | |
1368 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1369 | } | |
1370 | ||
1371 | if (new != pci_command) { | |
9ac7849e TH |
1372 | struct pci_devres *dr; |
1373 | ||
2fd9d74b | 1374 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1375 | |
1376 | dr = find_pci_dr(pdev); | |
1377 | if (dr && !dr->restore_intx) { | |
1378 | dr->restore_intx = 1; | |
1379 | dr->orig_intx = !enable; | |
1380 | } | |
a04ce0ff BR |
1381 | } |
1382 | } | |
1383 | ||
f5f2b131 EB |
1384 | /** |
1385 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1386 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1387 | * |
1388 | * If you want to use msi see pci_enable_msi and friends. | |
1389 | * This is a lower level primitive that allows us to disable | |
1390 | * msi operation at the device level. | |
1391 | */ | |
1392 | void pci_msi_off(struct pci_dev *dev) | |
1393 | { | |
1394 | int pos; | |
1395 | u16 control; | |
1396 | ||
1397 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1398 | if (pos) { | |
1399 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1400 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1401 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1402 | } | |
1403 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1404 | if (pos) { | |
1405 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1406 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1407 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1408 | } | |
1409 | } | |
1410 | ||
1da177e4 LT |
1411 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1412 | /* | |
1413 | * These can be overridden by arch-specific implementations | |
1414 | */ | |
1415 | int | |
1416 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1417 | { | |
1418 | if (!pci_dma_supported(dev, mask)) | |
1419 | return -EIO; | |
1420 | ||
1421 | dev->dma_mask = mask; | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
1da177e4 LT |
1426 | int |
1427 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1428 | { | |
1429 | if (!pci_dma_supported(dev, mask)) | |
1430 | return -EIO; | |
1431 | ||
1432 | dev->dev.coherent_dma_mask = mask; | |
1433 | ||
1434 | return 0; | |
1435 | } | |
1436 | #endif | |
c87deff7 | 1437 | |
4d57cdfa FT |
1438 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1439 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1440 | { | |
1441 | return dma_set_max_seg_size(&dev->dev, size); | |
1442 | } | |
1443 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1444 | #endif | |
1445 | ||
59fc67de FT |
1446 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1447 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1448 | { | |
1449 | return dma_set_seg_boundary(&dev->dev, mask); | |
1450 | } | |
1451 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1452 | #endif | |
1453 | ||
d556ad4b PO |
1454 | /** |
1455 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1456 | * @dev: PCI device to query | |
1457 | * | |
1458 | * Returns mmrbc: maximum designed memory read count in bytes | |
1459 | * or appropriate error value. | |
1460 | */ | |
1461 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1462 | { | |
b7b095c1 | 1463 | int err, cap; |
d556ad4b PO |
1464 | u32 stat; |
1465 | ||
1466 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1467 | if (!cap) | |
1468 | return -EINVAL; | |
1469 | ||
1470 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1471 | if (err) | |
1472 | return -EINVAL; | |
1473 | ||
b7b095c1 | 1474 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1475 | } |
1476 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1477 | ||
1478 | /** | |
1479 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1480 | * @dev: PCI device to query | |
1481 | * | |
1482 | * Returns mmrbc: maximum memory read count in bytes | |
1483 | * or appropriate error value. | |
1484 | */ | |
1485 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1486 | { | |
1487 | int ret, cap; | |
1488 | u32 cmd; | |
1489 | ||
1490 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1491 | if (!cap) | |
1492 | return -EINVAL; | |
1493 | ||
1494 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1495 | if (!ret) | |
1496 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1497 | ||
1498 | return ret; | |
1499 | } | |
1500 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1501 | ||
1502 | /** | |
1503 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1504 | * @dev: PCI device to query | |
1505 | * @mmrbc: maximum memory read count in bytes | |
1506 | * valid values are 512, 1024, 2048, 4096 | |
1507 | * | |
1508 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1509 | * that prevent this. | |
1510 | */ | |
1511 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1512 | { | |
1513 | int cap, err = -EINVAL; | |
1514 | u32 stat, cmd, v, o; | |
1515 | ||
229f5afd | 1516 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1517 | goto out; |
1518 | ||
1519 | v = ffs(mmrbc) - 10; | |
1520 | ||
1521 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1522 | if (!cap) | |
1523 | goto out; | |
1524 | ||
1525 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1526 | if (err) | |
1527 | goto out; | |
1528 | ||
1529 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1530 | return -E2BIG; | |
1531 | ||
1532 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1533 | if (err) | |
1534 | goto out; | |
1535 | ||
1536 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1537 | if (o != v) { | |
1538 | if (v > o && dev->bus && | |
1539 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1540 | return -EIO; | |
1541 | ||
1542 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1543 | cmd |= v << 2; | |
1544 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1545 | } | |
1546 | out: | |
1547 | return err; | |
1548 | } | |
1549 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1550 | ||
1551 | /** | |
1552 | * pcie_get_readrq - get PCI Express read request size | |
1553 | * @dev: PCI device to query | |
1554 | * | |
1555 | * Returns maximum memory read request in bytes | |
1556 | * or appropriate error value. | |
1557 | */ | |
1558 | int pcie_get_readrq(struct pci_dev *dev) | |
1559 | { | |
1560 | int ret, cap; | |
1561 | u16 ctl; | |
1562 | ||
1563 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1564 | if (!cap) | |
1565 | return -EINVAL; | |
1566 | ||
1567 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1568 | if (!ret) | |
1569 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1570 | ||
1571 | return ret; | |
1572 | } | |
1573 | EXPORT_SYMBOL(pcie_get_readrq); | |
1574 | ||
1575 | /** | |
1576 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1577 | * @dev: PCI device to query | |
42e61f4a | 1578 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1579 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1580 | * | |
1581 | * If possible sets maximum read byte count | |
1582 | */ | |
1583 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1584 | { | |
1585 | int cap, err = -EINVAL; | |
1586 | u16 ctl, v; | |
1587 | ||
229f5afd | 1588 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1589 | goto out; |
1590 | ||
1591 | v = (ffs(rq) - 8) << 12; | |
1592 | ||
1593 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1594 | if (!cap) | |
1595 | goto out; | |
1596 | ||
1597 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1598 | if (err) | |
1599 | goto out; | |
1600 | ||
1601 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1602 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1603 | ctl |= v; | |
1604 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1605 | } | |
1606 | ||
1607 | out: | |
1608 | return err; | |
1609 | } | |
1610 | EXPORT_SYMBOL(pcie_set_readrq); | |
1611 | ||
c87deff7 HS |
1612 | /** |
1613 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1614 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1615 | * @flags: resource type mask to be selected |
1616 | * | |
1617 | * This helper routine makes bar mask from the type of resource. | |
1618 | */ | |
1619 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1620 | { | |
1621 | int i, bars = 0; | |
1622 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1623 | if (pci_resource_flags(dev, i) & flags) | |
1624 | bars |= (1 << i); | |
1625 | return bars; | |
1626 | } | |
1627 | ||
32a2eea7 JG |
1628 | static void __devinit pci_no_domains(void) |
1629 | { | |
1630 | #ifdef CONFIG_PCI_DOMAINS | |
1631 | pci_domains_supported = 0; | |
1632 | #endif | |
1633 | } | |
1634 | ||
1da177e4 LT |
1635 | static int __devinit pci_init(void) |
1636 | { | |
1637 | struct pci_dev *dev = NULL; | |
1638 | ||
1639 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1640 | pci_fixup_device(pci_fixup_final, dev); | |
1641 | } | |
1642 | return 0; | |
1643 | } | |
1644 | ||
1645 | static int __devinit pci_setup(char *str) | |
1646 | { | |
1647 | while (str) { | |
1648 | char *k = strchr(str, ','); | |
1649 | if (k) | |
1650 | *k++ = 0; | |
1651 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1652 | if (!strcmp(str, "nomsi")) { |
1653 | pci_no_msi(); | |
7f785763 RD |
1654 | } else if (!strcmp(str, "noaer")) { |
1655 | pci_no_aer(); | |
32a2eea7 JG |
1656 | } else if (!strcmp(str, "nodomains")) { |
1657 | pci_no_domains(); | |
4516a618 AN |
1658 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1659 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1660 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1661 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1662 | } else { |
1663 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1664 | str); | |
1665 | } | |
1da177e4 LT |
1666 | } |
1667 | str = k; | |
1668 | } | |
0637a70a | 1669 | return 0; |
1da177e4 | 1670 | } |
0637a70a | 1671 | early_param("pci", pci_setup); |
1da177e4 LT |
1672 | |
1673 | device_initcall(pci_init); | |
1da177e4 | 1674 | |
0b62e13b | 1675 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
1676 | EXPORT_SYMBOL(pci_enable_device_io); |
1677 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 1678 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
1679 | EXPORT_SYMBOL(pcim_enable_device); |
1680 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1681 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1682 | EXPORT_SYMBOL(pci_find_capability); |
1683 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1684 | EXPORT_SYMBOL(pci_release_regions); | |
1685 | EXPORT_SYMBOL(pci_request_regions); | |
1686 | EXPORT_SYMBOL(pci_release_region); | |
1687 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1688 | EXPORT_SYMBOL(pci_release_selected_regions); |
1689 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1690 | EXPORT_SYMBOL(pci_set_master); |
1691 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1692 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1693 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1694 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1695 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1696 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1697 | EXPORT_SYMBOL(pci_assign_resource); | |
1698 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1699 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1700 | |
1701 | EXPORT_SYMBOL(pci_set_power_state); | |
1702 | EXPORT_SYMBOL(pci_save_state); | |
1703 | EXPORT_SYMBOL(pci_restore_state); | |
1704 | EXPORT_SYMBOL(pci_enable_wake); | |
f7bdd12d | 1705 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1706 |