Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
075c1771 | 16 | #include <linux/pm.h> |
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> | |
4e57b681 | 19 | #include <linux/string.h> |
229f5afd | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 22 | #include "pci.h" |
1da177e4 | 23 | |
ffadcc2f | 24 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 25 | |
32a2eea7 JG |
26 | #ifdef CONFIG_PCI_DOMAINS |
27 | int pci_domains_supported = 1; | |
28 | #endif | |
29 | ||
4516a618 AN |
30 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
31 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
32 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
33 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
34 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
35 | ||
1da177e4 LT |
36 | /** |
37 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
38 | * @bus: pointer to PCI bus structure to search | |
39 | * | |
40 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
41 | * including the given PCI bus and its list of child PCI buses. | |
42 | */ | |
96bde06a | 43 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
44 | { |
45 | struct list_head *tmp; | |
46 | unsigned char max, n; | |
47 | ||
b82db5ce | 48 | max = bus->subordinate; |
1da177e4 LT |
49 | list_for_each(tmp, &bus->children) { |
50 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
51 | if(n > max) | |
52 | max = n; | |
53 | } | |
54 | return max; | |
55 | } | |
b82db5ce | 56 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 57 | |
b82db5ce | 58 | #if 0 |
1da177e4 LT |
59 | /** |
60 | * pci_max_busnr - returns maximum PCI bus number | |
61 | * | |
62 | * Returns the highest PCI bus number present in the system global list of | |
63 | * PCI buses. | |
64 | */ | |
65 | unsigned char __devinit | |
66 | pci_max_busnr(void) | |
67 | { | |
68 | struct pci_bus *bus = NULL; | |
69 | unsigned char max, n; | |
70 | ||
71 | max = 0; | |
72 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
73 | n = pci_bus_max_busnr(bus); | |
74 | if(n > max) | |
75 | max = n; | |
76 | } | |
77 | return max; | |
78 | } | |
79 | ||
54c762fe AB |
80 | #endif /* 0 */ |
81 | ||
687d5fe3 ME |
82 | #define PCI_FIND_CAP_TTL 48 |
83 | ||
84 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
85 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
86 | { |
87 | u8 id; | |
24a4e377 | 88 | |
687d5fe3 | 89 | while ((*ttl)--) { |
24a4e377 RD |
90 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
91 | if (pos < 0x40) | |
92 | break; | |
93 | pos &= ~3; | |
94 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
95 | &id); | |
96 | if (id == 0xff) | |
97 | break; | |
98 | if (id == cap) | |
99 | return pos; | |
100 | pos += PCI_CAP_LIST_NEXT; | |
101 | } | |
102 | return 0; | |
103 | } | |
104 | ||
687d5fe3 ME |
105 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
106 | u8 pos, int cap) | |
107 | { | |
108 | int ttl = PCI_FIND_CAP_TTL; | |
109 | ||
110 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
111 | } | |
112 | ||
24a4e377 RD |
113 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
114 | { | |
115 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
116 | pos + PCI_CAP_LIST_NEXT, cap); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
119 | ||
d3bac118 ME |
120 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
121 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
122 | { |
123 | u16 status; | |
1da177e4 LT |
124 | |
125 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
126 | if (!(status & PCI_STATUS_CAP_LIST)) | |
127 | return 0; | |
128 | ||
129 | switch (hdr_type) { | |
130 | case PCI_HEADER_TYPE_NORMAL: | |
131 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 132 | return PCI_CAPABILITY_LIST; |
1da177e4 | 133 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 134 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
135 | default: |
136 | return 0; | |
137 | } | |
d3bac118 ME |
138 | |
139 | return 0; | |
1da177e4 LT |
140 | } |
141 | ||
142 | /** | |
143 | * pci_find_capability - query for devices' capabilities | |
144 | * @dev: PCI device to query | |
145 | * @cap: capability code | |
146 | * | |
147 | * Tell if a device supports a given PCI capability. | |
148 | * Returns the address of the requested capability structure within the | |
149 | * device's PCI configuration space or 0 in case the device does not | |
150 | * support it. Possible values for @cap: | |
151 | * | |
152 | * %PCI_CAP_ID_PM Power Management | |
153 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
154 | * %PCI_CAP_ID_VPD Vital Product Data | |
155 | * %PCI_CAP_ID_SLOTID Slot Identification | |
156 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
157 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
158 | * %PCI_CAP_ID_PCIX PCI-X | |
159 | * %PCI_CAP_ID_EXP PCI Express | |
160 | */ | |
161 | int pci_find_capability(struct pci_dev *dev, int cap) | |
162 | { | |
d3bac118 ME |
163 | int pos; |
164 | ||
165 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
166 | if (pos) | |
167 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
168 | ||
169 | return pos; | |
1da177e4 LT |
170 | } |
171 | ||
172 | /** | |
173 | * pci_bus_find_capability - query for devices' capabilities | |
174 | * @bus: the PCI bus to query | |
175 | * @devfn: PCI device to query | |
176 | * @cap: capability code | |
177 | * | |
178 | * Like pci_find_capability() but works for pci devices that do not have a | |
179 | * pci_dev structure set up yet. | |
180 | * | |
181 | * Returns the address of the requested capability structure within the | |
182 | * device's PCI configuration space or 0 in case the device does not | |
183 | * support it. | |
184 | */ | |
185 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
186 | { | |
d3bac118 | 187 | int pos; |
1da177e4 LT |
188 | u8 hdr_type; |
189 | ||
190 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
191 | ||
d3bac118 ME |
192 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
193 | if (pos) | |
194 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
195 | ||
196 | return pos; | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
200 | * pci_find_ext_capability - Find an extended capability | |
201 | * @dev: PCI device to query | |
202 | * @cap: capability code | |
203 | * | |
204 | * Returns the address of the requested extended capability structure | |
205 | * within the device's PCI configuration space or 0 if the device does | |
206 | * not support it. Possible values for @cap: | |
207 | * | |
208 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
209 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
210 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
211 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
212 | */ | |
213 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
214 | { | |
215 | u32 header; | |
216 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
217 | int pos = 0x100; | |
218 | ||
219 | if (dev->cfg_size <= 256) | |
220 | return 0; | |
221 | ||
222 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
223 | return 0; | |
224 | ||
225 | /* | |
226 | * If we have no capabilities, this is indicated by cap ID, | |
227 | * cap version and next pointer all being 0. | |
228 | */ | |
229 | if (header == 0) | |
230 | return 0; | |
231 | ||
232 | while (ttl-- > 0) { | |
233 | if (PCI_EXT_CAP_ID(header) == cap) | |
234 | return pos; | |
235 | ||
236 | pos = PCI_EXT_CAP_NEXT(header); | |
237 | if (pos < 0x100) | |
238 | break; | |
239 | ||
240 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
241 | break; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
3a720d72 | 246 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 247 | |
687d5fe3 ME |
248 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
249 | { | |
250 | int rc, ttl = PCI_FIND_CAP_TTL; | |
251 | u8 cap, mask; | |
252 | ||
253 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
254 | mask = HT_3BIT_CAP_MASK; | |
255 | else | |
256 | mask = HT_5BIT_CAP_MASK; | |
257 | ||
258 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
259 | PCI_CAP_ID_HT, &ttl); | |
260 | while (pos) { | |
261 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
262 | if (rc != PCIBIOS_SUCCESSFUL) | |
263 | return 0; | |
264 | ||
265 | if ((cap & mask) == ht_cap) | |
266 | return pos; | |
267 | ||
47a4d5be BG |
268 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
269 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
270 | PCI_CAP_ID_HT, &ttl); |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | /** | |
276 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
277 | * @dev: PCI device to query | |
278 | * @pos: Position from which to continue searching | |
279 | * @ht_cap: Hypertransport capability code | |
280 | * | |
281 | * To be used in conjunction with pci_find_ht_capability() to search for | |
282 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
283 | * from pci_find_ht_capability(). | |
284 | * | |
285 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
286 | * steps to avoid an infinite loop. | |
287 | */ | |
288 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
289 | { | |
290 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
291 | } | |
292 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
293 | ||
294 | /** | |
295 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
296 | * @dev: PCI device to query | |
297 | * @ht_cap: Hypertransport capability code | |
298 | * | |
299 | * Tell if a device supports a given Hypertransport capability. | |
300 | * Returns an address within the device's PCI configuration space | |
301 | * or 0 in case the device does not support the request capability. | |
302 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
303 | * which has a Hypertransport capability matching @ht_cap. | |
304 | */ | |
305 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
306 | { | |
307 | int pos; | |
308 | ||
309 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
310 | if (pos) | |
311 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
312 | ||
313 | return pos; | |
314 | } | |
315 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
316 | ||
4348a2dc SL |
317 | void pcie_wait_pending_transaction(struct pci_dev *dev) |
318 | { | |
319 | int pos; | |
320 | u16 reg16; | |
321 | ||
322 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
323 | if (!pos) | |
324 | return; | |
325 | while (1) { | |
326 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); | |
327 | if (!(reg16 & PCI_EXP_DEVSTA_TRPND)) | |
328 | break; | |
329 | cpu_relax(); | |
330 | } | |
331 | ||
332 | } | |
333 | EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction); | |
334 | ||
1da177e4 LT |
335 | /** |
336 | * pci_find_parent_resource - return resource region of parent bus of given region | |
337 | * @dev: PCI device structure contains resources to be searched | |
338 | * @res: child resource record for which parent is sought | |
339 | * | |
340 | * For given resource region of given device, return the resource | |
341 | * region of parent bus the given region is contained in or where | |
342 | * it should be allocated from. | |
343 | */ | |
344 | struct resource * | |
345 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
346 | { | |
347 | const struct pci_bus *bus = dev->bus; | |
348 | int i; | |
349 | struct resource *best = NULL; | |
350 | ||
351 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
352 | struct resource *r = bus->resource[i]; | |
353 | if (!r) | |
354 | continue; | |
355 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
356 | continue; /* Not contained */ | |
357 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
358 | continue; /* Wrong type */ | |
359 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
360 | return r; /* Exact match */ | |
361 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
362 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
363 | } | |
364 | return best; | |
365 | } | |
366 | ||
064b53db JL |
367 | /** |
368 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
369 | * @dev: PCI device to have its BARs restored | |
370 | * | |
371 | * Restore the BAR values for a given device, so as to make it | |
372 | * accessible by its driver. | |
373 | */ | |
ad668599 | 374 | static void |
064b53db JL |
375 | pci_restore_bars(struct pci_dev *dev) |
376 | { | |
377 | int i, numres; | |
378 | ||
379 | switch (dev->hdr_type) { | |
380 | case PCI_HEADER_TYPE_NORMAL: | |
381 | numres = 6; | |
382 | break; | |
383 | case PCI_HEADER_TYPE_BRIDGE: | |
384 | numres = 2; | |
385 | break; | |
386 | case PCI_HEADER_TYPE_CARDBUS: | |
387 | numres = 1; | |
388 | break; | |
389 | default: | |
390 | /* Should never get here, but just in case... */ | |
391 | return; | |
392 | } | |
393 | ||
394 | for (i = 0; i < numres; i ++) | |
395 | pci_update_resource(dev, &dev->resource[i], i); | |
396 | } | |
397 | ||
8f7020d3 RD |
398 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
399 | ||
1da177e4 LT |
400 | /** |
401 | * pci_set_power_state - Set the power state of a PCI device | |
402 | * @dev: PCI device to be suspended | |
403 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
404 | * | |
405 | * Transition a device to a new power state, using the Power Management | |
406 | * Capabilities in the device's config space. | |
407 | * | |
408 | * RETURN VALUE: | |
409 | * -EINVAL if trying to enter a lower state than we're already in. | |
410 | * 0 if we're already in the requested state. | |
411 | * -EIO if device does not support PCI PM. | |
412 | * 0 if we can successfully change the power state. | |
413 | */ | |
1da177e4 LT |
414 | int |
415 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
416 | { | |
064b53db | 417 | int pm, need_restore = 0; |
1da177e4 LT |
418 | u16 pmcsr, pmc; |
419 | ||
420 | /* bound the state we're entering */ | |
421 | if (state > PCI_D3hot) | |
422 | state = PCI_D3hot; | |
423 | ||
e36c455c PM |
424 | /* |
425 | * If the device or the parent bridge can't support PCI PM, ignore | |
426 | * the request if we're doing anything besides putting it into D0 | |
427 | * (which would only happen on boot). | |
428 | */ | |
429 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
430 | return 0; | |
431 | ||
cca03dec AL |
432 | /* find PCI PM capability in list */ |
433 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
434 | ||
435 | /* abort if the device doesn't support PM capabilities */ | |
436 | if (!pm) | |
437 | return -EIO; | |
438 | ||
1da177e4 LT |
439 | /* Validate current state: |
440 | * Can enter D0 from any state, but if we can only go deeper | |
441 | * to sleep if we're already in a low power state | |
442 | */ | |
02669492 AM |
443 | if (state != PCI_D0 && dev->current_state > state) { |
444 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
445 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 446 | return -EINVAL; |
02669492 | 447 | } else if (dev->current_state == state) |
1da177e4 LT |
448 | return 0; /* we're already there */ |
449 | ||
ffadcc2f | 450 | |
1da177e4 | 451 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); |
3fe9d19f | 452 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
453 | printk(KERN_DEBUG |
454 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
455 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
456 | return -EIO; | |
457 | } | |
458 | ||
459 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
460 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
461 | return -EIO; | |
462 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
463 | return -EIO; | |
1da177e4 | 464 | |
064b53db JL |
465 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
466 | ||
32a36585 | 467 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
468 | * This doesn't affect PME_Status, disables PME_En, and |
469 | * sets PowerState to 0. | |
470 | */ | |
32a36585 | 471 | switch (dev->current_state) { |
d3535fbb JL |
472 | case PCI_D0: |
473 | case PCI_D1: | |
474 | case PCI_D2: | |
475 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
476 | pmcsr |= state; | |
477 | break; | |
32a36585 JL |
478 | case PCI_UNKNOWN: /* Boot-up */ |
479 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
480 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 481 | need_restore = 1; |
32a36585 | 482 | /* Fall-through: force to D0 */ |
32a36585 | 483 | default: |
d3535fbb | 484 | pmcsr = 0; |
32a36585 | 485 | break; |
1da177e4 LT |
486 | } |
487 | ||
488 | /* enter specified state */ | |
489 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
490 | ||
491 | /* Mandatory power management transition delays */ | |
492 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
493 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 494 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
495 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
496 | udelay(200); | |
1da177e4 | 497 | |
b913100d DSL |
498 | /* |
499 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 500 | * Firmware method after native method ? |
b913100d DSL |
501 | */ |
502 | if (platform_pci_set_power_state) | |
503 | platform_pci_set_power_state(dev, state); | |
504 | ||
505 | dev->current_state = state; | |
064b53db JL |
506 | |
507 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
508 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
509 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
510 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
511 | * For example, at least some versions of the 3c905B and the | |
512 | * 3c556B exhibit this behaviour. | |
513 | * | |
514 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
515 | * devices in a D3hot state at boot. Consequently, we need to | |
516 | * restore at least the BARs so that the device will be | |
517 | * accessible to its driver. | |
518 | */ | |
519 | if (need_restore) | |
520 | pci_restore_bars(dev); | |
521 | ||
1da177e4 LT |
522 | return 0; |
523 | } | |
524 | ||
ab826ca4 | 525 | pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 526 | |
1da177e4 LT |
527 | /** |
528 | * pci_choose_state - Choose the power state of a PCI device | |
529 | * @dev: PCI device to be suspended | |
530 | * @state: target sleep state for the whole system. This is the value | |
531 | * that is passed to suspend() function. | |
532 | * | |
533 | * Returns PCI power state suitable for given device and given system | |
534 | * message. | |
535 | */ | |
536 | ||
537 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
538 | { | |
ab826ca4 | 539 | pci_power_t ret; |
0f64474b | 540 | |
1da177e4 LT |
541 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
542 | return PCI_D0; | |
543 | ||
0f64474b DSL |
544 | if (platform_pci_choose_state) { |
545 | ret = platform_pci_choose_state(dev, state); | |
ab826ca4 SL |
546 | if (ret != PCI_POWER_ERROR) |
547 | return ret; | |
0f64474b | 548 | } |
ca078bae PM |
549 | |
550 | switch (state.event) { | |
551 | case PM_EVENT_ON: | |
552 | return PCI_D0; | |
553 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
554 | case PM_EVENT_PRETHAW: |
555 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae PM |
556 | case PM_EVENT_SUSPEND: |
557 | return PCI_D3hot; | |
1da177e4 | 558 | default: |
b887d2e6 | 559 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
560 | BUG(); |
561 | } | |
562 | return PCI_D0; | |
563 | } | |
564 | ||
565 | EXPORT_SYMBOL(pci_choose_state); | |
566 | ||
b56a5a23 MT |
567 | static int pci_save_pcie_state(struct pci_dev *dev) |
568 | { | |
569 | int pos, i = 0; | |
570 | struct pci_cap_saved_state *save_state; | |
571 | u16 *cap; | |
017fc480 | 572 | int found = 0; |
b56a5a23 MT |
573 | |
574 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
575 | if (pos <= 0) | |
576 | return 0; | |
577 | ||
9f35575d EB |
578 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
579 | if (!save_state) | |
580 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
581 | else |
582 | found = 1; | |
b56a5a23 MT |
583 | if (!save_state) { |
584 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
585 | return -ENOMEM; | |
586 | } | |
587 | cap = (u16 *)&save_state->data[0]; | |
588 | ||
589 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
590 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
591 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
592 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 593 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
594 | if (!found) |
595 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
596 | return 0; |
597 | } | |
598 | ||
599 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
600 | { | |
601 | int i = 0, pos; | |
602 | struct pci_cap_saved_state *save_state; | |
603 | u16 *cap; | |
604 | ||
605 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
606 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
607 | if (!save_state || pos <= 0) | |
608 | return; | |
609 | cap = (u16 *)&save_state->data[0]; | |
610 | ||
611 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
612 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
613 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
614 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
615 | } |
616 | ||
cc692a5f SH |
617 | |
618 | static int pci_save_pcix_state(struct pci_dev *dev) | |
619 | { | |
620 | int pos, i = 0; | |
621 | struct pci_cap_saved_state *save_state; | |
622 | u16 *cap; | |
017fc480 | 623 | int found = 0; |
cc692a5f SH |
624 | |
625 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
626 | if (pos <= 0) | |
627 | return 0; | |
628 | ||
f34303de | 629 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
630 | if (!save_state) |
631 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
632 | else |
633 | found = 1; | |
cc692a5f SH |
634 | if (!save_state) { |
635 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
636 | return -ENOMEM; | |
637 | } | |
638 | cap = (u16 *)&save_state->data[0]; | |
639 | ||
640 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 641 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
642 | if (!found) |
643 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
644 | return 0; |
645 | } | |
646 | ||
647 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
648 | { | |
649 | int i = 0, pos; | |
650 | struct pci_cap_saved_state *save_state; | |
651 | u16 *cap; | |
652 | ||
653 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
654 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
655 | if (!save_state || pos <= 0) | |
656 | return; | |
657 | cap = (u16 *)&save_state->data[0]; | |
658 | ||
659 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
660 | } |
661 | ||
662 | ||
1da177e4 LT |
663 | /** |
664 | * pci_save_state - save the PCI configuration space of a device before suspending | |
665 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
666 | */ |
667 | int | |
668 | pci_save_state(struct pci_dev *dev) | |
669 | { | |
670 | int i; | |
671 | /* XXX: 100% dword access ok here? */ | |
672 | for (i = 0; i < 16; i++) | |
673 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
674 | if ((i = pci_save_pcie_state(dev)) != 0) |
675 | return i; | |
cc692a5f SH |
676 | if ((i = pci_save_pcix_state(dev)) != 0) |
677 | return i; | |
1da177e4 LT |
678 | return 0; |
679 | } | |
680 | ||
681 | /** | |
682 | * pci_restore_state - Restore the saved state of a PCI device | |
683 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
684 | */ |
685 | int | |
686 | pci_restore_state(struct pci_dev *dev) | |
687 | { | |
688 | int i; | |
b4482a4b | 689 | u32 val; |
1da177e4 | 690 | |
b56a5a23 MT |
691 | /* PCI Express register must be restored first */ |
692 | pci_restore_pcie_state(dev); | |
693 | ||
8b8c8d28 YL |
694 | /* |
695 | * The Base Address register should be programmed before the command | |
696 | * register(s) | |
697 | */ | |
698 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
699 | pci_read_config_dword(dev, i * 4, &val); |
700 | if (val != dev->saved_config_space[i]) { | |
701 | printk(KERN_DEBUG "PM: Writing back config space on " | |
702 | "device %s at offset %x (was %x, writing %x)\n", | |
703 | pci_name(dev), i, | |
704 | val, (int)dev->saved_config_space[i]); | |
705 | pci_write_config_dword(dev,i * 4, | |
706 | dev->saved_config_space[i]); | |
707 | } | |
708 | } | |
cc692a5f | 709 | pci_restore_pcix_state(dev); |
41017f0c | 710 | pci_restore_msi_state(dev); |
8fed4b65 | 711 | |
1da177e4 LT |
712 | return 0; |
713 | } | |
714 | ||
38cc1302 HS |
715 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
716 | { | |
717 | int err; | |
718 | ||
719 | err = pci_set_power_state(dev, PCI_D0); | |
720 | if (err < 0 && err != -EIO) | |
721 | return err; | |
722 | err = pcibios_enable_device(dev, bars); | |
723 | if (err < 0) | |
724 | return err; | |
725 | pci_fixup_device(pci_fixup_enable, dev); | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
730 | /** | |
0b62e13b | 731 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
732 | * @dev: PCI device to be resumed |
733 | * | |
734 | * Note this function is a backend of pci_default_resume and is not supposed | |
735 | * to be called by normal code, write proper resume handler and use it instead. | |
736 | */ | |
0b62e13b | 737 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
738 | { |
739 | if (atomic_read(&dev->enable_cnt)) | |
740 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
741 | return 0; | |
742 | } | |
743 | ||
1da177e4 LT |
744 | /** |
745 | * pci_enable_device_bars - Initialize some of a device for use | |
746 | * @dev: PCI device to be initialized | |
747 | * @bars: bitmask of BAR's that must be configured | |
748 | * | |
749 | * Initialize device before it's used by a driver. Ask low-level code | |
9fb625c3 | 750 | * to enable selected I/O and memory resources. Wake up the device if it |
1da177e4 LT |
751 | * was suspended. Beware, this function can fail. |
752 | */ | |
1da177e4 LT |
753 | int |
754 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
755 | { | |
756 | int err; | |
757 | ||
9fb625c3 HS |
758 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
759 | return 0; /* already enabled */ | |
760 | ||
38cc1302 | 761 | err = do_pci_enable_device(dev, bars); |
95a62965 | 762 | if (err < 0) |
38cc1302 | 763 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 764 | return err; |
1da177e4 LT |
765 | } |
766 | ||
bae94d02 IPG |
767 | /** |
768 | * pci_enable_device - Initialize device before it's used by a driver. | |
769 | * @dev: PCI device to be initialized | |
770 | * | |
771 | * Initialize device before it's used by a driver. Ask low-level code | |
772 | * to enable I/O and memory. Wake up the device if it was suspended. | |
773 | * Beware, this function can fail. | |
774 | * | |
775 | * Note we don't actually enable the device many times if we call | |
776 | * this function repeatedly (we just increment the count). | |
777 | */ | |
778 | int pci_enable_device(struct pci_dev *dev) | |
779 | { | |
9fb625c3 | 780 | return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
bae94d02 IPG |
781 | } |
782 | ||
9ac7849e TH |
783 | /* |
784 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
785 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
786 | * there's no need to track it separately. pci_devres is initialized | |
787 | * when a device is enabled using managed PCI device enable interface. | |
788 | */ | |
789 | struct pci_devres { | |
7f375f32 TH |
790 | unsigned int enabled:1; |
791 | unsigned int pinned:1; | |
9ac7849e TH |
792 | unsigned int orig_intx:1; |
793 | unsigned int restore_intx:1; | |
794 | u32 region_mask; | |
795 | }; | |
796 | ||
797 | static void pcim_release(struct device *gendev, void *res) | |
798 | { | |
799 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
800 | struct pci_devres *this = res; | |
801 | int i; | |
802 | ||
803 | if (dev->msi_enabled) | |
804 | pci_disable_msi(dev); | |
805 | if (dev->msix_enabled) | |
806 | pci_disable_msix(dev); | |
807 | ||
808 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
809 | if (this->region_mask & (1 << i)) | |
810 | pci_release_region(dev, i); | |
811 | ||
812 | if (this->restore_intx) | |
813 | pci_intx(dev, this->orig_intx); | |
814 | ||
7f375f32 | 815 | if (this->enabled && !this->pinned) |
9ac7849e TH |
816 | pci_disable_device(dev); |
817 | } | |
818 | ||
819 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
820 | { | |
821 | struct pci_devres *dr, *new_dr; | |
822 | ||
823 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
824 | if (dr) | |
825 | return dr; | |
826 | ||
827 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
828 | if (!new_dr) | |
829 | return NULL; | |
830 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
831 | } | |
832 | ||
833 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
834 | { | |
835 | if (pci_is_managed(pdev)) | |
836 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
837 | return NULL; | |
838 | } | |
839 | ||
840 | /** | |
841 | * pcim_enable_device - Managed pci_enable_device() | |
842 | * @pdev: PCI device to be initialized | |
843 | * | |
844 | * Managed pci_enable_device(). | |
845 | */ | |
846 | int pcim_enable_device(struct pci_dev *pdev) | |
847 | { | |
848 | struct pci_devres *dr; | |
849 | int rc; | |
850 | ||
851 | dr = get_pci_dr(pdev); | |
852 | if (unlikely(!dr)) | |
853 | return -ENOMEM; | |
7f375f32 | 854 | WARN_ON(!!dr->enabled); |
9ac7849e TH |
855 | |
856 | rc = pci_enable_device(pdev); | |
857 | if (!rc) { | |
858 | pdev->is_managed = 1; | |
7f375f32 | 859 | dr->enabled = 1; |
9ac7849e TH |
860 | } |
861 | return rc; | |
862 | } | |
863 | ||
864 | /** | |
865 | * pcim_pin_device - Pin managed PCI device | |
866 | * @pdev: PCI device to pin | |
867 | * | |
868 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
869 | * driver detach. @pdev must have been enabled with | |
870 | * pcim_enable_device(). | |
871 | */ | |
872 | void pcim_pin_device(struct pci_dev *pdev) | |
873 | { | |
874 | struct pci_devres *dr; | |
875 | ||
876 | dr = find_pci_dr(pdev); | |
7f375f32 | 877 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 878 | if (dr) |
7f375f32 | 879 | dr->pinned = 1; |
9ac7849e TH |
880 | } |
881 | ||
1da177e4 LT |
882 | /** |
883 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
884 | * @dev: the PCI device to disable | |
885 | * | |
886 | * Disables architecture specific PCI resources for the device. This | |
887 | * is the default implementation. Architecture implementations can | |
888 | * override this. | |
889 | */ | |
890 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
891 | ||
892 | /** | |
893 | * pci_disable_device - Disable PCI device after use | |
894 | * @dev: PCI device to be disabled | |
895 | * | |
896 | * Signal to the system that the PCI device is not in use by the system | |
897 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
898 | * |
899 | * Note we don't actually disable the device until all callers of | |
900 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
901 | */ |
902 | void | |
903 | pci_disable_device(struct pci_dev *dev) | |
904 | { | |
9ac7849e | 905 | struct pci_devres *dr; |
1da177e4 | 906 | u16 pci_command; |
99dc804d | 907 | |
9ac7849e TH |
908 | dr = find_pci_dr(dev); |
909 | if (dr) | |
7f375f32 | 910 | dr->enabled = 0; |
9ac7849e | 911 | |
bae94d02 IPG |
912 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
913 | return; | |
914 | ||
4348a2dc SL |
915 | /* Wait for all transactions are finished before disabling the device */ |
916 | pcie_wait_pending_transaction(dev); | |
917 | ||
1da177e4 LT |
918 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
919 | if (pci_command & PCI_COMMAND_MASTER) { | |
920 | pci_command &= ~PCI_COMMAND_MASTER; | |
921 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
922 | } | |
ceb43744 | 923 | dev->is_busmaster = 0; |
1da177e4 LT |
924 | |
925 | pcibios_disable_device(dev); | |
926 | } | |
927 | ||
f7bdd12d BK |
928 | /** |
929 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
930 | * @dev: the PCI-E device reset | |
931 | * @state: Reset state to enter into | |
932 | * | |
933 | * | |
934 | * Sets the PCI-E reset state for the device. This is the default | |
935 | * implementation. Architecture implementations can override this. | |
936 | */ | |
937 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
938 | enum pcie_reset_state state) | |
939 | { | |
940 | return -EINVAL; | |
941 | } | |
942 | ||
943 | /** | |
944 | * pci_set_pcie_reset_state - set reset state for device dev | |
945 | * @dev: the PCI-E device reset | |
946 | * @state: Reset state to enter into | |
947 | * | |
948 | * | |
949 | * Sets the PCI reset state for the device. | |
950 | */ | |
951 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
952 | { | |
953 | return pcibios_set_pcie_reset_state(dev, state); | |
954 | } | |
955 | ||
1da177e4 | 956 | /** |
075c1771 DB |
957 | * pci_enable_wake - enable PCI device as wakeup event source |
958 | * @dev: PCI device affected | |
959 | * @state: PCI state from which device will issue wakeup events | |
960 | * @enable: True to enable event generation; false to disable | |
961 | * | |
962 | * This enables the device as a wakeup event source, or disables it. | |
963 | * When such events involves platform-specific hooks, those hooks are | |
964 | * called automatically by this routine. | |
965 | * | |
966 | * Devices with legacy power management (no standard PCI PM capabilities) | |
967 | * always require such platform hooks. Depending on the platform, devices | |
968 | * supporting the standard PCI PME# signal may require such platform hooks; | |
969 | * they always update bits in config space to allow PME# generation. | |
970 | * | |
971 | * -EIO is returned if the device can't ever be a wakeup event source. | |
972 | * -EINVAL is returned if the device can't generate wakeup events from | |
973 | * the specified PCI state. Returns zero if the operation is successful. | |
1da177e4 LT |
974 | */ |
975 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
976 | { | |
977 | int pm; | |
075c1771 | 978 | int status; |
1da177e4 LT |
979 | u16 value; |
980 | ||
075c1771 DB |
981 | /* Note that drivers should verify device_may_wakeup(&dev->dev) |
982 | * before calling this function. Platform code should report | |
983 | * errors when drivers try to enable wakeup on devices that | |
984 | * can't issue wakeups, or on which wakeups were disabled by | |
985 | * userspace updating the /sys/devices.../power/wakeup file. | |
986 | */ | |
987 | ||
988 | status = call_platform_enable_wakeup(&dev->dev, enable); | |
989 | ||
1da177e4 LT |
990 | /* find PCI PM capability in list */ |
991 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
992 | ||
075c1771 DB |
993 | /* If device doesn't support PM Capabilities, but caller wants to |
994 | * disable wake events, it's a NOP. Otherwise fail unless the | |
995 | * platform hooks handled this legacy device already. | |
996 | */ | |
997 | if (!pm) | |
998 | return enable ? status : 0; | |
1da177e4 LT |
999 | |
1000 | /* Check device's ability to generate PME# */ | |
1001 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
1002 | ||
1003 | value &= PCI_PM_CAP_PME_MASK; | |
1004 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
1005 | ||
1006 | /* Check if it can generate PME# from requested state. */ | |
075c1771 DB |
1007 | if (!value || !(value & (1 << state))) { |
1008 | /* if it can't, revert what the platform hook changed, | |
1009 | * always reporting the base "EINVAL, can't PME#" error | |
1010 | */ | |
1011 | if (enable) | |
1012 | call_platform_enable_wakeup(&dev->dev, 0); | |
1da177e4 | 1013 | return enable ? -EINVAL : 0; |
075c1771 | 1014 | } |
1da177e4 LT |
1015 | |
1016 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
1017 | ||
1018 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
1019 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1020 | ||
1021 | if (!enable) | |
1022 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
1023 | ||
1024 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
075c1771 | 1025 | |
1da177e4 LT |
1026 | return 0; |
1027 | } | |
1028 | ||
1029 | int | |
1030 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1031 | { | |
1032 | u8 pin; | |
1033 | ||
514d207d | 1034 | pin = dev->pin; |
1da177e4 LT |
1035 | if (!pin) |
1036 | return -1; | |
1037 | pin--; | |
1038 | while (dev->bus->self) { | |
1039 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1040 | dev = dev->bus->self; | |
1041 | } | |
1042 | *bridge = dev; | |
1043 | return pin; | |
1044 | } | |
1045 | ||
1046 | /** | |
1047 | * pci_release_region - Release a PCI bar | |
1048 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1049 | * @bar: BAR to release | |
1050 | * | |
1051 | * Releases the PCI I/O and memory resources previously reserved by a | |
1052 | * successful call to pci_request_region. Call this function only | |
1053 | * after all use of the PCI regions has ceased. | |
1054 | */ | |
1055 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1056 | { | |
9ac7849e TH |
1057 | struct pci_devres *dr; |
1058 | ||
1da177e4 LT |
1059 | if (pci_resource_len(pdev, bar) == 0) |
1060 | return; | |
1061 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1062 | release_region(pci_resource_start(pdev, bar), | |
1063 | pci_resource_len(pdev, bar)); | |
1064 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1065 | release_mem_region(pci_resource_start(pdev, bar), | |
1066 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1067 | |
1068 | dr = find_pci_dr(pdev); | |
1069 | if (dr) | |
1070 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1071 | } |
1072 | ||
1073 | /** | |
1074 | * pci_request_region - Reserved PCI I/O and memory resource | |
1075 | * @pdev: PCI device whose resources are to be reserved | |
1076 | * @bar: BAR to be reserved | |
1077 | * @res_name: Name to be associated with resource. | |
1078 | * | |
1079 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1080 | * being reserved by owner @res_name. Do not access any | |
1081 | * address inside the PCI regions unless this call returns | |
1082 | * successfully. | |
1083 | * | |
1084 | * Returns 0 on success, or %EBUSY on error. A warning | |
1085 | * message is also printed on failure. | |
1086 | */ | |
3c990e92 | 1087 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1088 | { |
9ac7849e TH |
1089 | struct pci_devres *dr; |
1090 | ||
1da177e4 LT |
1091 | if (pci_resource_len(pdev, bar) == 0) |
1092 | return 0; | |
1093 | ||
1094 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1095 | if (!request_region(pci_resource_start(pdev, bar), | |
1096 | pci_resource_len(pdev, bar), res_name)) | |
1097 | goto err_out; | |
1098 | } | |
1099 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1100 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1101 | pci_resource_len(pdev, bar), res_name)) | |
1102 | goto err_out; | |
1103 | } | |
9ac7849e TH |
1104 | |
1105 | dr = find_pci_dr(pdev); | |
1106 | if (dr) | |
1107 | dr->region_mask |= 1 << bar; | |
1108 | ||
1da177e4 LT |
1109 | return 0; |
1110 | ||
1111 | err_out: | |
1396a8c3 GKH |
1112 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
1113 | "for device %s\n", | |
1da177e4 LT |
1114 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
1115 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
1116 | (unsigned long long)pci_resource_len(pdev, bar), |
1117 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
1118 | pci_name(pdev)); |
1119 | return -EBUSY; | |
1120 | } | |
1121 | ||
c87deff7 HS |
1122 | /** |
1123 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1124 | * @pdev: PCI device whose resources were previously reserved | |
1125 | * @bars: Bitmask of BARs to be released | |
1126 | * | |
1127 | * Release selected PCI I/O and memory resources previously reserved. | |
1128 | * Call this function only after all use of the PCI regions has ceased. | |
1129 | */ | |
1130 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1131 | { | |
1132 | int i; | |
1133 | ||
1134 | for (i = 0; i < 6; i++) | |
1135 | if (bars & (1 << i)) | |
1136 | pci_release_region(pdev, i); | |
1137 | } | |
1138 | ||
1139 | /** | |
1140 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1141 | * @pdev: PCI device whose resources are to be reserved | |
1142 | * @bars: Bitmask of BARs to be requested | |
1143 | * @res_name: Name to be associated with resource | |
1144 | */ | |
1145 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1146 | const char *res_name) | |
1147 | { | |
1148 | int i; | |
1149 | ||
1150 | for (i = 0; i < 6; i++) | |
1151 | if (bars & (1 << i)) | |
1152 | if(pci_request_region(pdev, i, res_name)) | |
1153 | goto err_out; | |
1154 | return 0; | |
1155 | ||
1156 | err_out: | |
1157 | while(--i >= 0) | |
1158 | if (bars & (1 << i)) | |
1159 | pci_release_region(pdev, i); | |
1160 | ||
1161 | return -EBUSY; | |
1162 | } | |
1da177e4 LT |
1163 | |
1164 | /** | |
1165 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1166 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1167 | * | |
1168 | * Releases all PCI I/O and memory resources previously reserved by a | |
1169 | * successful call to pci_request_regions. Call this function only | |
1170 | * after all use of the PCI regions has ceased. | |
1171 | */ | |
1172 | ||
1173 | void pci_release_regions(struct pci_dev *pdev) | |
1174 | { | |
c87deff7 | 1175 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1176 | } |
1177 | ||
1178 | /** | |
1179 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1180 | * @pdev: PCI device whose resources are to be reserved | |
1181 | * @res_name: Name to be associated with resource. | |
1182 | * | |
1183 | * Mark all PCI regions associated with PCI device @pdev as | |
1184 | * being reserved by owner @res_name. Do not access any | |
1185 | * address inside the PCI regions unless this call returns | |
1186 | * successfully. | |
1187 | * | |
1188 | * Returns 0 on success, or %EBUSY on error. A warning | |
1189 | * message is also printed on failure. | |
1190 | */ | |
3c990e92 | 1191 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1192 | { |
c87deff7 | 1193 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1194 | } |
1195 | ||
1196 | /** | |
1197 | * pci_set_master - enables bus-mastering for device dev | |
1198 | * @dev: the PCI device to enable | |
1199 | * | |
1200 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1201 | * to do the needed arch specific settings. | |
1202 | */ | |
1203 | void | |
1204 | pci_set_master(struct pci_dev *dev) | |
1205 | { | |
1206 | u16 cmd; | |
1207 | ||
1208 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1209 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
1210 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
1211 | cmd |= PCI_COMMAND_MASTER; | |
1212 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1213 | } | |
1214 | dev->is_busmaster = 1; | |
1215 | pcibios_set_master(dev); | |
1216 | } | |
1217 | ||
edb2d97e MW |
1218 | #ifdef PCI_DISABLE_MWI |
1219 | int pci_set_mwi(struct pci_dev *dev) | |
1220 | { | |
1221 | return 0; | |
1222 | } | |
1223 | ||
694625c0 RD |
1224 | int pci_try_set_mwi(struct pci_dev *dev) |
1225 | { | |
1226 | return 0; | |
1227 | } | |
1228 | ||
edb2d97e MW |
1229 | void pci_clear_mwi(struct pci_dev *dev) |
1230 | { | |
1231 | } | |
1232 | ||
1233 | #else | |
ebf5a248 MW |
1234 | |
1235 | #ifndef PCI_CACHE_LINE_BYTES | |
1236 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1237 | #endif | |
1238 | ||
1da177e4 | 1239 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1240 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1241 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1242 | |
1243 | /** | |
edb2d97e MW |
1244 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1245 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1246 | * |
edb2d97e MW |
1247 | * Helper function for pci_set_mwi. |
1248 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1249 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1250 | * | |
1251 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1252 | */ | |
1253 | static int | |
edb2d97e | 1254 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1255 | { |
1256 | u8 cacheline_size; | |
1257 | ||
1258 | if (!pci_cache_line_size) | |
1259 | return -EINVAL; /* The system doesn't support MWI. */ | |
1260 | ||
1261 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1262 | equal to or multiple of the right value. */ | |
1263 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1264 | if (cacheline_size >= pci_cache_line_size && | |
1265 | (cacheline_size % pci_cache_line_size) == 0) | |
1266 | return 0; | |
1267 | ||
1268 | /* Write the correct value. */ | |
1269 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1270 | /* Read it back. */ | |
1271 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1272 | if (cacheline_size == pci_cache_line_size) | |
1273 | return 0; | |
1274 | ||
1275 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
1276 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
1277 | ||
1278 | return -EINVAL; | |
1279 | } | |
1da177e4 LT |
1280 | |
1281 | /** | |
1282 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1283 | * @dev: the PCI device for which MWI is enabled | |
1284 | * | |
694625c0 | 1285 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1286 | * |
1287 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1288 | */ | |
1289 | int | |
1290 | pci_set_mwi(struct pci_dev *dev) | |
1291 | { | |
1292 | int rc; | |
1293 | u16 cmd; | |
1294 | ||
edb2d97e | 1295 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1296 | if (rc) |
1297 | return rc; | |
1298 | ||
1299 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1300 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
694625c0 RD |
1301 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", |
1302 | pci_name(dev)); | |
1da177e4 LT |
1303 | cmd |= PCI_COMMAND_INVALIDATE; |
1304 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1305 | } | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
694625c0 RD |
1310 | /** |
1311 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1312 | * @dev: the PCI device for which MWI is enabled | |
1313 | * | |
1314 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1315 | * Callers are not required to check the return value. | |
1316 | * | |
1317 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1318 | */ | |
1319 | int pci_try_set_mwi(struct pci_dev *dev) | |
1320 | { | |
1321 | int rc = pci_set_mwi(dev); | |
1322 | return rc; | |
1323 | } | |
1324 | ||
1da177e4 LT |
1325 | /** |
1326 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1327 | * @dev: the PCI device to disable | |
1328 | * | |
1329 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1330 | */ | |
1331 | void | |
1332 | pci_clear_mwi(struct pci_dev *dev) | |
1333 | { | |
1334 | u16 cmd; | |
1335 | ||
1336 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1337 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1338 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1339 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1340 | } | |
1341 | } | |
edb2d97e | 1342 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1343 | |
a04ce0ff BR |
1344 | /** |
1345 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1346 | * @pdev: the PCI device to operate on |
1347 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1348 | * |
1349 | * Enables/disables PCI INTx for device dev | |
1350 | */ | |
1351 | void | |
1352 | pci_intx(struct pci_dev *pdev, int enable) | |
1353 | { | |
1354 | u16 pci_command, new; | |
1355 | ||
1356 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1357 | ||
1358 | if (enable) { | |
1359 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1360 | } else { | |
1361 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1362 | } | |
1363 | ||
1364 | if (new != pci_command) { | |
9ac7849e TH |
1365 | struct pci_devres *dr; |
1366 | ||
2fd9d74b | 1367 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1368 | |
1369 | dr = find_pci_dr(pdev); | |
1370 | if (dr && !dr->restore_intx) { | |
1371 | dr->restore_intx = 1; | |
1372 | dr->orig_intx = !enable; | |
1373 | } | |
a04ce0ff BR |
1374 | } |
1375 | } | |
1376 | ||
f5f2b131 EB |
1377 | /** |
1378 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1379 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1380 | * |
1381 | * If you want to use msi see pci_enable_msi and friends. | |
1382 | * This is a lower level primitive that allows us to disable | |
1383 | * msi operation at the device level. | |
1384 | */ | |
1385 | void pci_msi_off(struct pci_dev *dev) | |
1386 | { | |
1387 | int pos; | |
1388 | u16 control; | |
1389 | ||
1390 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1391 | if (pos) { | |
1392 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1393 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1394 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1395 | } | |
1396 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1397 | if (pos) { | |
1398 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1399 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1400 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1401 | } | |
1402 | } | |
1403 | ||
1da177e4 LT |
1404 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1405 | /* | |
1406 | * These can be overridden by arch-specific implementations | |
1407 | */ | |
1408 | int | |
1409 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1410 | { | |
1411 | if (!pci_dma_supported(dev, mask)) | |
1412 | return -EIO; | |
1413 | ||
1414 | dev->dma_mask = mask; | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1da177e4 LT |
1419 | int |
1420 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1421 | { | |
1422 | if (!pci_dma_supported(dev, mask)) | |
1423 | return -EIO; | |
1424 | ||
1425 | dev->dev.coherent_dma_mask = mask; | |
1426 | ||
1427 | return 0; | |
1428 | } | |
1429 | #endif | |
c87deff7 | 1430 | |
d556ad4b PO |
1431 | /** |
1432 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1433 | * @dev: PCI device to query | |
1434 | * | |
1435 | * Returns mmrbc: maximum designed memory read count in bytes | |
1436 | * or appropriate error value. | |
1437 | */ | |
1438 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1439 | { | |
b7b095c1 | 1440 | int err, cap; |
d556ad4b PO |
1441 | u32 stat; |
1442 | ||
1443 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1444 | if (!cap) | |
1445 | return -EINVAL; | |
1446 | ||
1447 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1448 | if (err) | |
1449 | return -EINVAL; | |
1450 | ||
b7b095c1 | 1451 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1452 | } |
1453 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1454 | ||
1455 | /** | |
1456 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1457 | * @dev: PCI device to query | |
1458 | * | |
1459 | * Returns mmrbc: maximum memory read count in bytes | |
1460 | * or appropriate error value. | |
1461 | */ | |
1462 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1463 | { | |
1464 | int ret, cap; | |
1465 | u32 cmd; | |
1466 | ||
1467 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1468 | if (!cap) | |
1469 | return -EINVAL; | |
1470 | ||
1471 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1472 | if (!ret) | |
1473 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1474 | ||
1475 | return ret; | |
1476 | } | |
1477 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1478 | ||
1479 | /** | |
1480 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1481 | * @dev: PCI device to query | |
1482 | * @mmrbc: maximum memory read count in bytes | |
1483 | * valid values are 512, 1024, 2048, 4096 | |
1484 | * | |
1485 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1486 | * that prevent this. | |
1487 | */ | |
1488 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1489 | { | |
1490 | int cap, err = -EINVAL; | |
1491 | u32 stat, cmd, v, o; | |
1492 | ||
229f5afd | 1493 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1494 | goto out; |
1495 | ||
1496 | v = ffs(mmrbc) - 10; | |
1497 | ||
1498 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1499 | if (!cap) | |
1500 | goto out; | |
1501 | ||
1502 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1503 | if (err) | |
1504 | goto out; | |
1505 | ||
1506 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1507 | return -E2BIG; | |
1508 | ||
1509 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1510 | if (err) | |
1511 | goto out; | |
1512 | ||
1513 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1514 | if (o != v) { | |
1515 | if (v > o && dev->bus && | |
1516 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1517 | return -EIO; | |
1518 | ||
1519 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1520 | cmd |= v << 2; | |
1521 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1522 | } | |
1523 | out: | |
1524 | return err; | |
1525 | } | |
1526 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1527 | ||
1528 | /** | |
1529 | * pcie_get_readrq - get PCI Express read request size | |
1530 | * @dev: PCI device to query | |
1531 | * | |
1532 | * Returns maximum memory read request in bytes | |
1533 | * or appropriate error value. | |
1534 | */ | |
1535 | int pcie_get_readrq(struct pci_dev *dev) | |
1536 | { | |
1537 | int ret, cap; | |
1538 | u16 ctl; | |
1539 | ||
1540 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1541 | if (!cap) | |
1542 | return -EINVAL; | |
1543 | ||
1544 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1545 | if (!ret) | |
1546 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1547 | ||
1548 | return ret; | |
1549 | } | |
1550 | EXPORT_SYMBOL(pcie_get_readrq); | |
1551 | ||
1552 | /** | |
1553 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1554 | * @dev: PCI device to query | |
42e61f4a | 1555 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1556 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1557 | * | |
1558 | * If possible sets maximum read byte count | |
1559 | */ | |
1560 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1561 | { | |
1562 | int cap, err = -EINVAL; | |
1563 | u16 ctl, v; | |
1564 | ||
229f5afd | 1565 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1566 | goto out; |
1567 | ||
1568 | v = (ffs(rq) - 8) << 12; | |
1569 | ||
1570 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1571 | if (!cap) | |
1572 | goto out; | |
1573 | ||
1574 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1575 | if (err) | |
1576 | goto out; | |
1577 | ||
1578 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1579 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1580 | ctl |= v; | |
1581 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1582 | } | |
1583 | ||
1584 | out: | |
1585 | return err; | |
1586 | } | |
1587 | EXPORT_SYMBOL(pcie_set_readrq); | |
1588 | ||
c87deff7 HS |
1589 | /** |
1590 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1591 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1592 | * @flags: resource type mask to be selected |
1593 | * | |
1594 | * This helper routine makes bar mask from the type of resource. | |
1595 | */ | |
1596 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1597 | { | |
1598 | int i, bars = 0; | |
1599 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1600 | if (pci_resource_flags(dev, i) & flags) | |
1601 | bars |= (1 << i); | |
1602 | return bars; | |
1603 | } | |
1604 | ||
32a2eea7 JG |
1605 | static void __devinit pci_no_domains(void) |
1606 | { | |
1607 | #ifdef CONFIG_PCI_DOMAINS | |
1608 | pci_domains_supported = 0; | |
1609 | #endif | |
1610 | } | |
1611 | ||
1da177e4 LT |
1612 | static int __devinit pci_init(void) |
1613 | { | |
1614 | struct pci_dev *dev = NULL; | |
1615 | ||
1616 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1617 | pci_fixup_device(pci_fixup_final, dev); | |
1618 | } | |
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | static int __devinit pci_setup(char *str) | |
1623 | { | |
1624 | while (str) { | |
1625 | char *k = strchr(str, ','); | |
1626 | if (k) | |
1627 | *k++ = 0; | |
1628 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1629 | if (!strcmp(str, "nomsi")) { |
1630 | pci_no_msi(); | |
7f785763 RD |
1631 | } else if (!strcmp(str, "noaer")) { |
1632 | pci_no_aer(); | |
32a2eea7 JG |
1633 | } else if (!strcmp(str, "nodomains")) { |
1634 | pci_no_domains(); | |
4516a618 AN |
1635 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1636 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1637 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1638 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1639 | } else { |
1640 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1641 | str); | |
1642 | } | |
1da177e4 LT |
1643 | } |
1644 | str = k; | |
1645 | } | |
0637a70a | 1646 | return 0; |
1da177e4 | 1647 | } |
0637a70a | 1648 | early_param("pci", pci_setup); |
1da177e4 LT |
1649 | |
1650 | device_initcall(pci_init); | |
1da177e4 | 1651 | |
0b62e13b | 1652 | EXPORT_SYMBOL(pci_reenable_device); |
1da177e4 LT |
1653 | EXPORT_SYMBOL(pci_enable_device_bars); |
1654 | EXPORT_SYMBOL(pci_enable_device); | |
9ac7849e TH |
1655 | EXPORT_SYMBOL(pcim_enable_device); |
1656 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1657 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1658 | EXPORT_SYMBOL(pci_find_capability); |
1659 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1660 | EXPORT_SYMBOL(pci_release_regions); | |
1661 | EXPORT_SYMBOL(pci_request_regions); | |
1662 | EXPORT_SYMBOL(pci_release_region); | |
1663 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1664 | EXPORT_SYMBOL(pci_release_selected_regions); |
1665 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1666 | EXPORT_SYMBOL(pci_set_master); |
1667 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1668 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1669 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1670 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1671 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1672 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1673 | EXPORT_SYMBOL(pci_assign_resource); | |
1674 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1675 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1676 | |
1677 | EXPORT_SYMBOL(pci_set_power_state); | |
1678 | EXPORT_SYMBOL(pci_save_state); | |
1679 | EXPORT_SYMBOL(pci_restore_state); | |
1680 | EXPORT_SYMBOL(pci_enable_wake); | |
f7bdd12d | 1681 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1682 |