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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
1da177e4 | 19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 LT |
21 | |
22 | ||
23 | /** | |
24 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
25 | * @bus: pointer to PCI bus structure to search | |
26 | * | |
27 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
28 | * including the given PCI bus and its list of child PCI buses. | |
29 | */ | |
30 | unsigned char __devinit | |
31 | pci_bus_max_busnr(struct pci_bus* bus) | |
32 | { | |
33 | struct list_head *tmp; | |
34 | unsigned char max, n; | |
35 | ||
b82db5ce | 36 | max = bus->subordinate; |
1da177e4 LT |
37 | list_for_each(tmp, &bus->children) { |
38 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
39 | if(n > max) | |
40 | max = n; | |
41 | } | |
42 | return max; | |
43 | } | |
b82db5ce | 44 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 45 | |
b82db5ce | 46 | #if 0 |
1da177e4 LT |
47 | /** |
48 | * pci_max_busnr - returns maximum PCI bus number | |
49 | * | |
50 | * Returns the highest PCI bus number present in the system global list of | |
51 | * PCI buses. | |
52 | */ | |
53 | unsigned char __devinit | |
54 | pci_max_busnr(void) | |
55 | { | |
56 | struct pci_bus *bus = NULL; | |
57 | unsigned char max, n; | |
58 | ||
59 | max = 0; | |
60 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
61 | n = pci_bus_max_busnr(bus); | |
62 | if(n > max) | |
63 | max = n; | |
64 | } | |
65 | return max; | |
66 | } | |
67 | ||
54c762fe AB |
68 | #endif /* 0 */ |
69 | ||
24a4e377 RD |
70 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) |
71 | { | |
72 | u8 id; | |
73 | int ttl = 48; | |
74 | ||
75 | while (ttl--) { | |
76 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
77 | if (pos < 0x40) | |
78 | break; | |
79 | pos &= ~3; | |
80 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
81 | &id); | |
82 | if (id == 0xff) | |
83 | break; | |
84 | if (id == cap) | |
85 | return pos; | |
86 | pos += PCI_CAP_LIST_NEXT; | |
87 | } | |
88 | return 0; | |
89 | } | |
90 | ||
91 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) | |
92 | { | |
93 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
94 | pos + PCI_CAP_LIST_NEXT, cap); | |
95 | } | |
96 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
97 | ||
1da177e4 LT |
98 | static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) |
99 | { | |
100 | u16 status; | |
24a4e377 | 101 | u8 pos; |
1da177e4 LT |
102 | |
103 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
104 | if (!(status & PCI_STATUS_CAP_LIST)) | |
105 | return 0; | |
106 | ||
107 | switch (hdr_type) { | |
108 | case PCI_HEADER_TYPE_NORMAL: | |
109 | case PCI_HEADER_TYPE_BRIDGE: | |
24a4e377 | 110 | pos = PCI_CAPABILITY_LIST; |
1da177e4 LT |
111 | break; |
112 | case PCI_HEADER_TYPE_CARDBUS: | |
24a4e377 | 113 | pos = PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
114 | break; |
115 | default: | |
116 | return 0; | |
117 | } | |
24a4e377 | 118 | return __pci_find_next_cap(bus, devfn, pos, cap); |
1da177e4 LT |
119 | } |
120 | ||
121 | /** | |
122 | * pci_find_capability - query for devices' capabilities | |
123 | * @dev: PCI device to query | |
124 | * @cap: capability code | |
125 | * | |
126 | * Tell if a device supports a given PCI capability. | |
127 | * Returns the address of the requested capability structure within the | |
128 | * device's PCI configuration space or 0 in case the device does not | |
129 | * support it. Possible values for @cap: | |
130 | * | |
131 | * %PCI_CAP_ID_PM Power Management | |
132 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
133 | * %PCI_CAP_ID_VPD Vital Product Data | |
134 | * %PCI_CAP_ID_SLOTID Slot Identification | |
135 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
136 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
137 | * %PCI_CAP_ID_PCIX PCI-X | |
138 | * %PCI_CAP_ID_EXP PCI Express | |
139 | */ | |
140 | int pci_find_capability(struct pci_dev *dev, int cap) | |
141 | { | |
142 | return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); | |
143 | } | |
144 | ||
145 | /** | |
146 | * pci_bus_find_capability - query for devices' capabilities | |
147 | * @bus: the PCI bus to query | |
148 | * @devfn: PCI device to query | |
149 | * @cap: capability code | |
150 | * | |
151 | * Like pci_find_capability() but works for pci devices that do not have a | |
152 | * pci_dev structure set up yet. | |
153 | * | |
154 | * Returns the address of the requested capability structure within the | |
155 | * device's PCI configuration space or 0 in case the device does not | |
156 | * support it. | |
157 | */ | |
158 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
159 | { | |
160 | u8 hdr_type; | |
161 | ||
162 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
163 | ||
164 | return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); | |
165 | } | |
166 | ||
f8d65713 | 167 | #if 0 |
1da177e4 LT |
168 | /** |
169 | * pci_find_ext_capability - Find an extended capability | |
170 | * @dev: PCI device to query | |
171 | * @cap: capability code | |
172 | * | |
173 | * Returns the address of the requested extended capability structure | |
174 | * within the device's PCI configuration space or 0 if the device does | |
175 | * not support it. Possible values for @cap: | |
176 | * | |
177 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
178 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
179 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
180 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
181 | */ | |
182 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
183 | { | |
184 | u32 header; | |
185 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
186 | int pos = 0x100; | |
187 | ||
188 | if (dev->cfg_size <= 256) | |
189 | return 0; | |
190 | ||
191 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
192 | return 0; | |
193 | ||
194 | /* | |
195 | * If we have no capabilities, this is indicated by cap ID, | |
196 | * cap version and next pointer all being 0. | |
197 | */ | |
198 | if (header == 0) | |
199 | return 0; | |
200 | ||
201 | while (ttl-- > 0) { | |
202 | if (PCI_EXT_CAP_ID(header) == cap) | |
203 | return pos; | |
204 | ||
205 | pos = PCI_EXT_CAP_NEXT(header); | |
206 | if (pos < 0x100) | |
207 | break; | |
208 | ||
209 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
210 | break; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
f8d65713 | 215 | #endif /* 0 */ |
1da177e4 LT |
216 | |
217 | /** | |
218 | * pci_find_parent_resource - return resource region of parent bus of given region | |
219 | * @dev: PCI device structure contains resources to be searched | |
220 | * @res: child resource record for which parent is sought | |
221 | * | |
222 | * For given resource region of given device, return the resource | |
223 | * region of parent bus the given region is contained in or where | |
224 | * it should be allocated from. | |
225 | */ | |
226 | struct resource * | |
227 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
228 | { | |
229 | const struct pci_bus *bus = dev->bus; | |
230 | int i; | |
231 | struct resource *best = NULL; | |
232 | ||
233 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
234 | struct resource *r = bus->resource[i]; | |
235 | if (!r) | |
236 | continue; | |
237 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
238 | continue; /* Not contained */ | |
239 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
240 | continue; /* Wrong type */ | |
241 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
242 | return r; /* Exact match */ | |
243 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
244 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
245 | } | |
246 | return best; | |
247 | } | |
248 | ||
064b53db JL |
249 | /** |
250 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
251 | * @dev: PCI device to have its BARs restored | |
252 | * | |
253 | * Restore the BAR values for a given device, so as to make it | |
254 | * accessible by its driver. | |
255 | */ | |
256 | void | |
257 | pci_restore_bars(struct pci_dev *dev) | |
258 | { | |
259 | int i, numres; | |
260 | ||
261 | switch (dev->hdr_type) { | |
262 | case PCI_HEADER_TYPE_NORMAL: | |
263 | numres = 6; | |
264 | break; | |
265 | case PCI_HEADER_TYPE_BRIDGE: | |
266 | numres = 2; | |
267 | break; | |
268 | case PCI_HEADER_TYPE_CARDBUS: | |
269 | numres = 1; | |
270 | break; | |
271 | default: | |
272 | /* Should never get here, but just in case... */ | |
273 | return; | |
274 | } | |
275 | ||
276 | for (i = 0; i < numres; i ++) | |
277 | pci_update_resource(dev, &dev->resource[i], i); | |
278 | } | |
279 | ||
8f7020d3 RD |
280 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
281 | ||
1da177e4 LT |
282 | /** |
283 | * pci_set_power_state - Set the power state of a PCI device | |
284 | * @dev: PCI device to be suspended | |
285 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
286 | * | |
287 | * Transition a device to a new power state, using the Power Management | |
288 | * Capabilities in the device's config space. | |
289 | * | |
290 | * RETURN VALUE: | |
291 | * -EINVAL if trying to enter a lower state than we're already in. | |
292 | * 0 if we're already in the requested state. | |
293 | * -EIO if device does not support PCI PM. | |
294 | * 0 if we can successfully change the power state. | |
295 | */ | |
1da177e4 LT |
296 | int |
297 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
298 | { | |
064b53db | 299 | int pm, need_restore = 0; |
1da177e4 LT |
300 | u16 pmcsr, pmc; |
301 | ||
302 | /* bound the state we're entering */ | |
303 | if (state > PCI_D3hot) | |
304 | state = PCI_D3hot; | |
305 | ||
306 | /* Validate current state: | |
307 | * Can enter D0 from any state, but if we can only go deeper | |
308 | * to sleep if we're already in a low power state | |
309 | */ | |
02669492 AM |
310 | if (state != PCI_D0 && dev->current_state > state) { |
311 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
312 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 313 | return -EINVAL; |
02669492 | 314 | } else if (dev->current_state == state) |
1da177e4 LT |
315 | return 0; /* we're already there */ |
316 | ||
317 | /* find PCI PM capability in list */ | |
318 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
319 | ||
320 | /* abort if the device doesn't support PM capabilities */ | |
321 | if (!pm) | |
322 | return -EIO; | |
323 | ||
324 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); | |
3fe9d19f | 325 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
326 | printk(KERN_DEBUG |
327 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
328 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
329 | return -EIO; | |
330 | } | |
331 | ||
332 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
333 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
334 | return -EIO; | |
335 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
336 | return -EIO; | |
1da177e4 | 337 | |
064b53db JL |
338 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
339 | ||
32a36585 | 340 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
341 | * This doesn't affect PME_Status, disables PME_En, and |
342 | * sets PowerState to 0. | |
343 | */ | |
32a36585 | 344 | switch (dev->current_state) { |
d3535fbb JL |
345 | case PCI_D0: |
346 | case PCI_D1: | |
347 | case PCI_D2: | |
348 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
349 | pmcsr |= state; | |
350 | break; | |
32a36585 JL |
351 | case PCI_UNKNOWN: /* Boot-up */ |
352 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
353 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 354 | need_restore = 1; |
32a36585 | 355 | /* Fall-through: force to D0 */ |
32a36585 | 356 | default: |
d3535fbb | 357 | pmcsr = 0; |
32a36585 | 358 | break; |
1da177e4 LT |
359 | } |
360 | ||
361 | /* enter specified state */ | |
362 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
363 | ||
364 | /* Mandatory power management transition delays */ | |
365 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
366 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
367 | msleep(10); | |
368 | else if (state == PCI_D2 || dev->current_state == PCI_D2) | |
369 | udelay(200); | |
1da177e4 | 370 | |
b913100d DSL |
371 | /* |
372 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
373 | * Firmware method after natice method ? | |
374 | */ | |
375 | if (platform_pci_set_power_state) | |
376 | platform_pci_set_power_state(dev, state); | |
377 | ||
378 | dev->current_state = state; | |
064b53db JL |
379 | |
380 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
381 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
382 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
383 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
384 | * For example, at least some versions of the 3c905B and the | |
385 | * 3c556B exhibit this behaviour. | |
386 | * | |
387 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
388 | * devices in a D3hot state at boot. Consequently, we need to | |
389 | * restore at least the BARs so that the device will be | |
390 | * accessible to its driver. | |
391 | */ | |
392 | if (need_restore) | |
393 | pci_restore_bars(dev); | |
394 | ||
1da177e4 LT |
395 | return 0; |
396 | } | |
397 | ||
f165b10f | 398 | int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 399 | |
1da177e4 LT |
400 | /** |
401 | * pci_choose_state - Choose the power state of a PCI device | |
402 | * @dev: PCI device to be suspended | |
403 | * @state: target sleep state for the whole system. This is the value | |
404 | * that is passed to suspend() function. | |
405 | * | |
406 | * Returns PCI power state suitable for given device and given system | |
407 | * message. | |
408 | */ | |
409 | ||
410 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
411 | { | |
0f64474b DSL |
412 | int ret; |
413 | ||
1da177e4 LT |
414 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
415 | return PCI_D0; | |
416 | ||
0f64474b DSL |
417 | if (platform_pci_choose_state) { |
418 | ret = platform_pci_choose_state(dev, state); | |
419 | if (ret >= 0) | |
ca078bae | 420 | state.event = ret; |
0f64474b | 421 | } |
ca078bae PM |
422 | |
423 | switch (state.event) { | |
424 | case PM_EVENT_ON: | |
425 | return PCI_D0; | |
426 | case PM_EVENT_FREEZE: | |
427 | case PM_EVENT_SUSPEND: | |
428 | return PCI_D3hot; | |
1da177e4 | 429 | default: |
ca078bae | 430 | printk("They asked me for state %d\n", state.event); |
1da177e4 LT |
431 | BUG(); |
432 | } | |
433 | return PCI_D0; | |
434 | } | |
435 | ||
436 | EXPORT_SYMBOL(pci_choose_state); | |
437 | ||
438 | /** | |
439 | * pci_save_state - save the PCI configuration space of a device before suspending | |
440 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
441 | */ |
442 | int | |
443 | pci_save_state(struct pci_dev *dev) | |
444 | { | |
445 | int i; | |
446 | /* XXX: 100% dword access ok here? */ | |
447 | for (i = 0; i < 16; i++) | |
448 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
41017f0c SL |
449 | if ((i = pci_save_msi_state(dev)) != 0) |
450 | return i; | |
451 | if ((i = pci_save_msix_state(dev)) != 0) | |
452 | return i; | |
1da177e4 LT |
453 | return 0; |
454 | } | |
455 | ||
456 | /** | |
457 | * pci_restore_state - Restore the saved state of a PCI device | |
458 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
459 | */ |
460 | int | |
461 | pci_restore_state(struct pci_dev *dev) | |
462 | { | |
463 | int i; | |
04d9c1a1 DJ |
464 | int val; |
465 | ||
466 | for (i = 0; i < 16; i++) { | |
467 | pci_read_config_dword(dev, i * 4, &val); | |
468 | if (val != dev->saved_config_space[i]) { | |
469 | printk(KERN_DEBUG "PM: Writing back config space on " | |
470 | "device %s at offset %x (was %x, writing %x)\n", | |
471 | pci_name(dev), i, | |
472 | val, (int)dev->saved_config_space[i]); | |
473 | pci_write_config_dword(dev,i * 4, | |
474 | dev->saved_config_space[i]); | |
475 | } | |
476 | } | |
41017f0c SL |
477 | pci_restore_msi_state(dev); |
478 | pci_restore_msix_state(dev); | |
1da177e4 LT |
479 | return 0; |
480 | } | |
481 | ||
482 | /** | |
483 | * pci_enable_device_bars - Initialize some of a device for use | |
484 | * @dev: PCI device to be initialized | |
485 | * @bars: bitmask of BAR's that must be configured | |
486 | * | |
487 | * Initialize device before it's used by a driver. Ask low-level code | |
488 | * to enable selected I/O and memory resources. Wake up the device if it | |
489 | * was suspended. Beware, this function can fail. | |
490 | */ | |
491 | ||
492 | int | |
493 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
494 | { | |
495 | int err; | |
496 | ||
95a62965 | 497 | err = pci_set_power_state(dev, PCI_D0); |
11f3859b | 498 | if (err < 0 && err != -EIO) |
95a62965 GKH |
499 | return err; |
500 | err = pcibios_enable_device(dev, bars); | |
501 | if (err < 0) | |
1da177e4 LT |
502 | return err; |
503 | return 0; | |
504 | } | |
505 | ||
506 | /** | |
507 | * pci_enable_device - Initialize device before it's used by a driver. | |
508 | * @dev: PCI device to be initialized | |
509 | * | |
510 | * Initialize device before it's used by a driver. Ask low-level code | |
511 | * to enable I/O and memory. Wake up the device if it was suspended. | |
512 | * Beware, this function can fail. | |
513 | */ | |
514 | int | |
515 | pci_enable_device(struct pci_dev *dev) | |
516 | { | |
b64c05e7 GG |
517 | int err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
518 | if (err) | |
1da177e4 LT |
519 | return err; |
520 | pci_fixup_device(pci_fixup_enable, dev); | |
ceb43744 | 521 | dev->is_enabled = 1; |
1da177e4 LT |
522 | return 0; |
523 | } | |
524 | ||
525 | /** | |
526 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
527 | * @dev: the PCI device to disable | |
528 | * | |
529 | * Disables architecture specific PCI resources for the device. This | |
530 | * is the default implementation. Architecture implementations can | |
531 | * override this. | |
532 | */ | |
533 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
534 | ||
535 | /** | |
536 | * pci_disable_device - Disable PCI device after use | |
537 | * @dev: PCI device to be disabled | |
538 | * | |
539 | * Signal to the system that the PCI device is not in use by the system | |
540 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
541 | */ | |
542 | void | |
543 | pci_disable_device(struct pci_dev *dev) | |
544 | { | |
545 | u16 pci_command; | |
546 | ||
1da177e4 LT |
547 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
548 | if (pci_command & PCI_COMMAND_MASTER) { | |
549 | pci_command &= ~PCI_COMMAND_MASTER; | |
550 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
551 | } | |
ceb43744 | 552 | dev->is_busmaster = 0; |
1da177e4 LT |
553 | |
554 | pcibios_disable_device(dev); | |
ceb43744 | 555 | dev->is_enabled = 0; |
1da177e4 LT |
556 | } |
557 | ||
558 | /** | |
559 | * pci_enable_wake - enable device to generate PME# when suspended | |
560 | * @dev: - PCI device to operate on | |
561 | * @state: - Current state of device. | |
562 | * @enable: - Flag to enable or disable generation | |
563 | * | |
564 | * Set the bits in the device's PM Capabilities to generate PME# when | |
565 | * the system is suspended. | |
566 | * | |
567 | * -EIO is returned if device doesn't have PM Capabilities. | |
568 | * -EINVAL is returned if device supports it, but can't generate wake events. | |
569 | * 0 if operation is successful. | |
570 | * | |
571 | */ | |
572 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
573 | { | |
574 | int pm; | |
575 | u16 value; | |
576 | ||
577 | /* find PCI PM capability in list */ | |
578 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
579 | ||
580 | /* If device doesn't support PM Capabilities, but request is to disable | |
581 | * wake events, it's a nop; otherwise fail */ | |
582 | if (!pm) | |
583 | return enable ? -EIO : 0; | |
584 | ||
585 | /* Check device's ability to generate PME# */ | |
586 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
587 | ||
588 | value &= PCI_PM_CAP_PME_MASK; | |
589 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
590 | ||
591 | /* Check if it can generate PME# from requested state. */ | |
592 | if (!value || !(value & (1 << state))) | |
593 | return enable ? -EINVAL : 0; | |
594 | ||
595 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
596 | ||
597 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
598 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
599 | ||
600 | if (!enable) | |
601 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
602 | ||
603 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | int | |
609 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
610 | { | |
611 | u8 pin; | |
612 | ||
514d207d | 613 | pin = dev->pin; |
1da177e4 LT |
614 | if (!pin) |
615 | return -1; | |
616 | pin--; | |
617 | while (dev->bus->self) { | |
618 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
619 | dev = dev->bus->self; | |
620 | } | |
621 | *bridge = dev; | |
622 | return pin; | |
623 | } | |
624 | ||
625 | /** | |
626 | * pci_release_region - Release a PCI bar | |
627 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
628 | * @bar: BAR to release | |
629 | * | |
630 | * Releases the PCI I/O and memory resources previously reserved by a | |
631 | * successful call to pci_request_region. Call this function only | |
632 | * after all use of the PCI regions has ceased. | |
633 | */ | |
634 | void pci_release_region(struct pci_dev *pdev, int bar) | |
635 | { | |
636 | if (pci_resource_len(pdev, bar) == 0) | |
637 | return; | |
638 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
639 | release_region(pci_resource_start(pdev, bar), | |
640 | pci_resource_len(pdev, bar)); | |
641 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
642 | release_mem_region(pci_resource_start(pdev, bar), | |
643 | pci_resource_len(pdev, bar)); | |
644 | } | |
645 | ||
646 | /** | |
647 | * pci_request_region - Reserved PCI I/O and memory resource | |
648 | * @pdev: PCI device whose resources are to be reserved | |
649 | * @bar: BAR to be reserved | |
650 | * @res_name: Name to be associated with resource. | |
651 | * | |
652 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
653 | * being reserved by owner @res_name. Do not access any | |
654 | * address inside the PCI regions unless this call returns | |
655 | * successfully. | |
656 | * | |
657 | * Returns 0 on success, or %EBUSY on error. A warning | |
658 | * message is also printed on failure. | |
659 | */ | |
3c990e92 | 660 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 LT |
661 | { |
662 | if (pci_resource_len(pdev, bar) == 0) | |
663 | return 0; | |
664 | ||
665 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
666 | if (!request_region(pci_resource_start(pdev, bar), | |
667 | pci_resource_len(pdev, bar), res_name)) | |
668 | goto err_out; | |
669 | } | |
670 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
671 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
672 | pci_resource_len(pdev, bar), res_name)) | |
673 | goto err_out; | |
674 | } | |
675 | ||
676 | return 0; | |
677 | ||
678 | err_out: | |
679 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", | |
680 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
681 | bar + 1, /* PCI BAR # */ | |
682 | pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), | |
683 | pci_name(pdev)); | |
684 | return -EBUSY; | |
685 | } | |
686 | ||
687 | ||
688 | /** | |
689 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
690 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
691 | * | |
692 | * Releases all PCI I/O and memory resources previously reserved by a | |
693 | * successful call to pci_request_regions. Call this function only | |
694 | * after all use of the PCI regions has ceased. | |
695 | */ | |
696 | ||
697 | void pci_release_regions(struct pci_dev *pdev) | |
698 | { | |
699 | int i; | |
700 | ||
701 | for (i = 0; i < 6; i++) | |
702 | pci_release_region(pdev, i); | |
703 | } | |
704 | ||
705 | /** | |
706 | * pci_request_regions - Reserved PCI I/O and memory resources | |
707 | * @pdev: PCI device whose resources are to be reserved | |
708 | * @res_name: Name to be associated with resource. | |
709 | * | |
710 | * Mark all PCI regions associated with PCI device @pdev as | |
711 | * being reserved by owner @res_name. Do not access any | |
712 | * address inside the PCI regions unless this call returns | |
713 | * successfully. | |
714 | * | |
715 | * Returns 0 on success, or %EBUSY on error. A warning | |
716 | * message is also printed on failure. | |
717 | */ | |
3c990e92 | 718 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 LT |
719 | { |
720 | int i; | |
721 | ||
722 | for (i = 0; i < 6; i++) | |
723 | if(pci_request_region(pdev, i, res_name)) | |
724 | goto err_out; | |
725 | return 0; | |
726 | ||
727 | err_out: | |
728 | while(--i >= 0) | |
729 | pci_release_region(pdev, i); | |
730 | ||
731 | return -EBUSY; | |
732 | } | |
733 | ||
734 | /** | |
735 | * pci_set_master - enables bus-mastering for device dev | |
736 | * @dev: the PCI device to enable | |
737 | * | |
738 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
739 | * to do the needed arch specific settings. | |
740 | */ | |
741 | void | |
742 | pci_set_master(struct pci_dev *dev) | |
743 | { | |
744 | u16 cmd; | |
745 | ||
746 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
747 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
748 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
749 | cmd |= PCI_COMMAND_MASTER; | |
750 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
751 | } | |
752 | dev->is_busmaster = 1; | |
753 | pcibios_set_master(dev); | |
754 | } | |
755 | ||
756 | #ifndef HAVE_ARCH_PCI_MWI | |
757 | /* This can be overridden by arch code. */ | |
758 | u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; | |
759 | ||
760 | /** | |
761 | * pci_generic_prep_mwi - helper function for pci_set_mwi | |
762 | * @dev: the PCI device for which MWI is enabled | |
763 | * | |
764 | * Helper function for generic implementation of pcibios_prep_mwi | |
765 | * function. Originally copied from drivers/net/acenic.c. | |
766 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. | |
767 | * | |
768 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
769 | */ | |
770 | static int | |
771 | pci_generic_prep_mwi(struct pci_dev *dev) | |
772 | { | |
773 | u8 cacheline_size; | |
774 | ||
775 | if (!pci_cache_line_size) | |
776 | return -EINVAL; /* The system doesn't support MWI. */ | |
777 | ||
778 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
779 | equal to or multiple of the right value. */ | |
780 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
781 | if (cacheline_size >= pci_cache_line_size && | |
782 | (cacheline_size % pci_cache_line_size) == 0) | |
783 | return 0; | |
784 | ||
785 | /* Write the correct value. */ | |
786 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
787 | /* Read it back. */ | |
788 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
789 | if (cacheline_size == pci_cache_line_size) | |
790 | return 0; | |
791 | ||
792 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
793 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
794 | ||
795 | return -EINVAL; | |
796 | } | |
797 | #endif /* !HAVE_ARCH_PCI_MWI */ | |
798 | ||
799 | /** | |
800 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
801 | * @dev: the PCI device for which MWI is enabled | |
802 | * | |
803 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, | |
804 | * and then calls @pcibios_set_mwi to do the needed arch specific | |
805 | * operations or a generic mwi-prep function. | |
806 | * | |
807 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
808 | */ | |
809 | int | |
810 | pci_set_mwi(struct pci_dev *dev) | |
811 | { | |
812 | int rc; | |
813 | u16 cmd; | |
814 | ||
815 | #ifdef HAVE_ARCH_PCI_MWI | |
816 | rc = pcibios_prep_mwi(dev); | |
817 | #else | |
818 | rc = pci_generic_prep_mwi(dev); | |
819 | #endif | |
820 | ||
821 | if (rc) | |
822 | return rc; | |
823 | ||
824 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
825 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
826 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); | |
827 | cmd |= PCI_COMMAND_INVALIDATE; | |
828 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
829 | } | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
834 | /** | |
835 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
836 | * @dev: the PCI device to disable | |
837 | * | |
838 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
839 | */ | |
840 | void | |
841 | pci_clear_mwi(struct pci_dev *dev) | |
842 | { | |
843 | u16 cmd; | |
844 | ||
845 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
846 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
847 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
848 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
849 | } | |
850 | } | |
851 | ||
a04ce0ff BR |
852 | /** |
853 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
854 | * @pdev: the PCI device to operate on |
855 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
856 | * |
857 | * Enables/disables PCI INTx for device dev | |
858 | */ | |
859 | void | |
860 | pci_intx(struct pci_dev *pdev, int enable) | |
861 | { | |
862 | u16 pci_command, new; | |
863 | ||
864 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
865 | ||
866 | if (enable) { | |
867 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
868 | } else { | |
869 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
870 | } | |
871 | ||
872 | if (new != pci_command) { | |
2fd9d74b | 873 | pci_write_config_word(pdev, PCI_COMMAND, new); |
a04ce0ff BR |
874 | } |
875 | } | |
876 | ||
1da177e4 LT |
877 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
878 | /* | |
879 | * These can be overridden by arch-specific implementations | |
880 | */ | |
881 | int | |
882 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
883 | { | |
884 | if (!pci_dma_supported(dev, mask)) | |
885 | return -EIO; | |
886 | ||
887 | dev->dma_mask = mask; | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
1da177e4 LT |
892 | int |
893 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
894 | { | |
895 | if (!pci_dma_supported(dev, mask)) | |
896 | return -EIO; | |
897 | ||
898 | dev->dev.coherent_dma_mask = mask; | |
899 | ||
900 | return 0; | |
901 | } | |
902 | #endif | |
903 | ||
904 | static int __devinit pci_init(void) | |
905 | { | |
906 | struct pci_dev *dev = NULL; | |
907 | ||
908 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
909 | pci_fixup_device(pci_fixup_final, dev); | |
910 | } | |
911 | return 0; | |
912 | } | |
913 | ||
914 | static int __devinit pci_setup(char *str) | |
915 | { | |
916 | while (str) { | |
917 | char *k = strchr(str, ','); | |
918 | if (k) | |
919 | *k++ = 0; | |
920 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
921 | if (!strcmp(str, "nomsi")) { |
922 | pci_no_msi(); | |
923 | } else { | |
924 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
925 | str); | |
926 | } | |
1da177e4 LT |
927 | } |
928 | str = k; | |
929 | } | |
930 | return 1; | |
931 | } | |
932 | ||
933 | device_initcall(pci_init); | |
934 | ||
935 | __setup("pci=", pci_setup); | |
936 | ||
937 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
938 | /* FIXME: Some boxes have multiple ISA bridges! */ | |
939 | struct pci_dev *isa_bridge; | |
940 | EXPORT_SYMBOL(isa_bridge); | |
941 | #endif | |
942 | ||
064b53db | 943 | EXPORT_SYMBOL_GPL(pci_restore_bars); |
1da177e4 LT |
944 | EXPORT_SYMBOL(pci_enable_device_bars); |
945 | EXPORT_SYMBOL(pci_enable_device); | |
946 | EXPORT_SYMBOL(pci_disable_device); | |
1da177e4 LT |
947 | EXPORT_SYMBOL(pci_find_capability); |
948 | EXPORT_SYMBOL(pci_bus_find_capability); | |
949 | EXPORT_SYMBOL(pci_release_regions); | |
950 | EXPORT_SYMBOL(pci_request_regions); | |
951 | EXPORT_SYMBOL(pci_release_region); | |
952 | EXPORT_SYMBOL(pci_request_region); | |
953 | EXPORT_SYMBOL(pci_set_master); | |
954 | EXPORT_SYMBOL(pci_set_mwi); | |
955 | EXPORT_SYMBOL(pci_clear_mwi); | |
a04ce0ff | 956 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 957 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
958 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
959 | EXPORT_SYMBOL(pci_assign_resource); | |
960 | EXPORT_SYMBOL(pci_find_parent_resource); | |
961 | ||
962 | EXPORT_SYMBOL(pci_set_power_state); | |
963 | EXPORT_SYMBOL(pci_save_state); | |
964 | EXPORT_SYMBOL(pci_restore_state); | |
965 | EXPORT_SYMBOL(pci_enable_wake); | |
966 | ||
967 | /* Quirk info */ | |
968 | ||
969 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
970 | EXPORT_SYMBOL(pci_pci_problems); |