Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
1da177e4 | 20 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 21 | #include "pci.h" |
1da177e4 | 22 | |
ffadcc2f | 23 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 24 | |
32a2eea7 JG |
25 | #ifdef CONFIG_PCI_DOMAINS |
26 | int pci_domains_supported = 1; | |
27 | #endif | |
28 | ||
4516a618 AN |
29 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
30 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
31 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
32 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
33 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
34 | ||
1da177e4 LT |
35 | /** |
36 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
37 | * @bus: pointer to PCI bus structure to search | |
38 | * | |
39 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
40 | * including the given PCI bus and its list of child PCI buses. | |
41 | */ | |
96bde06a | 42 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
43 | { |
44 | struct list_head *tmp; | |
45 | unsigned char max, n; | |
46 | ||
b82db5ce | 47 | max = bus->subordinate; |
1da177e4 LT |
48 | list_for_each(tmp, &bus->children) { |
49 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
50 | if(n > max) | |
51 | max = n; | |
52 | } | |
53 | return max; | |
54 | } | |
b82db5ce | 55 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 56 | |
b82db5ce | 57 | #if 0 |
1da177e4 LT |
58 | /** |
59 | * pci_max_busnr - returns maximum PCI bus number | |
60 | * | |
61 | * Returns the highest PCI bus number present in the system global list of | |
62 | * PCI buses. | |
63 | */ | |
64 | unsigned char __devinit | |
65 | pci_max_busnr(void) | |
66 | { | |
67 | struct pci_bus *bus = NULL; | |
68 | unsigned char max, n; | |
69 | ||
70 | max = 0; | |
71 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
72 | n = pci_bus_max_busnr(bus); | |
73 | if(n > max) | |
74 | max = n; | |
75 | } | |
76 | return max; | |
77 | } | |
78 | ||
54c762fe AB |
79 | #endif /* 0 */ |
80 | ||
687d5fe3 ME |
81 | #define PCI_FIND_CAP_TTL 48 |
82 | ||
83 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
84 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
85 | { |
86 | u8 id; | |
24a4e377 | 87 | |
687d5fe3 | 88 | while ((*ttl)--) { |
24a4e377 RD |
89 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
90 | if (pos < 0x40) | |
91 | break; | |
92 | pos &= ~3; | |
93 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
94 | &id); | |
95 | if (id == 0xff) | |
96 | break; | |
97 | if (id == cap) | |
98 | return pos; | |
99 | pos += PCI_CAP_LIST_NEXT; | |
100 | } | |
101 | return 0; | |
102 | } | |
103 | ||
687d5fe3 ME |
104 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
105 | u8 pos, int cap) | |
106 | { | |
107 | int ttl = PCI_FIND_CAP_TTL; | |
108 | ||
109 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
110 | } | |
111 | ||
24a4e377 RD |
112 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
113 | { | |
114 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
115 | pos + PCI_CAP_LIST_NEXT, cap); | |
116 | } | |
117 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
118 | ||
d3bac118 ME |
119 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
120 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
121 | { |
122 | u16 status; | |
1da177e4 LT |
123 | |
124 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
125 | if (!(status & PCI_STATUS_CAP_LIST)) | |
126 | return 0; | |
127 | ||
128 | switch (hdr_type) { | |
129 | case PCI_HEADER_TYPE_NORMAL: | |
130 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 131 | return PCI_CAPABILITY_LIST; |
1da177e4 | 132 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 133 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
134 | default: |
135 | return 0; | |
136 | } | |
d3bac118 ME |
137 | |
138 | return 0; | |
1da177e4 LT |
139 | } |
140 | ||
141 | /** | |
142 | * pci_find_capability - query for devices' capabilities | |
143 | * @dev: PCI device to query | |
144 | * @cap: capability code | |
145 | * | |
146 | * Tell if a device supports a given PCI capability. | |
147 | * Returns the address of the requested capability structure within the | |
148 | * device's PCI configuration space or 0 in case the device does not | |
149 | * support it. Possible values for @cap: | |
150 | * | |
151 | * %PCI_CAP_ID_PM Power Management | |
152 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
153 | * %PCI_CAP_ID_VPD Vital Product Data | |
154 | * %PCI_CAP_ID_SLOTID Slot Identification | |
155 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
156 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
157 | * %PCI_CAP_ID_PCIX PCI-X | |
158 | * %PCI_CAP_ID_EXP PCI Express | |
159 | */ | |
160 | int pci_find_capability(struct pci_dev *dev, int cap) | |
161 | { | |
d3bac118 ME |
162 | int pos; |
163 | ||
164 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
165 | if (pos) | |
166 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
167 | ||
168 | return pos; | |
1da177e4 LT |
169 | } |
170 | ||
171 | /** | |
172 | * pci_bus_find_capability - query for devices' capabilities | |
173 | * @bus: the PCI bus to query | |
174 | * @devfn: PCI device to query | |
175 | * @cap: capability code | |
176 | * | |
177 | * Like pci_find_capability() but works for pci devices that do not have a | |
178 | * pci_dev structure set up yet. | |
179 | * | |
180 | * Returns the address of the requested capability structure within the | |
181 | * device's PCI configuration space or 0 in case the device does not | |
182 | * support it. | |
183 | */ | |
184 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
185 | { | |
d3bac118 | 186 | int pos; |
1da177e4 LT |
187 | u8 hdr_type; |
188 | ||
189 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
190 | ||
d3bac118 ME |
191 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
192 | if (pos) | |
193 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
194 | ||
195 | return pos; | |
1da177e4 LT |
196 | } |
197 | ||
198 | /** | |
199 | * pci_find_ext_capability - Find an extended capability | |
200 | * @dev: PCI device to query | |
201 | * @cap: capability code | |
202 | * | |
203 | * Returns the address of the requested extended capability structure | |
204 | * within the device's PCI configuration space or 0 if the device does | |
205 | * not support it. Possible values for @cap: | |
206 | * | |
207 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
208 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
209 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
210 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
211 | */ | |
212 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
213 | { | |
214 | u32 header; | |
215 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
216 | int pos = 0x100; | |
217 | ||
218 | if (dev->cfg_size <= 256) | |
219 | return 0; | |
220 | ||
221 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
222 | return 0; | |
223 | ||
224 | /* | |
225 | * If we have no capabilities, this is indicated by cap ID, | |
226 | * cap version and next pointer all being 0. | |
227 | */ | |
228 | if (header == 0) | |
229 | return 0; | |
230 | ||
231 | while (ttl-- > 0) { | |
232 | if (PCI_EXT_CAP_ID(header) == cap) | |
233 | return pos; | |
234 | ||
235 | pos = PCI_EXT_CAP_NEXT(header); | |
236 | if (pos < 0x100) | |
237 | break; | |
238 | ||
239 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
240 | break; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
3a720d72 | 245 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 246 | |
687d5fe3 ME |
247 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
248 | { | |
249 | int rc, ttl = PCI_FIND_CAP_TTL; | |
250 | u8 cap, mask; | |
251 | ||
252 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
253 | mask = HT_3BIT_CAP_MASK; | |
254 | else | |
255 | mask = HT_5BIT_CAP_MASK; | |
256 | ||
257 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
258 | PCI_CAP_ID_HT, &ttl); | |
259 | while (pos) { | |
260 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
261 | if (rc != PCIBIOS_SUCCESSFUL) | |
262 | return 0; | |
263 | ||
264 | if ((cap & mask) == ht_cap) | |
265 | return pos; | |
266 | ||
47a4d5be BG |
267 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
268 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
269 | PCI_CAP_ID_HT, &ttl); |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | /** | |
275 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
276 | * @dev: PCI device to query | |
277 | * @pos: Position from which to continue searching | |
278 | * @ht_cap: Hypertransport capability code | |
279 | * | |
280 | * To be used in conjunction with pci_find_ht_capability() to search for | |
281 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
282 | * from pci_find_ht_capability(). | |
283 | * | |
284 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
285 | * steps to avoid an infinite loop. | |
286 | */ | |
287 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
288 | { | |
289 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
290 | } | |
291 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
292 | ||
293 | /** | |
294 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
295 | * @dev: PCI device to query | |
296 | * @ht_cap: Hypertransport capability code | |
297 | * | |
298 | * Tell if a device supports a given Hypertransport capability. | |
299 | * Returns an address within the device's PCI configuration space | |
300 | * or 0 in case the device does not support the request capability. | |
301 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
302 | * which has a Hypertransport capability matching @ht_cap. | |
303 | */ | |
304 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
305 | { | |
306 | int pos; | |
307 | ||
308 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
309 | if (pos) | |
310 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
311 | ||
312 | return pos; | |
313 | } | |
314 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
315 | ||
1da177e4 LT |
316 | /** |
317 | * pci_find_parent_resource - return resource region of parent bus of given region | |
318 | * @dev: PCI device structure contains resources to be searched | |
319 | * @res: child resource record for which parent is sought | |
320 | * | |
321 | * For given resource region of given device, return the resource | |
322 | * region of parent bus the given region is contained in or where | |
323 | * it should be allocated from. | |
324 | */ | |
325 | struct resource * | |
326 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
327 | { | |
328 | const struct pci_bus *bus = dev->bus; | |
329 | int i; | |
330 | struct resource *best = NULL; | |
331 | ||
332 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
333 | struct resource *r = bus->resource[i]; | |
334 | if (!r) | |
335 | continue; | |
336 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
337 | continue; /* Not contained */ | |
338 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
339 | continue; /* Wrong type */ | |
340 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
341 | return r; /* Exact match */ | |
342 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
343 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
344 | } | |
345 | return best; | |
346 | } | |
347 | ||
064b53db JL |
348 | /** |
349 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
350 | * @dev: PCI device to have its BARs restored | |
351 | * | |
352 | * Restore the BAR values for a given device, so as to make it | |
353 | * accessible by its driver. | |
354 | */ | |
ad668599 | 355 | static void |
064b53db JL |
356 | pci_restore_bars(struct pci_dev *dev) |
357 | { | |
358 | int i, numres; | |
359 | ||
360 | switch (dev->hdr_type) { | |
361 | case PCI_HEADER_TYPE_NORMAL: | |
362 | numres = 6; | |
363 | break; | |
364 | case PCI_HEADER_TYPE_BRIDGE: | |
365 | numres = 2; | |
366 | break; | |
367 | case PCI_HEADER_TYPE_CARDBUS: | |
368 | numres = 1; | |
369 | break; | |
370 | default: | |
371 | /* Should never get here, but just in case... */ | |
372 | return; | |
373 | } | |
374 | ||
375 | for (i = 0; i < numres; i ++) | |
376 | pci_update_resource(dev, &dev->resource[i], i); | |
377 | } | |
378 | ||
961d9120 RW |
379 | static struct pci_platform_pm_ops *pci_platform_pm; |
380 | ||
381 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
382 | { | |
383 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state) | |
384 | return -EINVAL; | |
385 | pci_platform_pm = ops; | |
386 | return 0; | |
387 | } | |
388 | ||
389 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
390 | { | |
391 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
392 | } | |
393 | ||
394 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
395 | pci_power_t t) | |
396 | { | |
397 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
398 | } | |
399 | ||
400 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
401 | { | |
402 | return pci_platform_pm ? | |
403 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
404 | } | |
8f7020d3 | 405 | |
1da177e4 | 406 | /** |
44e4e66e RW |
407 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
408 | * given PCI device | |
409 | * @dev: PCI device to handle. | |
410 | * @pm: PCI PM capability offset of the device. | |
411 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1da177e4 | 412 | * |
44e4e66e RW |
413 | * RETURN VALUE: |
414 | * -EINVAL if the requested state is invalid. | |
415 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
416 | * wrong version, or device doesn't support the requested state. | |
417 | * 0 if device already is in the requested state. | |
418 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 419 | */ |
44e4e66e RW |
420 | static int |
421 | pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) | |
1da177e4 | 422 | { |
1da177e4 | 423 | u16 pmcsr, pmc; |
44e4e66e | 424 | bool need_restore = false; |
1da177e4 | 425 | |
cca03dec AL |
426 | if (!pm) |
427 | return -EIO; | |
428 | ||
44e4e66e RW |
429 | if (state < PCI_D0 || state > PCI_D3hot) |
430 | return -EINVAL; | |
431 | ||
1da177e4 LT |
432 | /* Validate current state: |
433 | * Can enter D0 from any state, but if we can only go deeper | |
434 | * to sleep if we're already in a low power state | |
435 | */ | |
44e4e66e RW |
436 | if (dev->current_state == state) { |
437 | /* we're already there */ | |
438 | return 0; | |
439 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
440 | && dev->current_state > state) { | |
80ccba11 BH |
441 | dev_err(&dev->dev, "invalid power transition " |
442 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 443 | return -EINVAL; |
44e4e66e | 444 | } |
1da177e4 | 445 | |
44e4e66e | 446 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); |
ffadcc2f | 447 | |
3fe9d19f | 448 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
44e4e66e RW |
449 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", |
450 | pmc & PCI_PM_CAP_VER_MASK); | |
1da177e4 LT |
451 | return -EIO; |
452 | } | |
453 | ||
454 | /* check if this device supports the desired state */ | |
44e4e66e RW |
455 | if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
456 | || (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))) | |
3fe9d19f | 457 | return -EIO; |
1da177e4 | 458 | |
064b53db JL |
459 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
460 | ||
32a36585 | 461 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
462 | * This doesn't affect PME_Status, disables PME_En, and |
463 | * sets PowerState to 0. | |
464 | */ | |
32a36585 | 465 | switch (dev->current_state) { |
d3535fbb JL |
466 | case PCI_D0: |
467 | case PCI_D1: | |
468 | case PCI_D2: | |
469 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
470 | pmcsr |= state; | |
471 | break; | |
32a36585 JL |
472 | case PCI_UNKNOWN: /* Boot-up */ |
473 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
474 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 475 | need_restore = true; |
32a36585 | 476 | /* Fall-through: force to D0 */ |
32a36585 | 477 | default: |
d3535fbb | 478 | pmcsr = 0; |
32a36585 | 479 | break; |
1da177e4 LT |
480 | } |
481 | ||
482 | /* enter specified state */ | |
483 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
484 | ||
485 | /* Mandatory power management transition delays */ | |
486 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
487 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 488 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
489 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
490 | udelay(200); | |
1da177e4 | 491 | |
b913100d | 492 | dev->current_state = state; |
064b53db JL |
493 | |
494 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
495 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
496 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
497 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
498 | * For example, at least some versions of the 3c905B and the | |
499 | * 3c556B exhibit this behaviour. | |
500 | * | |
501 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
502 | * devices in a D3hot state at boot. Consequently, we need to | |
503 | * restore at least the BARs so that the device will be | |
504 | * accessible to its driver. | |
505 | */ | |
506 | if (need_restore) | |
507 | pci_restore_bars(dev); | |
508 | ||
7d715a6c SL |
509 | if (dev->bus->self) |
510 | pcie_aspm_pm_state_change(dev->bus->self); | |
511 | ||
1da177e4 LT |
512 | return 0; |
513 | } | |
514 | ||
44e4e66e RW |
515 | /** |
516 | * pci_update_current_state - Read PCI power state of given device from its | |
517 | * PCI PM registers and cache it | |
518 | * @dev: PCI device to handle. | |
519 | * @pm: PCI PM capability offset of the device. | |
520 | */ | |
521 | static void pci_update_current_state(struct pci_dev *dev, int pm) | |
522 | { | |
523 | if (pm) { | |
524 | u16 pmcsr; | |
525 | ||
526 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
527 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
528 | } | |
529 | } | |
530 | ||
531 | /** | |
532 | * pci_set_power_state - Set the power state of a PCI device | |
533 | * @dev: PCI device to handle. | |
534 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
535 | * | |
536 | * Transition a device to a new power state, using the platform formware and/or | |
537 | * the device's PCI PM registers. | |
538 | * | |
539 | * RETURN VALUE: | |
540 | * -EINVAL if the requested state is invalid. | |
541 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
542 | * wrong version, or device doesn't support the requested state. | |
543 | * 0 if device already is in the requested state. | |
544 | * 0 if device's power state has been successfully changed. | |
545 | */ | |
546 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
547 | { | |
548 | int pm, error; | |
549 | ||
550 | /* bound the state we're entering */ | |
551 | if (state > PCI_D3hot) | |
552 | state = PCI_D3hot; | |
553 | else if (state < PCI_D0) | |
554 | state = PCI_D0; | |
555 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
556 | /* | |
557 | * If the device or the parent bridge do not support PCI PM, | |
558 | * ignore the request if we're doing anything other than putting | |
559 | * it into D0 (which would only happen on boot). | |
560 | */ | |
561 | return 0; | |
562 | ||
563 | /* Find PCI PM capability in the list */ | |
564 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
565 | ||
566 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { | |
567 | /* | |
568 | * Allow the platform to change the state, for example via ACPI | |
569 | * _PR0, _PS0 and some such, but do not trust it. | |
570 | */ | |
571 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
572 | if (!ret) | |
573 | pci_update_current_state(dev, pm); | |
574 | } | |
575 | ||
576 | error = pci_raw_set_power_state(dev, pm, state); | |
577 | ||
578 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
579 | /* Allow the platform to finalize the transition */ | |
580 | int ret = platform_pci_set_power_state(dev, state); | |
581 | if (!ret) { | |
582 | pci_update_current_state(dev, pm); | |
583 | error = 0; | |
584 | } | |
585 | } | |
586 | ||
587 | return error; | |
588 | } | |
589 | ||
1da177e4 LT |
590 | /** |
591 | * pci_choose_state - Choose the power state of a PCI device | |
592 | * @dev: PCI device to be suspended | |
593 | * @state: target sleep state for the whole system. This is the value | |
594 | * that is passed to suspend() function. | |
595 | * | |
596 | * Returns PCI power state suitable for given device and given system | |
597 | * message. | |
598 | */ | |
599 | ||
600 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
601 | { | |
ab826ca4 | 602 | pci_power_t ret; |
0f64474b | 603 | |
1da177e4 LT |
604 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
605 | return PCI_D0; | |
606 | ||
961d9120 RW |
607 | ret = platform_pci_choose_state(dev); |
608 | if (ret != PCI_POWER_ERROR) | |
609 | return ret; | |
ca078bae PM |
610 | |
611 | switch (state.event) { | |
612 | case PM_EVENT_ON: | |
613 | return PCI_D0; | |
614 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
615 | case PM_EVENT_PRETHAW: |
616 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 617 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 618 | case PM_EVENT_HIBERNATE: |
ca078bae | 619 | return PCI_D3hot; |
1da177e4 | 620 | default: |
80ccba11 BH |
621 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
622 | state.event); | |
1da177e4 LT |
623 | BUG(); |
624 | } | |
625 | return PCI_D0; | |
626 | } | |
627 | ||
628 | EXPORT_SYMBOL(pci_choose_state); | |
629 | ||
b56a5a23 MT |
630 | static int pci_save_pcie_state(struct pci_dev *dev) |
631 | { | |
632 | int pos, i = 0; | |
633 | struct pci_cap_saved_state *save_state; | |
634 | u16 *cap; | |
017fc480 | 635 | int found = 0; |
b56a5a23 MT |
636 | |
637 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
638 | if (pos <= 0) | |
639 | return 0; | |
640 | ||
9f35575d EB |
641 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
642 | if (!save_state) | |
643 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
644 | else |
645 | found = 1; | |
b56a5a23 | 646 | if (!save_state) { |
80ccba11 | 647 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
b56a5a23 MT |
648 | return -ENOMEM; |
649 | } | |
650 | cap = (u16 *)&save_state->data[0]; | |
651 | ||
652 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
653 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
654 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
655 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 656 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
657 | if (!found) |
658 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
659 | return 0; |
660 | } | |
661 | ||
662 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
663 | { | |
664 | int i = 0, pos; | |
665 | struct pci_cap_saved_state *save_state; | |
666 | u16 *cap; | |
667 | ||
668 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
669 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
670 | if (!save_state || pos <= 0) | |
671 | return; | |
672 | cap = (u16 *)&save_state->data[0]; | |
673 | ||
674 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
675 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
676 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
677 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
678 | } |
679 | ||
cc692a5f SH |
680 | |
681 | static int pci_save_pcix_state(struct pci_dev *dev) | |
682 | { | |
683 | int pos, i = 0; | |
684 | struct pci_cap_saved_state *save_state; | |
685 | u16 *cap; | |
017fc480 | 686 | int found = 0; |
cc692a5f SH |
687 | |
688 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
689 | if (pos <= 0) | |
690 | return 0; | |
691 | ||
f34303de | 692 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
693 | if (!save_state) |
694 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
695 | else |
696 | found = 1; | |
cc692a5f | 697 | if (!save_state) { |
80ccba11 | 698 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
cc692a5f SH |
699 | return -ENOMEM; |
700 | } | |
701 | cap = (u16 *)&save_state->data[0]; | |
702 | ||
703 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 704 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
705 | if (!found) |
706 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
707 | return 0; |
708 | } | |
709 | ||
710 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
711 | { | |
712 | int i = 0, pos; | |
713 | struct pci_cap_saved_state *save_state; | |
714 | u16 *cap; | |
715 | ||
716 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
717 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
718 | if (!save_state || pos <= 0) | |
719 | return; | |
720 | cap = (u16 *)&save_state->data[0]; | |
721 | ||
722 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
723 | } |
724 | ||
725 | ||
1da177e4 LT |
726 | /** |
727 | * pci_save_state - save the PCI configuration space of a device before suspending | |
728 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
729 | */ |
730 | int | |
731 | pci_save_state(struct pci_dev *dev) | |
732 | { | |
733 | int i; | |
734 | /* XXX: 100% dword access ok here? */ | |
735 | for (i = 0; i < 16; i++) | |
736 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
737 | if ((i = pci_save_pcie_state(dev)) != 0) |
738 | return i; | |
cc692a5f SH |
739 | if ((i = pci_save_pcix_state(dev)) != 0) |
740 | return i; | |
1da177e4 LT |
741 | return 0; |
742 | } | |
743 | ||
744 | /** | |
745 | * pci_restore_state - Restore the saved state of a PCI device | |
746 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
747 | */ |
748 | int | |
749 | pci_restore_state(struct pci_dev *dev) | |
750 | { | |
751 | int i; | |
b4482a4b | 752 | u32 val; |
1da177e4 | 753 | |
b56a5a23 MT |
754 | /* PCI Express register must be restored first */ |
755 | pci_restore_pcie_state(dev); | |
756 | ||
8b8c8d28 YL |
757 | /* |
758 | * The Base Address register should be programmed before the command | |
759 | * register(s) | |
760 | */ | |
761 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
762 | pci_read_config_dword(dev, i * 4, &val); |
763 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
764 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
765 | "space at offset %#x (was %#x, writing %#x)\n", | |
766 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
767 | pci_write_config_dword(dev,i * 4, |
768 | dev->saved_config_space[i]); | |
769 | } | |
770 | } | |
cc692a5f | 771 | pci_restore_pcix_state(dev); |
41017f0c | 772 | pci_restore_msi_state(dev); |
8fed4b65 | 773 | |
1da177e4 LT |
774 | return 0; |
775 | } | |
776 | ||
38cc1302 HS |
777 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
778 | { | |
779 | int err; | |
780 | ||
781 | err = pci_set_power_state(dev, PCI_D0); | |
782 | if (err < 0 && err != -EIO) | |
783 | return err; | |
784 | err = pcibios_enable_device(dev, bars); | |
785 | if (err < 0) | |
786 | return err; | |
787 | pci_fixup_device(pci_fixup_enable, dev); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | /** | |
0b62e13b | 793 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
794 | * @dev: PCI device to be resumed |
795 | * | |
796 | * Note this function is a backend of pci_default_resume and is not supposed | |
797 | * to be called by normal code, write proper resume handler and use it instead. | |
798 | */ | |
0b62e13b | 799 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
800 | { |
801 | if (atomic_read(&dev->enable_cnt)) | |
802 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
803 | return 0; | |
804 | } | |
805 | ||
b718989d BH |
806 | static int __pci_enable_device_flags(struct pci_dev *dev, |
807 | resource_size_t flags) | |
1da177e4 LT |
808 | { |
809 | int err; | |
b718989d | 810 | int i, bars = 0; |
1da177e4 | 811 | |
9fb625c3 HS |
812 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
813 | return 0; /* already enabled */ | |
814 | ||
b718989d BH |
815 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
816 | if (dev->resource[i].flags & flags) | |
817 | bars |= (1 << i); | |
818 | ||
38cc1302 | 819 | err = do_pci_enable_device(dev, bars); |
95a62965 | 820 | if (err < 0) |
38cc1302 | 821 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 822 | return err; |
1da177e4 LT |
823 | } |
824 | ||
b718989d BH |
825 | /** |
826 | * pci_enable_device_io - Initialize a device for use with IO space | |
827 | * @dev: PCI device to be initialized | |
828 | * | |
829 | * Initialize device before it's used by a driver. Ask low-level code | |
830 | * to enable I/O resources. Wake up the device if it was suspended. | |
831 | * Beware, this function can fail. | |
832 | */ | |
833 | int pci_enable_device_io(struct pci_dev *dev) | |
834 | { | |
835 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
836 | } | |
837 | ||
838 | /** | |
839 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
840 | * @dev: PCI device to be initialized | |
841 | * | |
842 | * Initialize device before it's used by a driver. Ask low-level code | |
843 | * to enable Memory resources. Wake up the device if it was suspended. | |
844 | * Beware, this function can fail. | |
845 | */ | |
846 | int pci_enable_device_mem(struct pci_dev *dev) | |
847 | { | |
848 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
849 | } | |
850 | ||
bae94d02 IPG |
851 | /** |
852 | * pci_enable_device - Initialize device before it's used by a driver. | |
853 | * @dev: PCI device to be initialized | |
854 | * | |
855 | * Initialize device before it's used by a driver. Ask low-level code | |
856 | * to enable I/O and memory. Wake up the device if it was suspended. | |
857 | * Beware, this function can fail. | |
858 | * | |
859 | * Note we don't actually enable the device many times if we call | |
860 | * this function repeatedly (we just increment the count). | |
861 | */ | |
862 | int pci_enable_device(struct pci_dev *dev) | |
863 | { | |
b718989d | 864 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
865 | } |
866 | ||
9ac7849e TH |
867 | /* |
868 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
869 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
870 | * there's no need to track it separately. pci_devres is initialized | |
871 | * when a device is enabled using managed PCI device enable interface. | |
872 | */ | |
873 | struct pci_devres { | |
7f375f32 TH |
874 | unsigned int enabled:1; |
875 | unsigned int pinned:1; | |
9ac7849e TH |
876 | unsigned int orig_intx:1; |
877 | unsigned int restore_intx:1; | |
878 | u32 region_mask; | |
879 | }; | |
880 | ||
881 | static void pcim_release(struct device *gendev, void *res) | |
882 | { | |
883 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
884 | struct pci_devres *this = res; | |
885 | int i; | |
886 | ||
887 | if (dev->msi_enabled) | |
888 | pci_disable_msi(dev); | |
889 | if (dev->msix_enabled) | |
890 | pci_disable_msix(dev); | |
891 | ||
892 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
893 | if (this->region_mask & (1 << i)) | |
894 | pci_release_region(dev, i); | |
895 | ||
896 | if (this->restore_intx) | |
897 | pci_intx(dev, this->orig_intx); | |
898 | ||
7f375f32 | 899 | if (this->enabled && !this->pinned) |
9ac7849e TH |
900 | pci_disable_device(dev); |
901 | } | |
902 | ||
903 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
904 | { | |
905 | struct pci_devres *dr, *new_dr; | |
906 | ||
907 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
908 | if (dr) | |
909 | return dr; | |
910 | ||
911 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
912 | if (!new_dr) | |
913 | return NULL; | |
914 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
915 | } | |
916 | ||
917 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
918 | { | |
919 | if (pci_is_managed(pdev)) | |
920 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
921 | return NULL; | |
922 | } | |
923 | ||
924 | /** | |
925 | * pcim_enable_device - Managed pci_enable_device() | |
926 | * @pdev: PCI device to be initialized | |
927 | * | |
928 | * Managed pci_enable_device(). | |
929 | */ | |
930 | int pcim_enable_device(struct pci_dev *pdev) | |
931 | { | |
932 | struct pci_devres *dr; | |
933 | int rc; | |
934 | ||
935 | dr = get_pci_dr(pdev); | |
936 | if (unlikely(!dr)) | |
937 | return -ENOMEM; | |
b95d58ea TH |
938 | if (dr->enabled) |
939 | return 0; | |
9ac7849e TH |
940 | |
941 | rc = pci_enable_device(pdev); | |
942 | if (!rc) { | |
943 | pdev->is_managed = 1; | |
7f375f32 | 944 | dr->enabled = 1; |
9ac7849e TH |
945 | } |
946 | return rc; | |
947 | } | |
948 | ||
949 | /** | |
950 | * pcim_pin_device - Pin managed PCI device | |
951 | * @pdev: PCI device to pin | |
952 | * | |
953 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
954 | * driver detach. @pdev must have been enabled with | |
955 | * pcim_enable_device(). | |
956 | */ | |
957 | void pcim_pin_device(struct pci_dev *pdev) | |
958 | { | |
959 | struct pci_devres *dr; | |
960 | ||
961 | dr = find_pci_dr(pdev); | |
7f375f32 | 962 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 963 | if (dr) |
7f375f32 | 964 | dr->pinned = 1; |
9ac7849e TH |
965 | } |
966 | ||
1da177e4 LT |
967 | /** |
968 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
969 | * @dev: the PCI device to disable | |
970 | * | |
971 | * Disables architecture specific PCI resources for the device. This | |
972 | * is the default implementation. Architecture implementations can | |
973 | * override this. | |
974 | */ | |
975 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
976 | ||
977 | /** | |
978 | * pci_disable_device - Disable PCI device after use | |
979 | * @dev: PCI device to be disabled | |
980 | * | |
981 | * Signal to the system that the PCI device is not in use by the system | |
982 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
983 | * |
984 | * Note we don't actually disable the device until all callers of | |
985 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
986 | */ |
987 | void | |
988 | pci_disable_device(struct pci_dev *dev) | |
989 | { | |
9ac7849e | 990 | struct pci_devres *dr; |
1da177e4 | 991 | u16 pci_command; |
99dc804d | 992 | |
9ac7849e TH |
993 | dr = find_pci_dr(dev); |
994 | if (dr) | |
7f375f32 | 995 | dr->enabled = 0; |
9ac7849e | 996 | |
bae94d02 IPG |
997 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
998 | return; | |
999 | ||
1da177e4 LT |
1000 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
1001 | if (pci_command & PCI_COMMAND_MASTER) { | |
1002 | pci_command &= ~PCI_COMMAND_MASTER; | |
1003 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1004 | } | |
ceb43744 | 1005 | dev->is_busmaster = 0; |
1da177e4 LT |
1006 | |
1007 | pcibios_disable_device(dev); | |
1008 | } | |
1009 | ||
f7bdd12d BK |
1010 | /** |
1011 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1012 | * @dev: the PCI-E device reset | |
1013 | * @state: Reset state to enter into | |
1014 | * | |
1015 | * | |
1016 | * Sets the PCI-E reset state for the device. This is the default | |
1017 | * implementation. Architecture implementations can override this. | |
1018 | */ | |
1019 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1020 | enum pcie_reset_state state) | |
1021 | { | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * pci_set_pcie_reset_state - set reset state for device dev | |
1027 | * @dev: the PCI-E device reset | |
1028 | * @state: Reset state to enter into | |
1029 | * | |
1030 | * | |
1031 | * Sets the PCI reset state for the device. | |
1032 | */ | |
1033 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1034 | { | |
1035 | return pcibios_set_pcie_reset_state(dev, state); | |
1036 | } | |
1037 | ||
1da177e4 | 1038 | /** |
075c1771 DB |
1039 | * pci_enable_wake - enable PCI device as wakeup event source |
1040 | * @dev: PCI device affected | |
1041 | * @state: PCI state from which device will issue wakeup events | |
1042 | * @enable: True to enable event generation; false to disable | |
1043 | * | |
1044 | * This enables the device as a wakeup event source, or disables it. | |
1045 | * When such events involves platform-specific hooks, those hooks are | |
1046 | * called automatically by this routine. | |
1047 | * | |
1048 | * Devices with legacy power management (no standard PCI PM capabilities) | |
1049 | * always require such platform hooks. Depending on the platform, devices | |
1050 | * supporting the standard PCI PME# signal may require such platform hooks; | |
1051 | * they always update bits in config space to allow PME# generation. | |
1052 | * | |
1053 | * -EIO is returned if the device can't ever be a wakeup event source. | |
1054 | * -EINVAL is returned if the device can't generate wakeup events from | |
1055 | * the specified PCI state. Returns zero if the operation is successful. | |
1da177e4 LT |
1056 | */ |
1057 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1058 | { | |
1059 | int pm; | |
075c1771 | 1060 | int status; |
1da177e4 LT |
1061 | u16 value; |
1062 | ||
075c1771 DB |
1063 | /* Note that drivers should verify device_may_wakeup(&dev->dev) |
1064 | * before calling this function. Platform code should report | |
1065 | * errors when drivers try to enable wakeup on devices that | |
1066 | * can't issue wakeups, or on which wakeups were disabled by | |
1067 | * userspace updating the /sys/devices.../power/wakeup file. | |
1068 | */ | |
1069 | ||
1070 | status = call_platform_enable_wakeup(&dev->dev, enable); | |
1071 | ||
1da177e4 LT |
1072 | /* find PCI PM capability in list */ |
1073 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1074 | ||
075c1771 DB |
1075 | /* If device doesn't support PM Capabilities, but caller wants to |
1076 | * disable wake events, it's a NOP. Otherwise fail unless the | |
1077 | * platform hooks handled this legacy device already. | |
1078 | */ | |
1079 | if (!pm) | |
1080 | return enable ? status : 0; | |
1da177e4 LT |
1081 | |
1082 | /* Check device's ability to generate PME# */ | |
1083 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
1084 | ||
1085 | value &= PCI_PM_CAP_PME_MASK; | |
1086 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
1087 | ||
1088 | /* Check if it can generate PME# from requested state. */ | |
075c1771 DB |
1089 | if (!value || !(value & (1 << state))) { |
1090 | /* if it can't, revert what the platform hook changed, | |
1091 | * always reporting the base "EINVAL, can't PME#" error | |
1092 | */ | |
1093 | if (enable) | |
1094 | call_platform_enable_wakeup(&dev->dev, 0); | |
1da177e4 | 1095 | return enable ? -EINVAL : 0; |
075c1771 | 1096 | } |
1da177e4 LT |
1097 | |
1098 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
1099 | ||
1100 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
1101 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1102 | ||
1103 | if (!enable) | |
1104 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
1105 | ||
1106 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
075c1771 | 1107 | |
1da177e4 LT |
1108 | return 0; |
1109 | } | |
1110 | ||
1111 | int | |
1112 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1113 | { | |
1114 | u8 pin; | |
1115 | ||
514d207d | 1116 | pin = dev->pin; |
1da177e4 LT |
1117 | if (!pin) |
1118 | return -1; | |
1119 | pin--; | |
1120 | while (dev->bus->self) { | |
1121 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1122 | dev = dev->bus->self; | |
1123 | } | |
1124 | *bridge = dev; | |
1125 | return pin; | |
1126 | } | |
1127 | ||
1128 | /** | |
1129 | * pci_release_region - Release a PCI bar | |
1130 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1131 | * @bar: BAR to release | |
1132 | * | |
1133 | * Releases the PCI I/O and memory resources previously reserved by a | |
1134 | * successful call to pci_request_region. Call this function only | |
1135 | * after all use of the PCI regions has ceased. | |
1136 | */ | |
1137 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1138 | { | |
9ac7849e TH |
1139 | struct pci_devres *dr; |
1140 | ||
1da177e4 LT |
1141 | if (pci_resource_len(pdev, bar) == 0) |
1142 | return; | |
1143 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1144 | release_region(pci_resource_start(pdev, bar), | |
1145 | pci_resource_len(pdev, bar)); | |
1146 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1147 | release_mem_region(pci_resource_start(pdev, bar), | |
1148 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1149 | |
1150 | dr = find_pci_dr(pdev); | |
1151 | if (dr) | |
1152 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1153 | } |
1154 | ||
1155 | /** | |
1156 | * pci_request_region - Reserved PCI I/O and memory resource | |
1157 | * @pdev: PCI device whose resources are to be reserved | |
1158 | * @bar: BAR to be reserved | |
1159 | * @res_name: Name to be associated with resource. | |
1160 | * | |
1161 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1162 | * being reserved by owner @res_name. Do not access any | |
1163 | * address inside the PCI regions unless this call returns | |
1164 | * successfully. | |
1165 | * | |
1166 | * Returns 0 on success, or %EBUSY on error. A warning | |
1167 | * message is also printed on failure. | |
1168 | */ | |
3c990e92 | 1169 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1170 | { |
9ac7849e TH |
1171 | struct pci_devres *dr; |
1172 | ||
1da177e4 LT |
1173 | if (pci_resource_len(pdev, bar) == 0) |
1174 | return 0; | |
1175 | ||
1176 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1177 | if (!request_region(pci_resource_start(pdev, bar), | |
1178 | pci_resource_len(pdev, bar), res_name)) | |
1179 | goto err_out; | |
1180 | } | |
1181 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1182 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1183 | pci_resource_len(pdev, bar), res_name)) | |
1184 | goto err_out; | |
1185 | } | |
9ac7849e TH |
1186 | |
1187 | dr = find_pci_dr(pdev); | |
1188 | if (dr) | |
1189 | dr->region_mask |= 1 << bar; | |
1190 | ||
1da177e4 LT |
1191 | return 0; |
1192 | ||
1193 | err_out: | |
80ccba11 | 1194 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n", |
e4ec7a00 JB |
1195 | bar, |
1196 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
1197 | (unsigned long long)pci_resource_start(pdev, bar), | |
1198 | (unsigned long long)pci_resource_end(pdev, bar)); | |
1da177e4 LT |
1199 | return -EBUSY; |
1200 | } | |
1201 | ||
c87deff7 HS |
1202 | /** |
1203 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1204 | * @pdev: PCI device whose resources were previously reserved | |
1205 | * @bars: Bitmask of BARs to be released | |
1206 | * | |
1207 | * Release selected PCI I/O and memory resources previously reserved. | |
1208 | * Call this function only after all use of the PCI regions has ceased. | |
1209 | */ | |
1210 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1211 | { | |
1212 | int i; | |
1213 | ||
1214 | for (i = 0; i < 6; i++) | |
1215 | if (bars & (1 << i)) | |
1216 | pci_release_region(pdev, i); | |
1217 | } | |
1218 | ||
1219 | /** | |
1220 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1221 | * @pdev: PCI device whose resources are to be reserved | |
1222 | * @bars: Bitmask of BARs to be requested | |
1223 | * @res_name: Name to be associated with resource | |
1224 | */ | |
1225 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1226 | const char *res_name) | |
1227 | { | |
1228 | int i; | |
1229 | ||
1230 | for (i = 0; i < 6; i++) | |
1231 | if (bars & (1 << i)) | |
1232 | if(pci_request_region(pdev, i, res_name)) | |
1233 | goto err_out; | |
1234 | return 0; | |
1235 | ||
1236 | err_out: | |
1237 | while(--i >= 0) | |
1238 | if (bars & (1 << i)) | |
1239 | pci_release_region(pdev, i); | |
1240 | ||
1241 | return -EBUSY; | |
1242 | } | |
1da177e4 LT |
1243 | |
1244 | /** | |
1245 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1246 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1247 | * | |
1248 | * Releases all PCI I/O and memory resources previously reserved by a | |
1249 | * successful call to pci_request_regions. Call this function only | |
1250 | * after all use of the PCI regions has ceased. | |
1251 | */ | |
1252 | ||
1253 | void pci_release_regions(struct pci_dev *pdev) | |
1254 | { | |
c87deff7 | 1255 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1256 | } |
1257 | ||
1258 | /** | |
1259 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1260 | * @pdev: PCI device whose resources are to be reserved | |
1261 | * @res_name: Name to be associated with resource. | |
1262 | * | |
1263 | * Mark all PCI regions associated with PCI device @pdev as | |
1264 | * being reserved by owner @res_name. Do not access any | |
1265 | * address inside the PCI regions unless this call returns | |
1266 | * successfully. | |
1267 | * | |
1268 | * Returns 0 on success, or %EBUSY on error. A warning | |
1269 | * message is also printed on failure. | |
1270 | */ | |
3c990e92 | 1271 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1272 | { |
c87deff7 | 1273 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1274 | } |
1275 | ||
1276 | /** | |
1277 | * pci_set_master - enables bus-mastering for device dev | |
1278 | * @dev: the PCI device to enable | |
1279 | * | |
1280 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1281 | * to do the needed arch specific settings. | |
1282 | */ | |
1283 | void | |
1284 | pci_set_master(struct pci_dev *dev) | |
1285 | { | |
1286 | u16 cmd; | |
1287 | ||
1288 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1289 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1290 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1291 | cmd |= PCI_COMMAND_MASTER; |
1292 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1293 | } | |
1294 | dev->is_busmaster = 1; | |
1295 | pcibios_set_master(dev); | |
1296 | } | |
1297 | ||
edb2d97e MW |
1298 | #ifdef PCI_DISABLE_MWI |
1299 | int pci_set_mwi(struct pci_dev *dev) | |
1300 | { | |
1301 | return 0; | |
1302 | } | |
1303 | ||
694625c0 RD |
1304 | int pci_try_set_mwi(struct pci_dev *dev) |
1305 | { | |
1306 | return 0; | |
1307 | } | |
1308 | ||
edb2d97e MW |
1309 | void pci_clear_mwi(struct pci_dev *dev) |
1310 | { | |
1311 | } | |
1312 | ||
1313 | #else | |
ebf5a248 MW |
1314 | |
1315 | #ifndef PCI_CACHE_LINE_BYTES | |
1316 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1317 | #endif | |
1318 | ||
1da177e4 | 1319 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1320 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1321 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1322 | |
1323 | /** | |
edb2d97e MW |
1324 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1325 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1326 | * |
edb2d97e MW |
1327 | * Helper function for pci_set_mwi. |
1328 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1329 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1330 | * | |
1331 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1332 | */ | |
1333 | static int | |
edb2d97e | 1334 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1335 | { |
1336 | u8 cacheline_size; | |
1337 | ||
1338 | if (!pci_cache_line_size) | |
1339 | return -EINVAL; /* The system doesn't support MWI. */ | |
1340 | ||
1341 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1342 | equal to or multiple of the right value. */ | |
1343 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1344 | if (cacheline_size >= pci_cache_line_size && | |
1345 | (cacheline_size % pci_cache_line_size) == 0) | |
1346 | return 0; | |
1347 | ||
1348 | /* Write the correct value. */ | |
1349 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1350 | /* Read it back. */ | |
1351 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1352 | if (cacheline_size == pci_cache_line_size) | |
1353 | return 0; | |
1354 | ||
80ccba11 BH |
1355 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1356 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1357 | |
1358 | return -EINVAL; | |
1359 | } | |
1da177e4 LT |
1360 | |
1361 | /** | |
1362 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1363 | * @dev: the PCI device for which MWI is enabled | |
1364 | * | |
694625c0 | 1365 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1366 | * |
1367 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1368 | */ | |
1369 | int | |
1370 | pci_set_mwi(struct pci_dev *dev) | |
1371 | { | |
1372 | int rc; | |
1373 | u16 cmd; | |
1374 | ||
edb2d97e | 1375 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1376 | if (rc) |
1377 | return rc; | |
1378 | ||
1379 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1380 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1381 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1382 | cmd |= PCI_COMMAND_INVALIDATE; |
1383 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1384 | } | |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
694625c0 RD |
1389 | /** |
1390 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1391 | * @dev: the PCI device for which MWI is enabled | |
1392 | * | |
1393 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1394 | * Callers are not required to check the return value. | |
1395 | * | |
1396 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1397 | */ | |
1398 | int pci_try_set_mwi(struct pci_dev *dev) | |
1399 | { | |
1400 | int rc = pci_set_mwi(dev); | |
1401 | return rc; | |
1402 | } | |
1403 | ||
1da177e4 LT |
1404 | /** |
1405 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1406 | * @dev: the PCI device to disable | |
1407 | * | |
1408 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1409 | */ | |
1410 | void | |
1411 | pci_clear_mwi(struct pci_dev *dev) | |
1412 | { | |
1413 | u16 cmd; | |
1414 | ||
1415 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1416 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1417 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1418 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1419 | } | |
1420 | } | |
edb2d97e | 1421 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1422 | |
a04ce0ff BR |
1423 | /** |
1424 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1425 | * @pdev: the PCI device to operate on |
1426 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1427 | * |
1428 | * Enables/disables PCI INTx for device dev | |
1429 | */ | |
1430 | void | |
1431 | pci_intx(struct pci_dev *pdev, int enable) | |
1432 | { | |
1433 | u16 pci_command, new; | |
1434 | ||
1435 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1436 | ||
1437 | if (enable) { | |
1438 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1439 | } else { | |
1440 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1441 | } | |
1442 | ||
1443 | if (new != pci_command) { | |
9ac7849e TH |
1444 | struct pci_devres *dr; |
1445 | ||
2fd9d74b | 1446 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1447 | |
1448 | dr = find_pci_dr(pdev); | |
1449 | if (dr && !dr->restore_intx) { | |
1450 | dr->restore_intx = 1; | |
1451 | dr->orig_intx = !enable; | |
1452 | } | |
a04ce0ff BR |
1453 | } |
1454 | } | |
1455 | ||
f5f2b131 EB |
1456 | /** |
1457 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1458 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1459 | * |
1460 | * If you want to use msi see pci_enable_msi and friends. | |
1461 | * This is a lower level primitive that allows us to disable | |
1462 | * msi operation at the device level. | |
1463 | */ | |
1464 | void pci_msi_off(struct pci_dev *dev) | |
1465 | { | |
1466 | int pos; | |
1467 | u16 control; | |
1468 | ||
1469 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1470 | if (pos) { | |
1471 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1472 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1473 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1474 | } | |
1475 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1476 | if (pos) { | |
1477 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1478 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1479 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1480 | } | |
1481 | } | |
1482 | ||
1da177e4 LT |
1483 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1484 | /* | |
1485 | * These can be overridden by arch-specific implementations | |
1486 | */ | |
1487 | int | |
1488 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1489 | { | |
1490 | if (!pci_dma_supported(dev, mask)) | |
1491 | return -EIO; | |
1492 | ||
1493 | dev->dma_mask = mask; | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1da177e4 LT |
1498 | int |
1499 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1500 | { | |
1501 | if (!pci_dma_supported(dev, mask)) | |
1502 | return -EIO; | |
1503 | ||
1504 | dev->dev.coherent_dma_mask = mask; | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | #endif | |
c87deff7 | 1509 | |
4d57cdfa FT |
1510 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1511 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1512 | { | |
1513 | return dma_set_max_seg_size(&dev->dev, size); | |
1514 | } | |
1515 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1516 | #endif | |
1517 | ||
59fc67de FT |
1518 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1519 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1520 | { | |
1521 | return dma_set_seg_boundary(&dev->dev, mask); | |
1522 | } | |
1523 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1524 | #endif | |
1525 | ||
d556ad4b PO |
1526 | /** |
1527 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1528 | * @dev: PCI device to query | |
1529 | * | |
1530 | * Returns mmrbc: maximum designed memory read count in bytes | |
1531 | * or appropriate error value. | |
1532 | */ | |
1533 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1534 | { | |
b7b095c1 | 1535 | int err, cap; |
d556ad4b PO |
1536 | u32 stat; |
1537 | ||
1538 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1539 | if (!cap) | |
1540 | return -EINVAL; | |
1541 | ||
1542 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1543 | if (err) | |
1544 | return -EINVAL; | |
1545 | ||
b7b095c1 | 1546 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1547 | } |
1548 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1549 | ||
1550 | /** | |
1551 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1552 | * @dev: PCI device to query | |
1553 | * | |
1554 | * Returns mmrbc: maximum memory read count in bytes | |
1555 | * or appropriate error value. | |
1556 | */ | |
1557 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1558 | { | |
1559 | int ret, cap; | |
1560 | u32 cmd; | |
1561 | ||
1562 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1563 | if (!cap) | |
1564 | return -EINVAL; | |
1565 | ||
1566 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1567 | if (!ret) | |
1568 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1569 | ||
1570 | return ret; | |
1571 | } | |
1572 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1573 | ||
1574 | /** | |
1575 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1576 | * @dev: PCI device to query | |
1577 | * @mmrbc: maximum memory read count in bytes | |
1578 | * valid values are 512, 1024, 2048, 4096 | |
1579 | * | |
1580 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1581 | * that prevent this. | |
1582 | */ | |
1583 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1584 | { | |
1585 | int cap, err = -EINVAL; | |
1586 | u32 stat, cmd, v, o; | |
1587 | ||
229f5afd | 1588 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1589 | goto out; |
1590 | ||
1591 | v = ffs(mmrbc) - 10; | |
1592 | ||
1593 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1594 | if (!cap) | |
1595 | goto out; | |
1596 | ||
1597 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1598 | if (err) | |
1599 | goto out; | |
1600 | ||
1601 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1602 | return -E2BIG; | |
1603 | ||
1604 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1605 | if (err) | |
1606 | goto out; | |
1607 | ||
1608 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1609 | if (o != v) { | |
1610 | if (v > o && dev->bus && | |
1611 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1612 | return -EIO; | |
1613 | ||
1614 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1615 | cmd |= v << 2; | |
1616 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1617 | } | |
1618 | out: | |
1619 | return err; | |
1620 | } | |
1621 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1622 | ||
1623 | /** | |
1624 | * pcie_get_readrq - get PCI Express read request size | |
1625 | * @dev: PCI device to query | |
1626 | * | |
1627 | * Returns maximum memory read request in bytes | |
1628 | * or appropriate error value. | |
1629 | */ | |
1630 | int pcie_get_readrq(struct pci_dev *dev) | |
1631 | { | |
1632 | int ret, cap; | |
1633 | u16 ctl; | |
1634 | ||
1635 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1636 | if (!cap) | |
1637 | return -EINVAL; | |
1638 | ||
1639 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1640 | if (!ret) | |
1641 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1642 | ||
1643 | return ret; | |
1644 | } | |
1645 | EXPORT_SYMBOL(pcie_get_readrq); | |
1646 | ||
1647 | /** | |
1648 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1649 | * @dev: PCI device to query | |
42e61f4a | 1650 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1651 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1652 | * | |
1653 | * If possible sets maximum read byte count | |
1654 | */ | |
1655 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1656 | { | |
1657 | int cap, err = -EINVAL; | |
1658 | u16 ctl, v; | |
1659 | ||
229f5afd | 1660 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1661 | goto out; |
1662 | ||
1663 | v = (ffs(rq) - 8) << 12; | |
1664 | ||
1665 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1666 | if (!cap) | |
1667 | goto out; | |
1668 | ||
1669 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1670 | if (err) | |
1671 | goto out; | |
1672 | ||
1673 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1674 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1675 | ctl |= v; | |
1676 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1677 | } | |
1678 | ||
1679 | out: | |
1680 | return err; | |
1681 | } | |
1682 | EXPORT_SYMBOL(pcie_set_readrq); | |
1683 | ||
c87deff7 HS |
1684 | /** |
1685 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1686 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1687 | * @flags: resource type mask to be selected |
1688 | * | |
1689 | * This helper routine makes bar mask from the type of resource. | |
1690 | */ | |
1691 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1692 | { | |
1693 | int i, bars = 0; | |
1694 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1695 | if (pci_resource_flags(dev, i) & flags) | |
1696 | bars |= (1 << i); | |
1697 | return bars; | |
1698 | } | |
1699 | ||
32a2eea7 JG |
1700 | static void __devinit pci_no_domains(void) |
1701 | { | |
1702 | #ifdef CONFIG_PCI_DOMAINS | |
1703 | pci_domains_supported = 0; | |
1704 | #endif | |
1705 | } | |
1706 | ||
1da177e4 LT |
1707 | static int __devinit pci_init(void) |
1708 | { | |
1709 | struct pci_dev *dev = NULL; | |
1710 | ||
1711 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1712 | pci_fixup_device(pci_fixup_final, dev); | |
1713 | } | |
1714 | return 0; | |
1715 | } | |
1716 | ||
1717 | static int __devinit pci_setup(char *str) | |
1718 | { | |
1719 | while (str) { | |
1720 | char *k = strchr(str, ','); | |
1721 | if (k) | |
1722 | *k++ = 0; | |
1723 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1724 | if (!strcmp(str, "nomsi")) { |
1725 | pci_no_msi(); | |
7f785763 RD |
1726 | } else if (!strcmp(str, "noaer")) { |
1727 | pci_no_aer(); | |
32a2eea7 JG |
1728 | } else if (!strcmp(str, "nodomains")) { |
1729 | pci_no_domains(); | |
4516a618 AN |
1730 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1731 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1732 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1733 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1734 | } else { |
1735 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1736 | str); | |
1737 | } | |
1da177e4 LT |
1738 | } |
1739 | str = k; | |
1740 | } | |
0637a70a | 1741 | return 0; |
1da177e4 | 1742 | } |
0637a70a | 1743 | early_param("pci", pci_setup); |
1da177e4 LT |
1744 | |
1745 | device_initcall(pci_init); | |
1da177e4 | 1746 | |
0b62e13b | 1747 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
1748 | EXPORT_SYMBOL(pci_enable_device_io); |
1749 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 1750 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
1751 | EXPORT_SYMBOL(pcim_enable_device); |
1752 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1753 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1754 | EXPORT_SYMBOL(pci_find_capability); |
1755 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1756 | EXPORT_SYMBOL(pci_release_regions); | |
1757 | EXPORT_SYMBOL(pci_request_regions); | |
1758 | EXPORT_SYMBOL(pci_release_region); | |
1759 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1760 | EXPORT_SYMBOL(pci_release_selected_regions); |
1761 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1762 | EXPORT_SYMBOL(pci_set_master); |
1763 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1764 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1765 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1766 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1767 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1768 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1769 | EXPORT_SYMBOL(pci_assign_resource); | |
1770 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1771 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1772 | |
1773 | EXPORT_SYMBOL(pci_set_power_state); | |
1774 | EXPORT_SYMBOL(pci_save_state); | |
1775 | EXPORT_SYMBOL(pci_restore_state); | |
1776 | EXPORT_SYMBOL(pci_enable_wake); | |
f7bdd12d | 1777 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1778 |