Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
8dd7f803 | 21 | #include <linux/interrupt.h> |
1da177e4 | 22 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 23 | #include "pci.h" |
1da177e4 | 24 | |
aa8c6c93 | 25 | unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT; |
1da177e4 | 26 | |
32a2eea7 JG |
27 | #ifdef CONFIG_PCI_DOMAINS |
28 | int pci_domains_supported = 1; | |
29 | #endif | |
30 | ||
4516a618 AN |
31 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
32 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
33 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
34 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
35 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
36 | ||
1da177e4 LT |
37 | /** |
38 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
39 | * @bus: pointer to PCI bus structure to search | |
40 | * | |
41 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
42 | * including the given PCI bus and its list of child PCI buses. | |
43 | */ | |
96bde06a | 44 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
45 | { |
46 | struct list_head *tmp; | |
47 | unsigned char max, n; | |
48 | ||
b82db5ce | 49 | max = bus->subordinate; |
1da177e4 LT |
50 | list_for_each(tmp, &bus->children) { |
51 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
52 | if(n > max) | |
53 | max = n; | |
54 | } | |
55 | return max; | |
56 | } | |
b82db5ce | 57 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 58 | |
1684f5dd AM |
59 | #ifdef CONFIG_HAS_IOMEM |
60 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
61 | { | |
62 | /* | |
63 | * Make sure the BAR is actually a memory resource, not an IO resource | |
64 | */ | |
65 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
66 | WARN_ON(1); | |
67 | return NULL; | |
68 | } | |
69 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
70 | pci_resource_len(pdev, bar)); | |
71 | } | |
72 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
73 | #endif | |
74 | ||
b82db5ce | 75 | #if 0 |
1da177e4 LT |
76 | /** |
77 | * pci_max_busnr - returns maximum PCI bus number | |
78 | * | |
79 | * Returns the highest PCI bus number present in the system global list of | |
80 | * PCI buses. | |
81 | */ | |
82 | unsigned char __devinit | |
83 | pci_max_busnr(void) | |
84 | { | |
85 | struct pci_bus *bus = NULL; | |
86 | unsigned char max, n; | |
87 | ||
88 | max = 0; | |
89 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
90 | n = pci_bus_max_busnr(bus); | |
91 | if(n > max) | |
92 | max = n; | |
93 | } | |
94 | return max; | |
95 | } | |
96 | ||
54c762fe AB |
97 | #endif /* 0 */ |
98 | ||
687d5fe3 ME |
99 | #define PCI_FIND_CAP_TTL 48 |
100 | ||
101 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
102 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
103 | { |
104 | u8 id; | |
24a4e377 | 105 | |
687d5fe3 | 106 | while ((*ttl)--) { |
24a4e377 RD |
107 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
108 | if (pos < 0x40) | |
109 | break; | |
110 | pos &= ~3; | |
111 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
112 | &id); | |
113 | if (id == 0xff) | |
114 | break; | |
115 | if (id == cap) | |
116 | return pos; | |
117 | pos += PCI_CAP_LIST_NEXT; | |
118 | } | |
119 | return 0; | |
120 | } | |
121 | ||
687d5fe3 ME |
122 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
123 | u8 pos, int cap) | |
124 | { | |
125 | int ttl = PCI_FIND_CAP_TTL; | |
126 | ||
127 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
128 | } | |
129 | ||
24a4e377 RD |
130 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
131 | { | |
132 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
133 | pos + PCI_CAP_LIST_NEXT, cap); | |
134 | } | |
135 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
136 | ||
d3bac118 ME |
137 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
138 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
139 | { |
140 | u16 status; | |
1da177e4 LT |
141 | |
142 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
143 | if (!(status & PCI_STATUS_CAP_LIST)) | |
144 | return 0; | |
145 | ||
146 | switch (hdr_type) { | |
147 | case PCI_HEADER_TYPE_NORMAL: | |
148 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 149 | return PCI_CAPABILITY_LIST; |
1da177e4 | 150 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 151 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
152 | default: |
153 | return 0; | |
154 | } | |
d3bac118 ME |
155 | |
156 | return 0; | |
1da177e4 LT |
157 | } |
158 | ||
159 | /** | |
160 | * pci_find_capability - query for devices' capabilities | |
161 | * @dev: PCI device to query | |
162 | * @cap: capability code | |
163 | * | |
164 | * Tell if a device supports a given PCI capability. | |
165 | * Returns the address of the requested capability structure within the | |
166 | * device's PCI configuration space or 0 in case the device does not | |
167 | * support it. Possible values for @cap: | |
168 | * | |
169 | * %PCI_CAP_ID_PM Power Management | |
170 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
171 | * %PCI_CAP_ID_VPD Vital Product Data | |
172 | * %PCI_CAP_ID_SLOTID Slot Identification | |
173 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
174 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
175 | * %PCI_CAP_ID_PCIX PCI-X | |
176 | * %PCI_CAP_ID_EXP PCI Express | |
177 | */ | |
178 | int pci_find_capability(struct pci_dev *dev, int cap) | |
179 | { | |
d3bac118 ME |
180 | int pos; |
181 | ||
182 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
183 | if (pos) | |
184 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
185 | ||
186 | return pos; | |
1da177e4 LT |
187 | } |
188 | ||
189 | /** | |
190 | * pci_bus_find_capability - query for devices' capabilities | |
191 | * @bus: the PCI bus to query | |
192 | * @devfn: PCI device to query | |
193 | * @cap: capability code | |
194 | * | |
195 | * Like pci_find_capability() but works for pci devices that do not have a | |
196 | * pci_dev structure set up yet. | |
197 | * | |
198 | * Returns the address of the requested capability structure within the | |
199 | * device's PCI configuration space or 0 in case the device does not | |
200 | * support it. | |
201 | */ | |
202 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
203 | { | |
d3bac118 | 204 | int pos; |
1da177e4 LT |
205 | u8 hdr_type; |
206 | ||
207 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
208 | ||
d3bac118 ME |
209 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
210 | if (pos) | |
211 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
212 | ||
213 | return pos; | |
1da177e4 LT |
214 | } |
215 | ||
216 | /** | |
217 | * pci_find_ext_capability - Find an extended capability | |
218 | * @dev: PCI device to query | |
219 | * @cap: capability code | |
220 | * | |
221 | * Returns the address of the requested extended capability structure | |
222 | * within the device's PCI configuration space or 0 if the device does | |
223 | * not support it. Possible values for @cap: | |
224 | * | |
225 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
226 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
227 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
228 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
229 | */ | |
230 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
231 | { | |
232 | u32 header; | |
557848c3 ZY |
233 | int ttl; |
234 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 235 | |
557848c3 ZY |
236 | /* minimum 8 bytes per capability */ |
237 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
238 | ||
239 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
240 | return 0; |
241 | ||
242 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
243 | return 0; | |
244 | ||
245 | /* | |
246 | * If we have no capabilities, this is indicated by cap ID, | |
247 | * cap version and next pointer all being 0. | |
248 | */ | |
249 | if (header == 0) | |
250 | return 0; | |
251 | ||
252 | while (ttl-- > 0) { | |
253 | if (PCI_EXT_CAP_ID(header) == cap) | |
254 | return pos; | |
255 | ||
256 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 257 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
258 | break; |
259 | ||
260 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
261 | break; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
3a720d72 | 266 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 267 | |
687d5fe3 ME |
268 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
269 | { | |
270 | int rc, ttl = PCI_FIND_CAP_TTL; | |
271 | u8 cap, mask; | |
272 | ||
273 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
274 | mask = HT_3BIT_CAP_MASK; | |
275 | else | |
276 | mask = HT_5BIT_CAP_MASK; | |
277 | ||
278 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
279 | PCI_CAP_ID_HT, &ttl); | |
280 | while (pos) { | |
281 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
282 | if (rc != PCIBIOS_SUCCESSFUL) | |
283 | return 0; | |
284 | ||
285 | if ((cap & mask) == ht_cap) | |
286 | return pos; | |
287 | ||
47a4d5be BG |
288 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
289 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
290 | PCI_CAP_ID_HT, &ttl); |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | /** | |
296 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
297 | * @dev: PCI device to query | |
298 | * @pos: Position from which to continue searching | |
299 | * @ht_cap: Hypertransport capability code | |
300 | * | |
301 | * To be used in conjunction with pci_find_ht_capability() to search for | |
302 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
303 | * from pci_find_ht_capability(). | |
304 | * | |
305 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
306 | * steps to avoid an infinite loop. | |
307 | */ | |
308 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
309 | { | |
310 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
311 | } | |
312 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
313 | ||
314 | /** | |
315 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
316 | * @dev: PCI device to query | |
317 | * @ht_cap: Hypertransport capability code | |
318 | * | |
319 | * Tell if a device supports a given Hypertransport capability. | |
320 | * Returns an address within the device's PCI configuration space | |
321 | * or 0 in case the device does not support the request capability. | |
322 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
323 | * which has a Hypertransport capability matching @ht_cap. | |
324 | */ | |
325 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
326 | { | |
327 | int pos; | |
328 | ||
329 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
330 | if (pos) | |
331 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
332 | ||
333 | return pos; | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
336 | ||
1da177e4 LT |
337 | /** |
338 | * pci_find_parent_resource - return resource region of parent bus of given region | |
339 | * @dev: PCI device structure contains resources to be searched | |
340 | * @res: child resource record for which parent is sought | |
341 | * | |
342 | * For given resource region of given device, return the resource | |
343 | * region of parent bus the given region is contained in or where | |
344 | * it should be allocated from. | |
345 | */ | |
346 | struct resource * | |
347 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
348 | { | |
349 | const struct pci_bus *bus = dev->bus; | |
350 | int i; | |
351 | struct resource *best = NULL; | |
352 | ||
353 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
354 | struct resource *r = bus->resource[i]; | |
355 | if (!r) | |
356 | continue; | |
357 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
358 | continue; /* Not contained */ | |
359 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
360 | continue; /* Wrong type */ | |
361 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
362 | return r; /* Exact match */ | |
363 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
364 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
365 | } | |
366 | return best; | |
367 | } | |
368 | ||
064b53db JL |
369 | /** |
370 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
371 | * @dev: PCI device to have its BARs restored | |
372 | * | |
373 | * Restore the BAR values for a given device, so as to make it | |
374 | * accessible by its driver. | |
375 | */ | |
ad668599 | 376 | static void |
064b53db JL |
377 | pci_restore_bars(struct pci_dev *dev) |
378 | { | |
bc5f5a82 | 379 | int i; |
064b53db | 380 | |
bc5f5a82 | 381 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 382 | pci_update_resource(dev, i); |
064b53db JL |
383 | } |
384 | ||
961d9120 RW |
385 | static struct pci_platform_pm_ops *pci_platform_pm; |
386 | ||
387 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
388 | { | |
eb9d0fe4 RW |
389 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
390 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
391 | return -EINVAL; |
392 | pci_platform_pm = ops; | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
397 | { | |
398 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
399 | } | |
400 | ||
401 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
402 | pci_power_t t) | |
403 | { | |
404 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
405 | } | |
406 | ||
407 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
408 | { | |
409 | return pci_platform_pm ? | |
410 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
411 | } | |
8f7020d3 | 412 | |
eb9d0fe4 RW |
413 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
414 | { | |
415 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
416 | } | |
417 | ||
418 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
419 | { | |
420 | return pci_platform_pm ? | |
421 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
422 | } | |
423 | ||
1da177e4 | 424 | /** |
44e4e66e RW |
425 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
426 | * given PCI device | |
427 | * @dev: PCI device to handle. | |
44e4e66e | 428 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 429 | * |
44e4e66e RW |
430 | * RETURN VALUE: |
431 | * -EINVAL if the requested state is invalid. | |
432 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
433 | * wrong version, or device doesn't support the requested state. | |
434 | * 0 if device already is in the requested state. | |
435 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 436 | */ |
f00a20ef | 437 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 438 | { |
337001b6 | 439 | u16 pmcsr; |
44e4e66e | 440 | bool need_restore = false; |
1da177e4 | 441 | |
4a865905 RW |
442 | /* Check if we're already there */ |
443 | if (dev->current_state == state) | |
444 | return 0; | |
445 | ||
337001b6 | 446 | if (!dev->pm_cap) |
cca03dec AL |
447 | return -EIO; |
448 | ||
44e4e66e RW |
449 | if (state < PCI_D0 || state > PCI_D3hot) |
450 | return -EINVAL; | |
451 | ||
1da177e4 LT |
452 | /* Validate current state: |
453 | * Can enter D0 from any state, but if we can only go deeper | |
454 | * to sleep if we're already in a low power state | |
455 | */ | |
4a865905 | 456 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 457 | && dev->current_state > state) { |
80ccba11 BH |
458 | dev_err(&dev->dev, "invalid power transition " |
459 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 460 | return -EINVAL; |
44e4e66e | 461 | } |
1da177e4 | 462 | |
1da177e4 | 463 | /* check if this device supports the desired state */ |
337001b6 RW |
464 | if ((state == PCI_D1 && !dev->d1_support) |
465 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 466 | return -EIO; |
1da177e4 | 467 | |
337001b6 | 468 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 469 | |
32a36585 | 470 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
471 | * This doesn't affect PME_Status, disables PME_En, and |
472 | * sets PowerState to 0. | |
473 | */ | |
32a36585 | 474 | switch (dev->current_state) { |
d3535fbb JL |
475 | case PCI_D0: |
476 | case PCI_D1: | |
477 | case PCI_D2: | |
478 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
479 | pmcsr |= state; | |
480 | break; | |
32a36585 JL |
481 | case PCI_UNKNOWN: /* Boot-up */ |
482 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 483 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 484 | need_restore = true; |
32a36585 | 485 | /* Fall-through: force to D0 */ |
32a36585 | 486 | default: |
d3535fbb | 487 | pmcsr = 0; |
32a36585 | 488 | break; |
1da177e4 LT |
489 | } |
490 | ||
491 | /* enter specified state */ | |
337001b6 | 492 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
493 | |
494 | /* Mandatory power management transition delays */ | |
495 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
496 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 497 | msleep(pci_pm_d3_delay); |
1da177e4 | 498 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 499 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 500 | |
b913100d | 501 | dev->current_state = state; |
064b53db JL |
502 | |
503 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
504 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
505 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
506 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
507 | * For example, at least some versions of the 3c905B and the | |
508 | * 3c556B exhibit this behaviour. | |
509 | * | |
510 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
511 | * devices in a D3hot state at boot. Consequently, we need to | |
512 | * restore at least the BARs so that the device will be | |
513 | * accessible to its driver. | |
514 | */ | |
515 | if (need_restore) | |
516 | pci_restore_bars(dev); | |
517 | ||
f00a20ef | 518 | if (dev->bus->self) |
7d715a6c SL |
519 | pcie_aspm_pm_state_change(dev->bus->self); |
520 | ||
1da177e4 LT |
521 | return 0; |
522 | } | |
523 | ||
44e4e66e RW |
524 | /** |
525 | * pci_update_current_state - Read PCI power state of given device from its | |
526 | * PCI PM registers and cache it | |
527 | * @dev: PCI device to handle. | |
f06fc0b6 | 528 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 529 | */ |
73410429 | 530 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 531 | { |
337001b6 | 532 | if (dev->pm_cap) { |
44e4e66e RW |
533 | u16 pmcsr; |
534 | ||
337001b6 | 535 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 536 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
537 | } else { |
538 | dev->current_state = state; | |
44e4e66e RW |
539 | } |
540 | } | |
541 | ||
0e5dd46b RW |
542 | /** |
543 | * pci_platform_power_transition - Use platform to change device power state | |
544 | * @dev: PCI device to handle. | |
545 | * @state: State to put the device into. | |
546 | */ | |
547 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
548 | { | |
549 | int error; | |
550 | ||
551 | if (platform_pci_power_manageable(dev)) { | |
552 | error = platform_pci_set_power_state(dev, state); | |
553 | if (!error) | |
554 | pci_update_current_state(dev, state); | |
555 | } else { | |
556 | error = -ENODEV; | |
557 | /* Fall back to PCI_D0 if native PM is not supported */ | |
558 | pci_update_current_state(dev, PCI_D0); | |
559 | } | |
560 | ||
561 | return error; | |
562 | } | |
563 | ||
564 | /** | |
565 | * __pci_start_power_transition - Start power transition of a PCI device | |
566 | * @dev: PCI device to handle. | |
567 | * @state: State to put the device into. | |
568 | */ | |
569 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
570 | { | |
571 | if (state == PCI_D0) | |
572 | pci_platform_power_transition(dev, PCI_D0); | |
573 | } | |
574 | ||
575 | /** | |
576 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
577 | * @dev: PCI device to handle. | |
578 | * @state: State to put the device into. | |
579 | * | |
580 | * This function should not be called directly by device drivers. | |
581 | */ | |
582 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
583 | { | |
584 | return state > PCI_D0 ? | |
585 | pci_platform_power_transition(dev, state) : -EINVAL; | |
586 | } | |
587 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
588 | ||
44e4e66e RW |
589 | /** |
590 | * pci_set_power_state - Set the power state of a PCI device | |
591 | * @dev: PCI device to handle. | |
592 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
593 | * | |
594 | * Transition a device to a new power state, using the platform formware and/or | |
595 | * the device's PCI PM registers. | |
596 | * | |
597 | * RETURN VALUE: | |
598 | * -EINVAL if the requested state is invalid. | |
599 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
600 | * wrong version, or device doesn't support the requested state. | |
601 | * 0 if device already is in the requested state. | |
602 | * 0 if device's power state has been successfully changed. | |
603 | */ | |
604 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
605 | { | |
337001b6 | 606 | int error; |
44e4e66e RW |
607 | |
608 | /* bound the state we're entering */ | |
609 | if (state > PCI_D3hot) | |
610 | state = PCI_D3hot; | |
611 | else if (state < PCI_D0) | |
612 | state = PCI_D0; | |
613 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
614 | /* | |
615 | * If the device or the parent bridge do not support PCI PM, | |
616 | * ignore the request if we're doing anything other than putting | |
617 | * it into D0 (which would only happen on boot). | |
618 | */ | |
619 | return 0; | |
620 | ||
4a865905 RW |
621 | /* Check if we're already there */ |
622 | if (dev->current_state == state) | |
623 | return 0; | |
624 | ||
0e5dd46b RW |
625 | __pci_start_power_transition(dev, state); |
626 | ||
979b1791 AC |
627 | /* This device is quirked not to be put into D3, so |
628 | don't put it in D3 */ | |
629 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
630 | return 0; | |
44e4e66e | 631 | |
f00a20ef | 632 | error = pci_raw_set_power_state(dev, state); |
44e4e66e | 633 | |
0e5dd46b RW |
634 | if (!__pci_complete_power_transition(dev, state)) |
635 | error = 0; | |
44e4e66e RW |
636 | |
637 | return error; | |
638 | } | |
639 | ||
1da177e4 LT |
640 | /** |
641 | * pci_choose_state - Choose the power state of a PCI device | |
642 | * @dev: PCI device to be suspended | |
643 | * @state: target sleep state for the whole system. This is the value | |
644 | * that is passed to suspend() function. | |
645 | * | |
646 | * Returns PCI power state suitable for given device and given system | |
647 | * message. | |
648 | */ | |
649 | ||
650 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
651 | { | |
ab826ca4 | 652 | pci_power_t ret; |
0f64474b | 653 | |
1da177e4 LT |
654 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
655 | return PCI_D0; | |
656 | ||
961d9120 RW |
657 | ret = platform_pci_choose_state(dev); |
658 | if (ret != PCI_POWER_ERROR) | |
659 | return ret; | |
ca078bae PM |
660 | |
661 | switch (state.event) { | |
662 | case PM_EVENT_ON: | |
663 | return PCI_D0; | |
664 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
665 | case PM_EVENT_PRETHAW: |
666 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 667 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 668 | case PM_EVENT_HIBERNATE: |
ca078bae | 669 | return PCI_D3hot; |
1da177e4 | 670 | default: |
80ccba11 BH |
671 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
672 | state.event); | |
1da177e4 LT |
673 | BUG(); |
674 | } | |
675 | return PCI_D0; | |
676 | } | |
677 | ||
678 | EXPORT_SYMBOL(pci_choose_state); | |
679 | ||
b56a5a23 MT |
680 | static int pci_save_pcie_state(struct pci_dev *dev) |
681 | { | |
682 | int pos, i = 0; | |
683 | struct pci_cap_saved_state *save_state; | |
684 | u16 *cap; | |
685 | ||
686 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
687 | if (pos <= 0) | |
688 | return 0; | |
689 | ||
9f35575d | 690 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 691 | if (!save_state) { |
63f4898a | 692 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
b56a5a23 MT |
693 | return -ENOMEM; |
694 | } | |
695 | cap = (u16 *)&save_state->data[0]; | |
696 | ||
697 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
698 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
699 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
700 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
63f4898a | 701 | |
b56a5a23 MT |
702 | return 0; |
703 | } | |
704 | ||
705 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
706 | { | |
707 | int i = 0, pos; | |
708 | struct pci_cap_saved_state *save_state; | |
709 | u16 *cap; | |
710 | ||
711 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
712 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
713 | if (!save_state || pos <= 0) | |
714 | return; | |
715 | cap = (u16 *)&save_state->data[0]; | |
716 | ||
717 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
718 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
719 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
720 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
721 | } |
722 | ||
cc692a5f SH |
723 | |
724 | static int pci_save_pcix_state(struct pci_dev *dev) | |
725 | { | |
63f4898a | 726 | int pos; |
cc692a5f | 727 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
728 | |
729 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
730 | if (pos <= 0) | |
731 | return 0; | |
732 | ||
f34303de | 733 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 734 | if (!save_state) { |
63f4898a | 735 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
cc692a5f SH |
736 | return -ENOMEM; |
737 | } | |
cc692a5f | 738 | |
63f4898a RW |
739 | pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); |
740 | ||
cc692a5f SH |
741 | return 0; |
742 | } | |
743 | ||
744 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
745 | { | |
746 | int i = 0, pos; | |
747 | struct pci_cap_saved_state *save_state; | |
748 | u16 *cap; | |
749 | ||
750 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
751 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
752 | if (!save_state || pos <= 0) | |
753 | return; | |
754 | cap = (u16 *)&save_state->data[0]; | |
755 | ||
756 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
757 | } |
758 | ||
759 | ||
1da177e4 LT |
760 | /** |
761 | * pci_save_state - save the PCI configuration space of a device before suspending | |
762 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
763 | */ |
764 | int | |
765 | pci_save_state(struct pci_dev *dev) | |
766 | { | |
767 | int i; | |
768 | /* XXX: 100% dword access ok here? */ | |
769 | for (i = 0; i < 16; i++) | |
770 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
aa8c6c93 | 771 | dev->state_saved = true; |
b56a5a23 MT |
772 | if ((i = pci_save_pcie_state(dev)) != 0) |
773 | return i; | |
cc692a5f SH |
774 | if ((i = pci_save_pcix_state(dev)) != 0) |
775 | return i; | |
1da177e4 LT |
776 | return 0; |
777 | } | |
778 | ||
779 | /** | |
780 | * pci_restore_state - Restore the saved state of a PCI device | |
781 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
782 | */ |
783 | int | |
784 | pci_restore_state(struct pci_dev *dev) | |
785 | { | |
786 | int i; | |
b4482a4b | 787 | u32 val; |
1da177e4 | 788 | |
b56a5a23 MT |
789 | /* PCI Express register must be restored first */ |
790 | pci_restore_pcie_state(dev); | |
791 | ||
8b8c8d28 YL |
792 | /* |
793 | * The Base Address register should be programmed before the command | |
794 | * register(s) | |
795 | */ | |
796 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
797 | pci_read_config_dword(dev, i * 4, &val); |
798 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
799 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
800 | "space at offset %#x (was %#x, writing %#x)\n", | |
801 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
802 | pci_write_config_dword(dev,i * 4, |
803 | dev->saved_config_space[i]); | |
804 | } | |
805 | } | |
cc692a5f | 806 | pci_restore_pcix_state(dev); |
41017f0c | 807 | pci_restore_msi_state(dev); |
8fed4b65 | 808 | |
1da177e4 LT |
809 | return 0; |
810 | } | |
811 | ||
38cc1302 HS |
812 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
813 | { | |
814 | int err; | |
815 | ||
816 | err = pci_set_power_state(dev, PCI_D0); | |
817 | if (err < 0 && err != -EIO) | |
818 | return err; | |
819 | err = pcibios_enable_device(dev, bars); | |
820 | if (err < 0) | |
821 | return err; | |
822 | pci_fixup_device(pci_fixup_enable, dev); | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | /** | |
0b62e13b | 828 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
829 | * @dev: PCI device to be resumed |
830 | * | |
831 | * Note this function is a backend of pci_default_resume and is not supposed | |
832 | * to be called by normal code, write proper resume handler and use it instead. | |
833 | */ | |
0b62e13b | 834 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
835 | { |
836 | if (atomic_read(&dev->enable_cnt)) | |
837 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
838 | return 0; | |
839 | } | |
840 | ||
b718989d BH |
841 | static int __pci_enable_device_flags(struct pci_dev *dev, |
842 | resource_size_t flags) | |
1da177e4 LT |
843 | { |
844 | int err; | |
b718989d | 845 | int i, bars = 0; |
1da177e4 | 846 | |
9fb625c3 HS |
847 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
848 | return 0; /* already enabled */ | |
849 | ||
b718989d BH |
850 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
851 | if (dev->resource[i].flags & flags) | |
852 | bars |= (1 << i); | |
853 | ||
38cc1302 | 854 | err = do_pci_enable_device(dev, bars); |
95a62965 | 855 | if (err < 0) |
38cc1302 | 856 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 857 | return err; |
1da177e4 LT |
858 | } |
859 | ||
b718989d BH |
860 | /** |
861 | * pci_enable_device_io - Initialize a device for use with IO space | |
862 | * @dev: PCI device to be initialized | |
863 | * | |
864 | * Initialize device before it's used by a driver. Ask low-level code | |
865 | * to enable I/O resources. Wake up the device if it was suspended. | |
866 | * Beware, this function can fail. | |
867 | */ | |
868 | int pci_enable_device_io(struct pci_dev *dev) | |
869 | { | |
870 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
871 | } | |
872 | ||
873 | /** | |
874 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
875 | * @dev: PCI device to be initialized | |
876 | * | |
877 | * Initialize device before it's used by a driver. Ask low-level code | |
878 | * to enable Memory resources. Wake up the device if it was suspended. | |
879 | * Beware, this function can fail. | |
880 | */ | |
881 | int pci_enable_device_mem(struct pci_dev *dev) | |
882 | { | |
883 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
884 | } | |
885 | ||
bae94d02 IPG |
886 | /** |
887 | * pci_enable_device - Initialize device before it's used by a driver. | |
888 | * @dev: PCI device to be initialized | |
889 | * | |
890 | * Initialize device before it's used by a driver. Ask low-level code | |
891 | * to enable I/O and memory. Wake up the device if it was suspended. | |
892 | * Beware, this function can fail. | |
893 | * | |
894 | * Note we don't actually enable the device many times if we call | |
895 | * this function repeatedly (we just increment the count). | |
896 | */ | |
897 | int pci_enable_device(struct pci_dev *dev) | |
898 | { | |
b718989d | 899 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
900 | } |
901 | ||
9ac7849e TH |
902 | /* |
903 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
904 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
905 | * there's no need to track it separately. pci_devres is initialized | |
906 | * when a device is enabled using managed PCI device enable interface. | |
907 | */ | |
908 | struct pci_devres { | |
7f375f32 TH |
909 | unsigned int enabled:1; |
910 | unsigned int pinned:1; | |
9ac7849e TH |
911 | unsigned int orig_intx:1; |
912 | unsigned int restore_intx:1; | |
913 | u32 region_mask; | |
914 | }; | |
915 | ||
916 | static void pcim_release(struct device *gendev, void *res) | |
917 | { | |
918 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
919 | struct pci_devres *this = res; | |
920 | int i; | |
921 | ||
922 | if (dev->msi_enabled) | |
923 | pci_disable_msi(dev); | |
924 | if (dev->msix_enabled) | |
925 | pci_disable_msix(dev); | |
926 | ||
927 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
928 | if (this->region_mask & (1 << i)) | |
929 | pci_release_region(dev, i); | |
930 | ||
931 | if (this->restore_intx) | |
932 | pci_intx(dev, this->orig_intx); | |
933 | ||
7f375f32 | 934 | if (this->enabled && !this->pinned) |
9ac7849e TH |
935 | pci_disable_device(dev); |
936 | } | |
937 | ||
938 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
939 | { | |
940 | struct pci_devres *dr, *new_dr; | |
941 | ||
942 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
943 | if (dr) | |
944 | return dr; | |
945 | ||
946 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
947 | if (!new_dr) | |
948 | return NULL; | |
949 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
950 | } | |
951 | ||
952 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
953 | { | |
954 | if (pci_is_managed(pdev)) | |
955 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
956 | return NULL; | |
957 | } | |
958 | ||
959 | /** | |
960 | * pcim_enable_device - Managed pci_enable_device() | |
961 | * @pdev: PCI device to be initialized | |
962 | * | |
963 | * Managed pci_enable_device(). | |
964 | */ | |
965 | int pcim_enable_device(struct pci_dev *pdev) | |
966 | { | |
967 | struct pci_devres *dr; | |
968 | int rc; | |
969 | ||
970 | dr = get_pci_dr(pdev); | |
971 | if (unlikely(!dr)) | |
972 | return -ENOMEM; | |
b95d58ea TH |
973 | if (dr->enabled) |
974 | return 0; | |
9ac7849e TH |
975 | |
976 | rc = pci_enable_device(pdev); | |
977 | if (!rc) { | |
978 | pdev->is_managed = 1; | |
7f375f32 | 979 | dr->enabled = 1; |
9ac7849e TH |
980 | } |
981 | return rc; | |
982 | } | |
983 | ||
984 | /** | |
985 | * pcim_pin_device - Pin managed PCI device | |
986 | * @pdev: PCI device to pin | |
987 | * | |
988 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
989 | * driver detach. @pdev must have been enabled with | |
990 | * pcim_enable_device(). | |
991 | */ | |
992 | void pcim_pin_device(struct pci_dev *pdev) | |
993 | { | |
994 | struct pci_devres *dr; | |
995 | ||
996 | dr = find_pci_dr(pdev); | |
7f375f32 | 997 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 998 | if (dr) |
7f375f32 | 999 | dr->pinned = 1; |
9ac7849e TH |
1000 | } |
1001 | ||
1da177e4 LT |
1002 | /** |
1003 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1004 | * @dev: the PCI device to disable | |
1005 | * | |
1006 | * Disables architecture specific PCI resources for the device. This | |
1007 | * is the default implementation. Architecture implementations can | |
1008 | * override this. | |
1009 | */ | |
1010 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
1011 | ||
fa58d305 RW |
1012 | static void do_pci_disable_device(struct pci_dev *dev) |
1013 | { | |
1014 | u16 pci_command; | |
1015 | ||
1016 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1017 | if (pci_command & PCI_COMMAND_MASTER) { | |
1018 | pci_command &= ~PCI_COMMAND_MASTER; | |
1019 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1020 | } | |
1021 | ||
1022 | pcibios_disable_device(dev); | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1027 | * @dev: PCI device to disable | |
1028 | * | |
1029 | * NOTE: This function is a backend of PCI power management routines and is | |
1030 | * not supposed to be called drivers. | |
1031 | */ | |
1032 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1033 | { | |
1034 | if (atomic_read(&dev->enable_cnt)) | |
1035 | do_pci_disable_device(dev); | |
1036 | } | |
1037 | ||
1da177e4 LT |
1038 | /** |
1039 | * pci_disable_device - Disable PCI device after use | |
1040 | * @dev: PCI device to be disabled | |
1041 | * | |
1042 | * Signal to the system that the PCI device is not in use by the system | |
1043 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1044 | * |
1045 | * Note we don't actually disable the device until all callers of | |
1046 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
1047 | */ |
1048 | void | |
1049 | pci_disable_device(struct pci_dev *dev) | |
1050 | { | |
9ac7849e | 1051 | struct pci_devres *dr; |
99dc804d | 1052 | |
9ac7849e TH |
1053 | dr = find_pci_dr(dev); |
1054 | if (dr) | |
7f375f32 | 1055 | dr->enabled = 0; |
9ac7849e | 1056 | |
bae94d02 IPG |
1057 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1058 | return; | |
1059 | ||
fa58d305 | 1060 | do_pci_disable_device(dev); |
1da177e4 | 1061 | |
fa58d305 | 1062 | dev->is_busmaster = 0; |
1da177e4 LT |
1063 | } |
1064 | ||
f7bdd12d BK |
1065 | /** |
1066 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1067 | * @dev: the PCI-E device reset | |
1068 | * @state: Reset state to enter into | |
1069 | * | |
1070 | * | |
1071 | * Sets the PCI-E reset state for the device. This is the default | |
1072 | * implementation. Architecture implementations can override this. | |
1073 | */ | |
1074 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1075 | enum pcie_reset_state state) | |
1076 | { | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * pci_set_pcie_reset_state - set reset state for device dev | |
1082 | * @dev: the PCI-E device reset | |
1083 | * @state: Reset state to enter into | |
1084 | * | |
1085 | * | |
1086 | * Sets the PCI reset state for the device. | |
1087 | */ | |
1088 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1089 | { | |
1090 | return pcibios_set_pcie_reset_state(dev, state); | |
1091 | } | |
1092 | ||
eb9d0fe4 RW |
1093 | /** |
1094 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1095 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1096 | * @state: PCI state from which device will issue PME#. |
1097 | */ | |
e5899e1b | 1098 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1099 | { |
337001b6 | 1100 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1101 | return false; |
1102 | ||
337001b6 | 1103 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1104 | } |
1105 | ||
1106 | /** | |
1107 | * pci_pme_active - enable or disable PCI device's PME# function | |
1108 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1109 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1110 | * | |
1111 | * The caller must verify that the device is capable of generating PME# before | |
1112 | * calling this function with @enable equal to 'true'. | |
1113 | */ | |
5a6c9b60 | 1114 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1115 | { |
1116 | u16 pmcsr; | |
1117 | ||
337001b6 | 1118 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1119 | return; |
1120 | ||
337001b6 | 1121 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1122 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1123 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1124 | if (!enable) | |
1125 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1126 | ||
337001b6 | 1127 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 RW |
1128 | |
1129 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1130 | enable ? "enabled" : "disabled"); | |
1131 | } | |
1132 | ||
1da177e4 | 1133 | /** |
075c1771 DB |
1134 | * pci_enable_wake - enable PCI device as wakeup event source |
1135 | * @dev: PCI device affected | |
1136 | * @state: PCI state from which device will issue wakeup events | |
1137 | * @enable: True to enable event generation; false to disable | |
1138 | * | |
1139 | * This enables the device as a wakeup event source, or disables it. | |
1140 | * When such events involves platform-specific hooks, those hooks are | |
1141 | * called automatically by this routine. | |
1142 | * | |
1143 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1144 | * always require such platform hooks. |
075c1771 | 1145 | * |
eb9d0fe4 RW |
1146 | * RETURN VALUE: |
1147 | * 0 is returned on success | |
1148 | * -EINVAL is returned if device is not supposed to wake up the system | |
1149 | * Error code depending on the platform is returned if both the platform and | |
1150 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1151 | */ |
1152 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1153 | { | |
eb9d0fe4 RW |
1154 | int error = 0; |
1155 | bool pme_done = false; | |
075c1771 | 1156 | |
bebd590c | 1157 | if (enable && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1158 | return -EINVAL; |
1da177e4 | 1159 | |
eb9d0fe4 RW |
1160 | /* |
1161 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1162 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1163 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1164 | */ |
1da177e4 | 1165 | |
eb9d0fe4 RW |
1166 | if (!enable && platform_pci_can_wakeup(dev)) |
1167 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1168 | |
337001b6 RW |
1169 | if (!enable || pci_pme_capable(dev, state)) { |
1170 | pci_pme_active(dev, enable); | |
eb9d0fe4 | 1171 | pme_done = true; |
075c1771 | 1172 | } |
1da177e4 | 1173 | |
eb9d0fe4 RW |
1174 | if (enable && platform_pci_can_wakeup(dev)) |
1175 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1176 | |
eb9d0fe4 RW |
1177 | return pme_done ? 0 : error; |
1178 | } | |
1da177e4 | 1179 | |
0235c4fc RW |
1180 | /** |
1181 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1182 | * @dev: PCI device to prepare | |
1183 | * @enable: True to enable wake-up event generation; false to disable | |
1184 | * | |
1185 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1186 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1187 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1188 | * ordering constraints. | |
1189 | * | |
1190 | * This function only returns error code if the device is not capable of | |
1191 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1192 | * enable wake-up power for it. | |
1193 | */ | |
1194 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1195 | { | |
1196 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1197 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1198 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1199 | } | |
1200 | ||
404cc2d8 | 1201 | /** |
37139074 JB |
1202 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1203 | * @dev: PCI device | |
1204 | * | |
1205 | * Use underlying platform code to find a supported low power state for @dev. | |
1206 | * If the platform can't manage @dev, return the deepest state from which it | |
1207 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1208 | */ |
e5899e1b | 1209 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1210 | { |
1211 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1212 | |
1213 | if (platform_pci_power_manageable(dev)) { | |
1214 | /* | |
1215 | * Call the platform to choose the target state of the device | |
1216 | * and enable wake-up from this state if supported. | |
1217 | */ | |
1218 | pci_power_t state = platform_pci_choose_state(dev); | |
1219 | ||
1220 | switch (state) { | |
1221 | case PCI_POWER_ERROR: | |
1222 | case PCI_UNKNOWN: | |
1223 | break; | |
1224 | case PCI_D1: | |
1225 | case PCI_D2: | |
1226 | if (pci_no_d1d2(dev)) | |
1227 | break; | |
1228 | default: | |
1229 | target_state = state; | |
404cc2d8 RW |
1230 | } |
1231 | } else if (device_may_wakeup(&dev->dev)) { | |
1232 | /* | |
1233 | * Find the deepest state from which the device can generate | |
1234 | * wake-up events, make it the target state and enable device | |
1235 | * to generate PME#. | |
1236 | */ | |
337001b6 | 1237 | if (!dev->pm_cap) |
e5899e1b | 1238 | return PCI_POWER_ERROR; |
404cc2d8 | 1239 | |
337001b6 RW |
1240 | if (dev->pme_support) { |
1241 | while (target_state | |
1242 | && !(dev->pme_support & (1 << target_state))) | |
1243 | target_state--; | |
404cc2d8 RW |
1244 | } |
1245 | } | |
1246 | ||
e5899e1b RW |
1247 | return target_state; |
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1252 | * @dev: Device to handle. | |
1253 | * | |
1254 | * Choose the power state appropriate for the device depending on whether | |
1255 | * it can wake up the system and/or is power manageable by the platform | |
1256 | * (PCI_D3hot is the default) and put the device into that state. | |
1257 | */ | |
1258 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1259 | { | |
1260 | pci_power_t target_state = pci_target_state(dev); | |
1261 | int error; | |
1262 | ||
1263 | if (target_state == PCI_POWER_ERROR) | |
1264 | return -EIO; | |
1265 | ||
c157dfa3 RW |
1266 | pci_enable_wake(dev, target_state, true); |
1267 | ||
404cc2d8 RW |
1268 | error = pci_set_power_state(dev, target_state); |
1269 | ||
1270 | if (error) | |
1271 | pci_enable_wake(dev, target_state, false); | |
1272 | ||
1273 | return error; | |
1274 | } | |
1275 | ||
1276 | /** | |
443bd1c4 | 1277 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1278 | * @dev: Device to handle. |
1279 | * | |
1280 | * Disable device's sytem wake-up capability and put it into D0. | |
1281 | */ | |
1282 | int pci_back_from_sleep(struct pci_dev *dev) | |
1283 | { | |
1284 | pci_enable_wake(dev, PCI_D0, false); | |
1285 | return pci_set_power_state(dev, PCI_D0); | |
1286 | } | |
1287 | ||
eb9d0fe4 RW |
1288 | /** |
1289 | * pci_pm_init - Initialize PM functions of given PCI device | |
1290 | * @dev: PCI device to handle. | |
1291 | */ | |
1292 | void pci_pm_init(struct pci_dev *dev) | |
1293 | { | |
1294 | int pm; | |
1295 | u16 pmc; | |
1da177e4 | 1296 | |
337001b6 RW |
1297 | dev->pm_cap = 0; |
1298 | ||
eb9d0fe4 RW |
1299 | /* find PCI PM capability in list */ |
1300 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1301 | if (!pm) | |
50246dd4 | 1302 | return; |
eb9d0fe4 RW |
1303 | /* Check device's ability to generate PME# */ |
1304 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1305 | |
eb9d0fe4 RW |
1306 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1307 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1308 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 1309 | return; |
eb9d0fe4 RW |
1310 | } |
1311 | ||
337001b6 RW |
1312 | dev->pm_cap = pm; |
1313 | ||
1314 | dev->d1_support = false; | |
1315 | dev->d2_support = false; | |
1316 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1317 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1318 | dev->d1_support = true; |
c9ed77ee | 1319 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1320 | dev->d2_support = true; |
c9ed77ee BH |
1321 | |
1322 | if (dev->d1_support || dev->d2_support) | |
1323 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1324 | dev->d1_support ? " D1" : "", |
1325 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1326 | } |
1327 | ||
1328 | pmc &= PCI_PM_CAP_PME_MASK; | |
1329 | if (pmc) { | |
c9ed77ee BH |
1330 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
1331 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1332 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1333 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1334 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1335 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1336 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1337 | /* |
1338 | * Make device's PM flags reflect the wake-up capability, but | |
1339 | * let the user space enable it to wake up the system as needed. | |
1340 | */ | |
1341 | device_set_wakeup_capable(&dev->dev, true); | |
1342 | device_set_wakeup_enable(&dev->dev, false); | |
1343 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1344 | pci_pme_active(dev, false); |
1345 | } else { | |
1346 | dev->pme_support = 0; | |
eb9d0fe4 | 1347 | } |
1da177e4 LT |
1348 | } |
1349 | ||
eb9c39d0 JB |
1350 | /** |
1351 | * platform_pci_wakeup_init - init platform wakeup if present | |
1352 | * @dev: PCI device | |
1353 | * | |
1354 | * Some devices don't have PCI PM caps but can still generate wakeup | |
1355 | * events through platform methods (like ACPI events). If @dev supports | |
1356 | * platform wakeup events, set the device flag to indicate as much. This | |
1357 | * may be redundant if the device also supports PCI PM caps, but double | |
1358 | * initialization should be safe in that case. | |
1359 | */ | |
1360 | void platform_pci_wakeup_init(struct pci_dev *dev) | |
1361 | { | |
1362 | if (!platform_pci_can_wakeup(dev)) | |
1363 | return; | |
1364 | ||
1365 | device_set_wakeup_capable(&dev->dev, true); | |
1366 | device_set_wakeup_enable(&dev->dev, false); | |
1367 | platform_pci_sleep_wake(dev, false); | |
1368 | } | |
1369 | ||
63f4898a RW |
1370 | /** |
1371 | * pci_add_save_buffer - allocate buffer for saving given capability registers | |
1372 | * @dev: the PCI device | |
1373 | * @cap: the capability to allocate the buffer for | |
1374 | * @size: requested size of the buffer | |
1375 | */ | |
1376 | static int pci_add_cap_save_buffer( | |
1377 | struct pci_dev *dev, char cap, unsigned int size) | |
1378 | { | |
1379 | int pos; | |
1380 | struct pci_cap_saved_state *save_state; | |
1381 | ||
1382 | pos = pci_find_capability(dev, cap); | |
1383 | if (pos <= 0) | |
1384 | return 0; | |
1385 | ||
1386 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
1387 | if (!save_state) | |
1388 | return -ENOMEM; | |
1389 | ||
1390 | save_state->cap_nr = cap; | |
1391 | pci_add_saved_cap(dev, save_state); | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | /** | |
1397 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
1398 | * @dev: the PCI device | |
1399 | */ | |
1400 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
1401 | { | |
1402 | int error; | |
1403 | ||
1404 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 4 * sizeof(u16)); | |
1405 | if (error) | |
1406 | dev_err(&dev->dev, | |
1407 | "unable to preallocate PCI Express save buffer\n"); | |
1408 | ||
1409 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
1410 | if (error) | |
1411 | dev_err(&dev->dev, | |
1412 | "unable to preallocate PCI-X save buffer\n"); | |
1413 | } | |
1414 | ||
58c3a727 YZ |
1415 | /** |
1416 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
1417 | * @dev: the PCI device | |
1418 | */ | |
1419 | void pci_enable_ari(struct pci_dev *dev) | |
1420 | { | |
1421 | int pos; | |
1422 | u32 cap; | |
1423 | u16 ctrl; | |
8113587c | 1424 | struct pci_dev *bridge; |
58c3a727 | 1425 | |
8113587c | 1426 | if (!dev->is_pcie || dev->devfn) |
58c3a727 YZ |
1427 | return; |
1428 | ||
8113587c ZY |
1429 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
1430 | if (!pos) | |
58c3a727 YZ |
1431 | return; |
1432 | ||
8113587c ZY |
1433 | bridge = dev->bus->self; |
1434 | if (!bridge || !bridge->is_pcie) | |
1435 | return; | |
1436 | ||
1437 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
58c3a727 YZ |
1438 | if (!pos) |
1439 | return; | |
1440 | ||
8113587c | 1441 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
1442 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
1443 | return; | |
1444 | ||
8113587c | 1445 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
58c3a727 | 1446 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
8113587c | 1447 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
58c3a727 | 1448 | |
8113587c | 1449 | bridge->ari_enabled = 1; |
58c3a727 YZ |
1450 | } |
1451 | ||
57c2cf71 BH |
1452 | /** |
1453 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
1454 | * @dev: the PCI device | |
1455 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1456 | * | |
1457 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
1458 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
1459 | * behind bridges on add-in cards. | |
1460 | */ | |
1461 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) | |
1462 | { | |
1463 | return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1; | |
1464 | } | |
1465 | ||
1da177e4 LT |
1466 | int |
1467 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1468 | { | |
1469 | u8 pin; | |
1470 | ||
514d207d | 1471 | pin = dev->pin; |
1da177e4 LT |
1472 | if (!pin) |
1473 | return -1; | |
878f2e50 | 1474 | |
1da177e4 | 1475 | while (dev->bus->self) { |
57c2cf71 | 1476 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
1477 | dev = dev->bus->self; |
1478 | } | |
1479 | *bridge = dev; | |
1480 | return pin; | |
1481 | } | |
1482 | ||
68feac87 BH |
1483 | /** |
1484 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
1485 | * @dev: the PCI device | |
1486 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1487 | * | |
1488 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
1489 | * bridges all the way up to a PCI root bus. | |
1490 | */ | |
1491 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
1492 | { | |
1493 | u8 pin = *pinp; | |
1494 | ||
1495 | while (dev->bus->self) { | |
1496 | pin = pci_swizzle_interrupt_pin(dev, pin); | |
1497 | dev = dev->bus->self; | |
1498 | } | |
1499 | *pinp = pin; | |
1500 | return PCI_SLOT(dev->devfn); | |
1501 | } | |
1502 | ||
1da177e4 LT |
1503 | /** |
1504 | * pci_release_region - Release a PCI bar | |
1505 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1506 | * @bar: BAR to release | |
1507 | * | |
1508 | * Releases the PCI I/O and memory resources previously reserved by a | |
1509 | * successful call to pci_request_region. Call this function only | |
1510 | * after all use of the PCI regions has ceased. | |
1511 | */ | |
1512 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1513 | { | |
9ac7849e TH |
1514 | struct pci_devres *dr; |
1515 | ||
1da177e4 LT |
1516 | if (pci_resource_len(pdev, bar) == 0) |
1517 | return; | |
1518 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1519 | release_region(pci_resource_start(pdev, bar), | |
1520 | pci_resource_len(pdev, bar)); | |
1521 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1522 | release_mem_region(pci_resource_start(pdev, bar), | |
1523 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1524 | |
1525 | dr = find_pci_dr(pdev); | |
1526 | if (dr) | |
1527 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1528 | } |
1529 | ||
1530 | /** | |
f5ddcac4 | 1531 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
1532 | * @pdev: PCI device whose resources are to be reserved |
1533 | * @bar: BAR to be reserved | |
1534 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 1535 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
1536 | * |
1537 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1538 | * being reserved by owner @res_name. Do not access any | |
1539 | * address inside the PCI regions unless this call returns | |
1540 | * successfully. | |
1541 | * | |
f5ddcac4 RD |
1542 | * If @exclusive is set, then the region is marked so that userspace |
1543 | * is explicitly not allowed to map the resource via /dev/mem or | |
1544 | * sysfs MMIO access. | |
1545 | * | |
1da177e4 LT |
1546 | * Returns 0 on success, or %EBUSY on error. A warning |
1547 | * message is also printed on failure. | |
1548 | */ | |
e8de1481 AV |
1549 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
1550 | int exclusive) | |
1da177e4 | 1551 | { |
9ac7849e TH |
1552 | struct pci_devres *dr; |
1553 | ||
1da177e4 LT |
1554 | if (pci_resource_len(pdev, bar) == 0) |
1555 | return 0; | |
1556 | ||
1557 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1558 | if (!request_region(pci_resource_start(pdev, bar), | |
1559 | pci_resource_len(pdev, bar), res_name)) | |
1560 | goto err_out; | |
1561 | } | |
1562 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
1563 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
1564 | pci_resource_len(pdev, bar), res_name, | |
1565 | exclusive)) | |
1da177e4 LT |
1566 | goto err_out; |
1567 | } | |
9ac7849e TH |
1568 | |
1569 | dr = find_pci_dr(pdev); | |
1570 | if (dr) | |
1571 | dr->region_mask |= 1 << bar; | |
1572 | ||
1da177e4 LT |
1573 | return 0; |
1574 | ||
1575 | err_out: | |
096e6f67 | 1576 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
e4ec7a00 JB |
1577 | bar, |
1578 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
096e6f67 | 1579 | &pdev->resource[bar]); |
1da177e4 LT |
1580 | return -EBUSY; |
1581 | } | |
1582 | ||
e8de1481 | 1583 | /** |
f5ddcac4 | 1584 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
1585 | * @pdev: PCI device whose resources are to be reserved |
1586 | * @bar: BAR to be reserved | |
f5ddcac4 | 1587 | * @res_name: Name to be associated with resource |
e8de1481 | 1588 | * |
f5ddcac4 | 1589 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
1590 | * being reserved by owner @res_name. Do not access any |
1591 | * address inside the PCI regions unless this call returns | |
1592 | * successfully. | |
1593 | * | |
1594 | * Returns 0 on success, or %EBUSY on error. A warning | |
1595 | * message is also printed on failure. | |
1596 | */ | |
1597 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
1598 | { | |
1599 | return __pci_request_region(pdev, bar, res_name, 0); | |
1600 | } | |
1601 | ||
1602 | /** | |
1603 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
1604 | * @pdev: PCI device whose resources are to be reserved | |
1605 | * @bar: BAR to be reserved | |
1606 | * @res_name: Name to be associated with resource. | |
1607 | * | |
1608 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1609 | * being reserved by owner @res_name. Do not access any | |
1610 | * address inside the PCI regions unless this call returns | |
1611 | * successfully. | |
1612 | * | |
1613 | * Returns 0 on success, or %EBUSY on error. A warning | |
1614 | * message is also printed on failure. | |
1615 | * | |
1616 | * The key difference that _exclusive makes it that userspace is | |
1617 | * explicitly not allowed to map the resource via /dev/mem or | |
1618 | * sysfs. | |
1619 | */ | |
1620 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
1621 | { | |
1622 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
1623 | } | |
c87deff7 HS |
1624 | /** |
1625 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1626 | * @pdev: PCI device whose resources were previously reserved | |
1627 | * @bars: Bitmask of BARs to be released | |
1628 | * | |
1629 | * Release selected PCI I/O and memory resources previously reserved. | |
1630 | * Call this function only after all use of the PCI regions has ceased. | |
1631 | */ | |
1632 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1633 | { | |
1634 | int i; | |
1635 | ||
1636 | for (i = 0; i < 6; i++) | |
1637 | if (bars & (1 << i)) | |
1638 | pci_release_region(pdev, i); | |
1639 | } | |
1640 | ||
e8de1481 AV |
1641 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
1642 | const char *res_name, int excl) | |
c87deff7 HS |
1643 | { |
1644 | int i; | |
1645 | ||
1646 | for (i = 0; i < 6; i++) | |
1647 | if (bars & (1 << i)) | |
e8de1481 | 1648 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
1649 | goto err_out; |
1650 | return 0; | |
1651 | ||
1652 | err_out: | |
1653 | while(--i >= 0) | |
1654 | if (bars & (1 << i)) | |
1655 | pci_release_region(pdev, i); | |
1656 | ||
1657 | return -EBUSY; | |
1658 | } | |
1da177e4 | 1659 | |
e8de1481 AV |
1660 | |
1661 | /** | |
1662 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1663 | * @pdev: PCI device whose resources are to be reserved | |
1664 | * @bars: Bitmask of BARs to be requested | |
1665 | * @res_name: Name to be associated with resource | |
1666 | */ | |
1667 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1668 | const char *res_name) | |
1669 | { | |
1670 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
1671 | } | |
1672 | ||
1673 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
1674 | int bars, const char *res_name) | |
1675 | { | |
1676 | return __pci_request_selected_regions(pdev, bars, res_name, | |
1677 | IORESOURCE_EXCLUSIVE); | |
1678 | } | |
1679 | ||
1da177e4 LT |
1680 | /** |
1681 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1682 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1683 | * | |
1684 | * Releases all PCI I/O and memory resources previously reserved by a | |
1685 | * successful call to pci_request_regions. Call this function only | |
1686 | * after all use of the PCI regions has ceased. | |
1687 | */ | |
1688 | ||
1689 | void pci_release_regions(struct pci_dev *pdev) | |
1690 | { | |
c87deff7 | 1691 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1692 | } |
1693 | ||
1694 | /** | |
1695 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1696 | * @pdev: PCI device whose resources are to be reserved | |
1697 | * @res_name: Name to be associated with resource. | |
1698 | * | |
1699 | * Mark all PCI regions associated with PCI device @pdev as | |
1700 | * being reserved by owner @res_name. Do not access any | |
1701 | * address inside the PCI regions unless this call returns | |
1702 | * successfully. | |
1703 | * | |
1704 | * Returns 0 on success, or %EBUSY on error. A warning | |
1705 | * message is also printed on failure. | |
1706 | */ | |
3c990e92 | 1707 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1708 | { |
c87deff7 | 1709 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1710 | } |
1711 | ||
e8de1481 AV |
1712 | /** |
1713 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
1714 | * @pdev: PCI device whose resources are to be reserved | |
1715 | * @res_name: Name to be associated with resource. | |
1716 | * | |
1717 | * Mark all PCI regions associated with PCI device @pdev as | |
1718 | * being reserved by owner @res_name. Do not access any | |
1719 | * address inside the PCI regions unless this call returns | |
1720 | * successfully. | |
1721 | * | |
1722 | * pci_request_regions_exclusive() will mark the region so that | |
1723 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
1724 | * | |
1725 | * Returns 0 on success, or %EBUSY on error. A warning | |
1726 | * message is also printed on failure. | |
1727 | */ | |
1728 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
1729 | { | |
1730 | return pci_request_selected_regions_exclusive(pdev, | |
1731 | ((1 << 6) - 1), res_name); | |
1732 | } | |
1733 | ||
6a479079 BH |
1734 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
1735 | { | |
1736 | u16 old_cmd, cmd; | |
1737 | ||
1738 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
1739 | if (enable) | |
1740 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
1741 | else | |
1742 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
1743 | if (cmd != old_cmd) { | |
1744 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
1745 | enable ? "enabling" : "disabling"); | |
1746 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1747 | } | |
1748 | dev->is_busmaster = enable; | |
1749 | } | |
e8de1481 | 1750 | |
1da177e4 LT |
1751 | /** |
1752 | * pci_set_master - enables bus-mastering for device dev | |
1753 | * @dev: the PCI device to enable | |
1754 | * | |
1755 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1756 | * to do the needed arch specific settings. | |
1757 | */ | |
6a479079 | 1758 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 1759 | { |
6a479079 | 1760 | __pci_set_master(dev, true); |
1da177e4 LT |
1761 | pcibios_set_master(dev); |
1762 | } | |
1763 | ||
6a479079 BH |
1764 | /** |
1765 | * pci_clear_master - disables bus-mastering for device dev | |
1766 | * @dev: the PCI device to disable | |
1767 | */ | |
1768 | void pci_clear_master(struct pci_dev *dev) | |
1769 | { | |
1770 | __pci_set_master(dev, false); | |
1771 | } | |
1772 | ||
edb2d97e MW |
1773 | #ifdef PCI_DISABLE_MWI |
1774 | int pci_set_mwi(struct pci_dev *dev) | |
1775 | { | |
1776 | return 0; | |
1777 | } | |
1778 | ||
694625c0 RD |
1779 | int pci_try_set_mwi(struct pci_dev *dev) |
1780 | { | |
1781 | return 0; | |
1782 | } | |
1783 | ||
edb2d97e MW |
1784 | void pci_clear_mwi(struct pci_dev *dev) |
1785 | { | |
1786 | } | |
1787 | ||
1788 | #else | |
ebf5a248 MW |
1789 | |
1790 | #ifndef PCI_CACHE_LINE_BYTES | |
1791 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1792 | #endif | |
1793 | ||
1da177e4 | 1794 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1795 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1796 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1797 | |
1798 | /** | |
edb2d97e MW |
1799 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1800 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1801 | * |
edb2d97e MW |
1802 | * Helper function for pci_set_mwi. |
1803 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1804 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1805 | * | |
1806 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1807 | */ | |
1808 | static int | |
edb2d97e | 1809 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1810 | { |
1811 | u8 cacheline_size; | |
1812 | ||
1813 | if (!pci_cache_line_size) | |
1814 | return -EINVAL; /* The system doesn't support MWI. */ | |
1815 | ||
1816 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1817 | equal to or multiple of the right value. */ | |
1818 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1819 | if (cacheline_size >= pci_cache_line_size && | |
1820 | (cacheline_size % pci_cache_line_size) == 0) | |
1821 | return 0; | |
1822 | ||
1823 | /* Write the correct value. */ | |
1824 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1825 | /* Read it back. */ | |
1826 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1827 | if (cacheline_size == pci_cache_line_size) | |
1828 | return 0; | |
1829 | ||
80ccba11 BH |
1830 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1831 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1832 | |
1833 | return -EINVAL; | |
1834 | } | |
1da177e4 LT |
1835 | |
1836 | /** | |
1837 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1838 | * @dev: the PCI device for which MWI is enabled | |
1839 | * | |
694625c0 | 1840 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1841 | * |
1842 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1843 | */ | |
1844 | int | |
1845 | pci_set_mwi(struct pci_dev *dev) | |
1846 | { | |
1847 | int rc; | |
1848 | u16 cmd; | |
1849 | ||
edb2d97e | 1850 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1851 | if (rc) |
1852 | return rc; | |
1853 | ||
1854 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1855 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1856 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1857 | cmd |= PCI_COMMAND_INVALIDATE; |
1858 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1859 | } | |
1860 | ||
1861 | return 0; | |
1862 | } | |
1863 | ||
694625c0 RD |
1864 | /** |
1865 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1866 | * @dev: the PCI device for which MWI is enabled | |
1867 | * | |
1868 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1869 | * Callers are not required to check the return value. | |
1870 | * | |
1871 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1872 | */ | |
1873 | int pci_try_set_mwi(struct pci_dev *dev) | |
1874 | { | |
1875 | int rc = pci_set_mwi(dev); | |
1876 | return rc; | |
1877 | } | |
1878 | ||
1da177e4 LT |
1879 | /** |
1880 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1881 | * @dev: the PCI device to disable | |
1882 | * | |
1883 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1884 | */ | |
1885 | void | |
1886 | pci_clear_mwi(struct pci_dev *dev) | |
1887 | { | |
1888 | u16 cmd; | |
1889 | ||
1890 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1891 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1892 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1893 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1894 | } | |
1895 | } | |
edb2d97e | 1896 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1897 | |
a04ce0ff BR |
1898 | /** |
1899 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1900 | * @pdev: the PCI device to operate on |
1901 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1902 | * |
1903 | * Enables/disables PCI INTx for device dev | |
1904 | */ | |
1905 | void | |
1906 | pci_intx(struct pci_dev *pdev, int enable) | |
1907 | { | |
1908 | u16 pci_command, new; | |
1909 | ||
1910 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1911 | ||
1912 | if (enable) { | |
1913 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1914 | } else { | |
1915 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1916 | } | |
1917 | ||
1918 | if (new != pci_command) { | |
9ac7849e TH |
1919 | struct pci_devres *dr; |
1920 | ||
2fd9d74b | 1921 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1922 | |
1923 | dr = find_pci_dr(pdev); | |
1924 | if (dr && !dr->restore_intx) { | |
1925 | dr->restore_intx = 1; | |
1926 | dr->orig_intx = !enable; | |
1927 | } | |
a04ce0ff BR |
1928 | } |
1929 | } | |
1930 | ||
f5f2b131 EB |
1931 | /** |
1932 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1933 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1934 | * |
1935 | * If you want to use msi see pci_enable_msi and friends. | |
1936 | * This is a lower level primitive that allows us to disable | |
1937 | * msi operation at the device level. | |
1938 | */ | |
1939 | void pci_msi_off(struct pci_dev *dev) | |
1940 | { | |
1941 | int pos; | |
1942 | u16 control; | |
1943 | ||
1944 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1945 | if (pos) { | |
1946 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1947 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1948 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1949 | } | |
1950 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1951 | if (pos) { | |
1952 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1953 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1954 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1955 | } | |
1956 | } | |
1957 | ||
1da177e4 LT |
1958 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1959 | /* | |
1960 | * These can be overridden by arch-specific implementations | |
1961 | */ | |
1962 | int | |
1963 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1964 | { | |
1965 | if (!pci_dma_supported(dev, mask)) | |
1966 | return -EIO; | |
1967 | ||
1968 | dev->dma_mask = mask; | |
1969 | ||
1970 | return 0; | |
1971 | } | |
1972 | ||
1da177e4 LT |
1973 | int |
1974 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1975 | { | |
1976 | if (!pci_dma_supported(dev, mask)) | |
1977 | return -EIO; | |
1978 | ||
1979 | dev->dev.coherent_dma_mask = mask; | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | #endif | |
c87deff7 | 1984 | |
4d57cdfa FT |
1985 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1986 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1987 | { | |
1988 | return dma_set_max_seg_size(&dev->dev, size); | |
1989 | } | |
1990 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1991 | #endif | |
1992 | ||
59fc67de FT |
1993 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1994 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1995 | { | |
1996 | return dma_set_seg_boundary(&dev->dev, mask); | |
1997 | } | |
1998 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1999 | #endif | |
2000 | ||
d91cdc74 | 2001 | static int __pcie_flr(struct pci_dev *dev, int probe) |
8dd7f803 SY |
2002 | { |
2003 | u16 status; | |
2004 | u32 cap; | |
2005 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2006 | ||
2007 | if (!exppos) | |
2008 | return -ENOTTY; | |
2009 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); | |
2010 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
2011 | return -ENOTTY; | |
2012 | ||
d91cdc74 SY |
2013 | if (probe) |
2014 | return 0; | |
2015 | ||
8dd7f803 SY |
2016 | pci_block_user_cfg_access(dev); |
2017 | ||
2018 | /* Wait for Transaction Pending bit clean */ | |
2019 | msleep(100); | |
2020 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
2021 | if (status & PCI_EXP_DEVSTA_TRPND) { | |
2022 | dev_info(&dev->dev, "Busy after 100ms while trying to reset; " | |
2023 | "sleeping for 1 second\n"); | |
2024 | ssleep(1); | |
2025 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
2026 | if (status & PCI_EXP_DEVSTA_TRPND) | |
2027 | dev_info(&dev->dev, "Still busy after 1s; " | |
2028 | "proceeding with reset anyway\n"); | |
2029 | } | |
2030 | ||
2031 | pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL, | |
2032 | PCI_EXP_DEVCTL_BCR_FLR); | |
2033 | mdelay(100); | |
2034 | ||
2035 | pci_unblock_user_cfg_access(dev); | |
2036 | return 0; | |
2037 | } | |
d91cdc74 | 2038 | |
1ca88797 SY |
2039 | static int __pci_af_flr(struct pci_dev *dev, int probe) |
2040 | { | |
2041 | int cappos = pci_find_capability(dev, PCI_CAP_ID_AF); | |
2042 | u8 status; | |
2043 | u8 cap; | |
2044 | ||
2045 | if (!cappos) | |
2046 | return -ENOTTY; | |
2047 | pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap); | |
2048 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) | |
2049 | return -ENOTTY; | |
2050 | ||
2051 | if (probe) | |
2052 | return 0; | |
2053 | ||
2054 | pci_block_user_cfg_access(dev); | |
2055 | ||
2056 | /* Wait for Transaction Pending bit clean */ | |
2057 | msleep(100); | |
2058 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); | |
2059 | if (status & PCI_AF_STATUS_TP) { | |
2060 | dev_info(&dev->dev, "Busy after 100ms while trying to" | |
2061 | " reset; sleeping for 1 second\n"); | |
2062 | ssleep(1); | |
2063 | pci_read_config_byte(dev, | |
2064 | cappos + PCI_AF_STATUS, &status); | |
2065 | if (status & PCI_AF_STATUS_TP) | |
2066 | dev_info(&dev->dev, "Still busy after 1s; " | |
2067 | "proceeding with reset anyway\n"); | |
2068 | } | |
2069 | pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
2070 | mdelay(100); | |
2071 | ||
2072 | pci_unblock_user_cfg_access(dev); | |
2073 | return 0; | |
2074 | } | |
2075 | ||
d91cdc74 SY |
2076 | static int __pci_reset_function(struct pci_dev *pdev, int probe) |
2077 | { | |
2078 | int res; | |
2079 | ||
2080 | res = __pcie_flr(pdev, probe); | |
2081 | if (res != -ENOTTY) | |
2082 | return res; | |
2083 | ||
1ca88797 SY |
2084 | res = __pci_af_flr(pdev, probe); |
2085 | if (res != -ENOTTY) | |
2086 | return res; | |
2087 | ||
d91cdc74 SY |
2088 | return res; |
2089 | } | |
2090 | ||
2091 | /** | |
2092 | * pci_execute_reset_function() - Reset a PCI device function | |
2093 | * @dev: Device function to reset | |
2094 | * | |
2095 | * Some devices allow an individual function to be reset without affecting | |
2096 | * other functions in the same device. The PCI device must be responsive | |
2097 | * to PCI config space in order to use this function. | |
2098 | * | |
2099 | * The device function is presumed to be unused when this function is called. | |
2100 | * Resetting the device will make the contents of PCI configuration space | |
2101 | * random, so any caller of this must be prepared to reinitialise the | |
2102 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
2103 | * etc. | |
2104 | * | |
2105 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
2106 | * device doesn't support resetting a single function. | |
2107 | */ | |
2108 | int pci_execute_reset_function(struct pci_dev *dev) | |
2109 | { | |
2110 | return __pci_reset_function(dev, 0); | |
2111 | } | |
8dd7f803 SY |
2112 | EXPORT_SYMBOL_GPL(pci_execute_reset_function); |
2113 | ||
2114 | /** | |
2115 | * pci_reset_function() - quiesce and reset a PCI device function | |
2116 | * @dev: Device function to reset | |
2117 | * | |
2118 | * Some devices allow an individual function to be reset without affecting | |
2119 | * other functions in the same device. The PCI device must be responsive | |
2120 | * to PCI config space in order to use this function. | |
2121 | * | |
2122 | * This function does not just reset the PCI portion of a device, but | |
2123 | * clears all the state associated with the device. This function differs | |
2124 | * from pci_execute_reset_function in that it saves and restores device state | |
2125 | * over the reset. | |
2126 | * | |
2127 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
2128 | * device doesn't support resetting a single function. | |
2129 | */ | |
2130 | int pci_reset_function(struct pci_dev *dev) | |
2131 | { | |
d91cdc74 | 2132 | int r = __pci_reset_function(dev, 1); |
8dd7f803 | 2133 | |
d91cdc74 SY |
2134 | if (r < 0) |
2135 | return r; | |
8dd7f803 | 2136 | |
1df8fb3d | 2137 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
2138 | disable_irq(dev->irq); |
2139 | pci_save_state(dev); | |
2140 | ||
2141 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
2142 | ||
2143 | r = pci_execute_reset_function(dev); | |
2144 | ||
2145 | pci_restore_state(dev); | |
1df8fb3d | 2146 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
2147 | enable_irq(dev->irq); |
2148 | ||
2149 | return r; | |
2150 | } | |
2151 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
2152 | ||
d556ad4b PO |
2153 | /** |
2154 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
2155 | * @dev: PCI device to query | |
2156 | * | |
2157 | * Returns mmrbc: maximum designed memory read count in bytes | |
2158 | * or appropriate error value. | |
2159 | */ | |
2160 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
2161 | { | |
b7b095c1 | 2162 | int err, cap; |
d556ad4b PO |
2163 | u32 stat; |
2164 | ||
2165 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2166 | if (!cap) | |
2167 | return -EINVAL; | |
2168 | ||
2169 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2170 | if (err) | |
2171 | return -EINVAL; | |
2172 | ||
b7b095c1 | 2173 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
2174 | } |
2175 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
2176 | ||
2177 | /** | |
2178 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
2179 | * @dev: PCI device to query | |
2180 | * | |
2181 | * Returns mmrbc: maximum memory read count in bytes | |
2182 | * or appropriate error value. | |
2183 | */ | |
2184 | int pcix_get_mmrbc(struct pci_dev *dev) | |
2185 | { | |
2186 | int ret, cap; | |
2187 | u32 cmd; | |
2188 | ||
2189 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2190 | if (!cap) | |
2191 | return -EINVAL; | |
2192 | ||
2193 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2194 | if (!ret) | |
2195 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
2196 | ||
2197 | return ret; | |
2198 | } | |
2199 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
2200 | ||
2201 | /** | |
2202 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
2203 | * @dev: PCI device to query | |
2204 | * @mmrbc: maximum memory read count in bytes | |
2205 | * valid values are 512, 1024, 2048, 4096 | |
2206 | * | |
2207 | * If possible sets maximum memory read byte count, some bridges have erratas | |
2208 | * that prevent this. | |
2209 | */ | |
2210 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
2211 | { | |
2212 | int cap, err = -EINVAL; | |
2213 | u32 stat, cmd, v, o; | |
2214 | ||
229f5afd | 2215 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
2216 | goto out; |
2217 | ||
2218 | v = ffs(mmrbc) - 10; | |
2219 | ||
2220 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2221 | if (!cap) | |
2222 | goto out; | |
2223 | ||
2224 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2225 | if (err) | |
2226 | goto out; | |
2227 | ||
2228 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
2229 | return -E2BIG; | |
2230 | ||
2231 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2232 | if (err) | |
2233 | goto out; | |
2234 | ||
2235 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
2236 | if (o != v) { | |
2237 | if (v > o && dev->bus && | |
2238 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
2239 | return -EIO; | |
2240 | ||
2241 | cmd &= ~PCI_X_CMD_MAX_READ; | |
2242 | cmd |= v << 2; | |
2243 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
2244 | } | |
2245 | out: | |
2246 | return err; | |
2247 | } | |
2248 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
2249 | ||
2250 | /** | |
2251 | * pcie_get_readrq - get PCI Express read request size | |
2252 | * @dev: PCI device to query | |
2253 | * | |
2254 | * Returns maximum memory read request in bytes | |
2255 | * or appropriate error value. | |
2256 | */ | |
2257 | int pcie_get_readrq(struct pci_dev *dev) | |
2258 | { | |
2259 | int ret, cap; | |
2260 | u16 ctl; | |
2261 | ||
2262 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2263 | if (!cap) | |
2264 | return -EINVAL; | |
2265 | ||
2266 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2267 | if (!ret) | |
2268 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
2269 | ||
2270 | return ret; | |
2271 | } | |
2272 | EXPORT_SYMBOL(pcie_get_readrq); | |
2273 | ||
2274 | /** | |
2275 | * pcie_set_readrq - set PCI Express maximum memory read request | |
2276 | * @dev: PCI device to query | |
42e61f4a | 2277 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
2278 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
2279 | * | |
2280 | * If possible sets maximum read byte count | |
2281 | */ | |
2282 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
2283 | { | |
2284 | int cap, err = -EINVAL; | |
2285 | u16 ctl, v; | |
2286 | ||
229f5afd | 2287 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
2288 | goto out; |
2289 | ||
2290 | v = (ffs(rq) - 8) << 12; | |
2291 | ||
2292 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2293 | if (!cap) | |
2294 | goto out; | |
2295 | ||
2296 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2297 | if (err) | |
2298 | goto out; | |
2299 | ||
2300 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
2301 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
2302 | ctl |= v; | |
2303 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
2304 | } | |
2305 | ||
2306 | out: | |
2307 | return err; | |
2308 | } | |
2309 | EXPORT_SYMBOL(pcie_set_readrq); | |
2310 | ||
c87deff7 HS |
2311 | /** |
2312 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 2313 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
2314 | * @flags: resource type mask to be selected |
2315 | * | |
2316 | * This helper routine makes bar mask from the type of resource. | |
2317 | */ | |
2318 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
2319 | { | |
2320 | int i, bars = 0; | |
2321 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
2322 | if (pci_resource_flags(dev, i) & flags) | |
2323 | bars |= (1 << i); | |
2324 | return bars; | |
2325 | } | |
2326 | ||
613e7ed6 YZ |
2327 | /** |
2328 | * pci_resource_bar - get position of the BAR associated with a resource | |
2329 | * @dev: the PCI device | |
2330 | * @resno: the resource number | |
2331 | * @type: the BAR type to be filled in | |
2332 | * | |
2333 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
2334 | */ | |
2335 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
2336 | { | |
2337 | if (resno < PCI_ROM_RESOURCE) { | |
2338 | *type = pci_bar_unknown; | |
2339 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
2340 | } else if (resno == PCI_ROM_RESOURCE) { | |
2341 | *type = pci_bar_mem32; | |
2342 | return dev->rom_base_reg; | |
2343 | } | |
2344 | ||
2345 | dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno); | |
2346 | return 0; | |
2347 | } | |
2348 | ||
32a2eea7 JG |
2349 | static void __devinit pci_no_domains(void) |
2350 | { | |
2351 | #ifdef CONFIG_PCI_DOMAINS | |
2352 | pci_domains_supported = 0; | |
2353 | #endif | |
2354 | } | |
2355 | ||
0ef5f8f6 AP |
2356 | /** |
2357 | * pci_ext_cfg_enabled - can we access extended PCI config space? | |
2358 | * @dev: The PCI device of the root bridge. | |
2359 | * | |
2360 | * Returns 1 if we can access PCI extended config space (offsets | |
2361 | * greater than 0xff). This is the default implementation. Architecture | |
2362 | * implementations can override this. | |
2363 | */ | |
2364 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) | |
2365 | { | |
2366 | return 1; | |
2367 | } | |
2368 | ||
1da177e4 LT |
2369 | static int __devinit pci_init(void) |
2370 | { | |
2371 | struct pci_dev *dev = NULL; | |
2372 | ||
2373 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2374 | pci_fixup_device(pci_fixup_final, dev); | |
2375 | } | |
d389fec6 | 2376 | |
1da177e4 LT |
2377 | return 0; |
2378 | } | |
2379 | ||
ad04d31e | 2380 | static int __init pci_setup(char *str) |
1da177e4 LT |
2381 | { |
2382 | while (str) { | |
2383 | char *k = strchr(str, ','); | |
2384 | if (k) | |
2385 | *k++ = 0; | |
2386 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
2387 | if (!strcmp(str, "nomsi")) { |
2388 | pci_no_msi(); | |
7f785763 RD |
2389 | } else if (!strcmp(str, "noaer")) { |
2390 | pci_no_aer(); | |
32a2eea7 JG |
2391 | } else if (!strcmp(str, "nodomains")) { |
2392 | pci_no_domains(); | |
4516a618 AN |
2393 | } else if (!strncmp(str, "cbiosize=", 9)) { |
2394 | pci_cardbus_io_size = memparse(str + 9, &str); | |
2395 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
2396 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
2397 | } else { |
2398 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
2399 | str); | |
2400 | } | |
1da177e4 LT |
2401 | } |
2402 | str = k; | |
2403 | } | |
0637a70a | 2404 | return 0; |
1da177e4 | 2405 | } |
0637a70a | 2406 | early_param("pci", pci_setup); |
1da177e4 LT |
2407 | |
2408 | device_initcall(pci_init); | |
1da177e4 | 2409 | |
0b62e13b | 2410 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
2411 | EXPORT_SYMBOL(pci_enable_device_io); |
2412 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 2413 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
2414 | EXPORT_SYMBOL(pcim_enable_device); |
2415 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 2416 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
2417 | EXPORT_SYMBOL(pci_find_capability); |
2418 | EXPORT_SYMBOL(pci_bus_find_capability); | |
2419 | EXPORT_SYMBOL(pci_release_regions); | |
2420 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 2421 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
2422 | EXPORT_SYMBOL(pci_release_region); |
2423 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 2424 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
2425 | EXPORT_SYMBOL(pci_release_selected_regions); |
2426 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 2427 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 2428 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 2429 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 2430 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 2431 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 2432 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 2433 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 2434 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
2435 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
2436 | EXPORT_SYMBOL(pci_assign_resource); | |
2437 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 2438 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
2439 | |
2440 | EXPORT_SYMBOL(pci_set_power_state); | |
2441 | EXPORT_SYMBOL(pci_save_state); | |
2442 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 2443 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 2444 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 2445 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 2446 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 2447 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
2448 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
2449 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 2450 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 2451 |