Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
1da177e4 | 21 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 22 | #include "pci.h" |
1da177e4 | 23 | |
ffadcc2f | 24 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 25 | |
32a2eea7 JG |
26 | #ifdef CONFIG_PCI_DOMAINS |
27 | int pci_domains_supported = 1; | |
28 | #endif | |
29 | ||
4516a618 AN |
30 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
31 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
32 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
33 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
34 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
35 | ||
1da177e4 LT |
36 | /** |
37 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
38 | * @bus: pointer to PCI bus structure to search | |
39 | * | |
40 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
41 | * including the given PCI bus and its list of child PCI buses. | |
42 | */ | |
96bde06a | 43 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
44 | { |
45 | struct list_head *tmp; | |
46 | unsigned char max, n; | |
47 | ||
b82db5ce | 48 | max = bus->subordinate; |
1da177e4 LT |
49 | list_for_each(tmp, &bus->children) { |
50 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
51 | if(n > max) | |
52 | max = n; | |
53 | } | |
54 | return max; | |
55 | } | |
b82db5ce | 56 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 57 | |
b82db5ce | 58 | #if 0 |
1da177e4 LT |
59 | /** |
60 | * pci_max_busnr - returns maximum PCI bus number | |
61 | * | |
62 | * Returns the highest PCI bus number present in the system global list of | |
63 | * PCI buses. | |
64 | */ | |
65 | unsigned char __devinit | |
66 | pci_max_busnr(void) | |
67 | { | |
68 | struct pci_bus *bus = NULL; | |
69 | unsigned char max, n; | |
70 | ||
71 | max = 0; | |
72 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
73 | n = pci_bus_max_busnr(bus); | |
74 | if(n > max) | |
75 | max = n; | |
76 | } | |
77 | return max; | |
78 | } | |
79 | ||
54c762fe AB |
80 | #endif /* 0 */ |
81 | ||
687d5fe3 ME |
82 | #define PCI_FIND_CAP_TTL 48 |
83 | ||
84 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
85 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
86 | { |
87 | u8 id; | |
24a4e377 | 88 | |
687d5fe3 | 89 | while ((*ttl)--) { |
24a4e377 RD |
90 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
91 | if (pos < 0x40) | |
92 | break; | |
93 | pos &= ~3; | |
94 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
95 | &id); | |
96 | if (id == 0xff) | |
97 | break; | |
98 | if (id == cap) | |
99 | return pos; | |
100 | pos += PCI_CAP_LIST_NEXT; | |
101 | } | |
102 | return 0; | |
103 | } | |
104 | ||
687d5fe3 ME |
105 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
106 | u8 pos, int cap) | |
107 | { | |
108 | int ttl = PCI_FIND_CAP_TTL; | |
109 | ||
110 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
111 | } | |
112 | ||
24a4e377 RD |
113 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
114 | { | |
115 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
116 | pos + PCI_CAP_LIST_NEXT, cap); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
119 | ||
d3bac118 ME |
120 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
121 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
122 | { |
123 | u16 status; | |
1da177e4 LT |
124 | |
125 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
126 | if (!(status & PCI_STATUS_CAP_LIST)) | |
127 | return 0; | |
128 | ||
129 | switch (hdr_type) { | |
130 | case PCI_HEADER_TYPE_NORMAL: | |
131 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 132 | return PCI_CAPABILITY_LIST; |
1da177e4 | 133 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 134 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
135 | default: |
136 | return 0; | |
137 | } | |
d3bac118 ME |
138 | |
139 | return 0; | |
1da177e4 LT |
140 | } |
141 | ||
142 | /** | |
143 | * pci_find_capability - query for devices' capabilities | |
144 | * @dev: PCI device to query | |
145 | * @cap: capability code | |
146 | * | |
147 | * Tell if a device supports a given PCI capability. | |
148 | * Returns the address of the requested capability structure within the | |
149 | * device's PCI configuration space or 0 in case the device does not | |
150 | * support it. Possible values for @cap: | |
151 | * | |
152 | * %PCI_CAP_ID_PM Power Management | |
153 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
154 | * %PCI_CAP_ID_VPD Vital Product Data | |
155 | * %PCI_CAP_ID_SLOTID Slot Identification | |
156 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
157 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
158 | * %PCI_CAP_ID_PCIX PCI-X | |
159 | * %PCI_CAP_ID_EXP PCI Express | |
160 | */ | |
161 | int pci_find_capability(struct pci_dev *dev, int cap) | |
162 | { | |
d3bac118 ME |
163 | int pos; |
164 | ||
165 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
166 | if (pos) | |
167 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
168 | ||
169 | return pos; | |
1da177e4 LT |
170 | } |
171 | ||
172 | /** | |
173 | * pci_bus_find_capability - query for devices' capabilities | |
174 | * @bus: the PCI bus to query | |
175 | * @devfn: PCI device to query | |
176 | * @cap: capability code | |
177 | * | |
178 | * Like pci_find_capability() but works for pci devices that do not have a | |
179 | * pci_dev structure set up yet. | |
180 | * | |
181 | * Returns the address of the requested capability structure within the | |
182 | * device's PCI configuration space or 0 in case the device does not | |
183 | * support it. | |
184 | */ | |
185 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
186 | { | |
d3bac118 | 187 | int pos; |
1da177e4 LT |
188 | u8 hdr_type; |
189 | ||
190 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
191 | ||
d3bac118 ME |
192 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
193 | if (pos) | |
194 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
195 | ||
196 | return pos; | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
200 | * pci_find_ext_capability - Find an extended capability | |
201 | * @dev: PCI device to query | |
202 | * @cap: capability code | |
203 | * | |
204 | * Returns the address of the requested extended capability structure | |
205 | * within the device's PCI configuration space or 0 if the device does | |
206 | * not support it. Possible values for @cap: | |
207 | * | |
208 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
209 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
210 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
211 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
212 | */ | |
213 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
214 | { | |
215 | u32 header; | |
557848c3 ZY |
216 | int ttl; |
217 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 218 | |
557848c3 ZY |
219 | /* minimum 8 bytes per capability */ |
220 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
221 | ||
222 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
223 | return 0; |
224 | ||
225 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
226 | return 0; | |
227 | ||
228 | /* | |
229 | * If we have no capabilities, this is indicated by cap ID, | |
230 | * cap version and next pointer all being 0. | |
231 | */ | |
232 | if (header == 0) | |
233 | return 0; | |
234 | ||
235 | while (ttl-- > 0) { | |
236 | if (PCI_EXT_CAP_ID(header) == cap) | |
237 | return pos; | |
238 | ||
239 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 240 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
241 | break; |
242 | ||
243 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
244 | break; | |
245 | } | |
246 | ||
247 | return 0; | |
248 | } | |
3a720d72 | 249 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 250 | |
687d5fe3 ME |
251 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
252 | { | |
253 | int rc, ttl = PCI_FIND_CAP_TTL; | |
254 | u8 cap, mask; | |
255 | ||
256 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
257 | mask = HT_3BIT_CAP_MASK; | |
258 | else | |
259 | mask = HT_5BIT_CAP_MASK; | |
260 | ||
261 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
262 | PCI_CAP_ID_HT, &ttl); | |
263 | while (pos) { | |
264 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
265 | if (rc != PCIBIOS_SUCCESSFUL) | |
266 | return 0; | |
267 | ||
268 | if ((cap & mask) == ht_cap) | |
269 | return pos; | |
270 | ||
47a4d5be BG |
271 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
272 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
273 | PCI_CAP_ID_HT, &ttl); |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | /** | |
279 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
280 | * @dev: PCI device to query | |
281 | * @pos: Position from which to continue searching | |
282 | * @ht_cap: Hypertransport capability code | |
283 | * | |
284 | * To be used in conjunction with pci_find_ht_capability() to search for | |
285 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
286 | * from pci_find_ht_capability(). | |
287 | * | |
288 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
289 | * steps to avoid an infinite loop. | |
290 | */ | |
291 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
292 | { | |
293 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
294 | } | |
295 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
296 | ||
297 | /** | |
298 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
299 | * @dev: PCI device to query | |
300 | * @ht_cap: Hypertransport capability code | |
301 | * | |
302 | * Tell if a device supports a given Hypertransport capability. | |
303 | * Returns an address within the device's PCI configuration space | |
304 | * or 0 in case the device does not support the request capability. | |
305 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
306 | * which has a Hypertransport capability matching @ht_cap. | |
307 | */ | |
308 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
309 | { | |
310 | int pos; | |
311 | ||
312 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
313 | if (pos) | |
314 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
315 | ||
316 | return pos; | |
317 | } | |
318 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
319 | ||
1da177e4 LT |
320 | /** |
321 | * pci_find_parent_resource - return resource region of parent bus of given region | |
322 | * @dev: PCI device structure contains resources to be searched | |
323 | * @res: child resource record for which parent is sought | |
324 | * | |
325 | * For given resource region of given device, return the resource | |
326 | * region of parent bus the given region is contained in or where | |
327 | * it should be allocated from. | |
328 | */ | |
329 | struct resource * | |
330 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
331 | { | |
332 | const struct pci_bus *bus = dev->bus; | |
333 | int i; | |
334 | struct resource *best = NULL; | |
335 | ||
336 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
337 | struct resource *r = bus->resource[i]; | |
338 | if (!r) | |
339 | continue; | |
340 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
341 | continue; /* Not contained */ | |
342 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
343 | continue; /* Wrong type */ | |
344 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
345 | return r; /* Exact match */ | |
346 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
347 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
348 | } | |
349 | return best; | |
350 | } | |
351 | ||
064b53db JL |
352 | /** |
353 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
354 | * @dev: PCI device to have its BARs restored | |
355 | * | |
356 | * Restore the BAR values for a given device, so as to make it | |
357 | * accessible by its driver. | |
358 | */ | |
ad668599 | 359 | static void |
064b53db JL |
360 | pci_restore_bars(struct pci_dev *dev) |
361 | { | |
362 | int i, numres; | |
363 | ||
364 | switch (dev->hdr_type) { | |
365 | case PCI_HEADER_TYPE_NORMAL: | |
366 | numres = 6; | |
367 | break; | |
368 | case PCI_HEADER_TYPE_BRIDGE: | |
369 | numres = 2; | |
370 | break; | |
371 | case PCI_HEADER_TYPE_CARDBUS: | |
372 | numres = 1; | |
373 | break; | |
374 | default: | |
375 | /* Should never get here, but just in case... */ | |
376 | return; | |
377 | } | |
378 | ||
379 | for (i = 0; i < numres; i ++) | |
380 | pci_update_resource(dev, &dev->resource[i], i); | |
381 | } | |
382 | ||
961d9120 RW |
383 | static struct pci_platform_pm_ops *pci_platform_pm; |
384 | ||
385 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
386 | { | |
eb9d0fe4 RW |
387 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
388 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
389 | return -EINVAL; |
390 | pci_platform_pm = ops; | |
391 | return 0; | |
392 | } | |
393 | ||
394 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
395 | { | |
396 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
397 | } | |
398 | ||
399 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
400 | pci_power_t t) | |
401 | { | |
402 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
403 | } | |
404 | ||
405 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
406 | { | |
407 | return pci_platform_pm ? | |
408 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
409 | } | |
8f7020d3 | 410 | |
eb9d0fe4 RW |
411 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
412 | { | |
413 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
414 | } | |
415 | ||
416 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
417 | { | |
418 | return pci_platform_pm ? | |
419 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
420 | } | |
421 | ||
1da177e4 | 422 | /** |
44e4e66e RW |
423 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
424 | * given PCI device | |
425 | * @dev: PCI device to handle. | |
44e4e66e | 426 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 427 | * |
44e4e66e RW |
428 | * RETURN VALUE: |
429 | * -EINVAL if the requested state is invalid. | |
430 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
431 | * wrong version, or device doesn't support the requested state. | |
432 | * 0 if device already is in the requested state. | |
433 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 434 | */ |
44e4e66e | 435 | static int |
337001b6 | 436 | pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 437 | { |
337001b6 | 438 | u16 pmcsr; |
44e4e66e | 439 | bool need_restore = false; |
1da177e4 | 440 | |
337001b6 | 441 | if (!dev->pm_cap) |
cca03dec AL |
442 | return -EIO; |
443 | ||
44e4e66e RW |
444 | if (state < PCI_D0 || state > PCI_D3hot) |
445 | return -EINVAL; | |
446 | ||
1da177e4 LT |
447 | /* Validate current state: |
448 | * Can enter D0 from any state, but if we can only go deeper | |
449 | * to sleep if we're already in a low power state | |
450 | */ | |
44e4e66e RW |
451 | if (dev->current_state == state) { |
452 | /* we're already there */ | |
453 | return 0; | |
454 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
455 | && dev->current_state > state) { | |
80ccba11 BH |
456 | dev_err(&dev->dev, "invalid power transition " |
457 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 458 | return -EINVAL; |
44e4e66e | 459 | } |
1da177e4 | 460 | |
1da177e4 | 461 | /* check if this device supports the desired state */ |
337001b6 RW |
462 | if ((state == PCI_D1 && !dev->d1_support) |
463 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 464 | return -EIO; |
1da177e4 | 465 | |
337001b6 | 466 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 467 | |
32a36585 | 468 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
469 | * This doesn't affect PME_Status, disables PME_En, and |
470 | * sets PowerState to 0. | |
471 | */ | |
32a36585 | 472 | switch (dev->current_state) { |
d3535fbb JL |
473 | case PCI_D0: |
474 | case PCI_D1: | |
475 | case PCI_D2: | |
476 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
477 | pmcsr |= state; | |
478 | break; | |
32a36585 JL |
479 | case PCI_UNKNOWN: /* Boot-up */ |
480 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
481 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 482 | need_restore = true; |
32a36585 | 483 | /* Fall-through: force to D0 */ |
32a36585 | 484 | default: |
d3535fbb | 485 | pmcsr = 0; |
32a36585 | 486 | break; |
1da177e4 LT |
487 | } |
488 | ||
489 | /* enter specified state */ | |
337001b6 | 490 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
491 | |
492 | /* Mandatory power management transition delays */ | |
493 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
494 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 495 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
496 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
497 | udelay(200); | |
1da177e4 | 498 | |
b913100d | 499 | dev->current_state = state; |
064b53db JL |
500 | |
501 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
502 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
503 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
504 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
505 | * For example, at least some versions of the 3c905B and the | |
506 | * 3c556B exhibit this behaviour. | |
507 | * | |
508 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
509 | * devices in a D3hot state at boot. Consequently, we need to | |
510 | * restore at least the BARs so that the device will be | |
511 | * accessible to its driver. | |
512 | */ | |
513 | if (need_restore) | |
514 | pci_restore_bars(dev); | |
515 | ||
7d715a6c SL |
516 | if (dev->bus->self) |
517 | pcie_aspm_pm_state_change(dev->bus->self); | |
518 | ||
1da177e4 LT |
519 | return 0; |
520 | } | |
521 | ||
44e4e66e RW |
522 | /** |
523 | * pci_update_current_state - Read PCI power state of given device from its | |
524 | * PCI PM registers and cache it | |
525 | * @dev: PCI device to handle. | |
44e4e66e | 526 | */ |
337001b6 | 527 | static void pci_update_current_state(struct pci_dev *dev) |
44e4e66e | 528 | { |
337001b6 | 529 | if (dev->pm_cap) { |
44e4e66e RW |
530 | u16 pmcsr; |
531 | ||
337001b6 | 532 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e RW |
533 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
534 | } | |
535 | } | |
536 | ||
537 | /** | |
538 | * pci_set_power_state - Set the power state of a PCI device | |
539 | * @dev: PCI device to handle. | |
540 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
541 | * | |
542 | * Transition a device to a new power state, using the platform formware and/or | |
543 | * the device's PCI PM registers. | |
544 | * | |
545 | * RETURN VALUE: | |
546 | * -EINVAL if the requested state is invalid. | |
547 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
548 | * wrong version, or device doesn't support the requested state. | |
549 | * 0 if device already is in the requested state. | |
550 | * 0 if device's power state has been successfully changed. | |
551 | */ | |
552 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
553 | { | |
337001b6 | 554 | int error; |
44e4e66e RW |
555 | |
556 | /* bound the state we're entering */ | |
557 | if (state > PCI_D3hot) | |
558 | state = PCI_D3hot; | |
559 | else if (state < PCI_D0) | |
560 | state = PCI_D0; | |
561 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
562 | /* | |
563 | * If the device or the parent bridge do not support PCI PM, | |
564 | * ignore the request if we're doing anything other than putting | |
565 | * it into D0 (which would only happen on boot). | |
566 | */ | |
567 | return 0; | |
568 | ||
44e4e66e RW |
569 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { |
570 | /* | |
571 | * Allow the platform to change the state, for example via ACPI | |
572 | * _PR0, _PS0 and some such, but do not trust it. | |
573 | */ | |
574 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
575 | if (!ret) | |
337001b6 | 576 | pci_update_current_state(dev); |
44e4e66e | 577 | } |
979b1791 AC |
578 | /* This device is quirked not to be put into D3, so |
579 | don't put it in D3 */ | |
580 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
581 | return 0; | |
44e4e66e | 582 | |
337001b6 | 583 | error = pci_raw_set_power_state(dev, state); |
44e4e66e RW |
584 | |
585 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
586 | /* Allow the platform to finalize the transition */ | |
587 | int ret = platform_pci_set_power_state(dev, state); | |
588 | if (!ret) { | |
337001b6 | 589 | pci_update_current_state(dev); |
44e4e66e RW |
590 | error = 0; |
591 | } | |
592 | } | |
593 | ||
594 | return error; | |
595 | } | |
596 | ||
1da177e4 LT |
597 | /** |
598 | * pci_choose_state - Choose the power state of a PCI device | |
599 | * @dev: PCI device to be suspended | |
600 | * @state: target sleep state for the whole system. This is the value | |
601 | * that is passed to suspend() function. | |
602 | * | |
603 | * Returns PCI power state suitable for given device and given system | |
604 | * message. | |
605 | */ | |
606 | ||
607 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
608 | { | |
ab826ca4 | 609 | pci_power_t ret; |
0f64474b | 610 | |
1da177e4 LT |
611 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
612 | return PCI_D0; | |
613 | ||
961d9120 RW |
614 | ret = platform_pci_choose_state(dev); |
615 | if (ret != PCI_POWER_ERROR) | |
616 | return ret; | |
ca078bae PM |
617 | |
618 | switch (state.event) { | |
619 | case PM_EVENT_ON: | |
620 | return PCI_D0; | |
621 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
622 | case PM_EVENT_PRETHAW: |
623 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 624 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 625 | case PM_EVENT_HIBERNATE: |
ca078bae | 626 | return PCI_D3hot; |
1da177e4 | 627 | default: |
80ccba11 BH |
628 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
629 | state.event); | |
1da177e4 LT |
630 | BUG(); |
631 | } | |
632 | return PCI_D0; | |
633 | } | |
634 | ||
635 | EXPORT_SYMBOL(pci_choose_state); | |
636 | ||
b56a5a23 MT |
637 | static int pci_save_pcie_state(struct pci_dev *dev) |
638 | { | |
639 | int pos, i = 0; | |
640 | struct pci_cap_saved_state *save_state; | |
641 | u16 *cap; | |
017fc480 | 642 | int found = 0; |
b56a5a23 MT |
643 | |
644 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
645 | if (pos <= 0) | |
646 | return 0; | |
647 | ||
9f35575d EB |
648 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
649 | if (!save_state) | |
650 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
651 | else |
652 | found = 1; | |
b56a5a23 | 653 | if (!save_state) { |
80ccba11 | 654 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
b56a5a23 MT |
655 | return -ENOMEM; |
656 | } | |
657 | cap = (u16 *)&save_state->data[0]; | |
658 | ||
659 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
660 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
661 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
662 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 663 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
664 | if (!found) |
665 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
666 | return 0; |
667 | } | |
668 | ||
669 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
670 | { | |
671 | int i = 0, pos; | |
672 | struct pci_cap_saved_state *save_state; | |
673 | u16 *cap; | |
674 | ||
675 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
676 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
677 | if (!save_state || pos <= 0) | |
678 | return; | |
679 | cap = (u16 *)&save_state->data[0]; | |
680 | ||
681 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
682 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
683 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
684 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
685 | } |
686 | ||
cc692a5f SH |
687 | |
688 | static int pci_save_pcix_state(struct pci_dev *dev) | |
689 | { | |
690 | int pos, i = 0; | |
691 | struct pci_cap_saved_state *save_state; | |
692 | u16 *cap; | |
017fc480 | 693 | int found = 0; |
cc692a5f SH |
694 | |
695 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
696 | if (pos <= 0) | |
697 | return 0; | |
698 | ||
f34303de | 699 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
700 | if (!save_state) |
701 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
702 | else |
703 | found = 1; | |
cc692a5f | 704 | if (!save_state) { |
80ccba11 | 705 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
cc692a5f SH |
706 | return -ENOMEM; |
707 | } | |
708 | cap = (u16 *)&save_state->data[0]; | |
709 | ||
710 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 711 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
712 | if (!found) |
713 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
714 | return 0; |
715 | } | |
716 | ||
717 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
718 | { | |
719 | int i = 0, pos; | |
720 | struct pci_cap_saved_state *save_state; | |
721 | u16 *cap; | |
722 | ||
723 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
724 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
725 | if (!save_state || pos <= 0) | |
726 | return; | |
727 | cap = (u16 *)&save_state->data[0]; | |
728 | ||
729 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
730 | } |
731 | ||
732 | ||
1da177e4 LT |
733 | /** |
734 | * pci_save_state - save the PCI configuration space of a device before suspending | |
735 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
736 | */ |
737 | int | |
738 | pci_save_state(struct pci_dev *dev) | |
739 | { | |
740 | int i; | |
741 | /* XXX: 100% dword access ok here? */ | |
742 | for (i = 0; i < 16; i++) | |
743 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
744 | if ((i = pci_save_pcie_state(dev)) != 0) |
745 | return i; | |
cc692a5f SH |
746 | if ((i = pci_save_pcix_state(dev)) != 0) |
747 | return i; | |
1da177e4 LT |
748 | return 0; |
749 | } | |
750 | ||
751 | /** | |
752 | * pci_restore_state - Restore the saved state of a PCI device | |
753 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
754 | */ |
755 | int | |
756 | pci_restore_state(struct pci_dev *dev) | |
757 | { | |
758 | int i; | |
b4482a4b | 759 | u32 val; |
1da177e4 | 760 | |
b56a5a23 MT |
761 | /* PCI Express register must be restored first */ |
762 | pci_restore_pcie_state(dev); | |
763 | ||
8b8c8d28 YL |
764 | /* |
765 | * The Base Address register should be programmed before the command | |
766 | * register(s) | |
767 | */ | |
768 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
769 | pci_read_config_dword(dev, i * 4, &val); |
770 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
771 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
772 | "space at offset %#x (was %#x, writing %#x)\n", | |
773 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
774 | pci_write_config_dword(dev,i * 4, |
775 | dev->saved_config_space[i]); | |
776 | } | |
777 | } | |
cc692a5f | 778 | pci_restore_pcix_state(dev); |
41017f0c | 779 | pci_restore_msi_state(dev); |
8fed4b65 | 780 | |
1da177e4 LT |
781 | return 0; |
782 | } | |
783 | ||
38cc1302 HS |
784 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
785 | { | |
786 | int err; | |
787 | ||
788 | err = pci_set_power_state(dev, PCI_D0); | |
789 | if (err < 0 && err != -EIO) | |
790 | return err; | |
791 | err = pcibios_enable_device(dev, bars); | |
792 | if (err < 0) | |
793 | return err; | |
794 | pci_fixup_device(pci_fixup_enable, dev); | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | /** | |
0b62e13b | 800 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
801 | * @dev: PCI device to be resumed |
802 | * | |
803 | * Note this function is a backend of pci_default_resume and is not supposed | |
804 | * to be called by normal code, write proper resume handler and use it instead. | |
805 | */ | |
0b62e13b | 806 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
807 | { |
808 | if (atomic_read(&dev->enable_cnt)) | |
809 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
810 | return 0; | |
811 | } | |
812 | ||
b718989d BH |
813 | static int __pci_enable_device_flags(struct pci_dev *dev, |
814 | resource_size_t flags) | |
1da177e4 LT |
815 | { |
816 | int err; | |
b718989d | 817 | int i, bars = 0; |
1da177e4 | 818 | |
9fb625c3 HS |
819 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
820 | return 0; /* already enabled */ | |
821 | ||
b718989d BH |
822 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
823 | if (dev->resource[i].flags & flags) | |
824 | bars |= (1 << i); | |
825 | ||
38cc1302 | 826 | err = do_pci_enable_device(dev, bars); |
95a62965 | 827 | if (err < 0) |
38cc1302 | 828 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 829 | return err; |
1da177e4 LT |
830 | } |
831 | ||
b718989d BH |
832 | /** |
833 | * pci_enable_device_io - Initialize a device for use with IO space | |
834 | * @dev: PCI device to be initialized | |
835 | * | |
836 | * Initialize device before it's used by a driver. Ask low-level code | |
837 | * to enable I/O resources. Wake up the device if it was suspended. | |
838 | * Beware, this function can fail. | |
839 | */ | |
840 | int pci_enable_device_io(struct pci_dev *dev) | |
841 | { | |
842 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
843 | } | |
844 | ||
845 | /** | |
846 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
847 | * @dev: PCI device to be initialized | |
848 | * | |
849 | * Initialize device before it's used by a driver. Ask low-level code | |
850 | * to enable Memory resources. Wake up the device if it was suspended. | |
851 | * Beware, this function can fail. | |
852 | */ | |
853 | int pci_enable_device_mem(struct pci_dev *dev) | |
854 | { | |
855 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
856 | } | |
857 | ||
bae94d02 IPG |
858 | /** |
859 | * pci_enable_device - Initialize device before it's used by a driver. | |
860 | * @dev: PCI device to be initialized | |
861 | * | |
862 | * Initialize device before it's used by a driver. Ask low-level code | |
863 | * to enable I/O and memory. Wake up the device if it was suspended. | |
864 | * Beware, this function can fail. | |
865 | * | |
866 | * Note we don't actually enable the device many times if we call | |
867 | * this function repeatedly (we just increment the count). | |
868 | */ | |
869 | int pci_enable_device(struct pci_dev *dev) | |
870 | { | |
b718989d | 871 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
872 | } |
873 | ||
9ac7849e TH |
874 | /* |
875 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
876 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
877 | * there's no need to track it separately. pci_devres is initialized | |
878 | * when a device is enabled using managed PCI device enable interface. | |
879 | */ | |
880 | struct pci_devres { | |
7f375f32 TH |
881 | unsigned int enabled:1; |
882 | unsigned int pinned:1; | |
9ac7849e TH |
883 | unsigned int orig_intx:1; |
884 | unsigned int restore_intx:1; | |
885 | u32 region_mask; | |
886 | }; | |
887 | ||
888 | static void pcim_release(struct device *gendev, void *res) | |
889 | { | |
890 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
891 | struct pci_devres *this = res; | |
892 | int i; | |
893 | ||
894 | if (dev->msi_enabled) | |
895 | pci_disable_msi(dev); | |
896 | if (dev->msix_enabled) | |
897 | pci_disable_msix(dev); | |
898 | ||
899 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
900 | if (this->region_mask & (1 << i)) | |
901 | pci_release_region(dev, i); | |
902 | ||
903 | if (this->restore_intx) | |
904 | pci_intx(dev, this->orig_intx); | |
905 | ||
7f375f32 | 906 | if (this->enabled && !this->pinned) |
9ac7849e TH |
907 | pci_disable_device(dev); |
908 | } | |
909 | ||
910 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
911 | { | |
912 | struct pci_devres *dr, *new_dr; | |
913 | ||
914 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
915 | if (dr) | |
916 | return dr; | |
917 | ||
918 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
919 | if (!new_dr) | |
920 | return NULL; | |
921 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
922 | } | |
923 | ||
924 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
925 | { | |
926 | if (pci_is_managed(pdev)) | |
927 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
928 | return NULL; | |
929 | } | |
930 | ||
931 | /** | |
932 | * pcim_enable_device - Managed pci_enable_device() | |
933 | * @pdev: PCI device to be initialized | |
934 | * | |
935 | * Managed pci_enable_device(). | |
936 | */ | |
937 | int pcim_enable_device(struct pci_dev *pdev) | |
938 | { | |
939 | struct pci_devres *dr; | |
940 | int rc; | |
941 | ||
942 | dr = get_pci_dr(pdev); | |
943 | if (unlikely(!dr)) | |
944 | return -ENOMEM; | |
b95d58ea TH |
945 | if (dr->enabled) |
946 | return 0; | |
9ac7849e TH |
947 | |
948 | rc = pci_enable_device(pdev); | |
949 | if (!rc) { | |
950 | pdev->is_managed = 1; | |
7f375f32 | 951 | dr->enabled = 1; |
9ac7849e TH |
952 | } |
953 | return rc; | |
954 | } | |
955 | ||
956 | /** | |
957 | * pcim_pin_device - Pin managed PCI device | |
958 | * @pdev: PCI device to pin | |
959 | * | |
960 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
961 | * driver detach. @pdev must have been enabled with | |
962 | * pcim_enable_device(). | |
963 | */ | |
964 | void pcim_pin_device(struct pci_dev *pdev) | |
965 | { | |
966 | struct pci_devres *dr; | |
967 | ||
968 | dr = find_pci_dr(pdev); | |
7f375f32 | 969 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 970 | if (dr) |
7f375f32 | 971 | dr->pinned = 1; |
9ac7849e TH |
972 | } |
973 | ||
1da177e4 LT |
974 | /** |
975 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
976 | * @dev: the PCI device to disable | |
977 | * | |
978 | * Disables architecture specific PCI resources for the device. This | |
979 | * is the default implementation. Architecture implementations can | |
980 | * override this. | |
981 | */ | |
982 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
983 | ||
984 | /** | |
985 | * pci_disable_device - Disable PCI device after use | |
986 | * @dev: PCI device to be disabled | |
987 | * | |
988 | * Signal to the system that the PCI device is not in use by the system | |
989 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
990 | * |
991 | * Note we don't actually disable the device until all callers of | |
992 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
993 | */ |
994 | void | |
995 | pci_disable_device(struct pci_dev *dev) | |
996 | { | |
9ac7849e | 997 | struct pci_devres *dr; |
1da177e4 | 998 | u16 pci_command; |
99dc804d | 999 | |
9ac7849e TH |
1000 | dr = find_pci_dr(dev); |
1001 | if (dr) | |
7f375f32 | 1002 | dr->enabled = 0; |
9ac7849e | 1003 | |
bae94d02 IPG |
1004 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1005 | return; | |
1006 | ||
1da177e4 LT |
1007 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
1008 | if (pci_command & PCI_COMMAND_MASTER) { | |
1009 | pci_command &= ~PCI_COMMAND_MASTER; | |
1010 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1011 | } | |
ceb43744 | 1012 | dev->is_busmaster = 0; |
1da177e4 LT |
1013 | |
1014 | pcibios_disable_device(dev); | |
1015 | } | |
1016 | ||
f7bdd12d BK |
1017 | /** |
1018 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1019 | * @dev: the PCI-E device reset | |
1020 | * @state: Reset state to enter into | |
1021 | * | |
1022 | * | |
1023 | * Sets the PCI-E reset state for the device. This is the default | |
1024 | * implementation. Architecture implementations can override this. | |
1025 | */ | |
1026 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1027 | enum pcie_reset_state state) | |
1028 | { | |
1029 | return -EINVAL; | |
1030 | } | |
1031 | ||
1032 | /** | |
1033 | * pci_set_pcie_reset_state - set reset state for device dev | |
1034 | * @dev: the PCI-E device reset | |
1035 | * @state: Reset state to enter into | |
1036 | * | |
1037 | * | |
1038 | * Sets the PCI reset state for the device. | |
1039 | */ | |
1040 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1041 | { | |
1042 | return pcibios_set_pcie_reset_state(dev, state); | |
1043 | } | |
1044 | ||
eb9d0fe4 RW |
1045 | /** |
1046 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1047 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1048 | * @state: PCI state from which device will issue PME#. |
1049 | */ | |
e5899e1b | 1050 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1051 | { |
337001b6 | 1052 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1053 | return false; |
1054 | ||
337001b6 | 1055 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1056 | } |
1057 | ||
1058 | /** | |
1059 | * pci_pme_active - enable or disable PCI device's PME# function | |
1060 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1061 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1062 | * | |
1063 | * The caller must verify that the device is capable of generating PME# before | |
1064 | * calling this function with @enable equal to 'true'. | |
1065 | */ | |
5a6c9b60 | 1066 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1067 | { |
1068 | u16 pmcsr; | |
1069 | ||
337001b6 | 1070 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1071 | return; |
1072 | ||
337001b6 | 1073 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1074 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1075 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1076 | if (!enable) | |
1077 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1078 | ||
337001b6 | 1079 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 RW |
1080 | |
1081 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1082 | enable ? "enabled" : "disabled"); | |
1083 | } | |
1084 | ||
1da177e4 | 1085 | /** |
075c1771 DB |
1086 | * pci_enable_wake - enable PCI device as wakeup event source |
1087 | * @dev: PCI device affected | |
1088 | * @state: PCI state from which device will issue wakeup events | |
1089 | * @enable: True to enable event generation; false to disable | |
1090 | * | |
1091 | * This enables the device as a wakeup event source, or disables it. | |
1092 | * When such events involves platform-specific hooks, those hooks are | |
1093 | * called automatically by this routine. | |
1094 | * | |
1095 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1096 | * always require such platform hooks. |
075c1771 | 1097 | * |
eb9d0fe4 RW |
1098 | * RETURN VALUE: |
1099 | * 0 is returned on success | |
1100 | * -EINVAL is returned if device is not supposed to wake up the system | |
1101 | * Error code depending on the platform is returned if both the platform and | |
1102 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1103 | */ |
1104 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1105 | { | |
eb9d0fe4 RW |
1106 | int error = 0; |
1107 | bool pme_done = false; | |
075c1771 | 1108 | |
eb9d0fe4 RW |
1109 | if (!device_may_wakeup(&dev->dev)) |
1110 | return -EINVAL; | |
1da177e4 | 1111 | |
eb9d0fe4 RW |
1112 | /* |
1113 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1114 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1115 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1116 | */ |
1da177e4 | 1117 | |
eb9d0fe4 RW |
1118 | if (!enable && platform_pci_can_wakeup(dev)) |
1119 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1120 | |
337001b6 RW |
1121 | if (!enable || pci_pme_capable(dev, state)) { |
1122 | pci_pme_active(dev, enable); | |
eb9d0fe4 | 1123 | pme_done = true; |
075c1771 | 1124 | } |
1da177e4 | 1125 | |
eb9d0fe4 RW |
1126 | if (enable && platform_pci_can_wakeup(dev)) |
1127 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1128 | |
eb9d0fe4 RW |
1129 | return pme_done ? 0 : error; |
1130 | } | |
1da177e4 | 1131 | |
0235c4fc RW |
1132 | /** |
1133 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1134 | * @dev: PCI device to prepare | |
1135 | * @enable: True to enable wake-up event generation; false to disable | |
1136 | * | |
1137 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1138 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1139 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1140 | * ordering constraints. | |
1141 | * | |
1142 | * This function only returns error code if the device is not capable of | |
1143 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1144 | * enable wake-up power for it. | |
1145 | */ | |
1146 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1147 | { | |
1148 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1149 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1150 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1151 | } | |
1152 | ||
404cc2d8 | 1153 | /** |
37139074 JB |
1154 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1155 | * @dev: PCI device | |
1156 | * | |
1157 | * Use underlying platform code to find a supported low power state for @dev. | |
1158 | * If the platform can't manage @dev, return the deepest state from which it | |
1159 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1160 | */ |
e5899e1b | 1161 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1162 | { |
1163 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1164 | |
1165 | if (platform_pci_power_manageable(dev)) { | |
1166 | /* | |
1167 | * Call the platform to choose the target state of the device | |
1168 | * and enable wake-up from this state if supported. | |
1169 | */ | |
1170 | pci_power_t state = platform_pci_choose_state(dev); | |
1171 | ||
1172 | switch (state) { | |
1173 | case PCI_POWER_ERROR: | |
1174 | case PCI_UNKNOWN: | |
1175 | break; | |
1176 | case PCI_D1: | |
1177 | case PCI_D2: | |
1178 | if (pci_no_d1d2(dev)) | |
1179 | break; | |
1180 | default: | |
1181 | target_state = state; | |
404cc2d8 RW |
1182 | } |
1183 | } else if (device_may_wakeup(&dev->dev)) { | |
1184 | /* | |
1185 | * Find the deepest state from which the device can generate | |
1186 | * wake-up events, make it the target state and enable device | |
1187 | * to generate PME#. | |
1188 | */ | |
337001b6 | 1189 | if (!dev->pm_cap) |
e5899e1b | 1190 | return PCI_POWER_ERROR; |
404cc2d8 | 1191 | |
337001b6 RW |
1192 | if (dev->pme_support) { |
1193 | while (target_state | |
1194 | && !(dev->pme_support & (1 << target_state))) | |
1195 | target_state--; | |
404cc2d8 RW |
1196 | } |
1197 | } | |
1198 | ||
e5899e1b RW |
1199 | return target_state; |
1200 | } | |
1201 | ||
1202 | /** | |
1203 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1204 | * @dev: Device to handle. | |
1205 | * | |
1206 | * Choose the power state appropriate for the device depending on whether | |
1207 | * it can wake up the system and/or is power manageable by the platform | |
1208 | * (PCI_D3hot is the default) and put the device into that state. | |
1209 | */ | |
1210 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1211 | { | |
1212 | pci_power_t target_state = pci_target_state(dev); | |
1213 | int error; | |
1214 | ||
1215 | if (target_state == PCI_POWER_ERROR) | |
1216 | return -EIO; | |
1217 | ||
c157dfa3 RW |
1218 | pci_enable_wake(dev, target_state, true); |
1219 | ||
404cc2d8 RW |
1220 | error = pci_set_power_state(dev, target_state); |
1221 | ||
1222 | if (error) | |
1223 | pci_enable_wake(dev, target_state, false); | |
1224 | ||
1225 | return error; | |
1226 | } | |
1227 | ||
1228 | /** | |
443bd1c4 | 1229 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1230 | * @dev: Device to handle. |
1231 | * | |
1232 | * Disable device's sytem wake-up capability and put it into D0. | |
1233 | */ | |
1234 | int pci_back_from_sleep(struct pci_dev *dev) | |
1235 | { | |
1236 | pci_enable_wake(dev, PCI_D0, false); | |
1237 | return pci_set_power_state(dev, PCI_D0); | |
1238 | } | |
1239 | ||
eb9d0fe4 RW |
1240 | /** |
1241 | * pci_pm_init - Initialize PM functions of given PCI device | |
1242 | * @dev: PCI device to handle. | |
1243 | */ | |
1244 | void pci_pm_init(struct pci_dev *dev) | |
1245 | { | |
1246 | int pm; | |
1247 | u16 pmc; | |
1da177e4 | 1248 | |
337001b6 RW |
1249 | dev->pm_cap = 0; |
1250 | ||
eb9d0fe4 RW |
1251 | /* find PCI PM capability in list */ |
1252 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1253 | if (!pm) | |
1254 | return; | |
1255 | /* Check device's ability to generate PME# */ | |
1256 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1257 | |
eb9d0fe4 RW |
1258 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1259 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1260 | pmc & PCI_PM_CAP_VER_MASK); | |
1261 | return; | |
1262 | } | |
1263 | ||
337001b6 RW |
1264 | dev->pm_cap = pm; |
1265 | ||
1266 | dev->d1_support = false; | |
1267 | dev->d2_support = false; | |
1268 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1269 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1270 | dev->d1_support = true; |
c9ed77ee | 1271 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1272 | dev->d2_support = true; |
c9ed77ee BH |
1273 | |
1274 | if (dev->d1_support || dev->d2_support) | |
1275 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1276 | dev->d1_support ? " D1" : "", |
1277 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1278 | } |
1279 | ||
1280 | pmc &= PCI_PM_CAP_PME_MASK; | |
1281 | if (pmc) { | |
c9ed77ee BH |
1282 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
1283 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1284 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1285 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1286 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1287 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1288 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1289 | /* |
1290 | * Make device's PM flags reflect the wake-up capability, but | |
1291 | * let the user space enable it to wake up the system as needed. | |
1292 | */ | |
1293 | device_set_wakeup_capable(&dev->dev, true); | |
1294 | device_set_wakeup_enable(&dev->dev, false); | |
1295 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1296 | pci_pme_active(dev, false); |
1297 | } else { | |
1298 | dev->pme_support = 0; | |
eb9d0fe4 | 1299 | } |
1da177e4 LT |
1300 | } |
1301 | ||
1302 | int | |
1303 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1304 | { | |
1305 | u8 pin; | |
1306 | ||
514d207d | 1307 | pin = dev->pin; |
1da177e4 LT |
1308 | if (!pin) |
1309 | return -1; | |
1310 | pin--; | |
1311 | while (dev->bus->self) { | |
1312 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1313 | dev = dev->bus->self; | |
1314 | } | |
1315 | *bridge = dev; | |
1316 | return pin; | |
1317 | } | |
1318 | ||
1319 | /** | |
1320 | * pci_release_region - Release a PCI bar | |
1321 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1322 | * @bar: BAR to release | |
1323 | * | |
1324 | * Releases the PCI I/O and memory resources previously reserved by a | |
1325 | * successful call to pci_request_region. Call this function only | |
1326 | * after all use of the PCI regions has ceased. | |
1327 | */ | |
1328 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1329 | { | |
9ac7849e TH |
1330 | struct pci_devres *dr; |
1331 | ||
1da177e4 LT |
1332 | if (pci_resource_len(pdev, bar) == 0) |
1333 | return; | |
1334 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1335 | release_region(pci_resource_start(pdev, bar), | |
1336 | pci_resource_len(pdev, bar)); | |
1337 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1338 | release_mem_region(pci_resource_start(pdev, bar), | |
1339 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1340 | |
1341 | dr = find_pci_dr(pdev); | |
1342 | if (dr) | |
1343 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | /** | |
1347 | * pci_request_region - Reserved PCI I/O and memory resource | |
1348 | * @pdev: PCI device whose resources are to be reserved | |
1349 | * @bar: BAR to be reserved | |
1350 | * @res_name: Name to be associated with resource. | |
1351 | * | |
1352 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1353 | * being reserved by owner @res_name. Do not access any | |
1354 | * address inside the PCI regions unless this call returns | |
1355 | * successfully. | |
1356 | * | |
1357 | * Returns 0 on success, or %EBUSY on error. A warning | |
1358 | * message is also printed on failure. | |
1359 | */ | |
3c990e92 | 1360 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1361 | { |
9ac7849e TH |
1362 | struct pci_devres *dr; |
1363 | ||
1da177e4 LT |
1364 | if (pci_resource_len(pdev, bar) == 0) |
1365 | return 0; | |
1366 | ||
1367 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1368 | if (!request_region(pci_resource_start(pdev, bar), | |
1369 | pci_resource_len(pdev, bar), res_name)) | |
1370 | goto err_out; | |
1371 | } | |
1372 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1373 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1374 | pci_resource_len(pdev, bar), res_name)) | |
1375 | goto err_out; | |
1376 | } | |
9ac7849e TH |
1377 | |
1378 | dr = find_pci_dr(pdev); | |
1379 | if (dr) | |
1380 | dr->region_mask |= 1 << bar; | |
1381 | ||
1da177e4 LT |
1382 | return 0; |
1383 | ||
1384 | err_out: | |
096e6f67 | 1385 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
e4ec7a00 JB |
1386 | bar, |
1387 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
096e6f67 | 1388 | &pdev->resource[bar]); |
1da177e4 LT |
1389 | return -EBUSY; |
1390 | } | |
1391 | ||
c87deff7 HS |
1392 | /** |
1393 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1394 | * @pdev: PCI device whose resources were previously reserved | |
1395 | * @bars: Bitmask of BARs to be released | |
1396 | * | |
1397 | * Release selected PCI I/O and memory resources previously reserved. | |
1398 | * Call this function only after all use of the PCI regions has ceased. | |
1399 | */ | |
1400 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1401 | { | |
1402 | int i; | |
1403 | ||
1404 | for (i = 0; i < 6; i++) | |
1405 | if (bars & (1 << i)) | |
1406 | pci_release_region(pdev, i); | |
1407 | } | |
1408 | ||
1409 | /** | |
1410 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1411 | * @pdev: PCI device whose resources are to be reserved | |
1412 | * @bars: Bitmask of BARs to be requested | |
1413 | * @res_name: Name to be associated with resource | |
1414 | */ | |
1415 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1416 | const char *res_name) | |
1417 | { | |
1418 | int i; | |
1419 | ||
1420 | for (i = 0; i < 6; i++) | |
1421 | if (bars & (1 << i)) | |
1422 | if(pci_request_region(pdev, i, res_name)) | |
1423 | goto err_out; | |
1424 | return 0; | |
1425 | ||
1426 | err_out: | |
1427 | while(--i >= 0) | |
1428 | if (bars & (1 << i)) | |
1429 | pci_release_region(pdev, i); | |
1430 | ||
1431 | return -EBUSY; | |
1432 | } | |
1da177e4 LT |
1433 | |
1434 | /** | |
1435 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1436 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1437 | * | |
1438 | * Releases all PCI I/O and memory resources previously reserved by a | |
1439 | * successful call to pci_request_regions. Call this function only | |
1440 | * after all use of the PCI regions has ceased. | |
1441 | */ | |
1442 | ||
1443 | void pci_release_regions(struct pci_dev *pdev) | |
1444 | { | |
c87deff7 | 1445 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1446 | } |
1447 | ||
1448 | /** | |
1449 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1450 | * @pdev: PCI device whose resources are to be reserved | |
1451 | * @res_name: Name to be associated with resource. | |
1452 | * | |
1453 | * Mark all PCI regions associated with PCI device @pdev as | |
1454 | * being reserved by owner @res_name. Do not access any | |
1455 | * address inside the PCI regions unless this call returns | |
1456 | * successfully. | |
1457 | * | |
1458 | * Returns 0 on success, or %EBUSY on error. A warning | |
1459 | * message is also printed on failure. | |
1460 | */ | |
3c990e92 | 1461 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1462 | { |
c87deff7 | 1463 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1464 | } |
1465 | ||
1466 | /** | |
1467 | * pci_set_master - enables bus-mastering for device dev | |
1468 | * @dev: the PCI device to enable | |
1469 | * | |
1470 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1471 | * to do the needed arch specific settings. | |
1472 | */ | |
1473 | void | |
1474 | pci_set_master(struct pci_dev *dev) | |
1475 | { | |
1476 | u16 cmd; | |
1477 | ||
1478 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1479 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1480 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1481 | cmd |= PCI_COMMAND_MASTER; |
1482 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1483 | } | |
1484 | dev->is_busmaster = 1; | |
1485 | pcibios_set_master(dev); | |
1486 | } | |
1487 | ||
edb2d97e MW |
1488 | #ifdef PCI_DISABLE_MWI |
1489 | int pci_set_mwi(struct pci_dev *dev) | |
1490 | { | |
1491 | return 0; | |
1492 | } | |
1493 | ||
694625c0 RD |
1494 | int pci_try_set_mwi(struct pci_dev *dev) |
1495 | { | |
1496 | return 0; | |
1497 | } | |
1498 | ||
edb2d97e MW |
1499 | void pci_clear_mwi(struct pci_dev *dev) |
1500 | { | |
1501 | } | |
1502 | ||
1503 | #else | |
ebf5a248 MW |
1504 | |
1505 | #ifndef PCI_CACHE_LINE_BYTES | |
1506 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1507 | #endif | |
1508 | ||
1da177e4 | 1509 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1510 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1511 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1512 | |
1513 | /** | |
edb2d97e MW |
1514 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1515 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1516 | * |
edb2d97e MW |
1517 | * Helper function for pci_set_mwi. |
1518 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1519 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1520 | * | |
1521 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1522 | */ | |
1523 | static int | |
edb2d97e | 1524 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1525 | { |
1526 | u8 cacheline_size; | |
1527 | ||
1528 | if (!pci_cache_line_size) | |
1529 | return -EINVAL; /* The system doesn't support MWI. */ | |
1530 | ||
1531 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1532 | equal to or multiple of the right value. */ | |
1533 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1534 | if (cacheline_size >= pci_cache_line_size && | |
1535 | (cacheline_size % pci_cache_line_size) == 0) | |
1536 | return 0; | |
1537 | ||
1538 | /* Write the correct value. */ | |
1539 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1540 | /* Read it back. */ | |
1541 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1542 | if (cacheline_size == pci_cache_line_size) | |
1543 | return 0; | |
1544 | ||
80ccba11 BH |
1545 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1546 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1547 | |
1548 | return -EINVAL; | |
1549 | } | |
1da177e4 LT |
1550 | |
1551 | /** | |
1552 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1553 | * @dev: the PCI device for which MWI is enabled | |
1554 | * | |
694625c0 | 1555 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1556 | * |
1557 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1558 | */ | |
1559 | int | |
1560 | pci_set_mwi(struct pci_dev *dev) | |
1561 | { | |
1562 | int rc; | |
1563 | u16 cmd; | |
1564 | ||
edb2d97e | 1565 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1566 | if (rc) |
1567 | return rc; | |
1568 | ||
1569 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1570 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1571 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1572 | cmd |= PCI_COMMAND_INVALIDATE; |
1573 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
694625c0 RD |
1579 | /** |
1580 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1581 | * @dev: the PCI device for which MWI is enabled | |
1582 | * | |
1583 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1584 | * Callers are not required to check the return value. | |
1585 | * | |
1586 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1587 | */ | |
1588 | int pci_try_set_mwi(struct pci_dev *dev) | |
1589 | { | |
1590 | int rc = pci_set_mwi(dev); | |
1591 | return rc; | |
1592 | } | |
1593 | ||
1da177e4 LT |
1594 | /** |
1595 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1596 | * @dev: the PCI device to disable | |
1597 | * | |
1598 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1599 | */ | |
1600 | void | |
1601 | pci_clear_mwi(struct pci_dev *dev) | |
1602 | { | |
1603 | u16 cmd; | |
1604 | ||
1605 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1606 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1607 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1608 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1609 | } | |
1610 | } | |
edb2d97e | 1611 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1612 | |
a04ce0ff BR |
1613 | /** |
1614 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1615 | * @pdev: the PCI device to operate on |
1616 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1617 | * |
1618 | * Enables/disables PCI INTx for device dev | |
1619 | */ | |
1620 | void | |
1621 | pci_intx(struct pci_dev *pdev, int enable) | |
1622 | { | |
1623 | u16 pci_command, new; | |
1624 | ||
1625 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1626 | ||
1627 | if (enable) { | |
1628 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1629 | } else { | |
1630 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1631 | } | |
1632 | ||
1633 | if (new != pci_command) { | |
9ac7849e TH |
1634 | struct pci_devres *dr; |
1635 | ||
2fd9d74b | 1636 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1637 | |
1638 | dr = find_pci_dr(pdev); | |
1639 | if (dr && !dr->restore_intx) { | |
1640 | dr->restore_intx = 1; | |
1641 | dr->orig_intx = !enable; | |
1642 | } | |
a04ce0ff BR |
1643 | } |
1644 | } | |
1645 | ||
f5f2b131 EB |
1646 | /** |
1647 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1648 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1649 | * |
1650 | * If you want to use msi see pci_enable_msi and friends. | |
1651 | * This is a lower level primitive that allows us to disable | |
1652 | * msi operation at the device level. | |
1653 | */ | |
1654 | void pci_msi_off(struct pci_dev *dev) | |
1655 | { | |
1656 | int pos; | |
1657 | u16 control; | |
1658 | ||
1659 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1660 | if (pos) { | |
1661 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1662 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1663 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1664 | } | |
1665 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1666 | if (pos) { | |
1667 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1668 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1669 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1670 | } | |
1671 | } | |
1672 | ||
1da177e4 LT |
1673 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1674 | /* | |
1675 | * These can be overridden by arch-specific implementations | |
1676 | */ | |
1677 | int | |
1678 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1679 | { | |
1680 | if (!pci_dma_supported(dev, mask)) | |
1681 | return -EIO; | |
1682 | ||
1683 | dev->dma_mask = mask; | |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1da177e4 LT |
1688 | int |
1689 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1690 | { | |
1691 | if (!pci_dma_supported(dev, mask)) | |
1692 | return -EIO; | |
1693 | ||
1694 | dev->dev.coherent_dma_mask = mask; | |
1695 | ||
1696 | return 0; | |
1697 | } | |
1698 | #endif | |
c87deff7 | 1699 | |
4d57cdfa FT |
1700 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1701 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1702 | { | |
1703 | return dma_set_max_seg_size(&dev->dev, size); | |
1704 | } | |
1705 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1706 | #endif | |
1707 | ||
59fc67de FT |
1708 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1709 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1710 | { | |
1711 | return dma_set_seg_boundary(&dev->dev, mask); | |
1712 | } | |
1713 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1714 | #endif | |
1715 | ||
d556ad4b PO |
1716 | /** |
1717 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1718 | * @dev: PCI device to query | |
1719 | * | |
1720 | * Returns mmrbc: maximum designed memory read count in bytes | |
1721 | * or appropriate error value. | |
1722 | */ | |
1723 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1724 | { | |
b7b095c1 | 1725 | int err, cap; |
d556ad4b PO |
1726 | u32 stat; |
1727 | ||
1728 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1729 | if (!cap) | |
1730 | return -EINVAL; | |
1731 | ||
1732 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1733 | if (err) | |
1734 | return -EINVAL; | |
1735 | ||
b7b095c1 | 1736 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1737 | } |
1738 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1739 | ||
1740 | /** | |
1741 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1742 | * @dev: PCI device to query | |
1743 | * | |
1744 | * Returns mmrbc: maximum memory read count in bytes | |
1745 | * or appropriate error value. | |
1746 | */ | |
1747 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1748 | { | |
1749 | int ret, cap; | |
1750 | u32 cmd; | |
1751 | ||
1752 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1753 | if (!cap) | |
1754 | return -EINVAL; | |
1755 | ||
1756 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1757 | if (!ret) | |
1758 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1759 | ||
1760 | return ret; | |
1761 | } | |
1762 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1763 | ||
1764 | /** | |
1765 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1766 | * @dev: PCI device to query | |
1767 | * @mmrbc: maximum memory read count in bytes | |
1768 | * valid values are 512, 1024, 2048, 4096 | |
1769 | * | |
1770 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1771 | * that prevent this. | |
1772 | */ | |
1773 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1774 | { | |
1775 | int cap, err = -EINVAL; | |
1776 | u32 stat, cmd, v, o; | |
1777 | ||
229f5afd | 1778 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1779 | goto out; |
1780 | ||
1781 | v = ffs(mmrbc) - 10; | |
1782 | ||
1783 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1784 | if (!cap) | |
1785 | goto out; | |
1786 | ||
1787 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1788 | if (err) | |
1789 | goto out; | |
1790 | ||
1791 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1792 | return -E2BIG; | |
1793 | ||
1794 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1795 | if (err) | |
1796 | goto out; | |
1797 | ||
1798 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1799 | if (o != v) { | |
1800 | if (v > o && dev->bus && | |
1801 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1802 | return -EIO; | |
1803 | ||
1804 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1805 | cmd |= v << 2; | |
1806 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1807 | } | |
1808 | out: | |
1809 | return err; | |
1810 | } | |
1811 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1812 | ||
1813 | /** | |
1814 | * pcie_get_readrq - get PCI Express read request size | |
1815 | * @dev: PCI device to query | |
1816 | * | |
1817 | * Returns maximum memory read request in bytes | |
1818 | * or appropriate error value. | |
1819 | */ | |
1820 | int pcie_get_readrq(struct pci_dev *dev) | |
1821 | { | |
1822 | int ret, cap; | |
1823 | u16 ctl; | |
1824 | ||
1825 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1826 | if (!cap) | |
1827 | return -EINVAL; | |
1828 | ||
1829 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1830 | if (!ret) | |
1831 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1832 | ||
1833 | return ret; | |
1834 | } | |
1835 | EXPORT_SYMBOL(pcie_get_readrq); | |
1836 | ||
1837 | /** | |
1838 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1839 | * @dev: PCI device to query | |
42e61f4a | 1840 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1841 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1842 | * | |
1843 | * If possible sets maximum read byte count | |
1844 | */ | |
1845 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1846 | { | |
1847 | int cap, err = -EINVAL; | |
1848 | u16 ctl, v; | |
1849 | ||
229f5afd | 1850 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1851 | goto out; |
1852 | ||
1853 | v = (ffs(rq) - 8) << 12; | |
1854 | ||
1855 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1856 | if (!cap) | |
1857 | goto out; | |
1858 | ||
1859 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1860 | if (err) | |
1861 | goto out; | |
1862 | ||
1863 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1864 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1865 | ctl |= v; | |
1866 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1867 | } | |
1868 | ||
1869 | out: | |
1870 | return err; | |
1871 | } | |
1872 | EXPORT_SYMBOL(pcie_set_readrq); | |
1873 | ||
c87deff7 HS |
1874 | /** |
1875 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1876 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1877 | * @flags: resource type mask to be selected |
1878 | * | |
1879 | * This helper routine makes bar mask from the type of resource. | |
1880 | */ | |
1881 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1882 | { | |
1883 | int i, bars = 0; | |
1884 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1885 | if (pci_resource_flags(dev, i) & flags) | |
1886 | bars |= (1 << i); | |
1887 | return bars; | |
1888 | } | |
1889 | ||
32a2eea7 JG |
1890 | static void __devinit pci_no_domains(void) |
1891 | { | |
1892 | #ifdef CONFIG_PCI_DOMAINS | |
1893 | pci_domains_supported = 0; | |
1894 | #endif | |
1895 | } | |
1896 | ||
1da177e4 LT |
1897 | static int __devinit pci_init(void) |
1898 | { | |
1899 | struct pci_dev *dev = NULL; | |
1900 | ||
1901 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1902 | pci_fixup_device(pci_fixup_final, dev); | |
1903 | } | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | static int __devinit pci_setup(char *str) | |
1908 | { | |
1909 | while (str) { | |
1910 | char *k = strchr(str, ','); | |
1911 | if (k) | |
1912 | *k++ = 0; | |
1913 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1914 | if (!strcmp(str, "nomsi")) { |
1915 | pci_no_msi(); | |
7f785763 RD |
1916 | } else if (!strcmp(str, "noaer")) { |
1917 | pci_no_aer(); | |
32a2eea7 JG |
1918 | } else if (!strcmp(str, "nodomains")) { |
1919 | pci_no_domains(); | |
4516a618 AN |
1920 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1921 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1922 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1923 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1924 | } else { |
1925 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1926 | str); | |
1927 | } | |
1da177e4 LT |
1928 | } |
1929 | str = k; | |
1930 | } | |
0637a70a | 1931 | return 0; |
1da177e4 | 1932 | } |
0637a70a | 1933 | early_param("pci", pci_setup); |
1da177e4 LT |
1934 | |
1935 | device_initcall(pci_init); | |
1da177e4 | 1936 | |
0b62e13b | 1937 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
1938 | EXPORT_SYMBOL(pci_enable_device_io); |
1939 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 1940 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
1941 | EXPORT_SYMBOL(pcim_enable_device); |
1942 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1943 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1944 | EXPORT_SYMBOL(pci_find_capability); |
1945 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1946 | EXPORT_SYMBOL(pci_release_regions); | |
1947 | EXPORT_SYMBOL(pci_request_regions); | |
1948 | EXPORT_SYMBOL(pci_release_region); | |
1949 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1950 | EXPORT_SYMBOL(pci_release_selected_regions); |
1951 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1952 | EXPORT_SYMBOL(pci_set_master); |
1953 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1954 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1955 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1956 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1957 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1958 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1959 | EXPORT_SYMBOL(pci_assign_resource); | |
1960 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1961 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1962 | |
1963 | EXPORT_SYMBOL(pci_set_power_state); | |
1964 | EXPORT_SYMBOL(pci_save_state); | |
1965 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 1966 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 1967 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 1968 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 1969 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 1970 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
1971 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
1972 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 1973 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1974 |