projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI/e1000e: Add and use pci_disable_link_state_locked()
[deliverable/linux.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
32a9a682 25#include <asm/setup.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
00240c38
AS		 28const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30};
31EXPORT_SYMBOL_GPL(pci_power_names);
32
93177a74
RW		 33int isa_dma_bridge_buggy;
34EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36int pci_pci_problems;
37EXPORT_SYMBOL(pci_pci_problems);
38
1ae861e6
RW		 39unsigned int pci_pm_d3_delay;
40
df17e62e
MG		 41static void pci_pme_list_scan(struct work_struct *work);
42
43static LIST_HEAD(pci_pme_list);
44static DEFINE_MUTEX(pci_pme_list_mutex);
45static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
46
47struct pci_pme_device {
48 struct list_head list;
49 struct pci_dev *dev;
50};
51
52#define PME_TIMEOUT 1000 /* How long between PME checks */
53
1ae861e6
RW		 54static void pci_dev_d3_sleep(struct pci_dev *dev)
55{
56 unsigned int delay = dev->d3_delay;
57
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
60
61 msleep(delay);
62}
1da177e4 63
32a2eea7
JG		 64#ifdef CONFIG_PCI_DOMAINS
65int pci_domains_supported = 1;
66#endif
67
4516a618
AN		 68#define DEFAULT_CARDBUS_IO_SIZE (256)
69#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70/* pci=cbmemsize=nnM,cbiosize=nn can override this */
71unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
73
28760489
EB		 74#define DEFAULT_HOTPLUG_IO_SIZE (256)
75#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76/* pci=hpmemsize=nnM,hpiosize=nn can override this */
77unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
79
ac1aa47b
JB		 80/*
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
85 */
98e724c7 86u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 87u8 pci_cache_line_size;
88
1da177e4
LT		 89/**
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
92 *
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
95 */
96bde06a 96unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 97{
98 struct list_head *tmp;
99 unsigned char max, n;
100
b82db5ce 101 max = bus->subordinate;
1da177e4
LT		 102 list_for_each(tmp, &bus->children) {
103 n = pci_bus_max_busnr(pci_bus_b(tmp));
104 if(n > max)
105 max = n;
106 }
107 return max;
108}
b82db5ce 109EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 110
1684f5dd
AM		 111#ifdef CONFIG_HAS_IOMEM
112void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
113{
114 /*
115 * Make sure the BAR is actually a memory resource, not an IO resource
116 */
117 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
118 WARN_ON(1);
119 return NULL;
120 }
121 return ioremap_nocache(pci_resource_start(pdev, bar),
122 pci_resource_len(pdev, bar));
123}
124EXPORT_SYMBOL_GPL(pci_ioremap_bar);
125#endif
126
b82db5ce 127#if 0
1da177e4
LT		 128/**
129 * pci_max_busnr - returns maximum PCI bus number
130 *
131 * Returns the highest PCI bus number present in the system global list of
132 * PCI buses.
133 */
134unsigned char __devinit
135pci_max_busnr(void)
136{
137 struct pci_bus *bus = NULL;
138 unsigned char max, n;
139
140 max = 0;
141 while ((bus = pci_find_next_bus(bus)) != NULL) {
142 n = pci_bus_max_busnr(bus);
143 if(n > max)
144 max = n;
145 }
146 return max;
147}
148
54c762fe
AB		 149#endif /* 0 */
150
687d5fe3
ME		 151#define PCI_FIND_CAP_TTL 48
152
153static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
154 u8 pos, int cap, int *ttl)
24a4e377
RD		 155{
156 u8 id;
24a4e377 157
687d5fe3 158 while ((*ttl)--) {
24a4e377
RD		 159 pci_bus_read_config_byte(bus, devfn, pos, &pos);
160 if (pos < 0x40)
161 break;
162 pos &= ~3;
163 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
164 &id);
165 if (id == 0xff)
166 break;
167 if (id == cap)
168 return pos;
169 pos += PCI_CAP_LIST_NEXT;
170 }
171 return 0;
172}
173
687d5fe3
ME		 174static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
175 u8 pos, int cap)
176{
177 int ttl = PCI_FIND_CAP_TTL;
178
179 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
180}
181
24a4e377
RD		 182int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
183{
184 return __pci_find_next_cap(dev->bus, dev->devfn,
185 pos + PCI_CAP_LIST_NEXT, cap);
186}
187EXPORT_SYMBOL_GPL(pci_find_next_capability);
188
d3bac118
ME		 189static int __pci_bus_find_cap_start(struct pci_bus *bus,
190 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 191{
192 u16 status;
1da177e4
LT		 193
194 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
195 if (!(status & PCI_STATUS_CAP_LIST))
196 return 0;
197
198 switch (hdr_type) {
199 case PCI_HEADER_TYPE_NORMAL:
200 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 201 return PCI_CAPABILITY_LIST;
1da177e4 202 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 203 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 204 default:
205 return 0;
206 }
d3bac118
ME		 207
208 return 0;
1da177e4
LT		 209}
210
211/**
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
215 *
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
220 *
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
229 */
230int pci_find_capability(struct pci_dev *dev, int cap)
231{
d3bac118
ME		 232 int pos;
233
234 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
235 if (pos)
236 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
237
238 return pos;
1da177e4
LT		 239}
240
241/**
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
246 *
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
249 *
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
252 * support it.
253 */
254int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
255{
d3bac118 256 int pos;
1da177e4
LT		 257 u8 hdr_type;
258
259 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
260
d3bac118
ME		 261 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
262 if (pos)
263 pos = __pci_find_next_cap(bus, devfn, pos, cap);
264
265 return pos;
1da177e4
LT		 266}
267
268/**
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
272 *
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
276 *
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
281 */
282int pci_find_ext_capability(struct pci_dev *dev, int cap)
283{
284 u32 header;
557848c3
ZY		 285 int ttl;
286 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 287
557848c3
ZY		 288 /* minimum 8 bytes per capability */
289 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
290
291 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 292 return 0;
293
294 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
295 return 0;
296
297 /*
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
300 */
301 if (header == 0)
302 return 0;
303
304 while (ttl-- > 0) {
305 if (PCI_EXT_CAP_ID(header) == cap)
306 return pos;
307
308 pos = PCI_EXT_CAP_NEXT(header);
557848c3 309 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 310 break;
311
312 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
313 break;
314 }
315
316 return 0;
317}
3a720d72 318EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 319
cf4c43dd
JB		 320/**
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
325 *
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
328 *
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
331 * support it.
332 */
333int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
334 int cap)
335{
336 u32 header;
337 int ttl;
338 int pos = PCI_CFG_SPACE_SIZE;
339
340 /* minimum 8 bytes per capability */
341 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
342
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
344 return 0;
345 if (header == 0xffffffff || header == 0)
346 return 0;
347
348 while (ttl-- > 0) {
349 if (PCI_EXT_CAP_ID(header) == cap)
350 return pos;
351
352 pos = PCI_EXT_CAP_NEXT(header);
353 if (pos < PCI_CFG_SPACE_SIZE)
354 break;
355
356 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
357 break;
358 }
359
360 return 0;
361}
362
687d5fe3
ME		 363static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
364{
365 int rc, ttl = PCI_FIND_CAP_TTL;
366 u8 cap, mask;
367
368 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
369 mask = HT_3BIT_CAP_MASK;
370 else
371 mask = HT_5BIT_CAP_MASK;
372
373 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
374 PCI_CAP_ID_HT, &ttl);
375 while (pos) {
376 rc = pci_read_config_byte(dev, pos + 3, &cap);
377 if (rc != PCIBIOS_SUCCESSFUL)
378 return 0;
379
380 if ((cap & mask) == ht_cap)
381 return pos;
382
47a4d5be
BG		 383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
384 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 385 PCI_CAP_ID_HT, &ttl);
386 }
387
388 return 0;
389}
390/**
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
395 *
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
399 *
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
402 */
403int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
404{
405 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
406}
407EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
408
409/**
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
413 *
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
419 */
420int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
421{
422 int pos;
423
424 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
425 if (pos)
426 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
427
428 return pos;
429}
430EXPORT_SYMBOL_GPL(pci_find_ht_capability);
431
1da177e4
LT		 432/**
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
436 *
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
440 */
441struct resource *
442pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
443{
444 const struct pci_bus *bus = dev->bus;
445 int i;
89a74ecc 446 struct resource *best = NULL, *r;
1da177e4 447
89a74ecc 448 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 449 if (!r)
450 continue;
451 if (res->start && !(res->start >= r->start && res->end <= r->end))
452 continue; /* Not contained */
453 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
454 continue; /* Wrong type */
455 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
456 return r; /* Exact match */
8c8def26
LT		 457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r->flags & IORESOURCE_PREFETCH)
459 continue;
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
461 if (!best)
462 best = r;
1da177e4
LT		 463 }
464 return best;
465}
466
064b53db
JL		 467/**
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
470 *
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
473 */
ad668599 474static void
064b53db
JL		 475pci_restore_bars(struct pci_dev *dev)
476{
bc5f5a82 477 int i;
064b53db 478
bc5f5a82 479 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 480 pci_update_resource(dev, i);
064b53db
JL		 481}
482
961d9120
RW		 483static struct pci_platform_pm_ops *pci_platform_pm;
484
485int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
486{
eb9d0fe4
RW		 487 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
488 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 489 return -EINVAL;
490 pci_platform_pm = ops;
491 return 0;
492}
493
494static inline bool platform_pci_power_manageable(struct pci_dev *dev)
495{
496 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
497}
498
499static inline int platform_pci_set_power_state(struct pci_dev *dev,
500 pci_power_t t)
501{
502 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
503}
504
505static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
506{
507 return pci_platform_pm ?
508 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
509}
8f7020d3 510
eb9d0fe4
RW		 511static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
512{
513 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
514}
515
516static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
517{
518 return pci_platform_pm ?
519 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
520}
521
b67ea761
RW		 522static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
523{
524 return pci_platform_pm ?
525 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
526}
527
1da177e4 528/**
44e4e66e
RW		 529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
530 * given PCI device
531 * @dev: PCI device to handle.
44e4e66e 532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 533 *
44e4e66e
RW		 534 * RETURN VALUE:
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
1da177e4 540 */
f00a20ef 541static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 542{
337001b6 543 u16 pmcsr;
44e4e66e 544 bool need_restore = false;
1da177e4 545
4a865905
RW		 546 /* Check if we're already there */
547 if (dev->current_state == state)
548 return 0;
549
337001b6 550 if (!dev->pm_cap)
cca03dec
AL		 551 return -EIO;
552
44e4e66e
RW		 553 if (state < PCI_D0 || state > PCI_D3hot)
554 return -EINVAL;
555
1da177e4
LT		 556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
559 */
4a865905 560 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 561 && dev->current_state > state) {
80ccba11
BH		 562 dev_err(&dev->dev, "invalid power transition "
563 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 564 return -EINVAL;
44e4e66e 565 }
1da177e4 566
1da177e4 567 /* check if this device supports the desired state */
337001b6
RW		 568 if ((state == PCI_D1 && !dev->d1_support)
569 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 570 return -EIO;
1da177e4 571
337001b6 572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 573
32a36585 574 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
577 */
32a36585 578 switch (dev->current_state) {
d3535fbb
JL		 579 case PCI_D0:
580 case PCI_D1:
581 case PCI_D2:
582 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
583 pmcsr |= state;
584 break;
f62795f1
RW		 585 case PCI_D3hot:
586 case PCI_D3cold:
32a36585
JL		 587 case PCI_UNKNOWN: /* Boot-up */
588 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 589 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 590 need_restore = true;
32a36585 591 /* Fall-through: force to D0 */
32a36585 592 default:
d3535fbb 593 pmcsr = 0;
32a36585 594 break;
1da177e4
LT		 595 }
596
597 /* enter specified state */
337001b6 598 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 599
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 603 pci_dev_d3_sleep(dev);
1da177e4 604 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 605 udelay(PCI_PM_D2_DELAY);
1da177e4 606
e13cdbd7
RW		 607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
608 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
609 if (dev->current_state != state && printk_ratelimit())
610 dev_info(&dev->dev, "Refused to change power state, "
611 "currently in D%d\n", dev->current_state);
064b53db
JL		 612
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
619 *
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
624 */
625 if (need_restore)
626 pci_restore_bars(dev);
627
f00a20ef 628 if (dev->bus->self)
7d715a6c
SL		 629 pcie_aspm_pm_state_change(dev->bus->self);
630
1da177e4
LT		 631 return 0;
632}
633
44e4e66e
RW		 634/**
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
f06fc0b6 638 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 639 */
73410429 640void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 641{
337001b6 642 if (dev->pm_cap) {
44e4e66e
RW		 643 u16 pmcsr;
644
337001b6 645 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 646 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 647 } else {
648 dev->current_state = state;
44e4e66e
RW		 649 }
650}
651
0e5dd46b
RW		 652/**
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
656 */
657static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
658{
659 int error;
660
661 if (platform_pci_power_manageable(dev)) {
662 error = platform_pci_set_power_state(dev, state);
663 if (!error)
664 pci_update_current_state(dev, state);
665 } else {
666 error = -ENODEV;
667 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 668 if (!dev->pm_cap)
669 dev->current_state = PCI_D0;
0e5dd46b
RW		 670 }
671
672 return error;
673}
674
675/**
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
679 */
680static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
681{
682 if (state == PCI_D0)
683 pci_platform_power_transition(dev, PCI_D0);
684}
685
686/**
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
690 *
691 * This function should not be called directly by device drivers.
692 */
693int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
694{
cc2893b6 695 return state >= PCI_D0 ?
0e5dd46b
RW		 696 pci_platform_power_transition(dev, state) : -EINVAL;
697}
698EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
699
44e4e66e
RW		 700/**
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
704 *
877d0310 705 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 706 * the device's PCI PM registers.
707 *
708 * RETURN VALUE:
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
714 */
715int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
716{
337001b6 717 int error;
44e4e66e
RW		 718
719 /* bound the state we're entering */
720 if (state > PCI_D3hot)
721 state = PCI_D3hot;
722 else if (state < PCI_D0)
723 state = PCI_D0;
724 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
725 /*
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
729 */
730 return 0;
731
0e5dd46b
RW		 732 __pci_start_power_transition(dev, state);
733
979b1791
AC		 734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
737 return 0;
44e4e66e 738
f00a20ef 739 error = pci_raw_set_power_state(dev, state);
44e4e66e 740
0e5dd46b
RW		 741 if (!__pci_complete_power_transition(dev, state))
742 error = 0;
1a680b7c
NC		 743 /*
744 * When aspm_policy is "powersave" this call ensures
745 * that ASPM is configured.
746 */
747 if (!error && dev->bus->self)
748 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 749
750 return error;
751}
752
1da177e4
LT		 753/**
754 * pci_choose_state - Choose the power state of a PCI device
755 * @dev: PCI device to be suspended
756 * @state: target sleep state for the whole system. This is the value
757 * that is passed to suspend() function.
758 *
759 * Returns PCI power state suitable for given device and given system
760 * message.
761 */
762
763pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
764{
ab826ca4 765 pci_power_t ret;
0f64474b 766
1da177e4
LT		 767 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
768 return PCI_D0;
769
961d9120
RW		 770 ret = platform_pci_choose_state(dev);
771 if (ret != PCI_POWER_ERROR)
772 return ret;
ca078bae
PM		 773
774 switch (state.event) {
775 case PM_EVENT_ON:
776 return PCI_D0;
777 case PM_EVENT_FREEZE:
b887d2e6
DB		 778 case PM_EVENT_PRETHAW:
779 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 780 case PM_EVENT_SUSPEND:
3a2d5b70 781 case PM_EVENT_HIBERNATE:
ca078bae 782 return PCI_D3hot;
1da177e4 783 default:
80ccba11
BH		 784 dev_info(&dev->dev, "unrecognized suspend event %d\n",
785 state.event);
1da177e4
LT		 786 BUG();
787 }
788 return PCI_D0;
789}
790
791EXPORT_SYMBOL(pci_choose_state);
792
89858517
YZ		 793#define PCI_EXP_SAVE_REGS 7
794
1b6b8ce2
YZ		 795#define pcie_cap_has_devctl(type, flags) 1
796#define pcie_cap_has_lnkctl(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
798 (type == PCI_EXP_TYPE_ROOT_PORT || \
799 type == PCI_EXP_TYPE_ENDPOINT || \
800 type == PCI_EXP_TYPE_LEG_END))
801#define pcie_cap_has_sltctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
804 (type == PCI_EXP_TYPE_DOWNSTREAM && \
805 (flags & PCI_EXP_FLAGS_SLOT))))
806#define pcie_cap_has_rtctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_RC_EC))
810#define pcie_cap_has_devctl2(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1)
812#define pcie_cap_has_lnkctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814#define pcie_cap_has_sltctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
816
b56a5a23
MT		 817static int pci_save_pcie_state(struct pci_dev *dev)
818{
819 int pos, i = 0;
820 struct pci_cap_saved_state *save_state;
821 u16 *cap;
1b6b8ce2 822 u16 flags;
b56a5a23 823
06a1cbaf
KK		 824 pos = pci_pcie_cap(dev);
825 if (!pos)
b56a5a23
MT		 826 return 0;
827
9f35575d 828 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 829 if (!save_state) {
e496b617 830 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 831 return -ENOMEM;
832 }
833 cap = (u16 *)&save_state->data[0];
834
1b6b8ce2
YZ		 835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
836
837 if (pcie_cap_has_devctl(dev->pcie_type, flags))
838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
839 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
841 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
843 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
845 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
846 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
847 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
849 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
63f4898a 851
b56a5a23
MT		 852 return 0;
853}
854
855static void pci_restore_pcie_state(struct pci_dev *dev)
856{
857 int i = 0, pos;
858 struct pci_cap_saved_state *save_state;
859 u16 *cap;
1b6b8ce2 860 u16 flags;
b56a5a23
MT		 861
862 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
864 if (!save_state || pos <= 0)
865 return;
866 cap = (u16 *)&save_state->data[0];
867
1b6b8ce2
YZ		 868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
869
870 if (pcie_cap_has_devctl(dev->pcie_type, flags))
871 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
872 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
874 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
876 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
878 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
879 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
880 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
882 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 884}
885
cc692a5f
SH		 886
887static int pci_save_pcix_state(struct pci_dev *dev)
888{
63f4898a 889 int pos;
cc692a5f 890 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 891
892 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
893 if (pos <= 0)
894 return 0;
895
f34303de 896 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 897 if (!save_state) {
e496b617 898 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 899 return -ENOMEM;
900 }
cc692a5f 901
63f4898a
RW		 902 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
903
cc692a5f
SH		 904 return 0;
905}
906
907static void pci_restore_pcix_state(struct pci_dev *dev)
908{
909 int i = 0, pos;
910 struct pci_cap_saved_state *save_state;
911 u16 *cap;
912
913 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
914 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
915 if (!save_state || pos <= 0)
916 return;
917 cap = (u16 *)&save_state->data[0];
918
919 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 920}
921
922
1da177e4
LT		 923/**
924 * pci_save_state - save the PCI configuration space of a device before suspending
925 * @dev: - PCI device that we're dealing with
1da177e4
LT		 926 */
927int
928pci_save_state(struct pci_dev *dev)
929{
930 int i;
931 /* XXX: 100% dword access ok here? */
932 for (i = 0; i < 16; i++)
9e0b5b2c 933 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 934 dev->state_saved = true;
b56a5a23
MT		 935 if ((i = pci_save_pcie_state(dev)) != 0)
936 return i;
cc692a5f
SH		 937 if ((i = pci_save_pcix_state(dev)) != 0)
938 return i;
1da177e4
LT		 939 return 0;
940}
941
942/**
943 * pci_restore_state - Restore the saved state of a PCI device
944 * @dev: - PCI device that we're dealing with
1da177e4 945 */
1d3c16a8 946void pci_restore_state(struct pci_dev *dev)
1da177e4
LT		 947{
948 int i;
b4482a4b 949 u32 val;
1da177e4 950
c82f63e4 951 if (!dev->state_saved)
1d3c16a8 952 return;
4b77b0a2 953
b56a5a23
MT		 954 /* PCI Express register must be restored first */
955 pci_restore_pcie_state(dev);
956
8b8c8d28
YL		 957 /*
958 * The Base Address register should be programmed before the command
959 * register(s)
960 */
961 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 962 pci_read_config_dword(dev, i * 4, &val);
963 if (val != dev->saved_config_space[i]) {
80ccba11
BH		 964 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
965 "space at offset %#x (was %#x, writing %#x)\n",
966 i, val, (int)dev->saved_config_space[i]);
04d9c1a1
DJ		 967 pci_write_config_dword(dev,i * 4,
968 dev->saved_config_space[i]);
969 }
970 }
cc692a5f 971 pci_restore_pcix_state(dev);
41017f0c 972 pci_restore_msi_state(dev);
8c5cdb6a 973 pci_restore_iov_state(dev);
8fed4b65 974
4b77b0a2 975 dev->state_saved = false;
1da177e4
LT		 976}
977
38cc1302
HS		 978static int do_pci_enable_device(struct pci_dev *dev, int bars)
979{
980 int err;
981
982 err = pci_set_power_state(dev, PCI_D0);
983 if (err < 0 && err != -EIO)
984 return err;
985 err = pcibios_enable_device(dev, bars);
986 if (err < 0)
987 return err;
988 pci_fixup_device(pci_fixup_enable, dev);
989
990 return 0;
991}
992
993/**
0b62e13b 994 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 995 * @dev: PCI device to be resumed
996 *
997 * Note this function is a backend of pci_default_resume and is not supposed
998 * to be called by normal code, write proper resume handler and use it instead.
999 */
0b62e13b 1000int pci_reenable_device(struct pci_dev *dev)
38cc1302 1001{
296ccb08 1002 if (pci_is_enabled(dev))
38cc1302
HS		 1003 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1004 return 0;
1005}
1006
b718989d
BH		 1007static int __pci_enable_device_flags(struct pci_dev *dev,
1008 resource_size_t flags)
1da177e4
LT		 1009{
1010 int err;
b718989d 1011 int i, bars = 0;
1da177e4 1012
97c145f7
JB		 1013 /*
1014 * Power state could be unknown at this point, either due to a fresh
1015 * boot or a device removal call. So get the current power state
1016 * so that things like MSI message writing will behave as expected
1017 * (e.g. if the device really is in D0 at enable time).
1018 */
1019 if (dev->pm_cap) {
1020 u16 pmcsr;
1021 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1022 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1023 }
1024
9fb625c3
HS		 1025 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1026 return 0; /* already enabled */
1027
b718989d
BH		 1028 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1029 if (dev->resource[i].flags & flags)
1030 bars |= (1 << i);
1031
38cc1302 1032 err = do_pci_enable_device(dev, bars);
95a62965 1033 if (err < 0)
38cc1302 1034 atomic_dec(&dev->enable_cnt);
9fb625c3 1035 return err;
1da177e4
LT		 1036}
1037
b718989d
BH		 1038/**
1039 * pci_enable_device_io - Initialize a device for use with IO space
1040 * @dev: PCI device to be initialized
1041 *
1042 * Initialize device before it's used by a driver. Ask low-level code
1043 * to enable I/O resources. Wake up the device if it was suspended.
1044 * Beware, this function can fail.
1045 */
1046int pci_enable_device_io(struct pci_dev *dev)
1047{
1048 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1049}
1050
1051/**
1052 * pci_enable_device_mem - Initialize a device for use with Memory space
1053 * @dev: PCI device to be initialized
1054 *
1055 * Initialize device before it's used by a driver. Ask low-level code
1056 * to enable Memory resources. Wake up the device if it was suspended.
1057 * Beware, this function can fail.
1058 */
1059int pci_enable_device_mem(struct pci_dev *dev)
1060{
1061 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1062}
1063
bae94d02
IPG		 1064/**
1065 * pci_enable_device - Initialize device before it's used by a driver.
1066 * @dev: PCI device to be initialized
1067 *
1068 * Initialize device before it's used by a driver. Ask low-level code
1069 * to enable I/O and memory. Wake up the device if it was suspended.
1070 * Beware, this function can fail.
1071 *
1072 * Note we don't actually enable the device many times if we call
1073 * this function repeatedly (we just increment the count).
1074 */
1075int pci_enable_device(struct pci_dev *dev)
1076{
b718989d 1077 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1078}
1079
9ac7849e
TH		 1080/*
1081 * Managed PCI resources. This manages device on/off, intx/msi/msix
1082 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1083 * there's no need to track it separately. pci_devres is initialized
1084 * when a device is enabled using managed PCI device enable interface.
1085 */
1086struct pci_devres {
7f375f32
TH		 1087 unsigned int enabled:1;
1088 unsigned int pinned:1;
9ac7849e
TH		 1089 unsigned int orig_intx:1;
1090 unsigned int restore_intx:1;
1091 u32 region_mask;
1092};
1093
1094static void pcim_release(struct device *gendev, void *res)
1095{
1096 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1097 struct pci_devres *this = res;
1098 int i;
1099
1100 if (dev->msi_enabled)
1101 pci_disable_msi(dev);
1102 if (dev->msix_enabled)
1103 pci_disable_msix(dev);
1104
1105 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1106 if (this->region_mask & (1 << i))
1107 pci_release_region(dev, i);
1108
1109 if (this->restore_intx)
1110 pci_intx(dev, this->orig_intx);
1111
7f375f32 1112 if (this->enabled && !this->pinned)
9ac7849e
TH		 1113 pci_disable_device(dev);
1114}
1115
1116static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1117{
1118 struct pci_devres *dr, *new_dr;
1119
1120 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1121 if (dr)
1122 return dr;
1123
1124 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1125 if (!new_dr)
1126 return NULL;
1127 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1128}
1129
1130static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1131{
1132 if (pci_is_managed(pdev))
1133 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1134 return NULL;
1135}
1136
1137/**
1138 * pcim_enable_device - Managed pci_enable_device()
1139 * @pdev: PCI device to be initialized
1140 *
1141 * Managed pci_enable_device().
1142 */
1143int pcim_enable_device(struct pci_dev *pdev)
1144{
1145 struct pci_devres *dr;
1146 int rc;
1147
1148 dr = get_pci_dr(pdev);
1149 if (unlikely(!dr))
1150 return -ENOMEM;
b95d58ea
TH		 1151 if (dr->enabled)
1152 return 0;
9ac7849e
TH		 1153
1154 rc = pci_enable_device(pdev);
1155 if (!rc) {
1156 pdev->is_managed = 1;
7f375f32 1157 dr->enabled = 1;
9ac7849e
TH		 1158 }
1159 return rc;
1160}
1161
1162/**
1163 * pcim_pin_device - Pin managed PCI device
1164 * @pdev: PCI device to pin
1165 *
1166 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1167 * driver detach. @pdev must have been enabled with
1168 * pcim_enable_device().
1169 */
1170void pcim_pin_device(struct pci_dev *pdev)
1171{
1172 struct pci_devres *dr;
1173
1174 dr = find_pci_dr(pdev);
7f375f32 1175 WARN_ON(!dr || !dr->enabled);
9ac7849e 1176 if (dr)
7f375f32 1177 dr->pinned = 1;
9ac7849e
TH		 1178}
1179
1da177e4
LT		 1180/**
1181 * pcibios_disable_device - disable arch specific PCI resources for device dev
1182 * @dev: the PCI device to disable
1183 *
1184 * Disables architecture specific PCI resources for the device. This
1185 * is the default implementation. Architecture implementations can
1186 * override this.
1187 */
1188void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1189
fa58d305
RW		 1190static void do_pci_disable_device(struct pci_dev *dev)
1191{
1192 u16 pci_command;
1193
1194 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1195 if (pci_command & PCI_COMMAND_MASTER) {
1196 pci_command &= ~PCI_COMMAND_MASTER;
1197 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1198 }
1199
1200 pcibios_disable_device(dev);
1201}
1202
1203/**
1204 * pci_disable_enabled_device - Disable device without updating enable_cnt
1205 * @dev: PCI device to disable
1206 *
1207 * NOTE: This function is a backend of PCI power management routines and is
1208 * not supposed to be called drivers.
1209 */
1210void pci_disable_enabled_device(struct pci_dev *dev)
1211{
296ccb08 1212 if (pci_is_enabled(dev))
fa58d305
RW		 1213 do_pci_disable_device(dev);
1214}
1215
1da177e4
LT		 1216/**
1217 * pci_disable_device - Disable PCI device after use
1218 * @dev: PCI device to be disabled
1219 *
1220 * Signal to the system that the PCI device is not in use by the system
1221 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1222 *
1223 * Note we don't actually disable the device until all callers of
ee6583f6 1224 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1225 */
1226void
1227pci_disable_device(struct pci_dev *dev)
1228{
9ac7849e 1229 struct pci_devres *dr;
99dc804d 1230
9ac7849e
TH		 1231 dr = find_pci_dr(dev);
1232 if (dr)
7f375f32 1233 dr->enabled = 0;
9ac7849e 1234
bae94d02
IPG		 1235 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1236 return;
1237
fa58d305 1238 do_pci_disable_device(dev);
1da177e4 1239
fa58d305 1240 dev->is_busmaster = 0;
1da177e4
LT		 1241}
1242
f7bdd12d
BK		 1243/**
1244 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1245 * @dev: the PCIe device reset
f7bdd12d
BK		 1246 * @state: Reset state to enter into
1247 *
1248 *
45e829ea 1249 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1250 * implementation. Architecture implementations can override this.
1251 */
1252int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1253 enum pcie_reset_state state)
1254{
1255 return -EINVAL;
1256}
1257
1258/**
1259 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1260 * @dev: the PCIe device reset
f7bdd12d
BK		 1261 * @state: Reset state to enter into
1262 *
1263 *
1264 * Sets the PCI reset state for the device.
1265 */
1266int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1267{
1268 return pcibios_set_pcie_reset_state(dev, state);
1269}
1270
58ff4633
RW		 1271/**
1272 * pci_check_pme_status - Check if given device has generated PME.
1273 * @dev: Device to check.
1274 *
1275 * Check the PME status of the device and if set, clear it and clear PME enable
1276 * (if set). Return 'true' if PME status and PME enable were both set or
1277 * 'false' otherwise.
1278 */
1279bool pci_check_pme_status(struct pci_dev *dev)
1280{
1281 int pmcsr_pos;
1282 u16 pmcsr;
1283 bool ret = false;
1284
1285 if (!dev->pm_cap)
1286 return false;
1287
1288 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1289 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1290 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1291 return false;
1292
1293 /* Clear PME status. */
1294 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1295 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1296 /* Disable PME to avoid interrupt flood. */
1297 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1298 ret = true;
1299 }
1300
1301 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1302
1303 return ret;
1304}
1305
b67ea761
RW		 1306/**
1307 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1308 * @dev: Device to handle.
1309 * @ign: Ignored.
1310 *
1311 * Check if @dev has generated PME and queue a resume request for it in that
1312 * case.
1313 */
1314static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1315{
c125e96f 1316 if (pci_check_pme_status(dev)) {
c125e96f 1317 pci_wakeup_event(dev);
0f953bf6 1318 pm_request_resume(&dev->dev);
c125e96f 1319 }
b67ea761
RW		 1320 return 0;
1321}
1322
1323/**
1324 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1325 * @bus: Top bus of the subtree to walk.
1326 */
1327void pci_pme_wakeup_bus(struct pci_bus *bus)
1328{
1329 if (bus)
1330 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1331}
1332
eb9d0fe4
RW		 1333/**
1334 * pci_pme_capable - check the capability of PCI device to generate PME#
1335 * @dev: PCI device to handle.
eb9d0fe4
RW		 1336 * @state: PCI state from which device will issue PME#.
1337 */
e5899e1b 1338bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1339{
337001b6 1340 if (!dev->pm_cap)
eb9d0fe4
RW		 1341 return false;
1342
337001b6 1343 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1344}
1345
df17e62e
MG		 1346static void pci_pme_list_scan(struct work_struct *work)
1347{
1348 struct pci_pme_device *pme_dev;
1349
1350 mutex_lock(&pci_pme_list_mutex);
1351 if (!list_empty(&pci_pme_list)) {
1352 list_for_each_entry(pme_dev, &pci_pme_list, list)
1353 pci_pme_wakeup(pme_dev->dev, NULL);
1354 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1355 }
1356 mutex_unlock(&pci_pme_list_mutex);
1357}
1358
1359/**
1360 * pci_external_pme - is a device an external PCI PME source?
1361 * @dev: PCI device to check
1362 *
1363 */
1364
1365static bool pci_external_pme(struct pci_dev *dev)
1366{
1367 if (pci_is_pcie(dev) || dev->bus->number == 0)
1368 return false;
1369 return true;
1370}
1371
eb9d0fe4
RW		 1372/**
1373 * pci_pme_active - enable or disable PCI device's PME# function
1374 * @dev: PCI device to handle.
eb9d0fe4
RW		 1375 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1376 *
1377 * The caller must verify that the device is capable of generating PME# before
1378 * calling this function with @enable equal to 'true'.
1379 */
5a6c9b60 1380void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1381{
1382 u16 pmcsr;
1383
337001b6 1384 if (!dev->pm_cap)
eb9d0fe4
RW		 1385 return;
1386
337001b6 1387 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1388 /* Clear PME_Status by writing 1 to it and enable PME# */
1389 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1390 if (!enable)
1391 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1392
337001b6 1393 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1394
df17e62e
MG		 1395 /* PCI (as opposed to PCIe) PME requires that the device have
1396 its PME# line hooked up correctly. Not all hardware vendors
1397 do this, so the PME never gets delivered and the device
1398 remains asleep. The easiest way around this is to
1399 periodically walk the list of suspended devices and check
1400 whether any have their PME flag set. The assumption is that
1401 we'll wake up often enough anyway that this won't be a huge
1402 hit, and the power savings from the devices will still be a
1403 win. */
1404
1405 if (pci_external_pme(dev)) {
1406 struct pci_pme_device *pme_dev;
1407 if (enable) {
1408 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1409 GFP_KERNEL);
1410 if (!pme_dev)
1411 goto out;
1412 pme_dev->dev = dev;
1413 mutex_lock(&pci_pme_list_mutex);
1414 list_add(&pme_dev->list, &pci_pme_list);
1415 if (list_is_singular(&pci_pme_list))
1416 schedule_delayed_work(&pci_pme_work,
1417 msecs_to_jiffies(PME_TIMEOUT));
1418 mutex_unlock(&pci_pme_list_mutex);
1419 } else {
1420 mutex_lock(&pci_pme_list_mutex);
1421 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1422 if (pme_dev->dev == dev) {
1423 list_del(&pme_dev->list);
1424 kfree(pme_dev);
1425 break;
1426 }
1427 }
1428 mutex_unlock(&pci_pme_list_mutex);
1429 }
1430 }
1431
1432out:
10c3d71d 1433 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
eb9d0fe4
RW		 1434 enable ? "enabled" : "disabled");
1435}
1436
1da177e4 1437/**
6cbf8214 1438 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1439 * @dev: PCI device affected
1440 * @state: PCI state from which device will issue wakeup events
6cbf8214 1441 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1442 * @enable: True to enable event generation; false to disable
1443 *
1444 * This enables the device as a wakeup event source, or disables it.
1445 * When such events involves platform-specific hooks, those hooks are
1446 * called automatically by this routine.
1447 *
1448 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1449 * always require such platform hooks.
075c1771 1450 *
eb9d0fe4
RW		 1451 * RETURN VALUE:
1452 * 0 is returned on success
1453 * -EINVAL is returned if device is not supposed to wake up the system
1454 * Error code depending on the platform is returned if both the platform and
1455 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1456 */
6cbf8214
RW		 1457int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1458 bool runtime, bool enable)
1da177e4 1459{
5bcc2fb4 1460 int ret = 0;
075c1771 1461
6cbf8214 1462 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1463 return -EINVAL;
1da177e4 1464
e80bb09d
RW		 1465 /* Don't do the same thing twice in a row for one device. */
1466 if (!!enable == !!dev->wakeup_prepared)
1467 return 0;
1468
eb9d0fe4
RW		 1469 /*
1470 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1471 * Anderson we should be doing PME# wake enable followed by ACPI wake
1472 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1473 */
1da177e4 1474
5bcc2fb4
RW		 1475 if (enable) {
1476 int error;
1da177e4 1477
5bcc2fb4
RW		 1478 if (pci_pme_capable(dev, state))
1479 pci_pme_active(dev, true);
1480 else
1481 ret = 1;
6cbf8214
RW		 1482 error = runtime ? platform_pci_run_wake(dev, true) :
1483 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1484 if (ret)
1485 ret = error;
e80bb09d
RW		 1486 if (!ret)
1487 dev->wakeup_prepared = true;
5bcc2fb4 1488 } else {
6cbf8214
RW		 1489 if (runtime)
1490 platform_pci_run_wake(dev, false);
1491 else
1492 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1493 pci_pme_active(dev, false);
e80bb09d 1494 dev->wakeup_prepared = false;
5bcc2fb4 1495 }
1da177e4 1496
5bcc2fb4 1497 return ret;
eb9d0fe4 1498}
6cbf8214 1499EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1500
0235c4fc
RW		 1501/**
1502 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1503 * @dev: PCI device to prepare
1504 * @enable: True to enable wake-up event generation; false to disable
1505 *
1506 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1507 * and this function allows them to set that up cleanly - pci_enable_wake()
1508 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1509 * ordering constraints.
1510 *
1511 * This function only returns error code if the device is not capable of
1512 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1513 * enable wake-up power for it.
1514 */
1515int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1516{
1517 return pci_pme_capable(dev, PCI_D3cold) ?
1518 pci_enable_wake(dev, PCI_D3cold, enable) :
1519 pci_enable_wake(dev, PCI_D3hot, enable);
1520}
1521
404cc2d8 1522/**
37139074
JB		 1523 * pci_target_state - find an appropriate low power state for a given PCI dev
1524 * @dev: PCI device
1525 *
1526 * Use underlying platform code to find a supported low power state for @dev.
1527 * If the platform can't manage @dev, return the deepest state from which it
1528 * can generate wake events, based on any available PME info.
404cc2d8 1529 */
e5899e1b 1530pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1531{
1532 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1533
1534 if (platform_pci_power_manageable(dev)) {
1535 /*
1536 * Call the platform to choose the target state of the device
1537 * and enable wake-up from this state if supported.
1538 */
1539 pci_power_t state = platform_pci_choose_state(dev);
1540
1541 switch (state) {
1542 case PCI_POWER_ERROR:
1543 case PCI_UNKNOWN:
1544 break;
1545 case PCI_D1:
1546 case PCI_D2:
1547 if (pci_no_d1d2(dev))
1548 break;
1549 default:
1550 target_state = state;
404cc2d8 1551 }
d2abdf62
RW		 1552 } else if (!dev->pm_cap) {
1553 target_state = PCI_D0;
404cc2d8
RW		 1554 } else if (device_may_wakeup(&dev->dev)) {
1555 /*
1556 * Find the deepest state from which the device can generate
1557 * wake-up events, make it the target state and enable device
1558 * to generate PME#.
1559 */
337001b6
RW		 1560 if (dev->pme_support) {
1561 while (target_state
1562 && !(dev->pme_support & (1 << target_state)))
1563 target_state--;
404cc2d8
RW		 1564 }
1565 }
1566
e5899e1b
RW		 1567 return target_state;
1568}
1569
1570/**
1571 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1572 * @dev: Device to handle.
1573 *
1574 * Choose the power state appropriate for the device depending on whether
1575 * it can wake up the system and/or is power manageable by the platform
1576 * (PCI_D3hot is the default) and put the device into that state.
1577 */
1578int pci_prepare_to_sleep(struct pci_dev *dev)
1579{
1580 pci_power_t target_state = pci_target_state(dev);
1581 int error;
1582
1583 if (target_state == PCI_POWER_ERROR)
1584 return -EIO;
1585
8efb8c76 1586 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1587
404cc2d8
RW		 1588 error = pci_set_power_state(dev, target_state);
1589
1590 if (error)
1591 pci_enable_wake(dev, target_state, false);
1592
1593 return error;
1594}
1595
1596/**
443bd1c4 1597 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1598 * @dev: Device to handle.
1599 *
88393161 1600 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1601 */
1602int pci_back_from_sleep(struct pci_dev *dev)
1603{
1604 pci_enable_wake(dev, PCI_D0, false);
1605 return pci_set_power_state(dev, PCI_D0);
1606}
1607
6cbf8214
RW		 1608/**
1609 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1610 * @dev: PCI device being suspended.
1611 *
1612 * Prepare @dev to generate wake-up events at run time and put it into a low
1613 * power state.
1614 */
1615int pci_finish_runtime_suspend(struct pci_dev *dev)
1616{
1617 pci_power_t target_state = pci_target_state(dev);
1618 int error;
1619
1620 if (target_state == PCI_POWER_ERROR)
1621 return -EIO;
1622
1623 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1624
1625 error = pci_set_power_state(dev, target_state);
1626
1627 if (error)
1628 __pci_enable_wake(dev, target_state, true, false);
1629
1630 return error;
1631}
1632
b67ea761
RW		 1633/**
1634 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1635 * @dev: Device to check.
1636 *
1637 * Return true if the device itself is cabable of generating wake-up events
1638 * (through the platform or using the native PCIe PME) or if the device supports
1639 * PME and one of its upstream bridges can generate wake-up events.
1640 */
1641bool pci_dev_run_wake(struct pci_dev *dev)
1642{
1643 struct pci_bus *bus = dev->bus;
1644
1645 if (device_run_wake(&dev->dev))
1646 return true;
1647
1648 if (!dev->pme_support)
1649 return false;
1650
1651 while (bus->parent) {
1652 struct pci_dev *bridge = bus->self;
1653
1654 if (device_run_wake(&bridge->dev))
1655 return true;
1656
1657 bus = bus->parent;
1658 }
1659
1660 /* We have reached the root bus. */
1661 if (bus->bridge)
1662 return device_run_wake(bus->bridge);
1663
1664 return false;
1665}
1666EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1667
eb9d0fe4
RW		 1668/**
1669 * pci_pm_init - Initialize PM functions of given PCI device
1670 * @dev: PCI device to handle.
1671 */
1672void pci_pm_init(struct pci_dev *dev)
1673{
1674 int pm;
1675 u16 pmc;
1da177e4 1676
bb910a70 1677 pm_runtime_forbid(&dev->dev);
a1e4d72c 1678 device_enable_async_suspend(&dev->dev);
e80bb09d 1679 dev->wakeup_prepared = false;
bb910a70 1680
337001b6
RW		 1681 dev->pm_cap = 0;
1682
eb9d0fe4
RW		 1683 /* find PCI PM capability in list */
1684 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1685 if (!pm)
50246dd4 1686 return;
eb9d0fe4
RW		 1687 /* Check device's ability to generate PME# */
1688 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1689
eb9d0fe4
RW		 1690 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1691 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1692 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1693 return;
eb9d0fe4
RW		 1694 }
1695
337001b6 1696 dev->pm_cap = pm;
1ae861e6 1697 dev->d3_delay = PCI_PM_D3_WAIT;
337001b6
RW		 1698
1699 dev->d1_support = false;
1700 dev->d2_support = false;
1701 if (!pci_no_d1d2(dev)) {
c9ed77ee 1702 if (pmc & PCI_PM_CAP_D1)
337001b6 1703 dev->d1_support = true;
c9ed77ee 1704 if (pmc & PCI_PM_CAP_D2)
337001b6 1705 dev->d2_support = true;
c9ed77ee
BH		 1706
1707 if (dev->d1_support || dev->d2_support)
1708 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1709 dev->d1_support ? " D1" : "",
1710 dev->d2_support ? " D2" : "");
337001b6
RW		 1711 }
1712
1713 pmc &= PCI_PM_CAP_PME_MASK;
1714 if (pmc) {
10c3d71d
BH		 1715 dev_printk(KERN_DEBUG, &dev->dev,
1716 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1717 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1718 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1719 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1720 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1721 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1722 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
eb9d0fe4
RW		 1723 /*
1724 * Make device's PM flags reflect the wake-up capability, but
1725 * let the user space enable it to wake up the system as needed.
1726 */
1727 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 1728 /* Disable the PME# generation functionality */
337001b6
RW		 1729 pci_pme_active(dev, false);
1730 } else {
1731 dev->pme_support = 0;
eb9d0fe4 1732 }
1da177e4
LT		 1733}
1734
eb9c39d0
JB		 1735/**
1736 * platform_pci_wakeup_init - init platform wakeup if present
1737 * @dev: PCI device
1738 *
1739 * Some devices don't have PCI PM caps but can still generate wakeup
1740 * events through platform methods (like ACPI events). If @dev supports
1741 * platform wakeup events, set the device flag to indicate as much. This
1742 * may be redundant if the device also supports PCI PM caps, but double
1743 * initialization should be safe in that case.
1744 */
1745void platform_pci_wakeup_init(struct pci_dev *dev)
1746{
1747 if (!platform_pci_can_wakeup(dev))
1748 return;
1749
1750 device_set_wakeup_capable(&dev->dev, true);
eb9c39d0
JB		 1751 platform_pci_sleep_wake(dev, false);
1752}
1753
63f4898a
RW		 1754/**
1755 * pci_add_save_buffer - allocate buffer for saving given capability registers
1756 * @dev: the PCI device
1757 * @cap: the capability to allocate the buffer for
1758 * @size: requested size of the buffer
1759 */
1760static int pci_add_cap_save_buffer(
1761 struct pci_dev *dev, char cap, unsigned int size)
1762{
1763 int pos;
1764 struct pci_cap_saved_state *save_state;
1765
1766 pos = pci_find_capability(dev, cap);
1767 if (pos <= 0)
1768 return 0;
1769
1770 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1771 if (!save_state)
1772 return -ENOMEM;
1773
1774 save_state->cap_nr = cap;
1775 pci_add_saved_cap(dev, save_state);
1776
1777 return 0;
1778}
1779
1780/**
1781 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1782 * @dev: the PCI device
1783 */
1784void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1785{
1786 int error;
1787
89858517
YZ		 1788 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1789 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 1790 if (error)
1791 dev_err(&dev->dev,
1792 "unable to preallocate PCI Express save buffer\n");
1793
1794 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1795 if (error)
1796 dev_err(&dev->dev,
1797 "unable to preallocate PCI-X save buffer\n");
1798}
1799
58c3a727
YZ		 1800/**
1801 * pci_enable_ari - enable ARI forwarding if hardware support it
1802 * @dev: the PCI device
1803 */
1804void pci_enable_ari(struct pci_dev *dev)
1805{
1806 int pos;
1807 u32 cap;
1808 u16 ctrl;
8113587c 1809 struct pci_dev *bridge;
58c3a727 1810
5f4d91a1 1811 if (!pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 1812 return;
1813
8113587c
ZY		 1814 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1815 if (!pos)
58c3a727
YZ		 1816 return;
1817
8113587c 1818 bridge = dev->bus->self;
5f4d91a1 1819 if (!bridge || !pci_is_pcie(bridge))
8113587c
ZY		 1820 return;
1821
06a1cbaf 1822 pos = pci_pcie_cap(bridge);
58c3a727
YZ		 1823 if (!pos)
1824 return;
1825
8113587c 1826 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 1827 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1828 return;
1829
8113587c 1830 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
58c3a727 1831 ctrl |= PCI_EXP_DEVCTL2_ARI;
8113587c 1832 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
58c3a727 1833
8113587c 1834 bridge->ari_enabled = 1;
58c3a727
YZ		 1835}
1836
b48d4425
JB		 1837/**
1838 * pci_enable_ido - enable ID-based ordering on a device
1839 * @dev: the PCI device
1840 * @type: which types of IDO to enable
1841 *
1842 * Enable ID-based ordering on @dev. @type can contain the bits
1843 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1844 * which types of transactions are allowed to be re-ordered.
1845 */
1846void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1847{
1848 int pos;
1849 u16 ctrl;
1850
1851 pos = pci_pcie_cap(dev);
1852 if (!pos)
1853 return;
1854
1855 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1856 if (type & PCI_EXP_IDO_REQUEST)
1857 ctrl |= PCI_EXP_IDO_REQ_EN;
1858 if (type & PCI_EXP_IDO_COMPLETION)
1859 ctrl |= PCI_EXP_IDO_CMP_EN;
1860 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1861}
1862EXPORT_SYMBOL(pci_enable_ido);
1863
1864/**
1865 * pci_disable_ido - disable ID-based ordering on a device
1866 * @dev: the PCI device
1867 * @type: which types of IDO to disable
1868 */
1869void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1870{
1871 int pos;
1872 u16 ctrl;
1873
1874 if (!pci_is_pcie(dev))
1875 return;
1876
1877 pos = pci_pcie_cap(dev);
1878 if (!pos)
1879 return;
1880
1881 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1882 if (type & PCI_EXP_IDO_REQUEST)
1883 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1884 if (type & PCI_EXP_IDO_COMPLETION)
1885 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1886 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1887}
1888EXPORT_SYMBOL(pci_disable_ido);
1889
48a92a81
JB		 1890/**
1891 * pci_enable_obff - enable optimized buffer flush/fill
1892 * @dev: PCI device
1893 * @type: type of signaling to use
1894 *
1895 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
1896 * signaling if possible, falling back to message signaling only if
1897 * WAKE# isn't supported. @type should indicate whether the PCIe link
1898 * be brought out of L0s or L1 to send the message. It should be either
1899 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
1900 *
1901 * If your device can benefit from receiving all messages, even at the
1902 * power cost of bringing the link back up from a low power state, use
1903 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
1904 * preferred type).
1905 *
1906 * RETURNS:
1907 * Zero on success, appropriate error number on failure.
1908 */
1909int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
1910{
1911 int pos;
1912 u32 cap;
1913 u16 ctrl;
1914 int ret;
1915
1916 if (!pci_is_pcie(dev))
1917 return -ENOTSUPP;
1918
1919 pos = pci_pcie_cap(dev);
1920 if (!pos)
1921 return -ENOTSUPP;
1922
1923 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
1924 if (!(cap & PCI_EXP_OBFF_MASK))
1925 return -ENOTSUPP; /* no OBFF support at all */
1926
1927 /* Make sure the topology supports OBFF as well */
1928 if (dev->bus) {
1929 ret = pci_enable_obff(dev->bus->self, type);
1930 if (ret)
1931 return ret;
1932 }
1933
1934 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1935 if (cap & PCI_EXP_OBFF_WAKE)
1936 ctrl |= PCI_EXP_OBFF_WAKE_EN;
1937 else {
1938 switch (type) {
1939 case PCI_EXP_OBFF_SIGNAL_L0:
1940 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
1941 ctrl |= PCI_EXP_OBFF_MSGA_EN;
1942 break;
1943 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
1944 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
1945 ctrl |= PCI_EXP_OBFF_MSGB_EN;
1946 break;
1947 default:
1948 WARN(1, "bad OBFF signal type\n");
1949 return -ENOTSUPP;
1950 }
1951 }
1952 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1953
1954 return 0;
1955}
1956EXPORT_SYMBOL(pci_enable_obff);
1957
1958/**
1959 * pci_disable_obff - disable optimized buffer flush/fill
1960 * @dev: PCI device
1961 *
1962 * Disable OBFF on @dev.
1963 */
1964void pci_disable_obff(struct pci_dev *dev)
1965{
1966 int pos;
1967 u16 ctrl;
1968
1969 if (!pci_is_pcie(dev))
1970 return;
1971
1972 pos = pci_pcie_cap(dev);
1973 if (!pos)
1974 return;
1975
1976 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1977 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
1978 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1979}
1980EXPORT_SYMBOL(pci_disable_obff);
1981
51c2e0a7
JB		 1982/**
1983 * pci_ltr_supported - check whether a device supports LTR
1984 * @dev: PCI device
1985 *
1986 * RETURNS:
1987 * True if @dev supports latency tolerance reporting, false otherwise.
1988 */
1989bool pci_ltr_supported(struct pci_dev *dev)
1990{
1991 int pos;
1992 u32 cap;
1993
1994 if (!pci_is_pcie(dev))
1995 return false;
1996
1997 pos = pci_pcie_cap(dev);
1998 if (!pos)
1999 return false;
2000
2001 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2002
2003 return cap & PCI_EXP_DEVCAP2_LTR;
2004}
2005EXPORT_SYMBOL(pci_ltr_supported);
2006
2007/**
2008 * pci_enable_ltr - enable latency tolerance reporting
2009 * @dev: PCI device
2010 *
2011 * Enable LTR on @dev if possible, which means enabling it first on
2012 * upstream ports.
2013 *
2014 * RETURNS:
2015 * Zero on success, errno on failure.
2016 */
2017int pci_enable_ltr(struct pci_dev *dev)
2018{
2019 int pos;
2020 u16 ctrl;
2021 int ret;
2022
2023 if (!pci_ltr_supported(dev))
2024 return -ENOTSUPP;
2025
2026 pos = pci_pcie_cap(dev);
2027 if (!pos)
2028 return -ENOTSUPP;
2029
2030 /* Only primary function can enable/disable LTR */
2031 if (PCI_FUNC(dev->devfn) != 0)
2032 return -EINVAL;
2033
2034 /* Enable upstream ports first */
2035 if (dev->bus) {
2036 ret = pci_enable_ltr(dev->bus->self);
2037 if (ret)
2038 return ret;
2039 }
2040
2041 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2042 ctrl |= PCI_EXP_LTR_EN;
2043 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2044
2045 return 0;
2046}
2047EXPORT_SYMBOL(pci_enable_ltr);
2048
2049/**
2050 * pci_disable_ltr - disable latency tolerance reporting
2051 * @dev: PCI device
2052 */
2053void pci_disable_ltr(struct pci_dev *dev)
2054{
2055 int pos;
2056 u16 ctrl;
2057
2058 if (!pci_ltr_supported(dev))
2059 return;
2060
2061 pos = pci_pcie_cap(dev);
2062 if (!pos)
2063 return;
2064
2065 /* Only primary function can enable/disable LTR */
2066 if (PCI_FUNC(dev->devfn) != 0)
2067 return;
2068
2069 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2070 ctrl &= ~PCI_EXP_LTR_EN;
2071 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2072}
2073EXPORT_SYMBOL(pci_disable_ltr);
2074
2075static int __pci_ltr_scale(int *val)
2076{
2077 int scale = 0;
2078
2079 while (*val > 1023) {
2080 *val = (*val + 31) / 32;
2081 scale++;
2082 }
2083 return scale;
2084}
2085
2086/**
2087 * pci_set_ltr - set LTR latency values
2088 * @dev: PCI device
2089 * @snoop_lat_ns: snoop latency in nanoseconds
2090 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2091 *
2092 * Figure out the scale and set the LTR values accordingly.
2093 */
2094int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2095{
2096 int pos, ret, snoop_scale, nosnoop_scale;
2097 u16 val;
2098
2099 if (!pci_ltr_supported(dev))
2100 return -ENOTSUPP;
2101
2102 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2103 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2104
2105 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2106 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2107 return -EINVAL;
2108
2109 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2110 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2111 return -EINVAL;
2112
2113 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2114 if (!pos)
2115 return -ENOTSUPP;
2116
2117 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2118 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2119 if (ret != 4)
2120 return -EIO;
2121
2122 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2123 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2124 if (ret != 4)
2125 return -EIO;
2126
2127 return 0;
2128}
2129EXPORT_SYMBOL(pci_set_ltr);
2130
5d990b62
CW		 2131static int pci_acs_enable;
2132
2133/**
2134 * pci_request_acs - ask for ACS to be enabled if supported
2135 */
2136void pci_request_acs(void)
2137{
2138 pci_acs_enable = 1;
2139}
2140
ae21ee65
AK		 2141/**
2142 * pci_enable_acs - enable ACS if hardware support it
2143 * @dev: the PCI device
2144 */
2145void pci_enable_acs(struct pci_dev *dev)
2146{
2147 int pos;
2148 u16 cap;
2149 u16 ctrl;
2150
5d990b62
CW		 2151 if (!pci_acs_enable)
2152 return;
2153
5f4d91a1 2154 if (!pci_is_pcie(dev))
ae21ee65
AK		 2155 return;
2156
2157 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2158 if (!pos)
2159 return;
2160
2161 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2162 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2163
2164 /* Source Validation */
2165 ctrl |= (cap & PCI_ACS_SV);
2166
2167 /* P2P Request Redirect */
2168 ctrl |= (cap & PCI_ACS_RR);
2169
2170 /* P2P Completion Redirect */
2171 ctrl |= (cap & PCI_ACS_CR);
2172
2173 /* Upstream Forwarding */
2174 ctrl |= (cap & PCI_ACS_UF);
2175
2176 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2177}
2178
57c2cf71
BH		 2179/**
2180 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2181 * @dev: the PCI device
2182 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2183 *
2184 * Perform INTx swizzling for a device behind one level of bridge. This is
2185 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2186 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2187 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2188 * the PCI Express Base Specification, Revision 2.1)
57c2cf71
BH		 2189 */
2190u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2191{
46b952a3
MW		 2192 int slot;
2193
2194 if (pci_ari_enabled(dev->bus))
2195 slot = 0;
2196 else
2197 slot = PCI_SLOT(dev->devfn);
2198
2199 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2200}
2201
1da177e4
LT		 2202int
2203pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2204{
2205 u8 pin;
2206
514d207d 2207 pin = dev->pin;
1da177e4
LT		 2208 if (!pin)
2209 return -1;
878f2e50 2210
8784fd4d 2211 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2212 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2213 dev = dev->bus->self;
2214 }
2215 *bridge = dev;
2216 return pin;
2217}
2218
68feac87
BH		 2219/**
2220 * pci_common_swizzle - swizzle INTx all the way to root bridge
2221 * @dev: the PCI device
2222 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2223 *
2224 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2225 * bridges all the way up to a PCI root bus.
2226 */
2227u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2228{
2229 u8 pin = *pinp;
2230
1eb39487 2231 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2232 pin = pci_swizzle_interrupt_pin(dev, pin);
2233 dev = dev->bus->self;
2234 }
2235 *pinp = pin;
2236 return PCI_SLOT(dev->devfn);
2237}
2238
1da177e4
LT		 2239/**
2240 * pci_release_region - Release a PCI bar
2241 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2242 * @bar: BAR to release
2243 *
2244 * Releases the PCI I/O and memory resources previously reserved by a
2245 * successful call to pci_request_region. Call this function only
2246 * after all use of the PCI regions has ceased.
2247 */
2248void pci_release_region(struct pci_dev *pdev, int bar)
2249{
9ac7849e
TH		 2250 struct pci_devres *dr;
2251
1da177e4
LT		 2252 if (pci_resource_len(pdev, bar) == 0)
2253 return;
2254 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2255 release_region(pci_resource_start(pdev, bar),
2256 pci_resource_len(pdev, bar));
2257 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2258 release_mem_region(pci_resource_start(pdev, bar),
2259 pci_resource_len(pdev, bar));
9ac7849e
TH		 2260
2261 dr = find_pci_dr(pdev);
2262 if (dr)
2263 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2264}
2265
2266/**
f5ddcac4 2267 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2268 * @pdev: PCI device whose resources are to be reserved
2269 * @bar: BAR to be reserved
2270 * @res_name: Name to be associated with resource.
f5ddcac4 2271 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2272 *
2273 * Mark the PCI region associated with PCI device @pdev BR @bar as
2274 * being reserved by owner @res_name. Do not access any
2275 * address inside the PCI regions unless this call returns
2276 * successfully.
2277 *
f5ddcac4
RD		 2278 * If @exclusive is set, then the region is marked so that userspace
2279 * is explicitly not allowed to map the resource via /dev/mem or
2280 * sysfs MMIO access.
2281 *
1da177e4
LT		 2282 * Returns 0 on success, or %EBUSY on error. A warning
2283 * message is also printed on failure.
2284 */
e8de1481
AV		 2285static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2286 int exclusive)
1da177e4 2287{
9ac7849e
TH		 2288 struct pci_devres *dr;
2289
1da177e4
LT		 2290 if (pci_resource_len(pdev, bar) == 0)
2291 return 0;
2292
2293 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2294 if (!request_region(pci_resource_start(pdev, bar),
2295 pci_resource_len(pdev, bar), res_name))
2296 goto err_out;
2297 }
2298 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2299 if (!__request_mem_region(pci_resource_start(pdev, bar),
2300 pci_resource_len(pdev, bar), res_name,
2301 exclusive))
1da177e4
LT		 2302 goto err_out;
2303 }
9ac7849e
TH		 2304
2305 dr = find_pci_dr(pdev);
2306 if (dr)
2307 dr->region_mask |= 1 << bar;
2308
1da177e4
LT		 2309 return 0;
2310
2311err_out:
c7dabef8 2312 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2313 &pdev->resource[bar]);
1da177e4
LT		 2314 return -EBUSY;
2315}
2316
e8de1481 2317/**
f5ddcac4 2318 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2319 * @pdev: PCI device whose resources are to be reserved
2320 * @bar: BAR to be reserved
f5ddcac4 2321 * @res_name: Name to be associated with resource
e8de1481 2322 *
f5ddcac4 2323 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2324 * being reserved by owner @res_name. Do not access any
2325 * address inside the PCI regions unless this call returns
2326 * successfully.
2327 *
2328 * Returns 0 on success, or %EBUSY on error. A warning
2329 * message is also printed on failure.
2330 */
2331int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2332{
2333 return __pci_request_region(pdev, bar, res_name, 0);
2334}
2335
2336/**
2337 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2338 * @pdev: PCI device whose resources are to be reserved
2339 * @bar: BAR to be reserved
2340 * @res_name: Name to be associated with resource.
2341 *
2342 * Mark the PCI region associated with PCI device @pdev BR @bar as
2343 * being reserved by owner @res_name. Do not access any
2344 * address inside the PCI regions unless this call returns
2345 * successfully.
2346 *
2347 * Returns 0 on success, or %EBUSY on error. A warning
2348 * message is also printed on failure.
2349 *
2350 * The key difference that _exclusive makes it that userspace is
2351 * explicitly not allowed to map the resource via /dev/mem or
2352 * sysfs.
2353 */
2354int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2355{
2356 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2357}
c87deff7
HS		 2358/**
2359 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2360 * @pdev: PCI device whose resources were previously reserved
2361 * @bars: Bitmask of BARs to be released
2362 *
2363 * Release selected PCI I/O and memory resources previously reserved.
2364 * Call this function only after all use of the PCI regions has ceased.
2365 */
2366void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2367{
2368 int i;
2369
2370 for (i = 0; i < 6; i++)
2371 if (bars & (1 << i))
2372 pci_release_region(pdev, i);
2373}
2374
e8de1481
AV		 2375int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2376 const char *res_name, int excl)
c87deff7
HS		 2377{
2378 int i;
2379
2380 for (i = 0; i < 6; i++)
2381 if (bars & (1 << i))
e8de1481 2382 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2383 goto err_out;
2384 return 0;
2385
2386err_out:
2387 while(--i >= 0)
2388 if (bars & (1 << i))
2389 pci_release_region(pdev, i);
2390
2391 return -EBUSY;
2392}
1da177e4 2393
e8de1481
AV		 2394
2395/**
2396 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2397 * @pdev: PCI device whose resources are to be reserved
2398 * @bars: Bitmask of BARs to be requested
2399 * @res_name: Name to be associated with resource
2400 */
2401int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2402 const char *res_name)
2403{
2404 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2405}
2406
2407int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2408 int bars, const char *res_name)
2409{
2410 return __pci_request_selected_regions(pdev, bars, res_name,
2411 IORESOURCE_EXCLUSIVE);
2412}
2413
1da177e4
LT		 2414/**
2415 * pci_release_regions - Release reserved PCI I/O and memory resources
2416 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2417 *
2418 * Releases all PCI I/O and memory resources previously reserved by a
2419 * successful call to pci_request_regions. Call this function only
2420 * after all use of the PCI regions has ceased.
2421 */
2422
2423void pci_release_regions(struct pci_dev *pdev)
2424{
c87deff7 2425 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2426}
2427
2428/**
2429 * pci_request_regions - Reserved PCI I/O and memory resources
2430 * @pdev: PCI device whose resources are to be reserved
2431 * @res_name: Name to be associated with resource.
2432 *
2433 * Mark all PCI regions associated with PCI device @pdev as
2434 * being reserved by owner @res_name. Do not access any
2435 * address inside the PCI regions unless this call returns
2436 * successfully.
2437 *
2438 * Returns 0 on success, or %EBUSY on error. A warning
2439 * message is also printed on failure.
2440 */
3c990e92 2441int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2442{
c87deff7 2443 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2444}
2445
e8de1481
AV		 2446/**
2447 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2448 * @pdev: PCI device whose resources are to be reserved
2449 * @res_name: Name to be associated with resource.
2450 *
2451 * Mark all PCI regions associated with PCI device @pdev as
2452 * being reserved by owner @res_name. Do not access any
2453 * address inside the PCI regions unless this call returns
2454 * successfully.
2455 *
2456 * pci_request_regions_exclusive() will mark the region so that
2457 * /dev/mem and the sysfs MMIO access will not be allowed.
2458 *
2459 * Returns 0 on success, or %EBUSY on error. A warning
2460 * message is also printed on failure.
2461 */
2462int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2463{
2464 return pci_request_selected_regions_exclusive(pdev,
2465 ((1 << 6) - 1), res_name);
2466}
2467
6a479079
BH		 2468static void __pci_set_master(struct pci_dev *dev, bool enable)
2469{
2470 u16 old_cmd, cmd;
2471
2472 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2473 if (enable)
2474 cmd = old_cmd | PCI_COMMAND_MASTER;
2475 else
2476 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2477 if (cmd != old_cmd) {
2478 dev_dbg(&dev->dev, "%s bus mastering\n",
2479 enable ? "enabling" : "disabling");
2480 pci_write_config_word(dev, PCI_COMMAND, cmd);
2481 }
2482 dev->is_busmaster = enable;
2483}
e8de1481 2484
1da177e4
LT		 2485/**
2486 * pci_set_master - enables bus-mastering for device dev
2487 * @dev: the PCI device to enable
2488 *
2489 * Enables bus-mastering on the device and calls pcibios_set_master()
2490 * to do the needed arch specific settings.
2491 */
6a479079 2492void pci_set_master(struct pci_dev *dev)
1da177e4 2493{
6a479079 2494 __pci_set_master(dev, true);
1da177e4
LT		 2495 pcibios_set_master(dev);
2496}
2497
6a479079
BH		 2498/**
2499 * pci_clear_master - disables bus-mastering for device dev
2500 * @dev: the PCI device to disable
2501 */
2502void pci_clear_master(struct pci_dev *dev)
2503{
2504 __pci_set_master(dev, false);
2505}
2506
1da177e4 2507/**
edb2d97e
MW		 2508 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2509 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2510 *
edb2d97e
MW		 2511 * Helper function for pci_set_mwi.
2512 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2513 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2514 *
2515 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2516 */
15ea76d4 2517int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2518{
2519 u8 cacheline_size;
2520
2521 if (!pci_cache_line_size)
15ea76d4 2522 return -EINVAL;
1da177e4
LT		 2523
2524 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2525 equal to or multiple of the right value. */
2526 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2527 if (cacheline_size >= pci_cache_line_size &&
2528 (cacheline_size % pci_cache_line_size) == 0)
2529 return 0;
2530
2531 /* Write the correct value. */
2532 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2533 /* Read it back. */
2534 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2535 if (cacheline_size == pci_cache_line_size)
2536 return 0;
2537
80ccba11
BH		 2538 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2539 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2540
2541 return -EINVAL;
2542}
15ea76d4
TH		 2543EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2544
2545#ifdef PCI_DISABLE_MWI
2546int pci_set_mwi(struct pci_dev *dev)
2547{
2548 return 0;
2549}
2550
2551int pci_try_set_mwi(struct pci_dev *dev)
2552{
2553 return 0;
2554}
2555
2556void pci_clear_mwi(struct pci_dev *dev)
2557{
2558}
2559
2560#else
1da177e4
LT		 2561
2562/**
2563 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2564 * @dev: the PCI device for which MWI is enabled
2565 *
694625c0 2566 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2567 *
2568 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2569 */
2570int
2571pci_set_mwi(struct pci_dev *dev)
2572{
2573 int rc;
2574 u16 cmd;
2575
edb2d97e 2576 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2577 if (rc)
2578 return rc;
2579
2580 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2581 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2582 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2583 cmd |= PCI_COMMAND_INVALIDATE;
2584 pci_write_config_word(dev, PCI_COMMAND, cmd);
2585 }
2586
2587 return 0;
2588}
2589
694625c0
RD		 2590/**
2591 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2592 * @dev: the PCI device for which MWI is enabled
2593 *
2594 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2595 * Callers are not required to check the return value.
2596 *
2597 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2598 */
2599int pci_try_set_mwi(struct pci_dev *dev)
2600{
2601 int rc = pci_set_mwi(dev);
2602 return rc;
2603}
2604
1da177e4
LT		 2605/**
2606 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2607 * @dev: the PCI device to disable
2608 *
2609 * Disables PCI Memory-Write-Invalidate transaction on the device
2610 */
2611void
2612pci_clear_mwi(struct pci_dev *dev)
2613{
2614 u16 cmd;
2615
2616 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2617 if (cmd & PCI_COMMAND_INVALIDATE) {
2618 cmd &= ~PCI_COMMAND_INVALIDATE;
2619 pci_write_config_word(dev, PCI_COMMAND, cmd);
2620 }
2621}
edb2d97e 2622#endif /* ! PCI_DISABLE_MWI */
1da177e4 2623
a04ce0ff
BR		 2624/**
2625 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2626 * @pdev: the PCI device to operate on
2627 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2628 *
2629 * Enables/disables PCI INTx for device dev
2630 */
2631void
2632pci_intx(struct pci_dev *pdev, int enable)
2633{
2634 u16 pci_command, new;
2635
2636 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2637
2638 if (enable) {
2639 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2640 } else {
2641 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2642 }
2643
2644 if (new != pci_command) {
9ac7849e
TH		 2645 struct pci_devres *dr;
2646
2fd9d74b 2647 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2648
2649 dr = find_pci_dr(pdev);
2650 if (dr && !dr->restore_intx) {
2651 dr->restore_intx = 1;
2652 dr->orig_intx = !enable;
2653 }
a04ce0ff
BR		 2654 }
2655}
2656
f5f2b131
EB		 2657/**
2658 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 2659 * @dev: the PCI device to operate on
f5f2b131
EB		 2660 *
2661 * If you want to use msi see pci_enable_msi and friends.
2662 * This is a lower level primitive that allows us to disable
2663 * msi operation at the device level.
2664 */
2665void pci_msi_off(struct pci_dev *dev)
2666{
2667 int pos;
2668 u16 control;
2669
2670 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2671 if (pos) {
2672 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2673 control &= ~PCI_MSI_FLAGS_ENABLE;
2674 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2675 }
2676 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2677 if (pos) {
2678 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2679 control &= ~PCI_MSIX_FLAGS_ENABLE;
2680 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2681 }
2682}
b03214d5 2683EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 2684
4d57cdfa
FT		 2685int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2686{
2687 return dma_set_max_seg_size(&dev->dev, size);
2688}
2689EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 2690
59fc67de
FT		 2691int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2692{
2693 return dma_set_seg_boundary(&dev->dev, mask);
2694}
2695EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 2696
8c1c699f 2697static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 2698{
8c1c699f
YZ		 2699 int i;
2700 int pos;
8dd7f803 2701 u32 cap;
04b55c47 2702 u16 status, control;
8dd7f803 2703
06a1cbaf 2704 pos = pci_pcie_cap(dev);
8c1c699f 2705 if (!pos)
8dd7f803 2706 return -ENOTTY;
8c1c699f
YZ		 2707
2708 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 2709 if (!(cap & PCI_EXP_DEVCAP_FLR))
2710 return -ENOTTY;
2711
d91cdc74
SY		 2712 if (probe)
2713 return 0;
2714
8dd7f803 2715 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2716 for (i = 0; i < 4; i++) {
2717 if (i)
2718 msleep((1 << (i - 1)) * 100);
5fe5db05 2719
8c1c699f
YZ		 2720 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2721 if (!(status & PCI_EXP_DEVSTA_TRPND))
2722 goto clear;
2723 }
2724
2725 dev_err(&dev->dev, "transaction is not cleared; "
2726 "proceeding with reset anyway\n");
2727
2728clear:
04b55c47
SR		 2729 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2730 control |= PCI_EXP_DEVCTL_BCR_FLR;
2731 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2732
8c1c699f 2733 msleep(100);
8dd7f803 2734
8dd7f803
SY		 2735 return 0;
2736}
d91cdc74 2737
8c1c699f 2738static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 2739{
8c1c699f
YZ		 2740 int i;
2741 int pos;
1ca88797 2742 u8 cap;
8c1c699f 2743 u8 status;
1ca88797 2744
8c1c699f
YZ		 2745 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2746 if (!pos)
1ca88797 2747 return -ENOTTY;
8c1c699f
YZ		 2748
2749 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 2750 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2751 return -ENOTTY;
2752
2753 if (probe)
2754 return 0;
2755
1ca88797 2756 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2757 for (i = 0; i < 4; i++) {
2758 if (i)
2759 msleep((1 << (i - 1)) * 100);
2760
2761 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2762 if (!(status & PCI_AF_STATUS_TP))
2763 goto clear;
2764 }
5fe5db05 2765
8c1c699f
YZ		 2766 dev_err(&dev->dev, "transaction is not cleared; "
2767 "proceeding with reset anyway\n");
5fe5db05 2768
8c1c699f
YZ		 2769clear:
2770 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 2771 msleep(100);
8c1c699f 2772
1ca88797
SY		 2773 return 0;
2774}
2775
83d74e03
RW		 2776/**
2777 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2778 * @dev: Device to reset.
2779 * @probe: If set, only check if the device can be reset this way.
2780 *
2781 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2782 * unset, it will be reinitialized internally when going from PCI_D3hot to
2783 * PCI_D0. If that's the case and the device is not in a low-power state
2784 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2785 *
2786 * NOTE: This causes the caller to sleep for twice the device power transition
2787 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2788 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2789 * Moreover, only devices in D0 can be reset by this function.
2790 */
f85876ba 2791static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 2792{
f85876ba
YZ		 2793 u16 csr;
2794
2795 if (!dev->pm_cap)
2796 return -ENOTTY;
d91cdc74 2797
f85876ba
YZ		 2798 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2799 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2800 return -ENOTTY;
d91cdc74 2801
f85876ba
YZ		 2802 if (probe)
2803 return 0;
1ca88797 2804
f85876ba
YZ		 2805 if (dev->current_state != PCI_D0)
2806 return -EINVAL;
2807
2808 csr &= ~PCI_PM_CTRL_STATE_MASK;
2809 csr |= PCI_D3hot;
2810 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2811 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2812
2813 csr &= ~PCI_PM_CTRL_STATE_MASK;
2814 csr |= PCI_D0;
2815 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2816 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2817
2818 return 0;
2819}
2820
c12ff1df
YZ		 2821static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2822{
2823 u16 ctrl;
2824 struct pci_dev *pdev;
2825
654b75e0 2826 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 2827 return -ENOTTY;
2828
2829 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2830 if (pdev != dev)
2831 return -ENOTTY;
2832
2833 if (probe)
2834 return 0;
2835
2836 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2837 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2838 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2839 msleep(100);
2840
2841 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2842 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2843 msleep(100);
2844
2845 return 0;
2846}
2847
8c1c699f 2848static int pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 2849{
8c1c699f
YZ		 2850 int rc;
2851
2852 might_sleep();
2853
2854 if (!probe) {
2855 pci_block_user_cfg_access(dev);
2856 /* block PM suspend, driver probe, etc. */
8e9394ce 2857 device_lock(&dev->dev);
8c1c699f 2858 }
d91cdc74 2859
b9c3b266
DC		 2860 rc = pci_dev_specific_reset(dev, probe);
2861 if (rc != -ENOTTY)
2862 goto done;
2863
8c1c699f
YZ		 2864 rc = pcie_flr(dev, probe);
2865 if (rc != -ENOTTY)
2866 goto done;
d91cdc74 2867
8c1c699f 2868 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 2869 if (rc != -ENOTTY)
2870 goto done;
2871
2872 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 2873 if (rc != -ENOTTY)
2874 goto done;
2875
2876 rc = pci_parent_bus_reset(dev, probe);
8c1c699f
YZ		 2877done:
2878 if (!probe) {
8e9394ce 2879 device_unlock(&dev->dev);
8c1c699f
YZ		 2880 pci_unblock_user_cfg_access(dev);
2881 }
1ca88797 2882
8c1c699f 2883 return rc;
d91cdc74
SY		 2884}
2885
2886/**
8c1c699f
YZ		 2887 * __pci_reset_function - reset a PCI device function
2888 * @dev: PCI device to reset
d91cdc74
SY		 2889 *
2890 * Some devices allow an individual function to be reset without affecting
2891 * other functions in the same device. The PCI device must be responsive
2892 * to PCI config space in order to use this function.
2893 *
2894 * The device function is presumed to be unused when this function is called.
2895 * Resetting the device will make the contents of PCI configuration space
2896 * random, so any caller of this must be prepared to reinitialise the
2897 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2898 * etc.
2899 *
8c1c699f 2900 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 2901 * device doesn't support resetting a single function.
2902 */
8c1c699f 2903int __pci_reset_function(struct pci_dev *dev)
d91cdc74 2904{
8c1c699f 2905 return pci_dev_reset(dev, 0);
d91cdc74 2906}
8c1c699f 2907EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 2908
711d5779
MT		 2909/**
2910 * pci_probe_reset_function - check whether the device can be safely reset
2911 * @dev: PCI device to reset
2912 *
2913 * Some devices allow an individual function to be reset without affecting
2914 * other functions in the same device. The PCI device must be responsive
2915 * to PCI config space in order to use this function.
2916 *
2917 * Returns 0 if the device function can be reset or negative if the
2918 * device doesn't support resetting a single function.
2919 */
2920int pci_probe_reset_function(struct pci_dev *dev)
2921{
2922 return pci_dev_reset(dev, 1);
2923}
2924
8dd7f803 2925/**
8c1c699f
YZ		 2926 * pci_reset_function - quiesce and reset a PCI device function
2927 * @dev: PCI device to reset
8dd7f803
SY		 2928 *
2929 * Some devices allow an individual function to be reset without affecting
2930 * other functions in the same device. The PCI device must be responsive
2931 * to PCI config space in order to use this function.
2932 *
2933 * This function does not just reset the PCI portion of a device, but
2934 * clears all the state associated with the device. This function differs
8c1c699f 2935 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 2936 * over the reset.
2937 *
8c1c699f 2938 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 2939 * device doesn't support resetting a single function.
2940 */
2941int pci_reset_function(struct pci_dev *dev)
2942{
8c1c699f 2943 int rc;
8dd7f803 2944
8c1c699f
YZ		 2945 rc = pci_dev_reset(dev, 1);
2946 if (rc)
2947 return rc;
8dd7f803 2948
8dd7f803
SY		 2949 pci_save_state(dev);
2950
8c1c699f
YZ		 2951 /*
2952 * both INTx and MSI are disabled after the Interrupt Disable bit
2953 * is set and the Bus Master bit is cleared.
2954 */
8dd7f803
SY		 2955 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2956
8c1c699f 2957 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 2958
2959 pci_restore_state(dev);
8dd7f803 2960
8c1c699f 2961 return rc;
8dd7f803
SY		 2962}
2963EXPORT_SYMBOL_GPL(pci_reset_function);
2964
d556ad4b
PO		 2965/**
2966 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2967 * @dev: PCI device to query
2968 *
2969 * Returns mmrbc: maximum designed memory read count in bytes
2970 * or appropriate error value.
2971 */
2972int pcix_get_max_mmrbc(struct pci_dev *dev)
2973{
7c9e2b1c 2974 int cap;
d556ad4b
PO		 2975 u32 stat;
2976
2977 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2978 if (!cap)
2979 return -EINVAL;
2980
7c9e2b1c 2981 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 2982 return -EINVAL;
2983
25daeb55 2984 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 2985}
2986EXPORT_SYMBOL(pcix_get_max_mmrbc);
2987
2988/**
2989 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2990 * @dev: PCI device to query
2991 *
2992 * Returns mmrbc: maximum memory read count in bytes
2993 * or appropriate error value.
2994 */
2995int pcix_get_mmrbc(struct pci_dev *dev)
2996{
7c9e2b1c 2997 int cap;
bdc2bda7 2998 u16 cmd;
d556ad4b
PO		 2999
3000 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3001 if (!cap)
3002 return -EINVAL;
3003
7c9e2b1c
DN		 3004 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3005 return -EINVAL;
d556ad4b 3006
7c9e2b1c 3007 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3008}
3009EXPORT_SYMBOL(pcix_get_mmrbc);
3010
3011/**
3012 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3013 * @dev: PCI device to query
3014 * @mmrbc: maximum memory read count in bytes
3015 * valid values are 512, 1024, 2048, 4096
3016 *
3017 * If possible sets maximum memory read byte count, some bridges have erratas
3018 * that prevent this.
3019 */
3020int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3021{
7c9e2b1c 3022 int cap;
bdc2bda7
DN		 3023 u32 stat, v, o;
3024 u16 cmd;
d556ad4b 3025
229f5afd 3026 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3027 return -EINVAL;
d556ad4b
PO		 3028
3029 v = ffs(mmrbc) - 10;
3030
3031 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3032 if (!cap)
7c9e2b1c 3033 return -EINVAL;
d556ad4b 3034
7c9e2b1c
DN		 3035 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3036 return -EINVAL;
d556ad4b
PO		 3037
3038 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3039 return -E2BIG;
3040
7c9e2b1c
DN		 3041 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3042 return -EINVAL;
d556ad4b
PO		 3043
3044 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3045 if (o != v) {
3046 if (v > o && dev->bus &&
3047 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3048 return -EIO;
3049
3050 cmd &= ~PCI_X_CMD_MAX_READ;
3051 cmd |= v << 2;
7c9e2b1c
DN		 3052 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3053 return -EIO;
d556ad4b 3054 }
7c9e2b1c 3055 return 0;
d556ad4b
PO		 3056}
3057EXPORT_SYMBOL(pcix_set_mmrbc);
3058
3059/**
3060 * pcie_get_readrq - get PCI Express read request size
3061 * @dev: PCI device to query
3062 *
3063 * Returns maximum memory read request in bytes
3064 * or appropriate error value.
3065 */
3066int pcie_get_readrq(struct pci_dev *dev)
3067{
3068 int ret, cap;
3069 u16 ctl;
3070
06a1cbaf 3071 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3072 if (!cap)
3073 return -EINVAL;
3074
3075 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3076 if (!ret)
93e75fab 3077 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3078
3079 return ret;
3080}
3081EXPORT_SYMBOL(pcie_get_readrq);
3082
3083/**
3084 * pcie_set_readrq - set PCI Express maximum memory read request
3085 * @dev: PCI device to query
42e61f4a 3086 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3087 * valid values are 128, 256, 512, 1024, 2048, 4096
3088 *
3089 * If possible sets maximum read byte count
3090 */
3091int pcie_set_readrq(struct pci_dev *dev, int rq)
3092{
3093 int cap, err = -EINVAL;
3094 u16 ctl, v;
3095
229f5afd 3096 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
d556ad4b
PO		 3097 goto out;
3098
3099 v = (ffs(rq) - 8) << 12;
3100
06a1cbaf 3101 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3102 if (!cap)
3103 goto out;
3104
3105 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3106 if (err)
3107 goto out;
3108
3109 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3110 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3111 ctl |= v;
3112 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
3113 }
3114
3115out:
3116 return err;
3117}
3118EXPORT_SYMBOL(pcie_set_readrq);
3119
c87deff7
HS		 3120/**
3121 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 3122 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 3123 * @flags: resource type mask to be selected
3124 *
3125 * This helper routine makes bar mask from the type of resource.
3126 */
3127int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3128{
3129 int i, bars = 0;
3130 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3131 if (pci_resource_flags(dev, i) & flags)
3132 bars |= (1 << i);
3133 return bars;
3134}
3135
613e7ed6
YZ		 3136/**
3137 * pci_resource_bar - get position of the BAR associated with a resource
3138 * @dev: the PCI device
3139 * @resno: the resource number
3140 * @type: the BAR type to be filled in
3141 *
3142 * Returns BAR position in config space, or 0 if the BAR is invalid.
3143 */
3144int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3145{
d1b054da
YZ		 3146 int reg;
3147
613e7ed6
YZ		 3148 if (resno < PCI_ROM_RESOURCE) {
3149 *type = pci_bar_unknown;
3150 return PCI_BASE_ADDRESS_0 + 4 * resno;
3151 } else if (resno == PCI_ROM_RESOURCE) {
3152 *type = pci_bar_mem32;
3153 return dev->rom_base_reg;
d1b054da
YZ		 3154 } else if (resno < PCI_BRIDGE_RESOURCES) {
3155 /* device specific resource */
3156 reg = pci_iov_resource_bar(dev, resno, type);
3157 if (reg)
3158 return reg;
613e7ed6
YZ		 3159 }
3160
865df576 3161 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 3162 return 0;
3163}
3164
95a8b6ef
MT		 3165/* Some architectures require additional programming to enable VGA */
3166static arch_set_vga_state_t arch_set_vga_state;
3167
3168void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3169{
3170 arch_set_vga_state = func; /* NULL disables */
3171}
3172
3173static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3174 unsigned int command_bits, bool change_bridge)
3175{
3176 if (arch_set_vga_state)
3177 return arch_set_vga_state(dev, decode, command_bits,
3178 change_bridge);
3179 return 0;
3180}
3181
deb2d2ec
BH		 3182/**
3183 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 3184 * @dev: the PCI device
3185 * @decode: true = enable decoding, false = disable decoding
3186 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3187 * @change_bridge: traverse ancestors and change bridges
deb2d2ec
BH		 3188 */
3189int pci_set_vga_state(struct pci_dev *dev, bool decode,
3190 unsigned int command_bits, bool change_bridge)
3191{
3192 struct pci_bus *bus;
3193 struct pci_dev *bridge;
3194 u16 cmd;
95a8b6ef 3195 int rc;
deb2d2ec
BH		 3196
3197 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
3198
95a8b6ef
MT		 3199 /* ARCH specific VGA enables */
3200 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
3201 if (rc)
3202 return rc;
3203
deb2d2ec
BH		 3204 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3205 if (decode == true)
3206 cmd |= command_bits;
3207 else
3208 cmd &= ~command_bits;
3209 pci_write_config_word(dev, PCI_COMMAND, cmd);
3210
3211 if (change_bridge == false)
3212 return 0;
3213
3214 bus = dev->bus;
3215 while (bus) {
3216 bridge = bus->self;
3217 if (bridge) {
3218 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3219 &cmd);
3220 if (decode == true)
3221 cmd |= PCI_BRIDGE_CTL_VGA;
3222 else
3223 cmd &= ~PCI_BRIDGE_CTL_VGA;
3224 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3225 cmd);
3226 }
3227 bus = bus->parent;
3228 }
3229 return 0;
3230}
3231
32a9a682
YS		 3232#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3233static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 3234static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 3235
3236/**
3237 * pci_specified_resource_alignment - get resource alignment specified by user.
3238 * @dev: the PCI device to get
3239 *
3240 * RETURNS: Resource alignment if it is specified.
3241 * Zero if it is not specified.
3242 */
3243resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3244{
3245 int seg, bus, slot, func, align_order, count;
3246 resource_size_t align = 0;
3247 char *p;
3248
3249 spin_lock(&resource_alignment_lock);
3250 p = resource_alignment_param;
3251 while (*p) {
3252 count = 0;
3253 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3254 p[count] == '@') {
3255 p += count + 1;
3256 } else {
3257 align_order = -1;
3258 }
3259 if (sscanf(p, "%x:%x:%x.%x%n",
3260 &seg, &bus, &slot, &func, &count) != 4) {
3261 seg = 0;
3262 if (sscanf(p, "%x:%x.%x%n",
3263 &bus, &slot, &func, &count) != 3) {
3264 /* Invalid format */
3265 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3266 p);
3267 break;
3268 }
3269 }
3270 p += count;
3271 if (seg == pci_domain_nr(dev->bus) &&
3272 bus == dev->bus->number &&
3273 slot == PCI_SLOT(dev->devfn) &&
3274 func == PCI_FUNC(dev->devfn)) {
3275 if (align_order == -1) {
3276 align = PAGE_SIZE;
3277 } else {
3278 align = 1 << align_order;
3279 }
3280 /* Found */
3281 break;
3282 }
3283 if (*p != ';' && *p != ',') {
3284 /* End of param or invalid format */
3285 break;
3286 }
3287 p++;
3288 }
3289 spin_unlock(&resource_alignment_lock);
3290 return align;
3291}
3292
3293/**
3294 * pci_is_reassigndev - check if specified PCI is target device to reassign
3295 * @dev: the PCI device to check
3296 *
3297 * RETURNS: non-zero for PCI device is a target device to reassign,
3298 * or zero is not.
3299 */
3300int pci_is_reassigndev(struct pci_dev *dev)
3301{
3302 return (pci_specified_resource_alignment(dev) != 0);
3303}
3304
3305ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3306{
3307 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3308 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3309 spin_lock(&resource_alignment_lock);
3310 strncpy(resource_alignment_param, buf, count);
3311 resource_alignment_param[count] = '\0';
3312 spin_unlock(&resource_alignment_lock);
3313 return count;
3314}
3315
3316ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3317{
3318 size_t count;
3319 spin_lock(&resource_alignment_lock);
3320 count = snprintf(buf, size, "%s", resource_alignment_param);
3321 spin_unlock(&resource_alignment_lock);
3322 return count;
3323}
3324
3325static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3326{
3327 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3328}
3329
3330static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3331 const char *buf, size_t count)
3332{
3333 return pci_set_resource_alignment_param(buf, count);
3334}
3335
3336BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3337 pci_resource_alignment_store);
3338
3339static int __init pci_resource_alignment_sysfs_init(void)
3340{
3341 return bus_create_file(&pci_bus_type,
3342 &bus_attr_resource_alignment);
3343}
3344
3345late_initcall(pci_resource_alignment_sysfs_init);
3346
32a2eea7
JG		 3347static void __devinit pci_no_domains(void)
3348{
3349#ifdef CONFIG_PCI_DOMAINS
3350 pci_domains_supported = 0;
3351#endif
3352}
3353
0ef5f8f6
AP		 3354/**
3355 * pci_ext_cfg_enabled - can we access extended PCI config space?
3356 * @dev: The PCI device of the root bridge.
3357 *
3358 * Returns 1 if we can access PCI extended config space (offsets
3359 * greater than 0xff). This is the default implementation. Architecture
3360 * implementations can override this.
3361 */
3362int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3363{
3364 return 1;
3365}
3366
2d1c8618
BH		 3367void __weak pci_fixup_cardbus(struct pci_bus *bus)
3368{
3369}
3370EXPORT_SYMBOL(pci_fixup_cardbus);
3371
ad04d31e 3372static int __init pci_setup(char *str)
1da177e4
LT		 3373{
3374 while (str) {
3375 char *k = strchr(str, ',');
3376 if (k)
3377 *k++ = 0;
3378 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3379 if (!strcmp(str, "nomsi")) {
3380 pci_no_msi();
7f785763
RD		 3381 } else if (!strcmp(str, "noaer")) {
3382 pci_no_aer();
32a2eea7
JG		 3383 } else if (!strcmp(str, "nodomains")) {
3384 pci_no_domains();
4516a618
AN		 3385 } else if (!strncmp(str, "cbiosize=", 9)) {
3386 pci_cardbus_io_size = memparse(str + 9, &str);
3387 } else if (!strncmp(str, "cbmemsize=", 10)) {
3388 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3389 } else if (!strncmp(str, "resource_alignment=", 19)) {
3390 pci_set_resource_alignment_param(str + 19,
3391 strlen(str + 19));
43c16408
AP		 3392 } else if (!strncmp(str, "ecrc=", 5)) {
3393 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3394 } else if (!strncmp(str, "hpiosize=", 9)) {
3395 pci_hotplug_io_size = memparse(str + 9, &str);
3396 } else if (!strncmp(str, "hpmemsize=", 10)) {
3397 pci_hotplug_mem_size = memparse(str + 10, &str);
309e57df
MW		 3398 } else {
3399 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3400 str);
3401 }
1da177e4
LT		 3402 }
3403 str = k;
3404 }
0637a70a 3405 return 0;
1da177e4 3406}
0637a70a 3407early_param("pci", pci_setup);
1da177e4 3408
0b62e13b 3409EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3410EXPORT_SYMBOL(pci_enable_device_io);
3411EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3412EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3413EXPORT_SYMBOL(pcim_enable_device);
3414EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3415EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3416EXPORT_SYMBOL(pci_find_capability);
3417EXPORT_SYMBOL(pci_bus_find_capability);
3418EXPORT_SYMBOL(pci_release_regions);
3419EXPORT_SYMBOL(pci_request_regions);
e8de1481 3420EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3421EXPORT_SYMBOL(pci_release_region);
3422EXPORT_SYMBOL(pci_request_region);
e8de1481 3423EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3424EXPORT_SYMBOL(pci_release_selected_regions);
3425EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3426EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3427EXPORT_SYMBOL(pci_set_master);
6a479079 3428EXPORT_SYMBOL(pci_clear_master);
1da177e4 3429EXPORT_SYMBOL(pci_set_mwi);
694625c0 3430EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3431EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3432EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 3433EXPORT_SYMBOL(pci_assign_resource);
3434EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3435EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3436
3437EXPORT_SYMBOL(pci_set_power_state);
3438EXPORT_SYMBOL(pci_save_state);
3439EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3440EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3441EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3442EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3443EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3444EXPORT_SYMBOL(pci_prepare_to_sleep);
3445EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3446EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linux kernel - Deliverables
This page took 0.827669 seconds and 5 git commands to generate.