projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branches 'perf-urgent-for-linus' and 'sched-urgent-for-linus' of git://git...
[deliverable/linux.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
32a9a682 25#include <asm/setup.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
00240c38
AS		 28const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30};
31EXPORT_SYMBOL_GPL(pci_power_names);
32
93177a74
RW		 33int isa_dma_bridge_buggy;
34EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36int pci_pci_problems;
37EXPORT_SYMBOL(pci_pci_problems);
38
1ae861e6
RW		 39unsigned int pci_pm_d3_delay;
40
df17e62e
MG		 41static void pci_pme_list_scan(struct work_struct *work);
42
43static LIST_HEAD(pci_pme_list);
44static DEFINE_MUTEX(pci_pme_list_mutex);
45static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
46
47struct pci_pme_device {
48 struct list_head list;
49 struct pci_dev *dev;
50};
51
52#define PME_TIMEOUT 1000 /* How long between PME checks */
53
1ae861e6
RW		 54static void pci_dev_d3_sleep(struct pci_dev *dev)
55{
56 unsigned int delay = dev->d3_delay;
57
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
60
61 msleep(delay);
62}
1da177e4 63
32a2eea7
JG		 64#ifdef CONFIG_PCI_DOMAINS
65int pci_domains_supported = 1;
66#endif
67
4516a618
AN		 68#define DEFAULT_CARDBUS_IO_SIZE (256)
69#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70/* pci=cbmemsize=nnM,cbiosize=nn can override this */
71unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
73
28760489
EB		 74#define DEFAULT_HOTPLUG_IO_SIZE (256)
75#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76/* pci=hpmemsize=nnM,hpiosize=nn can override this */
77unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
79
5f39e670 80enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495 81
ac1aa47b
JB		 82/*
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
87 */
98e724c7 88u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 89u8 pci_cache_line_size;
90
1da177e4
LT		 91/**
92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
93 * @bus: pointer to PCI bus structure to search
94 *
95 * Given a PCI bus, returns the highest PCI bus number present in the set
96 * including the given PCI bus and its list of child PCI buses.
97 */
96bde06a 98unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 99{
100 struct list_head *tmp;
101 unsigned char max, n;
102
b82db5ce 103 max = bus->subordinate;
1da177e4
LT		 104 list_for_each(tmp, &bus->children) {
105 n = pci_bus_max_busnr(pci_bus_b(tmp));
106 if(n > max)
107 max = n;
108 }
109 return max;
110}
b82db5ce 111EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 112
1684f5dd
AM		 113#ifdef CONFIG_HAS_IOMEM
114void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
115{
116 /*
117 * Make sure the BAR is actually a memory resource, not an IO resource
118 */
119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
120 WARN_ON(1);
121 return NULL;
122 }
123 return ioremap_nocache(pci_resource_start(pdev, bar),
124 pci_resource_len(pdev, bar));
125}
126EXPORT_SYMBOL_GPL(pci_ioremap_bar);
127#endif
128
b82db5ce 129#if 0
1da177e4
LT		 130/**
131 * pci_max_busnr - returns maximum PCI bus number
132 *
133 * Returns the highest PCI bus number present in the system global list of
134 * PCI buses.
135 */
136unsigned char __devinit
137pci_max_busnr(void)
138{
139 struct pci_bus *bus = NULL;
140 unsigned char max, n;
141
142 max = 0;
143 while ((bus = pci_find_next_bus(bus)) != NULL) {
144 n = pci_bus_max_busnr(bus);
145 if(n > max)
146 max = n;
147 }
148 return max;
149}
150
54c762fe
AB		 151#endif /* 0 */
152
687d5fe3
ME		 153#define PCI_FIND_CAP_TTL 48
154
155static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
156 u8 pos, int cap, int *ttl)
24a4e377
RD		 157{
158 u8 id;
24a4e377 159
687d5fe3 160 while ((*ttl)--) {
24a4e377
RD		 161 pci_bus_read_config_byte(bus, devfn, pos, &pos);
162 if (pos < 0x40)
163 break;
164 pos &= ~3;
165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
166 &id);
167 if (id == 0xff)
168 break;
169 if (id == cap)
170 return pos;
171 pos += PCI_CAP_LIST_NEXT;
172 }
173 return 0;
174}
175
687d5fe3
ME		 176static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
177 u8 pos, int cap)
178{
179 int ttl = PCI_FIND_CAP_TTL;
180
181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
182}
183
24a4e377
RD		 184int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
185{
186 return __pci_find_next_cap(dev->bus, dev->devfn,
187 pos + PCI_CAP_LIST_NEXT, cap);
188}
189EXPORT_SYMBOL_GPL(pci_find_next_capability);
190
d3bac118
ME		 191static int __pci_bus_find_cap_start(struct pci_bus *bus,
192 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 193{
194 u16 status;
1da177e4
LT		 195
196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
197 if (!(status & PCI_STATUS_CAP_LIST))
198 return 0;
199
200 switch (hdr_type) {
201 case PCI_HEADER_TYPE_NORMAL:
202 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 203 return PCI_CAPABILITY_LIST;
1da177e4 204 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 205 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 206 default:
207 return 0;
208 }
d3bac118
ME		 209
210 return 0;
1da177e4
LT		 211}
212
213/**
214 * pci_find_capability - query for devices' capabilities
215 * @dev: PCI device to query
216 * @cap: capability code
217 *
218 * Tell if a device supports a given PCI capability.
219 * Returns the address of the requested capability structure within the
220 * device's PCI configuration space or 0 in case the device does not
221 * support it. Possible values for @cap:
222 *
223 * %PCI_CAP_ID_PM Power Management
224 * %PCI_CAP_ID_AGP Accelerated Graphics Port
225 * %PCI_CAP_ID_VPD Vital Product Data
226 * %PCI_CAP_ID_SLOTID Slot Identification
227 * %PCI_CAP_ID_MSI Message Signalled Interrupts
228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
229 * %PCI_CAP_ID_PCIX PCI-X
230 * %PCI_CAP_ID_EXP PCI Express
231 */
232int pci_find_capability(struct pci_dev *dev, int cap)
233{
d3bac118
ME		 234 int pos;
235
236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
237 if (pos)
238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
239
240 return pos;
1da177e4
LT		 241}
242
243/**
244 * pci_bus_find_capability - query for devices' capabilities
245 * @bus: the PCI bus to query
246 * @devfn: PCI device to query
247 * @cap: capability code
248 *
249 * Like pci_find_capability() but works for pci devices that do not have a
250 * pci_dev structure set up yet.
251 *
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
254 * support it.
255 */
256int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
257{
d3bac118 258 int pos;
1da177e4
LT		 259 u8 hdr_type;
260
261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
262
d3bac118
ME		 263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
264 if (pos)
265 pos = __pci_find_next_cap(bus, devfn, pos, cap);
266
267 return pos;
1da177e4
LT		 268}
269
270/**
271 * pci_find_ext_capability - Find an extended capability
272 * @dev: PCI device to query
273 * @cap: capability code
274 *
275 * Returns the address of the requested extended capability structure
276 * within the device's PCI configuration space or 0 if the device does
277 * not support it. Possible values for @cap:
278 *
279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
280 * %PCI_EXT_CAP_ID_VC Virtual Channel
281 * %PCI_EXT_CAP_ID_DSN Device Serial Number
282 * %PCI_EXT_CAP_ID_PWR Power Budgeting
283 */
284int pci_find_ext_capability(struct pci_dev *dev, int cap)
285{
286 u32 header;
557848c3
ZY		 287 int ttl;
288 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 289
557848c3
ZY		 290 /* minimum 8 bytes per capability */
291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
292
293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 294 return 0;
295
296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
297 return 0;
298
299 /*
300 * If we have no capabilities, this is indicated by cap ID,
301 * cap version and next pointer all being 0.
302 */
303 if (header == 0)
304 return 0;
305
306 while (ttl-- > 0) {
307 if (PCI_EXT_CAP_ID(header) == cap)
308 return pos;
309
310 pos = PCI_EXT_CAP_NEXT(header);
557848c3 311 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 312 break;
313
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
315 break;
316 }
317
318 return 0;
319}
3a720d72 320EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 321
cf4c43dd
JB		 322/**
323 * pci_bus_find_ext_capability - find an extended capability
324 * @bus: the PCI bus to query
325 * @devfn: PCI device to query
326 * @cap: capability code
327 *
328 * Like pci_find_ext_capability() but works for pci devices that do not have a
329 * pci_dev structure set up yet.
330 *
331 * Returns the address of the requested capability structure within the
332 * device's PCI configuration space or 0 in case the device does not
333 * support it.
334 */
335int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
336 int cap)
337{
338 u32 header;
339 int ttl;
340 int pos = PCI_CFG_SPACE_SIZE;
341
342 /* minimum 8 bytes per capability */
343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
344
345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
346 return 0;
347 if (header == 0xffffffff || header == 0)
348 return 0;
349
350 while (ttl-- > 0) {
351 if (PCI_EXT_CAP_ID(header) == cap)
352 return pos;
353
354 pos = PCI_EXT_CAP_NEXT(header);
355 if (pos < PCI_CFG_SPACE_SIZE)
356 break;
357
358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
359 break;
360 }
361
362 return 0;
363}
364
687d5fe3
ME		 365static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
366{
367 int rc, ttl = PCI_FIND_CAP_TTL;
368 u8 cap, mask;
369
370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
371 mask = HT_3BIT_CAP_MASK;
372 else
373 mask = HT_5BIT_CAP_MASK;
374
375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
376 PCI_CAP_ID_HT, &ttl);
377 while (pos) {
378 rc = pci_read_config_byte(dev, pos + 3, &cap);
379 if (rc != PCIBIOS_SUCCESSFUL)
380 return 0;
381
382 if ((cap & mask) == ht_cap)
383 return pos;
384
47a4d5be
BG		 385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
386 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 387 PCI_CAP_ID_HT, &ttl);
388 }
389
390 return 0;
391}
392/**
393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
394 * @dev: PCI device to query
395 * @pos: Position from which to continue searching
396 * @ht_cap: Hypertransport capability code
397 *
398 * To be used in conjunction with pci_find_ht_capability() to search for
399 * all capabilities matching @ht_cap. @pos should always be a value returned
400 * from pci_find_ht_capability().
401 *
402 * NB. To be 100% safe against broken PCI devices, the caller should take
403 * steps to avoid an infinite loop.
404 */
405int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
406{
407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
408}
409EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
410
411/**
412 * pci_find_ht_capability - query a device's Hypertransport capabilities
413 * @dev: PCI device to query
414 * @ht_cap: Hypertransport capability code
415 *
416 * Tell if a device supports a given Hypertransport capability.
417 * Returns an address within the device's PCI configuration space
418 * or 0 in case the device does not support the request capability.
419 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
420 * which has a Hypertransport capability matching @ht_cap.
421 */
422int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
423{
424 int pos;
425
426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
427 if (pos)
428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
429
430 return pos;
431}
432EXPORT_SYMBOL_GPL(pci_find_ht_capability);
433
1da177e4
LT		 434/**
435 * pci_find_parent_resource - return resource region of parent bus of given region
436 * @dev: PCI device structure contains resources to be searched
437 * @res: child resource record for which parent is sought
438 *
439 * For given resource region of given device, return the resource
440 * region of parent bus the given region is contained in or where
441 * it should be allocated from.
442 */
443struct resource *
444pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
445{
446 const struct pci_bus *bus = dev->bus;
447 int i;
89a74ecc 448 struct resource *best = NULL, *r;
1da177e4 449
89a74ecc 450 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 451 if (!r)
452 continue;
453 if (res->start && !(res->start >= r->start && res->end <= r->end))
454 continue; /* Not contained */
455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
456 continue; /* Wrong type */
457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
458 return r; /* Exact match */
8c8def26
LT		 459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
460 if (r->flags & IORESOURCE_PREFETCH)
461 continue;
462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
463 if (!best)
464 best = r;
1da177e4
LT		 465 }
466 return best;
467}
468
064b53db
JL		 469/**
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
472 *
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
475 */
ad668599 476static void
064b53db
JL		 477pci_restore_bars(struct pci_dev *dev)
478{
bc5f5a82 479 int i;
064b53db 480
bc5f5a82 481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 482 pci_update_resource(dev, i);
064b53db
JL		 483}
484
961d9120
RW		 485static struct pci_platform_pm_ops *pci_platform_pm;
486
487int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
488{
eb9d0fe4
RW		 489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
490 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 491 return -EINVAL;
492 pci_platform_pm = ops;
493 return 0;
494}
495
496static inline bool platform_pci_power_manageable(struct pci_dev *dev)
497{
498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
499}
500
501static inline int platform_pci_set_power_state(struct pci_dev *dev,
502 pci_power_t t)
503{
504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
505}
506
507static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
508{
509 return pci_platform_pm ?
510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
511}
8f7020d3 512
eb9d0fe4
RW		 513static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
514{
515 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
516}
517
518static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
519{
520 return pci_platform_pm ?
521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522}
523
b67ea761
RW		 524static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
525{
526 return pci_platform_pm ?
527 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
528}
529
1da177e4 530/**
44e4e66e
RW		 531 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
532 * given PCI device
533 * @dev: PCI device to handle.
44e4e66e 534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 535 *
44e4e66e
RW		 536 * RETURN VALUE:
537 * -EINVAL if the requested state is invalid.
538 * -EIO if device does not support PCI PM or its PM capabilities register has a
539 * wrong version, or device doesn't support the requested state.
540 * 0 if device already is in the requested state.
541 * 0 if device's power state has been successfully changed.
1da177e4 542 */
f00a20ef 543static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 544{
337001b6 545 u16 pmcsr;
44e4e66e 546 bool need_restore = false;
1da177e4 547
4a865905
RW		 548 /* Check if we're already there */
549 if (dev->current_state == state)
550 return 0;
551
337001b6 552 if (!dev->pm_cap)
cca03dec
AL		 553 return -EIO;
554
44e4e66e
RW		 555 if (state < PCI_D0 || state > PCI_D3hot)
556 return -EINVAL;
557
1da177e4
LT		 558 /* Validate current state:
559 * Can enter D0 from any state, but if we can only go deeper
560 * to sleep if we're already in a low power state
561 */
4a865905 562 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 563 && dev->current_state > state) {
80ccba11
BH		 564 dev_err(&dev->dev, "invalid power transition "
565 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 566 return -EINVAL;
44e4e66e 567 }
1da177e4 568
1da177e4 569 /* check if this device supports the desired state */
337001b6
RW		 570 if ((state == PCI_D1 && !dev->d1_support)
571 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 572 return -EIO;
1da177e4 573
337001b6 574 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 575
32a36585 576 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 577 * This doesn't affect PME_Status, disables PME_En, and
578 * sets PowerState to 0.
579 */
32a36585 580 switch (dev->current_state) {
d3535fbb
JL		 581 case PCI_D0:
582 case PCI_D1:
583 case PCI_D2:
584 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
585 pmcsr |= state;
586 break;
f62795f1
RW		 587 case PCI_D3hot:
588 case PCI_D3cold:
32a36585
JL		 589 case PCI_UNKNOWN: /* Boot-up */
590 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 591 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 592 need_restore = true;
32a36585 593 /* Fall-through: force to D0 */
32a36585 594 default:
d3535fbb 595 pmcsr = 0;
32a36585 596 break;
1da177e4
LT		 597 }
598
599 /* enter specified state */
337001b6 600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 601
602 /* Mandatory power management transition delays */
603 /* see PCI PM 1.1 5.6.1 table 18 */
604 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 605 pci_dev_d3_sleep(dev);
1da177e4 606 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 607 udelay(PCI_PM_D2_DELAY);
1da177e4 608
e13cdbd7
RW		 609 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
610 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
611 if (dev->current_state != state && printk_ratelimit())
612 dev_info(&dev->dev, "Refused to change power state, "
613 "currently in D%d\n", dev->current_state);
064b53db
JL		 614
615 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
616 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
617 * from D3hot to D0 _may_ perform an internal reset, thereby
618 * going to "D0 Uninitialized" rather than "D0 Initialized".
619 * For example, at least some versions of the 3c905B and the
620 * 3c556B exhibit this behaviour.
621 *
622 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
623 * devices in a D3hot state at boot. Consequently, we need to
624 * restore at least the BARs so that the device will be
625 * accessible to its driver.
626 */
627 if (need_restore)
628 pci_restore_bars(dev);
629
f00a20ef 630 if (dev->bus->self)
7d715a6c
SL		 631 pcie_aspm_pm_state_change(dev->bus->self);
632
1da177e4
LT		 633 return 0;
634}
635
44e4e66e
RW		 636/**
637 * pci_update_current_state - Read PCI power state of given device from its
638 * PCI PM registers and cache it
639 * @dev: PCI device to handle.
f06fc0b6 640 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 641 */
73410429 642void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 643{
337001b6 644 if (dev->pm_cap) {
44e4e66e
RW		 645 u16 pmcsr;
646
337001b6 647 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 648 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 649 } else {
650 dev->current_state = state;
44e4e66e
RW		 651 }
652}
653
0e5dd46b
RW		 654/**
655 * pci_platform_power_transition - Use platform to change device power state
656 * @dev: PCI device to handle.
657 * @state: State to put the device into.
658 */
659static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
660{
661 int error;
662
663 if (platform_pci_power_manageable(dev)) {
664 error = platform_pci_set_power_state(dev, state);
665 if (!error)
666 pci_update_current_state(dev, state);
b51306c6
AH		 667 /* Fall back to PCI_D0 if native PM is not supported */
668 if (!dev->pm_cap)
669 dev->current_state = PCI_D0;
0e5dd46b
RW		 670 } else {
671 error = -ENODEV;
672 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 673 if (!dev->pm_cap)
674 dev->current_state = PCI_D0;
0e5dd46b
RW		 675 }
676
677 return error;
678}
679
680/**
681 * __pci_start_power_transition - Start power transition of a PCI device
682 * @dev: PCI device to handle.
683 * @state: State to put the device into.
684 */
685static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
686{
687 if (state == PCI_D0)
688 pci_platform_power_transition(dev, PCI_D0);
689}
690
691/**
692 * __pci_complete_power_transition - Complete power transition of a PCI device
693 * @dev: PCI device to handle.
694 * @state: State to put the device into.
695 *
696 * This function should not be called directly by device drivers.
697 */
698int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
699{
cc2893b6 700 return state >= PCI_D0 ?
0e5dd46b
RW		 701 pci_platform_power_transition(dev, state) : -EINVAL;
702}
703EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
704
44e4e66e
RW		 705/**
706 * pci_set_power_state - Set the power state of a PCI device
707 * @dev: PCI device to handle.
708 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
709 *
877d0310 710 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 711 * the device's PCI PM registers.
712 *
713 * RETURN VALUE:
714 * -EINVAL if the requested state is invalid.
715 * -EIO if device does not support PCI PM or its PM capabilities register has a
716 * wrong version, or device doesn't support the requested state.
717 * 0 if device already is in the requested state.
718 * 0 if device's power state has been successfully changed.
719 */
720int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
721{
337001b6 722 int error;
44e4e66e
RW		 723
724 /* bound the state we're entering */
725 if (state > PCI_D3hot)
726 state = PCI_D3hot;
727 else if (state < PCI_D0)
728 state = PCI_D0;
729 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
730 /*
731 * If the device or the parent bridge do not support PCI PM,
732 * ignore the request if we're doing anything other than putting
733 * it into D0 (which would only happen on boot).
734 */
735 return 0;
736
0e5dd46b
RW		 737 __pci_start_power_transition(dev, state);
738
979b1791
AC		 739 /* This device is quirked not to be put into D3, so
740 don't put it in D3 */
741 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
742 return 0;
44e4e66e 743
f00a20ef 744 error = pci_raw_set_power_state(dev, state);
44e4e66e 745
0e5dd46b
RW		 746 if (!__pci_complete_power_transition(dev, state))
747 error = 0;
1a680b7c
NC		 748 /*
749 * When aspm_policy is "powersave" this call ensures
750 * that ASPM is configured.
751 */
752 if (!error && dev->bus->self)
753 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 754
755 return error;
756}
757
1da177e4
LT		 758/**
759 * pci_choose_state - Choose the power state of a PCI device
760 * @dev: PCI device to be suspended
761 * @state: target sleep state for the whole system. This is the value
762 * that is passed to suspend() function.
763 *
764 * Returns PCI power state suitable for given device and given system
765 * message.
766 */
767
768pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
769{
ab826ca4 770 pci_power_t ret;
0f64474b 771
1da177e4
LT		 772 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
773 return PCI_D0;
774
961d9120
RW		 775 ret = platform_pci_choose_state(dev);
776 if (ret != PCI_POWER_ERROR)
777 return ret;
ca078bae
PM		 778
779 switch (state.event) {
780 case PM_EVENT_ON:
781 return PCI_D0;
782 case PM_EVENT_FREEZE:
b887d2e6
DB		 783 case PM_EVENT_PRETHAW:
784 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 785 case PM_EVENT_SUSPEND:
3a2d5b70 786 case PM_EVENT_HIBERNATE:
ca078bae 787 return PCI_D3hot;
1da177e4 788 default:
80ccba11
BH		 789 dev_info(&dev->dev, "unrecognized suspend event %d\n",
790 state.event);
1da177e4
LT		 791 BUG();
792 }
793 return PCI_D0;
794}
795
796EXPORT_SYMBOL(pci_choose_state);
797
89858517
YZ		 798#define PCI_EXP_SAVE_REGS 7
799
1b6b8ce2
YZ		 800#define pcie_cap_has_devctl(type, flags) 1
801#define pcie_cap_has_lnkctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 (type == PCI_EXP_TYPE_ROOT_PORT || \
804 type == PCI_EXP_TYPE_ENDPOINT || \
805 type == PCI_EXP_TYPE_LEG_END))
806#define pcie_cap_has_sltctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
809 (type == PCI_EXP_TYPE_DOWNSTREAM && \
810 (flags & PCI_EXP_FLAGS_SLOT))))
811#define pcie_cap_has_rtctl(type, flags) \
812 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
813 (type == PCI_EXP_TYPE_ROOT_PORT || \
814 type == PCI_EXP_TYPE_RC_EC))
815#define pcie_cap_has_devctl2(type, flags) \
816 ((flags & PCI_EXP_FLAGS_VERS) > 1)
817#define pcie_cap_has_lnkctl2(type, flags) \
818 ((flags & PCI_EXP_FLAGS_VERS) > 1)
819#define pcie_cap_has_sltctl2(type, flags) \
820 ((flags & PCI_EXP_FLAGS_VERS) > 1)
821
b56a5a23
MT		 822static int pci_save_pcie_state(struct pci_dev *dev)
823{
824 int pos, i = 0;
825 struct pci_cap_saved_state *save_state;
826 u16 *cap;
1b6b8ce2 827 u16 flags;
b56a5a23 828
06a1cbaf
KK		 829 pos = pci_pcie_cap(dev);
830 if (!pos)
b56a5a23
MT		 831 return 0;
832
9f35575d 833 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 834 if (!save_state) {
e496b617 835 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 836 return -ENOMEM;
837 }
24a4742f 838 cap = (u16 *)&save_state->cap.data[0];
b56a5a23 839
1b6b8ce2
YZ		 840 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
841
842 if (pcie_cap_has_devctl(dev->pcie_type, flags))
843 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
844 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
845 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
846 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
847 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
848 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
849 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
850 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
851 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
852 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
853 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
854 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
855 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
63f4898a 856
b56a5a23
MT		 857 return 0;
858}
859
860static void pci_restore_pcie_state(struct pci_dev *dev)
861{
862 int i = 0, pos;
863 struct pci_cap_saved_state *save_state;
864 u16 *cap;
1b6b8ce2 865 u16 flags;
b56a5a23
MT		 866
867 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
868 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
869 if (!save_state || pos <= 0)
870 return;
24a4742f 871 cap = (u16 *)&save_state->cap.data[0];
b56a5a23 872
1b6b8ce2
YZ		 873 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
874
875 if (pcie_cap_has_devctl(dev->pcie_type, flags))
876 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
877 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
878 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
879 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
880 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
881 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
882 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
883 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
884 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
885 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
886 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
887 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
888 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 889}
890
cc692a5f
SH		 891
892static int pci_save_pcix_state(struct pci_dev *dev)
893{
63f4898a 894 int pos;
cc692a5f 895 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 896
897 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
898 if (pos <= 0)
899 return 0;
900
f34303de 901 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 902 if (!save_state) {
e496b617 903 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 904 return -ENOMEM;
905 }
cc692a5f 906
24a4742f
AW		 907 pci_read_config_word(dev, pos + PCI_X_CMD,
908 (u16 *)save_state->cap.data);
63f4898a 909
cc692a5f
SH		 910 return 0;
911}
912
913static void pci_restore_pcix_state(struct pci_dev *dev)
914{
915 int i = 0, pos;
916 struct pci_cap_saved_state *save_state;
917 u16 *cap;
918
919 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
920 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
921 if (!save_state || pos <= 0)
922 return;
24a4742f 923 cap = (u16 *)&save_state->cap.data[0];
cc692a5f
SH		 924
925 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 926}
927
928
1da177e4
LT		 929/**
930 * pci_save_state - save the PCI configuration space of a device before suspending
931 * @dev: - PCI device that we're dealing with
1da177e4
LT		 932 */
933int
934pci_save_state(struct pci_dev *dev)
935{
936 int i;
937 /* XXX: 100% dword access ok here? */
938 for (i = 0; i < 16; i++)
9e0b5b2c 939 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 940 dev->state_saved = true;
b56a5a23
MT		 941 if ((i = pci_save_pcie_state(dev)) != 0)
942 return i;
cc692a5f
SH		 943 if ((i = pci_save_pcix_state(dev)) != 0)
944 return i;
1da177e4
LT		 945 return 0;
946}
947
948/**
949 * pci_restore_state - Restore the saved state of a PCI device
950 * @dev: - PCI device that we're dealing with
1da177e4 951 */
1d3c16a8 952void pci_restore_state(struct pci_dev *dev)
1da177e4
LT		 953{
954 int i;
b4482a4b 955 u32 val;
1da177e4 956
c82f63e4 957 if (!dev->state_saved)
1d3c16a8 958 return;
4b77b0a2 959
b56a5a23
MT		 960 /* PCI Express register must be restored first */
961 pci_restore_pcie_state(dev);
962
8b8c8d28
YL		 963 /*
964 * The Base Address register should be programmed before the command
965 * register(s)
966 */
967 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 968 pci_read_config_dword(dev, i * 4, &val);
969 if (val != dev->saved_config_space[i]) {
80ccba11
BH		 970 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
971 "space at offset %#x (was %#x, writing %#x)\n",
972 i, val, (int)dev->saved_config_space[i]);
04d9c1a1
DJ		 973 pci_write_config_dword(dev,i * 4,
974 dev->saved_config_space[i]);
975 }
976 }
cc692a5f 977 pci_restore_pcix_state(dev);
41017f0c 978 pci_restore_msi_state(dev);
8c5cdb6a 979 pci_restore_iov_state(dev);
8fed4b65 980
4b77b0a2 981 dev->state_saved = false;
1da177e4
LT		 982}
983
ffbdd3f7
AW		 984struct pci_saved_state {
985 u32 config_space[16];
986 struct pci_cap_saved_data cap[0];
987};
988
989/**
990 * pci_store_saved_state - Allocate and return an opaque struct containing
991 * the device saved state.
992 * @dev: PCI device that we're dealing with
993 *
994 * Rerturn NULL if no state or error.
995 */
996struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
997{
998 struct pci_saved_state *state;
999 struct pci_cap_saved_state *tmp;
1000 struct pci_cap_saved_data *cap;
1001 struct hlist_node *pos;
1002 size_t size;
1003
1004 if (!dev->state_saved)
1005 return NULL;
1006
1007 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1008
1009 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1010 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1011
1012 state = kzalloc(size, GFP_KERNEL);
1013 if (!state)
1014 return NULL;
1015
1016 memcpy(state->config_space, dev->saved_config_space,
1017 sizeof(state->config_space));
1018
1019 cap = state->cap;
1020 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1021 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1022 memcpy(cap, &tmp->cap, len);
1023 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1024 }
1025 /* Empty cap_save terminates list */
1026
1027 return state;
1028}
1029EXPORT_SYMBOL_GPL(pci_store_saved_state);
1030
1031/**
1032 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1033 * @dev: PCI device that we're dealing with
1034 * @state: Saved state returned from pci_store_saved_state()
1035 */
1036int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1037{
1038 struct pci_cap_saved_data *cap;
1039
1040 dev->state_saved = false;
1041
1042 if (!state)
1043 return 0;
1044
1045 memcpy(dev->saved_config_space, state->config_space,
1046 sizeof(state->config_space));
1047
1048 cap = state->cap;
1049 while (cap->size) {
1050 struct pci_cap_saved_state *tmp;
1051
1052 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1053 if (!tmp || tmp->cap.size != cap->size)
1054 return -EINVAL;
1055
1056 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1057 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1058 sizeof(struct pci_cap_saved_data) + cap->size);
1059 }
1060
1061 dev->state_saved = true;
1062 return 0;
1063}
1064EXPORT_SYMBOL_GPL(pci_load_saved_state);
1065
1066/**
1067 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1068 * and free the memory allocated for it.
1069 * @dev: PCI device that we're dealing with
1070 * @state: Pointer to saved state returned from pci_store_saved_state()
1071 */
1072int pci_load_and_free_saved_state(struct pci_dev *dev,
1073 struct pci_saved_state **state)
1074{
1075 int ret = pci_load_saved_state(dev, *state);
1076 kfree(*state);
1077 *state = NULL;
1078 return ret;
1079}
1080EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1081
38cc1302
HS		 1082static int do_pci_enable_device(struct pci_dev *dev, int bars)
1083{
1084 int err;
1085
1086 err = pci_set_power_state(dev, PCI_D0);
1087 if (err < 0 && err != -EIO)
1088 return err;
1089 err = pcibios_enable_device(dev, bars);
1090 if (err < 0)
1091 return err;
1092 pci_fixup_device(pci_fixup_enable, dev);
1093
1094 return 0;
1095}
1096
1097/**
0b62e13b 1098 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 1099 * @dev: PCI device to be resumed
1100 *
1101 * Note this function is a backend of pci_default_resume and is not supposed
1102 * to be called by normal code, write proper resume handler and use it instead.
1103 */
0b62e13b 1104int pci_reenable_device(struct pci_dev *dev)
38cc1302 1105{
296ccb08 1106 if (pci_is_enabled(dev))
38cc1302
HS		 1107 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1108 return 0;
1109}
1110
b718989d
BH		 1111static int __pci_enable_device_flags(struct pci_dev *dev,
1112 resource_size_t flags)
1da177e4
LT		 1113{
1114 int err;
b718989d 1115 int i, bars = 0;
1da177e4 1116
97c145f7
JB		 1117 /*
1118 * Power state could be unknown at this point, either due to a fresh
1119 * boot or a device removal call. So get the current power state
1120 * so that things like MSI message writing will behave as expected
1121 * (e.g. if the device really is in D0 at enable time).
1122 */
1123 if (dev->pm_cap) {
1124 u16 pmcsr;
1125 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1126 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1127 }
1128
9fb625c3
HS		 1129 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1130 return 0; /* already enabled */
1131
bbef98ab 1132 for (i = 0; i < PCI_ROM_RESOURCE; i++)
b718989d
BH		 1133 if (dev->resource[i].flags & flags)
1134 bars |= (1 << i);
1135
38cc1302 1136 err = do_pci_enable_device(dev, bars);
95a62965 1137 if (err < 0)
38cc1302 1138 atomic_dec(&dev->enable_cnt);
9fb625c3 1139 return err;
1da177e4
LT		 1140}
1141
b718989d
BH		 1142/**
1143 * pci_enable_device_io - Initialize a device for use with IO space
1144 * @dev: PCI device to be initialized
1145 *
1146 * Initialize device before it's used by a driver. Ask low-level code
1147 * to enable I/O resources. Wake up the device if it was suspended.
1148 * Beware, this function can fail.
1149 */
1150int pci_enable_device_io(struct pci_dev *dev)
1151{
1152 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1153}
1154
1155/**
1156 * pci_enable_device_mem - Initialize a device for use with Memory space
1157 * @dev: PCI device to be initialized
1158 *
1159 * Initialize device before it's used by a driver. Ask low-level code
1160 * to enable Memory resources. Wake up the device if it was suspended.
1161 * Beware, this function can fail.
1162 */
1163int pci_enable_device_mem(struct pci_dev *dev)
1164{
1165 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1166}
1167
bae94d02
IPG		 1168/**
1169 * pci_enable_device - Initialize device before it's used by a driver.
1170 * @dev: PCI device to be initialized
1171 *
1172 * Initialize device before it's used by a driver. Ask low-level code
1173 * to enable I/O and memory. Wake up the device if it was suspended.
1174 * Beware, this function can fail.
1175 *
1176 * Note we don't actually enable the device many times if we call
1177 * this function repeatedly (we just increment the count).
1178 */
1179int pci_enable_device(struct pci_dev *dev)
1180{
b718989d 1181 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1182}
1183
9ac7849e
TH		 1184/*
1185 * Managed PCI resources. This manages device on/off, intx/msi/msix
1186 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1187 * there's no need to track it separately. pci_devres is initialized
1188 * when a device is enabled using managed PCI device enable interface.
1189 */
1190struct pci_devres {
7f375f32
TH		 1191 unsigned int enabled:1;
1192 unsigned int pinned:1;
9ac7849e
TH		 1193 unsigned int orig_intx:1;
1194 unsigned int restore_intx:1;
1195 u32 region_mask;
1196};
1197
1198static void pcim_release(struct device *gendev, void *res)
1199{
1200 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1201 struct pci_devres *this = res;
1202 int i;
1203
1204 if (dev->msi_enabled)
1205 pci_disable_msi(dev);
1206 if (dev->msix_enabled)
1207 pci_disable_msix(dev);
1208
1209 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1210 if (this->region_mask & (1 << i))
1211 pci_release_region(dev, i);
1212
1213 if (this->restore_intx)
1214 pci_intx(dev, this->orig_intx);
1215
7f375f32 1216 if (this->enabled && !this->pinned)
9ac7849e
TH		 1217 pci_disable_device(dev);
1218}
1219
1220static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1221{
1222 struct pci_devres *dr, *new_dr;
1223
1224 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1225 if (dr)
1226 return dr;
1227
1228 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1229 if (!new_dr)
1230 return NULL;
1231 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1232}
1233
1234static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1235{
1236 if (pci_is_managed(pdev))
1237 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1238 return NULL;
1239}
1240
1241/**
1242 * pcim_enable_device - Managed pci_enable_device()
1243 * @pdev: PCI device to be initialized
1244 *
1245 * Managed pci_enable_device().
1246 */
1247int pcim_enable_device(struct pci_dev *pdev)
1248{
1249 struct pci_devres *dr;
1250 int rc;
1251
1252 dr = get_pci_dr(pdev);
1253 if (unlikely(!dr))
1254 return -ENOMEM;
b95d58ea
TH		 1255 if (dr->enabled)
1256 return 0;
9ac7849e
TH		 1257
1258 rc = pci_enable_device(pdev);
1259 if (!rc) {
1260 pdev->is_managed = 1;
7f375f32 1261 dr->enabled = 1;
9ac7849e
TH		 1262 }
1263 return rc;
1264}
1265
1266/**
1267 * pcim_pin_device - Pin managed PCI device
1268 * @pdev: PCI device to pin
1269 *
1270 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1271 * driver detach. @pdev must have been enabled with
1272 * pcim_enable_device().
1273 */
1274void pcim_pin_device(struct pci_dev *pdev)
1275{
1276 struct pci_devres *dr;
1277
1278 dr = find_pci_dr(pdev);
7f375f32 1279 WARN_ON(!dr || !dr->enabled);
9ac7849e 1280 if (dr)
7f375f32 1281 dr->pinned = 1;
9ac7849e
TH		 1282}
1283
1da177e4
LT		 1284/**
1285 * pcibios_disable_device - disable arch specific PCI resources for device dev
1286 * @dev: the PCI device to disable
1287 *
1288 * Disables architecture specific PCI resources for the device. This
1289 * is the default implementation. Architecture implementations can
1290 * override this.
1291 */
1292void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1293
fa58d305
RW		 1294static void do_pci_disable_device(struct pci_dev *dev)
1295{
1296 u16 pci_command;
1297
1298 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1299 if (pci_command & PCI_COMMAND_MASTER) {
1300 pci_command &= ~PCI_COMMAND_MASTER;
1301 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1302 }
1303
1304 pcibios_disable_device(dev);
1305}
1306
1307/**
1308 * pci_disable_enabled_device - Disable device without updating enable_cnt
1309 * @dev: PCI device to disable
1310 *
1311 * NOTE: This function is a backend of PCI power management routines and is
1312 * not supposed to be called drivers.
1313 */
1314void pci_disable_enabled_device(struct pci_dev *dev)
1315{
296ccb08 1316 if (pci_is_enabled(dev))
fa58d305
RW		 1317 do_pci_disable_device(dev);
1318}
1319
1da177e4
LT		 1320/**
1321 * pci_disable_device - Disable PCI device after use
1322 * @dev: PCI device to be disabled
1323 *
1324 * Signal to the system that the PCI device is not in use by the system
1325 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1326 *
1327 * Note we don't actually disable the device until all callers of
ee6583f6 1328 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1329 */
1330void
1331pci_disable_device(struct pci_dev *dev)
1332{
9ac7849e 1333 struct pci_devres *dr;
99dc804d 1334
9ac7849e
TH		 1335 dr = find_pci_dr(dev);
1336 if (dr)
7f375f32 1337 dr->enabled = 0;
9ac7849e 1338
bae94d02
IPG		 1339 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1340 return;
1341
fa58d305 1342 do_pci_disable_device(dev);
1da177e4 1343
fa58d305 1344 dev->is_busmaster = 0;
1da177e4
LT		 1345}
1346
f7bdd12d
BK		 1347/**
1348 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1349 * @dev: the PCIe device reset
f7bdd12d
BK		 1350 * @state: Reset state to enter into
1351 *
1352 *
45e829ea 1353 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1354 * implementation. Architecture implementations can override this.
1355 */
1356int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1357 enum pcie_reset_state state)
1358{
1359 return -EINVAL;
1360}
1361
1362/**
1363 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1364 * @dev: the PCIe device reset
f7bdd12d
BK		 1365 * @state: Reset state to enter into
1366 *
1367 *
1368 * Sets the PCI reset state for the device.
1369 */
1370int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1371{
1372 return pcibios_set_pcie_reset_state(dev, state);
1373}
1374
58ff4633
RW		 1375/**
1376 * pci_check_pme_status - Check if given device has generated PME.
1377 * @dev: Device to check.
1378 *
1379 * Check the PME status of the device and if set, clear it and clear PME enable
1380 * (if set). Return 'true' if PME status and PME enable were both set or
1381 * 'false' otherwise.
1382 */
1383bool pci_check_pme_status(struct pci_dev *dev)
1384{
1385 int pmcsr_pos;
1386 u16 pmcsr;
1387 bool ret = false;
1388
1389 if (!dev->pm_cap)
1390 return false;
1391
1392 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1393 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1394 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1395 return false;
1396
1397 /* Clear PME status. */
1398 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1399 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1400 /* Disable PME to avoid interrupt flood. */
1401 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1402 ret = true;
1403 }
1404
1405 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1406
1407 return ret;
1408}
1409
b67ea761
RW		 1410/**
1411 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1412 * @dev: Device to handle.
379021d5 1413 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
b67ea761
RW		 1414 *
1415 * Check if @dev has generated PME and queue a resume request for it in that
1416 * case.
1417 */
379021d5 1418static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
b67ea761 1419{
379021d5
RW		 1420 if (pme_poll_reset && dev->pme_poll)
1421 dev->pme_poll = false;
1422
c125e96f 1423 if (pci_check_pme_status(dev)) {
c125e96f 1424 pci_wakeup_event(dev);
0f953bf6 1425 pm_request_resume(&dev->dev);
c125e96f 1426 }
b67ea761
RW		 1427 return 0;
1428}
1429
1430/**
1431 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1432 * @bus: Top bus of the subtree to walk.
1433 */
1434void pci_pme_wakeup_bus(struct pci_bus *bus)
1435{
1436 if (bus)
379021d5 1437 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
b67ea761
RW		 1438}
1439
eb9d0fe4
RW		 1440/**
1441 * pci_pme_capable - check the capability of PCI device to generate PME#
1442 * @dev: PCI device to handle.
eb9d0fe4
RW		 1443 * @state: PCI state from which device will issue PME#.
1444 */
e5899e1b 1445bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1446{
337001b6 1447 if (!dev->pm_cap)
eb9d0fe4
RW		 1448 return false;
1449
337001b6 1450 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1451}
1452
df17e62e
MG		 1453static void pci_pme_list_scan(struct work_struct *work)
1454{
379021d5 1455 struct pci_pme_device *pme_dev, *n;
df17e62e
MG		 1456
1457 mutex_lock(&pci_pme_list_mutex);
1458 if (!list_empty(&pci_pme_list)) {
379021d5
RW		 1459 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1460 if (pme_dev->dev->pme_poll) {
1461 pci_pme_wakeup(pme_dev->dev, NULL);
1462 } else {
1463 list_del(&pme_dev->list);
1464 kfree(pme_dev);
1465 }
1466 }
1467 if (!list_empty(&pci_pme_list))
1468 schedule_delayed_work(&pci_pme_work,
1469 msecs_to_jiffies(PME_TIMEOUT));
df17e62e
MG		 1470 }
1471 mutex_unlock(&pci_pme_list_mutex);
1472}
1473
eb9d0fe4
RW		 1474/**
1475 * pci_pme_active - enable or disable PCI device's PME# function
1476 * @dev: PCI device to handle.
eb9d0fe4
RW		 1477 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1478 *
1479 * The caller must verify that the device is capable of generating PME# before
1480 * calling this function with @enable equal to 'true'.
1481 */
5a6c9b60 1482void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1483{
1484 u16 pmcsr;
1485
337001b6 1486 if (!dev->pm_cap)
eb9d0fe4
RW		 1487 return;
1488
337001b6 1489 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1490 /* Clear PME_Status by writing 1 to it and enable PME# */
1491 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1492 if (!enable)
1493 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1494
337001b6 1495 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1496
df17e62e
MG		 1497 /* PCI (as opposed to PCIe) PME requires that the device have
1498 its PME# line hooked up correctly. Not all hardware vendors
1499 do this, so the PME never gets delivered and the device
1500 remains asleep. The easiest way around this is to
1501 periodically walk the list of suspended devices and check
1502 whether any have their PME flag set. The assumption is that
1503 we'll wake up often enough anyway that this won't be a huge
1504 hit, and the power savings from the devices will still be a
1505 win. */
1506
379021d5 1507 if (dev->pme_poll) {
df17e62e
MG		 1508 struct pci_pme_device *pme_dev;
1509 if (enable) {
1510 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1511 GFP_KERNEL);
1512 if (!pme_dev)
1513 goto out;
1514 pme_dev->dev = dev;
1515 mutex_lock(&pci_pme_list_mutex);
1516 list_add(&pme_dev->list, &pci_pme_list);
1517 if (list_is_singular(&pci_pme_list))
1518 schedule_delayed_work(&pci_pme_work,
1519 msecs_to_jiffies(PME_TIMEOUT));
1520 mutex_unlock(&pci_pme_list_mutex);
1521 } else {
1522 mutex_lock(&pci_pme_list_mutex);
1523 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1524 if (pme_dev->dev == dev) {
1525 list_del(&pme_dev->list);
1526 kfree(pme_dev);
1527 break;
1528 }
1529 }
1530 mutex_unlock(&pci_pme_list_mutex);
1531 }
1532 }
1533
1534out:
10c3d71d 1535 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
eb9d0fe4
RW		 1536 enable ? "enabled" : "disabled");
1537}
1538
1da177e4 1539/**
6cbf8214 1540 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1541 * @dev: PCI device affected
1542 * @state: PCI state from which device will issue wakeup events
6cbf8214 1543 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1544 * @enable: True to enable event generation; false to disable
1545 *
1546 * This enables the device as a wakeup event source, or disables it.
1547 * When such events involves platform-specific hooks, those hooks are
1548 * called automatically by this routine.
1549 *
1550 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1551 * always require such platform hooks.
075c1771 1552 *
eb9d0fe4
RW		 1553 * RETURN VALUE:
1554 * 0 is returned on success
1555 * -EINVAL is returned if device is not supposed to wake up the system
1556 * Error code depending on the platform is returned if both the platform and
1557 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1558 */
6cbf8214
RW		 1559int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1560 bool runtime, bool enable)
1da177e4 1561{
5bcc2fb4 1562 int ret = 0;
075c1771 1563
6cbf8214 1564 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1565 return -EINVAL;
1da177e4 1566
e80bb09d
RW		 1567 /* Don't do the same thing twice in a row for one device. */
1568 if (!!enable == !!dev->wakeup_prepared)
1569 return 0;
1570
eb9d0fe4
RW		 1571 /*
1572 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1573 * Anderson we should be doing PME# wake enable followed by ACPI wake
1574 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1575 */
1da177e4 1576
5bcc2fb4
RW		 1577 if (enable) {
1578 int error;
1da177e4 1579
5bcc2fb4
RW		 1580 if (pci_pme_capable(dev, state))
1581 pci_pme_active(dev, true);
1582 else
1583 ret = 1;
6cbf8214
RW		 1584 error = runtime ? platform_pci_run_wake(dev, true) :
1585 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1586 if (ret)
1587 ret = error;
e80bb09d
RW		 1588 if (!ret)
1589 dev->wakeup_prepared = true;
5bcc2fb4 1590 } else {
6cbf8214
RW		 1591 if (runtime)
1592 platform_pci_run_wake(dev, false);
1593 else
1594 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1595 pci_pme_active(dev, false);
e80bb09d 1596 dev->wakeup_prepared = false;
5bcc2fb4 1597 }
1da177e4 1598
5bcc2fb4 1599 return ret;
eb9d0fe4 1600}
6cbf8214 1601EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1602
0235c4fc
RW		 1603/**
1604 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1605 * @dev: PCI device to prepare
1606 * @enable: True to enable wake-up event generation; false to disable
1607 *
1608 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1609 * and this function allows them to set that up cleanly - pci_enable_wake()
1610 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1611 * ordering constraints.
1612 *
1613 * This function only returns error code if the device is not capable of
1614 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1615 * enable wake-up power for it.
1616 */
1617int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1618{
1619 return pci_pme_capable(dev, PCI_D3cold) ?
1620 pci_enable_wake(dev, PCI_D3cold, enable) :
1621 pci_enable_wake(dev, PCI_D3hot, enable);
1622}
1623
404cc2d8 1624/**
37139074
JB		 1625 * pci_target_state - find an appropriate low power state for a given PCI dev
1626 * @dev: PCI device
1627 *
1628 * Use underlying platform code to find a supported low power state for @dev.
1629 * If the platform can't manage @dev, return the deepest state from which it
1630 * can generate wake events, based on any available PME info.
404cc2d8 1631 */
e5899e1b 1632pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1633{
1634 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1635
1636 if (platform_pci_power_manageable(dev)) {
1637 /*
1638 * Call the platform to choose the target state of the device
1639 * and enable wake-up from this state if supported.
1640 */
1641 pci_power_t state = platform_pci_choose_state(dev);
1642
1643 switch (state) {
1644 case PCI_POWER_ERROR:
1645 case PCI_UNKNOWN:
1646 break;
1647 case PCI_D1:
1648 case PCI_D2:
1649 if (pci_no_d1d2(dev))
1650 break;
1651 default:
1652 target_state = state;
404cc2d8 1653 }
d2abdf62
RW		 1654 } else if (!dev->pm_cap) {
1655 target_state = PCI_D0;
404cc2d8
RW		 1656 } else if (device_may_wakeup(&dev->dev)) {
1657 /*
1658 * Find the deepest state from which the device can generate
1659 * wake-up events, make it the target state and enable device
1660 * to generate PME#.
1661 */
337001b6
RW		 1662 if (dev->pme_support) {
1663 while (target_state
1664 && !(dev->pme_support & (1 << target_state)))
1665 target_state--;
404cc2d8
RW		 1666 }
1667 }
1668
e5899e1b
RW		 1669 return target_state;
1670}
1671
1672/**
1673 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1674 * @dev: Device to handle.
1675 *
1676 * Choose the power state appropriate for the device depending on whether
1677 * it can wake up the system and/or is power manageable by the platform
1678 * (PCI_D3hot is the default) and put the device into that state.
1679 */
1680int pci_prepare_to_sleep(struct pci_dev *dev)
1681{
1682 pci_power_t target_state = pci_target_state(dev);
1683 int error;
1684
1685 if (target_state == PCI_POWER_ERROR)
1686 return -EIO;
1687
8efb8c76 1688 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1689
404cc2d8
RW		 1690 error = pci_set_power_state(dev, target_state);
1691
1692 if (error)
1693 pci_enable_wake(dev, target_state, false);
1694
1695 return error;
1696}
1697
1698/**
443bd1c4 1699 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1700 * @dev: Device to handle.
1701 *
88393161 1702 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1703 */
1704int pci_back_from_sleep(struct pci_dev *dev)
1705{
1706 pci_enable_wake(dev, PCI_D0, false);
1707 return pci_set_power_state(dev, PCI_D0);
1708}
1709
6cbf8214
RW		 1710/**
1711 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1712 * @dev: PCI device being suspended.
1713 *
1714 * Prepare @dev to generate wake-up events at run time and put it into a low
1715 * power state.
1716 */
1717int pci_finish_runtime_suspend(struct pci_dev *dev)
1718{
1719 pci_power_t target_state = pci_target_state(dev);
1720 int error;
1721
1722 if (target_state == PCI_POWER_ERROR)
1723 return -EIO;
1724
1725 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1726
1727 error = pci_set_power_state(dev, target_state);
1728
1729 if (error)
1730 __pci_enable_wake(dev, target_state, true, false);
1731
1732 return error;
1733}
1734
b67ea761
RW		 1735/**
1736 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1737 * @dev: Device to check.
1738 *
1739 * Return true if the device itself is cabable of generating wake-up events
1740 * (through the platform or using the native PCIe PME) or if the device supports
1741 * PME and one of its upstream bridges can generate wake-up events.
1742 */
1743bool pci_dev_run_wake(struct pci_dev *dev)
1744{
1745 struct pci_bus *bus = dev->bus;
1746
1747 if (device_run_wake(&dev->dev))
1748 return true;
1749
1750 if (!dev->pme_support)
1751 return false;
1752
1753 while (bus->parent) {
1754 struct pci_dev *bridge = bus->self;
1755
1756 if (device_run_wake(&bridge->dev))
1757 return true;
1758
1759 bus = bus->parent;
1760 }
1761
1762 /* We have reached the root bus. */
1763 if (bus->bridge)
1764 return device_run_wake(bus->bridge);
1765
1766 return false;
1767}
1768EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1769
eb9d0fe4
RW		 1770/**
1771 * pci_pm_init - Initialize PM functions of given PCI device
1772 * @dev: PCI device to handle.
1773 */
1774void pci_pm_init(struct pci_dev *dev)
1775{
1776 int pm;
1777 u16 pmc;
1da177e4 1778
bb910a70 1779 pm_runtime_forbid(&dev->dev);
a1e4d72c 1780 device_enable_async_suspend(&dev->dev);
e80bb09d 1781 dev->wakeup_prepared = false;
bb910a70 1782
337001b6
RW		 1783 dev->pm_cap = 0;
1784
eb9d0fe4
RW		 1785 /* find PCI PM capability in list */
1786 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1787 if (!pm)
50246dd4 1788 return;
eb9d0fe4
RW		 1789 /* Check device's ability to generate PME# */
1790 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1791
eb9d0fe4
RW		 1792 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1793 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1794 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1795 return;
eb9d0fe4
RW		 1796 }
1797
337001b6 1798 dev->pm_cap = pm;
1ae861e6 1799 dev->d3_delay = PCI_PM_D3_WAIT;
337001b6
RW		 1800
1801 dev->d1_support = false;
1802 dev->d2_support = false;
1803 if (!pci_no_d1d2(dev)) {
c9ed77ee 1804 if (pmc & PCI_PM_CAP_D1)
337001b6 1805 dev->d1_support = true;
c9ed77ee 1806 if (pmc & PCI_PM_CAP_D2)
337001b6 1807 dev->d2_support = true;
c9ed77ee
BH		 1808
1809 if (dev->d1_support || dev->d2_support)
1810 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1811 dev->d1_support ? " D1" : "",
1812 dev->d2_support ? " D2" : "");
337001b6
RW		 1813 }
1814
1815 pmc &= PCI_PM_CAP_PME_MASK;
1816 if (pmc) {
10c3d71d
BH		 1817 dev_printk(KERN_DEBUG, &dev->dev,
1818 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1819 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1820 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1821 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1822 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1823 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1824 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
379021d5 1825 dev->pme_poll = true;
eb9d0fe4
RW		 1826 /*
1827 * Make device's PM flags reflect the wake-up capability, but
1828 * let the user space enable it to wake up the system as needed.
1829 */
1830 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 1831 /* Disable the PME# generation functionality */
337001b6
RW		 1832 pci_pme_active(dev, false);
1833 } else {
1834 dev->pme_support = 0;
eb9d0fe4 1835 }
1da177e4
LT		 1836}
1837
eb9c39d0
JB		 1838/**
1839 * platform_pci_wakeup_init - init platform wakeup if present
1840 * @dev: PCI device
1841 *
1842 * Some devices don't have PCI PM caps but can still generate wakeup
1843 * events through platform methods (like ACPI events). If @dev supports
1844 * platform wakeup events, set the device flag to indicate as much. This
1845 * may be redundant if the device also supports PCI PM caps, but double
1846 * initialization should be safe in that case.
1847 */
1848void platform_pci_wakeup_init(struct pci_dev *dev)
1849{
1850 if (!platform_pci_can_wakeup(dev))
1851 return;
1852
1853 device_set_wakeup_capable(&dev->dev, true);
eb9c39d0
JB		 1854 platform_pci_sleep_wake(dev, false);
1855}
1856
63f4898a
RW		 1857/**
1858 * pci_add_save_buffer - allocate buffer for saving given capability registers
1859 * @dev: the PCI device
1860 * @cap: the capability to allocate the buffer for
1861 * @size: requested size of the buffer
1862 */
1863static int pci_add_cap_save_buffer(
1864 struct pci_dev *dev, char cap, unsigned int size)
1865{
1866 int pos;
1867 struct pci_cap_saved_state *save_state;
1868
1869 pos = pci_find_capability(dev, cap);
1870 if (pos <= 0)
1871 return 0;
1872
1873 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1874 if (!save_state)
1875 return -ENOMEM;
1876
24a4742f
AW		 1877 save_state->cap.cap_nr = cap;
1878 save_state->cap.size = size;
63f4898a
RW		 1879 pci_add_saved_cap(dev, save_state);
1880
1881 return 0;
1882}
1883
1884/**
1885 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1886 * @dev: the PCI device
1887 */
1888void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1889{
1890 int error;
1891
89858517
YZ		 1892 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1893 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 1894 if (error)
1895 dev_err(&dev->dev,
1896 "unable to preallocate PCI Express save buffer\n");
1897
1898 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1899 if (error)
1900 dev_err(&dev->dev,
1901 "unable to preallocate PCI-X save buffer\n");
1902}
1903
58c3a727
YZ		 1904/**
1905 * pci_enable_ari - enable ARI forwarding if hardware support it
1906 * @dev: the PCI device
1907 */
1908void pci_enable_ari(struct pci_dev *dev)
1909{
1910 int pos;
1911 u32 cap;
864d296c 1912 u16 flags, ctrl;
8113587c 1913 struct pci_dev *bridge;
58c3a727 1914
5f4d91a1 1915 if (!pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 1916 return;
1917
8113587c
ZY		 1918 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1919 if (!pos)
58c3a727
YZ		 1920 return;
1921
8113587c 1922 bridge = dev->bus->self;
5f4d91a1 1923 if (!bridge || !pci_is_pcie(bridge))
8113587c
ZY		 1924 return;
1925
06a1cbaf 1926 pos = pci_pcie_cap(bridge);
58c3a727
YZ		 1927 if (!pos)
1928 return;
1929
864d296c
CW		 1930 /* ARI is a PCIe v2 feature */
1931 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1932 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1933 return;
1934
8113587c 1935 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 1936 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1937 return;
1938
8113587c 1939 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
58c3a727 1940 ctrl |= PCI_EXP_DEVCTL2_ARI;
8113587c 1941 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
58c3a727 1942
8113587c 1943 bridge->ari_enabled = 1;
58c3a727
YZ		 1944}
1945
b48d4425
JB		 1946/**
1947 * pci_enable_ido - enable ID-based ordering on a device
1948 * @dev: the PCI device
1949 * @type: which types of IDO to enable
1950 *
1951 * Enable ID-based ordering on @dev. @type can contain the bits
1952 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1953 * which types of transactions are allowed to be re-ordered.
1954 */
1955void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1956{
1957 int pos;
1958 u16 ctrl;
1959
1960 pos = pci_pcie_cap(dev);
1961 if (!pos)
1962 return;
1963
1964 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1965 if (type & PCI_EXP_IDO_REQUEST)
1966 ctrl |= PCI_EXP_IDO_REQ_EN;
1967 if (type & PCI_EXP_IDO_COMPLETION)
1968 ctrl |= PCI_EXP_IDO_CMP_EN;
1969 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1970}
1971EXPORT_SYMBOL(pci_enable_ido);
1972
1973/**
1974 * pci_disable_ido - disable ID-based ordering on a device
1975 * @dev: the PCI device
1976 * @type: which types of IDO to disable
1977 */
1978void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1979{
1980 int pos;
1981 u16 ctrl;
1982
1983 if (!pci_is_pcie(dev))
1984 return;
1985
1986 pos = pci_pcie_cap(dev);
1987 if (!pos)
1988 return;
1989
1990 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1991 if (type & PCI_EXP_IDO_REQUEST)
1992 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1993 if (type & PCI_EXP_IDO_COMPLETION)
1994 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1995 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1996}
1997EXPORT_SYMBOL(pci_disable_ido);
1998
48a92a81
JB		 1999/**
2000 * pci_enable_obff - enable optimized buffer flush/fill
2001 * @dev: PCI device
2002 * @type: type of signaling to use
2003 *
2004 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2005 * signaling if possible, falling back to message signaling only if
2006 * WAKE# isn't supported. @type should indicate whether the PCIe link
2007 * be brought out of L0s or L1 to send the message. It should be either
2008 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2009 *
2010 * If your device can benefit from receiving all messages, even at the
2011 * power cost of bringing the link back up from a low power state, use
2012 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2013 * preferred type).
2014 *
2015 * RETURNS:
2016 * Zero on success, appropriate error number on failure.
2017 */
2018int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2019{
2020 int pos;
2021 u32 cap;
2022 u16 ctrl;
2023 int ret;
2024
2025 if (!pci_is_pcie(dev))
2026 return -ENOTSUPP;
2027
2028 pos = pci_pcie_cap(dev);
2029 if (!pos)
2030 return -ENOTSUPP;
2031
2032 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2033 if (!(cap & PCI_EXP_OBFF_MASK))
2034 return -ENOTSUPP; /* no OBFF support at all */
2035
2036 /* Make sure the topology supports OBFF as well */
2037 if (dev->bus) {
2038 ret = pci_enable_obff(dev->bus->self, type);
2039 if (ret)
2040 return ret;
2041 }
2042
2043 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2044 if (cap & PCI_EXP_OBFF_WAKE)
2045 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2046 else {
2047 switch (type) {
2048 case PCI_EXP_OBFF_SIGNAL_L0:
2049 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2050 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2051 break;
2052 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2053 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2054 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2055 break;
2056 default:
2057 WARN(1, "bad OBFF signal type\n");
2058 return -ENOTSUPP;
2059 }
2060 }
2061 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2062
2063 return 0;
2064}
2065EXPORT_SYMBOL(pci_enable_obff);
2066
2067/**
2068 * pci_disable_obff - disable optimized buffer flush/fill
2069 * @dev: PCI device
2070 *
2071 * Disable OBFF on @dev.
2072 */
2073void pci_disable_obff(struct pci_dev *dev)
2074{
2075 int pos;
2076 u16 ctrl;
2077
2078 if (!pci_is_pcie(dev))
2079 return;
2080
2081 pos = pci_pcie_cap(dev);
2082 if (!pos)
2083 return;
2084
2085 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2086 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2087 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2088}
2089EXPORT_SYMBOL(pci_disable_obff);
2090
51c2e0a7
JB		 2091/**
2092 * pci_ltr_supported - check whether a device supports LTR
2093 * @dev: PCI device
2094 *
2095 * RETURNS:
2096 * True if @dev supports latency tolerance reporting, false otherwise.
2097 */
2098bool pci_ltr_supported(struct pci_dev *dev)
2099{
2100 int pos;
2101 u32 cap;
2102
2103 if (!pci_is_pcie(dev))
2104 return false;
2105
2106 pos = pci_pcie_cap(dev);
2107 if (!pos)
2108 return false;
2109
2110 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2111
2112 return cap & PCI_EXP_DEVCAP2_LTR;
2113}
2114EXPORT_SYMBOL(pci_ltr_supported);
2115
2116/**
2117 * pci_enable_ltr - enable latency tolerance reporting
2118 * @dev: PCI device
2119 *
2120 * Enable LTR on @dev if possible, which means enabling it first on
2121 * upstream ports.
2122 *
2123 * RETURNS:
2124 * Zero on success, errno on failure.
2125 */
2126int pci_enable_ltr(struct pci_dev *dev)
2127{
2128 int pos;
2129 u16 ctrl;
2130 int ret;
2131
2132 if (!pci_ltr_supported(dev))
2133 return -ENOTSUPP;
2134
2135 pos = pci_pcie_cap(dev);
2136 if (!pos)
2137 return -ENOTSUPP;
2138
2139 /* Only primary function can enable/disable LTR */
2140 if (PCI_FUNC(dev->devfn) != 0)
2141 return -EINVAL;
2142
2143 /* Enable upstream ports first */
2144 if (dev->bus) {
2145 ret = pci_enable_ltr(dev->bus->self);
2146 if (ret)
2147 return ret;
2148 }
2149
2150 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2151 ctrl |= PCI_EXP_LTR_EN;
2152 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2153
2154 return 0;
2155}
2156EXPORT_SYMBOL(pci_enable_ltr);
2157
2158/**
2159 * pci_disable_ltr - disable latency tolerance reporting
2160 * @dev: PCI device
2161 */
2162void pci_disable_ltr(struct pci_dev *dev)
2163{
2164 int pos;
2165 u16 ctrl;
2166
2167 if (!pci_ltr_supported(dev))
2168 return;
2169
2170 pos = pci_pcie_cap(dev);
2171 if (!pos)
2172 return;
2173
2174 /* Only primary function can enable/disable LTR */
2175 if (PCI_FUNC(dev->devfn) != 0)
2176 return;
2177
2178 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2179 ctrl &= ~PCI_EXP_LTR_EN;
2180 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2181}
2182EXPORT_SYMBOL(pci_disable_ltr);
2183
2184static int __pci_ltr_scale(int *val)
2185{
2186 int scale = 0;
2187
2188 while (*val > 1023) {
2189 *val = (*val + 31) / 32;
2190 scale++;
2191 }
2192 return scale;
2193}
2194
2195/**
2196 * pci_set_ltr - set LTR latency values
2197 * @dev: PCI device
2198 * @snoop_lat_ns: snoop latency in nanoseconds
2199 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2200 *
2201 * Figure out the scale and set the LTR values accordingly.
2202 */
2203int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2204{
2205 int pos, ret, snoop_scale, nosnoop_scale;
2206 u16 val;
2207
2208 if (!pci_ltr_supported(dev))
2209 return -ENOTSUPP;
2210
2211 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2212 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2213
2214 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2215 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2216 return -EINVAL;
2217
2218 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2219 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2220 return -EINVAL;
2221
2222 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2223 if (!pos)
2224 return -ENOTSUPP;
2225
2226 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2227 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2228 if (ret != 4)
2229 return -EIO;
2230
2231 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2232 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2233 if (ret != 4)
2234 return -EIO;
2235
2236 return 0;
2237}
2238EXPORT_SYMBOL(pci_set_ltr);
2239
5d990b62
CW		 2240static int pci_acs_enable;
2241
2242/**
2243 * pci_request_acs - ask for ACS to be enabled if supported
2244 */
2245void pci_request_acs(void)
2246{
2247 pci_acs_enable = 1;
2248}
2249
ae21ee65
AK		 2250/**
2251 * pci_enable_acs - enable ACS if hardware support it
2252 * @dev: the PCI device
2253 */
2254void pci_enable_acs(struct pci_dev *dev)
2255{
2256 int pos;
2257 u16 cap;
2258 u16 ctrl;
2259
5d990b62
CW		 2260 if (!pci_acs_enable)
2261 return;
2262
5f4d91a1 2263 if (!pci_is_pcie(dev))
ae21ee65
AK		 2264 return;
2265
2266 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2267 if (!pos)
2268 return;
2269
2270 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2271 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2272
2273 /* Source Validation */
2274 ctrl |= (cap & PCI_ACS_SV);
2275
2276 /* P2P Request Redirect */
2277 ctrl |= (cap & PCI_ACS_RR);
2278
2279 /* P2P Completion Redirect */
2280 ctrl |= (cap & PCI_ACS_CR);
2281
2282 /* Upstream Forwarding */
2283 ctrl |= (cap & PCI_ACS_UF);
2284
2285 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2286}
2287
57c2cf71
BH		 2288/**
2289 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2290 * @dev: the PCI device
2291 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2292 *
2293 * Perform INTx swizzling for a device behind one level of bridge. This is
2294 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2295 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2296 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2297 * the PCI Express Base Specification, Revision 2.1)
57c2cf71
BH		 2298 */
2299u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2300{
46b952a3
MW		 2301 int slot;
2302
2303 if (pci_ari_enabled(dev->bus))
2304 slot = 0;
2305 else
2306 slot = PCI_SLOT(dev->devfn);
2307
2308 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2309}
2310
1da177e4
LT		 2311int
2312pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2313{
2314 u8 pin;
2315
514d207d 2316 pin = dev->pin;
1da177e4
LT		 2317 if (!pin)
2318 return -1;
878f2e50 2319
8784fd4d 2320 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2321 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2322 dev = dev->bus->self;
2323 }
2324 *bridge = dev;
2325 return pin;
2326}
2327
68feac87
BH		 2328/**
2329 * pci_common_swizzle - swizzle INTx all the way to root bridge
2330 * @dev: the PCI device
2331 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2332 *
2333 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2334 * bridges all the way up to a PCI root bus.
2335 */
2336u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2337{
2338 u8 pin = *pinp;
2339
1eb39487 2340 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2341 pin = pci_swizzle_interrupt_pin(dev, pin);
2342 dev = dev->bus->self;
2343 }
2344 *pinp = pin;
2345 return PCI_SLOT(dev->devfn);
2346}
2347
1da177e4
LT		 2348/**
2349 * pci_release_region - Release a PCI bar
2350 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2351 * @bar: BAR to release
2352 *
2353 * Releases the PCI I/O and memory resources previously reserved by a
2354 * successful call to pci_request_region. Call this function only
2355 * after all use of the PCI regions has ceased.
2356 */
2357void pci_release_region(struct pci_dev *pdev, int bar)
2358{
9ac7849e
TH		 2359 struct pci_devres *dr;
2360
1da177e4
LT		 2361 if (pci_resource_len(pdev, bar) == 0)
2362 return;
2363 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2364 release_region(pci_resource_start(pdev, bar),
2365 pci_resource_len(pdev, bar));
2366 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2367 release_mem_region(pci_resource_start(pdev, bar),
2368 pci_resource_len(pdev, bar));
9ac7849e
TH		 2369
2370 dr = find_pci_dr(pdev);
2371 if (dr)
2372 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2373}
2374
2375/**
f5ddcac4 2376 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2377 * @pdev: PCI device whose resources are to be reserved
2378 * @bar: BAR to be reserved
2379 * @res_name: Name to be associated with resource.
f5ddcac4 2380 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2381 *
2382 * Mark the PCI region associated with PCI device @pdev BR @bar as
2383 * being reserved by owner @res_name. Do not access any
2384 * address inside the PCI regions unless this call returns
2385 * successfully.
2386 *
f5ddcac4
RD		 2387 * If @exclusive is set, then the region is marked so that userspace
2388 * is explicitly not allowed to map the resource via /dev/mem or
2389 * sysfs MMIO access.
2390 *
1da177e4
LT		 2391 * Returns 0 on success, or %EBUSY on error. A warning
2392 * message is also printed on failure.
2393 */
e8de1481
AV		 2394static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2395 int exclusive)
1da177e4 2396{
9ac7849e
TH		 2397 struct pci_devres *dr;
2398
1da177e4
LT		 2399 if (pci_resource_len(pdev, bar) == 0)
2400 return 0;
2401
2402 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2403 if (!request_region(pci_resource_start(pdev, bar),
2404 pci_resource_len(pdev, bar), res_name))
2405 goto err_out;
2406 }
2407 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2408 if (!__request_mem_region(pci_resource_start(pdev, bar),
2409 pci_resource_len(pdev, bar), res_name,
2410 exclusive))
1da177e4
LT		 2411 goto err_out;
2412 }
9ac7849e
TH		 2413
2414 dr = find_pci_dr(pdev);
2415 if (dr)
2416 dr->region_mask |= 1 << bar;
2417
1da177e4
LT		 2418 return 0;
2419
2420err_out:
c7dabef8 2421 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2422 &pdev->resource[bar]);
1da177e4
LT		 2423 return -EBUSY;
2424}
2425
e8de1481 2426/**
f5ddcac4 2427 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2428 * @pdev: PCI device whose resources are to be reserved
2429 * @bar: BAR to be reserved
f5ddcac4 2430 * @res_name: Name to be associated with resource
e8de1481 2431 *
f5ddcac4 2432 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2433 * being reserved by owner @res_name. Do not access any
2434 * address inside the PCI regions unless this call returns
2435 * successfully.
2436 *
2437 * Returns 0 on success, or %EBUSY on error. A warning
2438 * message is also printed on failure.
2439 */
2440int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2441{
2442 return __pci_request_region(pdev, bar, res_name, 0);
2443}
2444
2445/**
2446 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2447 * @pdev: PCI device whose resources are to be reserved
2448 * @bar: BAR to be reserved
2449 * @res_name: Name to be associated with resource.
2450 *
2451 * Mark the PCI region associated with PCI device @pdev BR @bar as
2452 * being reserved by owner @res_name. Do not access any
2453 * address inside the PCI regions unless this call returns
2454 * successfully.
2455 *
2456 * Returns 0 on success, or %EBUSY on error. A warning
2457 * message is also printed on failure.
2458 *
2459 * The key difference that _exclusive makes it that userspace is
2460 * explicitly not allowed to map the resource via /dev/mem or
2461 * sysfs.
2462 */
2463int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2464{
2465 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2466}
c87deff7
HS		 2467/**
2468 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2469 * @pdev: PCI device whose resources were previously reserved
2470 * @bars: Bitmask of BARs to be released
2471 *
2472 * Release selected PCI I/O and memory resources previously reserved.
2473 * Call this function only after all use of the PCI regions has ceased.
2474 */
2475void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2476{
2477 int i;
2478
2479 for (i = 0; i < 6; i++)
2480 if (bars & (1 << i))
2481 pci_release_region(pdev, i);
2482}
2483
e8de1481
AV		 2484int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2485 const char *res_name, int excl)
c87deff7
HS		 2486{
2487 int i;
2488
2489 for (i = 0; i < 6; i++)
2490 if (bars & (1 << i))
e8de1481 2491 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2492 goto err_out;
2493 return 0;
2494
2495err_out:
2496 while(--i >= 0)
2497 if (bars & (1 << i))
2498 pci_release_region(pdev, i);
2499
2500 return -EBUSY;
2501}
1da177e4 2502
e8de1481
AV		 2503
2504/**
2505 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2506 * @pdev: PCI device whose resources are to be reserved
2507 * @bars: Bitmask of BARs to be requested
2508 * @res_name: Name to be associated with resource
2509 */
2510int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2511 const char *res_name)
2512{
2513 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2514}
2515
2516int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2517 int bars, const char *res_name)
2518{
2519 return __pci_request_selected_regions(pdev, bars, res_name,
2520 IORESOURCE_EXCLUSIVE);
2521}
2522
1da177e4
LT		 2523/**
2524 * pci_release_regions - Release reserved PCI I/O and memory resources
2525 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2526 *
2527 * Releases all PCI I/O and memory resources previously reserved by a
2528 * successful call to pci_request_regions. Call this function only
2529 * after all use of the PCI regions has ceased.
2530 */
2531
2532void pci_release_regions(struct pci_dev *pdev)
2533{
c87deff7 2534 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2535}
2536
2537/**
2538 * pci_request_regions - Reserved PCI I/O and memory resources
2539 * @pdev: PCI device whose resources are to be reserved
2540 * @res_name: Name to be associated with resource.
2541 *
2542 * Mark all PCI regions associated with PCI device @pdev as
2543 * being reserved by owner @res_name. Do not access any
2544 * address inside the PCI regions unless this call returns
2545 * successfully.
2546 *
2547 * Returns 0 on success, or %EBUSY on error. A warning
2548 * message is also printed on failure.
2549 */
3c990e92 2550int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2551{
c87deff7 2552 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2553}
2554
e8de1481
AV		 2555/**
2556 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2557 * @pdev: PCI device whose resources are to be reserved
2558 * @res_name: Name to be associated with resource.
2559 *
2560 * Mark all PCI regions associated with PCI device @pdev as
2561 * being reserved by owner @res_name. Do not access any
2562 * address inside the PCI regions unless this call returns
2563 * successfully.
2564 *
2565 * pci_request_regions_exclusive() will mark the region so that
2566 * /dev/mem and the sysfs MMIO access will not be allowed.
2567 *
2568 * Returns 0 on success, or %EBUSY on error. A warning
2569 * message is also printed on failure.
2570 */
2571int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2572{
2573 return pci_request_selected_regions_exclusive(pdev,
2574 ((1 << 6) - 1), res_name);
2575}
2576
6a479079
BH		 2577static void __pci_set_master(struct pci_dev *dev, bool enable)
2578{
2579 u16 old_cmd, cmd;
2580
2581 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2582 if (enable)
2583 cmd = old_cmd | PCI_COMMAND_MASTER;
2584 else
2585 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2586 if (cmd != old_cmd) {
2587 dev_dbg(&dev->dev, "%s bus mastering\n",
2588 enable ? "enabling" : "disabling");
2589 pci_write_config_word(dev, PCI_COMMAND, cmd);
2590 }
2591 dev->is_busmaster = enable;
2592}
e8de1481 2593
1da177e4
LT		 2594/**
2595 * pci_set_master - enables bus-mastering for device dev
2596 * @dev: the PCI device to enable
2597 *
2598 * Enables bus-mastering on the device and calls pcibios_set_master()
2599 * to do the needed arch specific settings.
2600 */
6a479079 2601void pci_set_master(struct pci_dev *dev)
1da177e4 2602{
6a479079 2603 __pci_set_master(dev, true);
1da177e4
LT		 2604 pcibios_set_master(dev);
2605}
2606
6a479079
BH		 2607/**
2608 * pci_clear_master - disables bus-mastering for device dev
2609 * @dev: the PCI device to disable
2610 */
2611void pci_clear_master(struct pci_dev *dev)
2612{
2613 __pci_set_master(dev, false);
2614}
2615
1da177e4 2616/**
edb2d97e
MW		 2617 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2618 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2619 *
edb2d97e
MW		 2620 * Helper function for pci_set_mwi.
2621 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2622 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2623 *
2624 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2625 */
15ea76d4 2626int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2627{
2628 u8 cacheline_size;
2629
2630 if (!pci_cache_line_size)
15ea76d4 2631 return -EINVAL;
1da177e4
LT		 2632
2633 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2634 equal to or multiple of the right value. */
2635 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2636 if (cacheline_size >= pci_cache_line_size &&
2637 (cacheline_size % pci_cache_line_size) == 0)
2638 return 0;
2639
2640 /* Write the correct value. */
2641 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2642 /* Read it back. */
2643 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2644 if (cacheline_size == pci_cache_line_size)
2645 return 0;
2646
80ccba11
BH		 2647 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2648 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2649
2650 return -EINVAL;
2651}
15ea76d4
TH		 2652EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2653
2654#ifdef PCI_DISABLE_MWI
2655int pci_set_mwi(struct pci_dev *dev)
2656{
2657 return 0;
2658}
2659
2660int pci_try_set_mwi(struct pci_dev *dev)
2661{
2662 return 0;
2663}
2664
2665void pci_clear_mwi(struct pci_dev *dev)
2666{
2667}
2668
2669#else
1da177e4
LT		 2670
2671/**
2672 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2673 * @dev: the PCI device for which MWI is enabled
2674 *
694625c0 2675 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2676 *
2677 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2678 */
2679int
2680pci_set_mwi(struct pci_dev *dev)
2681{
2682 int rc;
2683 u16 cmd;
2684
edb2d97e 2685 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2686 if (rc)
2687 return rc;
2688
2689 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2690 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2691 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2692 cmd |= PCI_COMMAND_INVALIDATE;
2693 pci_write_config_word(dev, PCI_COMMAND, cmd);
2694 }
2695
2696 return 0;
2697}
2698
694625c0
RD		 2699/**
2700 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2701 * @dev: the PCI device for which MWI is enabled
2702 *
2703 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2704 * Callers are not required to check the return value.
2705 *
2706 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2707 */
2708int pci_try_set_mwi(struct pci_dev *dev)
2709{
2710 int rc = pci_set_mwi(dev);
2711 return rc;
2712}
2713
1da177e4
LT		 2714/**
2715 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2716 * @dev: the PCI device to disable
2717 *
2718 * Disables PCI Memory-Write-Invalidate transaction on the device
2719 */
2720void
2721pci_clear_mwi(struct pci_dev *dev)
2722{
2723 u16 cmd;
2724
2725 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2726 if (cmd & PCI_COMMAND_INVALIDATE) {
2727 cmd &= ~PCI_COMMAND_INVALIDATE;
2728 pci_write_config_word(dev, PCI_COMMAND, cmd);
2729 }
2730}
edb2d97e 2731#endif /* ! PCI_DISABLE_MWI */
1da177e4 2732
a04ce0ff
BR		 2733/**
2734 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2735 * @pdev: the PCI device to operate on
2736 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2737 *
2738 * Enables/disables PCI INTx for device dev
2739 */
2740void
2741pci_intx(struct pci_dev *pdev, int enable)
2742{
2743 u16 pci_command, new;
2744
2745 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2746
2747 if (enable) {
2748 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2749 } else {
2750 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2751 }
2752
2753 if (new != pci_command) {
9ac7849e
TH		 2754 struct pci_devres *dr;
2755
2fd9d74b 2756 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2757
2758 dr = find_pci_dr(pdev);
2759 if (dr && !dr->restore_intx) {
2760 dr->restore_intx = 1;
2761 dr->orig_intx = !enable;
2762 }
a04ce0ff
BR		 2763 }
2764}
2765
f5f2b131
EB		 2766/**
2767 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 2768 * @dev: the PCI device to operate on
f5f2b131
EB		 2769 *
2770 * If you want to use msi see pci_enable_msi and friends.
2771 * This is a lower level primitive that allows us to disable
2772 * msi operation at the device level.
2773 */
2774void pci_msi_off(struct pci_dev *dev)
2775{
2776 int pos;
2777 u16 control;
2778
2779 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2780 if (pos) {
2781 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2782 control &= ~PCI_MSI_FLAGS_ENABLE;
2783 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2784 }
2785 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2786 if (pos) {
2787 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2788 control &= ~PCI_MSIX_FLAGS_ENABLE;
2789 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2790 }
2791}
b03214d5 2792EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 2793
4d57cdfa
FT		 2794int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2795{
2796 return dma_set_max_seg_size(&dev->dev, size);
2797}
2798EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 2799
59fc67de
FT		 2800int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2801{
2802 return dma_set_seg_boundary(&dev->dev, mask);
2803}
2804EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 2805
8c1c699f 2806static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 2807{
8c1c699f
YZ		 2808 int i;
2809 int pos;
8dd7f803 2810 u32 cap;
04b55c47 2811 u16 status, control;
8dd7f803 2812
06a1cbaf 2813 pos = pci_pcie_cap(dev);
8c1c699f 2814 if (!pos)
8dd7f803 2815 return -ENOTTY;
8c1c699f
YZ		 2816
2817 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 2818 if (!(cap & PCI_EXP_DEVCAP_FLR))
2819 return -ENOTTY;
2820
d91cdc74
SY		 2821 if (probe)
2822 return 0;
2823
8dd7f803 2824 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2825 for (i = 0; i < 4; i++) {
2826 if (i)
2827 msleep((1 << (i - 1)) * 100);
5fe5db05 2828
8c1c699f
YZ		 2829 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2830 if (!(status & PCI_EXP_DEVSTA_TRPND))
2831 goto clear;
2832 }
2833
2834 dev_err(&dev->dev, "transaction is not cleared; "
2835 "proceeding with reset anyway\n");
2836
2837clear:
04b55c47
SR		 2838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2839 control |= PCI_EXP_DEVCTL_BCR_FLR;
2840 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2841
8c1c699f 2842 msleep(100);
8dd7f803 2843
8dd7f803
SY		 2844 return 0;
2845}
d91cdc74 2846
8c1c699f 2847static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 2848{
8c1c699f
YZ		 2849 int i;
2850 int pos;
1ca88797 2851 u8 cap;
8c1c699f 2852 u8 status;
1ca88797 2853
8c1c699f
YZ		 2854 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2855 if (!pos)
1ca88797 2856 return -ENOTTY;
8c1c699f
YZ		 2857
2858 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 2859 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2860 return -ENOTTY;
2861
2862 if (probe)
2863 return 0;
2864
1ca88797 2865 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2866 for (i = 0; i < 4; i++) {
2867 if (i)
2868 msleep((1 << (i - 1)) * 100);
2869
2870 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2871 if (!(status & PCI_AF_STATUS_TP))
2872 goto clear;
2873 }
5fe5db05 2874
8c1c699f
YZ		 2875 dev_err(&dev->dev, "transaction is not cleared; "
2876 "proceeding with reset anyway\n");
5fe5db05 2877
8c1c699f
YZ		 2878clear:
2879 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 2880 msleep(100);
8c1c699f 2881
1ca88797
SY		 2882 return 0;
2883}
2884
83d74e03
RW		 2885/**
2886 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2887 * @dev: Device to reset.
2888 * @probe: If set, only check if the device can be reset this way.
2889 *
2890 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2891 * unset, it will be reinitialized internally when going from PCI_D3hot to
2892 * PCI_D0. If that's the case and the device is not in a low-power state
2893 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2894 *
2895 * NOTE: This causes the caller to sleep for twice the device power transition
2896 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2897 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2898 * Moreover, only devices in D0 can be reset by this function.
2899 */
f85876ba 2900static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 2901{
f85876ba
YZ		 2902 u16 csr;
2903
2904 if (!dev->pm_cap)
2905 return -ENOTTY;
d91cdc74 2906
f85876ba
YZ		 2907 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2908 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2909 return -ENOTTY;
d91cdc74 2910
f85876ba
YZ		 2911 if (probe)
2912 return 0;
1ca88797 2913
f85876ba
YZ		 2914 if (dev->current_state != PCI_D0)
2915 return -EINVAL;
2916
2917 csr &= ~PCI_PM_CTRL_STATE_MASK;
2918 csr |= PCI_D3hot;
2919 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2920 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2921
2922 csr &= ~PCI_PM_CTRL_STATE_MASK;
2923 csr |= PCI_D0;
2924 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2925 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2926
2927 return 0;
2928}
2929
c12ff1df
YZ		 2930static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2931{
2932 u16 ctrl;
2933 struct pci_dev *pdev;
2934
654b75e0 2935 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 2936 return -ENOTTY;
2937
2938 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2939 if (pdev != dev)
2940 return -ENOTTY;
2941
2942 if (probe)
2943 return 0;
2944
2945 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2946 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2947 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2948 msleep(100);
2949
2950 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2951 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2952 msleep(100);
2953
2954 return 0;
2955}
2956
8c1c699f 2957static int pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 2958{
8c1c699f
YZ		 2959 int rc;
2960
2961 might_sleep();
2962
2963 if (!probe) {
2964 pci_block_user_cfg_access(dev);
2965 /* block PM suspend, driver probe, etc. */
8e9394ce 2966 device_lock(&dev->dev);
8c1c699f 2967 }
d91cdc74 2968
b9c3b266
DC		 2969 rc = pci_dev_specific_reset(dev, probe);
2970 if (rc != -ENOTTY)
2971 goto done;
2972
8c1c699f
YZ		 2973 rc = pcie_flr(dev, probe);
2974 if (rc != -ENOTTY)
2975 goto done;
d91cdc74 2976
8c1c699f 2977 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 2978 if (rc != -ENOTTY)
2979 goto done;
2980
2981 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 2982 if (rc != -ENOTTY)
2983 goto done;
2984
2985 rc = pci_parent_bus_reset(dev, probe);
8c1c699f
YZ		 2986done:
2987 if (!probe) {
8e9394ce 2988 device_unlock(&dev->dev);
8c1c699f
YZ		 2989 pci_unblock_user_cfg_access(dev);
2990 }
1ca88797 2991
8c1c699f 2992 return rc;
d91cdc74
SY		 2993}
2994
2995/**
8c1c699f
YZ		 2996 * __pci_reset_function - reset a PCI device function
2997 * @dev: PCI device to reset
d91cdc74
SY		 2998 *
2999 * Some devices allow an individual function to be reset without affecting
3000 * other functions in the same device. The PCI device must be responsive
3001 * to PCI config space in order to use this function.
3002 *
3003 * The device function is presumed to be unused when this function is called.
3004 * Resetting the device will make the contents of PCI configuration space
3005 * random, so any caller of this must be prepared to reinitialise the
3006 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3007 * etc.
3008 *
8c1c699f 3009 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 3010 * device doesn't support resetting a single function.
3011 */
8c1c699f 3012int __pci_reset_function(struct pci_dev *dev)
d91cdc74 3013{
8c1c699f 3014 return pci_dev_reset(dev, 0);
d91cdc74 3015}
8c1c699f 3016EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 3017
711d5779
MT		 3018/**
3019 * pci_probe_reset_function - check whether the device can be safely reset
3020 * @dev: PCI device to reset
3021 *
3022 * Some devices allow an individual function to be reset without affecting
3023 * other functions in the same device. The PCI device must be responsive
3024 * to PCI config space in order to use this function.
3025 *
3026 * Returns 0 if the device function can be reset or negative if the
3027 * device doesn't support resetting a single function.
3028 */
3029int pci_probe_reset_function(struct pci_dev *dev)
3030{
3031 return pci_dev_reset(dev, 1);
3032}
3033
8dd7f803 3034/**
8c1c699f
YZ		 3035 * pci_reset_function - quiesce and reset a PCI device function
3036 * @dev: PCI device to reset
8dd7f803
SY		 3037 *
3038 * Some devices allow an individual function to be reset without affecting
3039 * other functions in the same device. The PCI device must be responsive
3040 * to PCI config space in order to use this function.
3041 *
3042 * This function does not just reset the PCI portion of a device, but
3043 * clears all the state associated with the device. This function differs
8c1c699f 3044 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 3045 * over the reset.
3046 *
8c1c699f 3047 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 3048 * device doesn't support resetting a single function.
3049 */
3050int pci_reset_function(struct pci_dev *dev)
3051{
8c1c699f 3052 int rc;
8dd7f803 3053
8c1c699f
YZ		 3054 rc = pci_dev_reset(dev, 1);
3055 if (rc)
3056 return rc;
8dd7f803 3057
8dd7f803
SY		 3058 pci_save_state(dev);
3059
8c1c699f
YZ		 3060 /*
3061 * both INTx and MSI are disabled after the Interrupt Disable bit
3062 * is set and the Bus Master bit is cleared.
3063 */
8dd7f803
SY		 3064 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3065
8c1c699f 3066 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 3067
3068 pci_restore_state(dev);
8dd7f803 3069
8c1c699f 3070 return rc;
8dd7f803
SY		 3071}
3072EXPORT_SYMBOL_GPL(pci_reset_function);
3073
d556ad4b
PO		 3074/**
3075 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3076 * @dev: PCI device to query
3077 *
3078 * Returns mmrbc: maximum designed memory read count in bytes
3079 * or appropriate error value.
3080 */
3081int pcix_get_max_mmrbc(struct pci_dev *dev)
3082{
7c9e2b1c 3083 int cap;
d556ad4b
PO		 3084 u32 stat;
3085
3086 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3087 if (!cap)
3088 return -EINVAL;
3089
7c9e2b1c 3090 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 3091 return -EINVAL;
3092
25daeb55 3093 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 3094}
3095EXPORT_SYMBOL(pcix_get_max_mmrbc);
3096
3097/**
3098 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3099 * @dev: PCI device to query
3100 *
3101 * Returns mmrbc: maximum memory read count in bytes
3102 * or appropriate error value.
3103 */
3104int pcix_get_mmrbc(struct pci_dev *dev)
3105{
7c9e2b1c 3106 int cap;
bdc2bda7 3107 u16 cmd;
d556ad4b
PO		 3108
3109 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3110 if (!cap)
3111 return -EINVAL;
3112
7c9e2b1c
DN		 3113 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3114 return -EINVAL;
d556ad4b 3115
7c9e2b1c 3116 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3117}
3118EXPORT_SYMBOL(pcix_get_mmrbc);
3119
3120/**
3121 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3122 * @dev: PCI device to query
3123 * @mmrbc: maximum memory read count in bytes
3124 * valid values are 512, 1024, 2048, 4096
3125 *
3126 * If possible sets maximum memory read byte count, some bridges have erratas
3127 * that prevent this.
3128 */
3129int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3130{
7c9e2b1c 3131 int cap;
bdc2bda7
DN		 3132 u32 stat, v, o;
3133 u16 cmd;
d556ad4b 3134
229f5afd 3135 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3136 return -EINVAL;
d556ad4b
PO		 3137
3138 v = ffs(mmrbc) - 10;
3139
3140 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3141 if (!cap)
7c9e2b1c 3142 return -EINVAL;
d556ad4b 3143
7c9e2b1c
DN		 3144 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3145 return -EINVAL;
d556ad4b
PO		 3146
3147 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3148 return -E2BIG;
3149
7c9e2b1c
DN		 3150 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3151 return -EINVAL;
d556ad4b
PO		 3152
3153 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3154 if (o != v) {
3155 if (v > o && dev->bus &&
3156 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3157 return -EIO;
3158
3159 cmd &= ~PCI_X_CMD_MAX_READ;
3160 cmd |= v << 2;
7c9e2b1c
DN		 3161 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3162 return -EIO;
d556ad4b 3163 }
7c9e2b1c 3164 return 0;
d556ad4b
PO		 3165}
3166EXPORT_SYMBOL(pcix_set_mmrbc);
3167
3168/**
3169 * pcie_get_readrq - get PCI Express read request size
3170 * @dev: PCI device to query
3171 *
3172 * Returns maximum memory read request in bytes
3173 * or appropriate error value.
3174 */
3175int pcie_get_readrq(struct pci_dev *dev)
3176{
3177 int ret, cap;
3178 u16 ctl;
3179
06a1cbaf 3180 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3181 if (!cap)
3182 return -EINVAL;
3183
3184 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3185 if (!ret)
93e75fab 3186 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3187
3188 return ret;
3189}
3190EXPORT_SYMBOL(pcie_get_readrq);
3191
3192/**
3193 * pcie_set_readrq - set PCI Express maximum memory read request
3194 * @dev: PCI device to query
42e61f4a 3195 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3196 * valid values are 128, 256, 512, 1024, 2048, 4096
3197 *
c9b378c7 3198 * If possible sets maximum memory read request in bytes
d556ad4b
PO		 3199 */
3200int pcie_set_readrq(struct pci_dev *dev, int rq)
3201{
3202 int cap, err = -EINVAL;
3203 u16 ctl, v;
3204
229f5afd 3205 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
d556ad4b
PO		 3206 goto out;
3207
06a1cbaf 3208 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3209 if (!cap)
3210 goto out;
3211
3212 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3213 if (err)
3214 goto out;
a1c473aa
BH		 3215 /*
3216 * If using the "performance" PCIe config, we clamp the
3217 * read rq size to the max packet size to prevent the
3218 * host bridge generating requests larger than we can
3219 * cope with
3220 */
3221 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3222 int mps = pcie_get_mps(dev);
3223
3224 if (mps < 0)
3225 return mps;
3226 if (mps < rq)
3227 rq = mps;
3228 }
3229
3230 v = (ffs(rq) - 8) << 12;
d556ad4b
PO		 3231
3232 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3233 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3234 ctl |= v;
c9b378c7 3235 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
d556ad4b
PO		 3236 }
3237
3238out:
3239 return err;
3240}
3241EXPORT_SYMBOL(pcie_set_readrq);
3242
b03e7495
JM		 3243/**
3244 * pcie_get_mps - get PCI Express maximum payload size
3245 * @dev: PCI device to query
3246 *
3247 * Returns maximum payload size in bytes
3248 * or appropriate error value.
3249 */
3250int pcie_get_mps(struct pci_dev *dev)
3251{
3252 int ret, cap;
3253 u16 ctl;
3254
3255 cap = pci_pcie_cap(dev);
3256 if (!cap)
3257 return -EINVAL;
3258
3259 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3260 if (!ret)
3261 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3262
3263 return ret;
3264}
3265
3266/**
3267 * pcie_set_mps - set PCI Express maximum payload size
3268 * @dev: PCI device to query
47c08f31 3269 * @mps: maximum payload size in bytes
b03e7495
JM		 3270 * valid values are 128, 256, 512, 1024, 2048, 4096
3271 *
3272 * If possible sets maximum payload size
3273 */
3274int pcie_set_mps(struct pci_dev *dev, int mps)
3275{
3276 int cap, err = -EINVAL;
3277 u16 ctl, v;
3278
3279 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3280 goto out;
3281
3282 v = ffs(mps) - 8;
3283 if (v > dev->pcie_mpss)
3284 goto out;
3285 v <<= 5;
3286
3287 cap = pci_pcie_cap(dev);
3288 if (!cap)
3289 goto out;
3290
3291 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3292 if (err)
3293 goto out;
3294
3295 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3296 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3297 ctl |= v;
3298 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3299 }
3300out:
3301 return err;
3302}
3303
c87deff7
HS		 3304/**
3305 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 3306 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 3307 * @flags: resource type mask to be selected
3308 *
3309 * This helper routine makes bar mask from the type of resource.
3310 */
3311int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3312{
3313 int i, bars = 0;
3314 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3315 if (pci_resource_flags(dev, i) & flags)
3316 bars |= (1 << i);
3317 return bars;
3318}
3319
613e7ed6
YZ		 3320/**
3321 * pci_resource_bar - get position of the BAR associated with a resource
3322 * @dev: the PCI device
3323 * @resno: the resource number
3324 * @type: the BAR type to be filled in
3325 *
3326 * Returns BAR position in config space, or 0 if the BAR is invalid.
3327 */
3328int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3329{
d1b054da
YZ		 3330 int reg;
3331
613e7ed6
YZ		 3332 if (resno < PCI_ROM_RESOURCE) {
3333 *type = pci_bar_unknown;
3334 return PCI_BASE_ADDRESS_0 + 4 * resno;
3335 } else if (resno == PCI_ROM_RESOURCE) {
3336 *type = pci_bar_mem32;
3337 return dev->rom_base_reg;
d1b054da
YZ		 3338 } else if (resno < PCI_BRIDGE_RESOURCES) {
3339 /* device specific resource */
3340 reg = pci_iov_resource_bar(dev, resno, type);
3341 if (reg)
3342 return reg;
613e7ed6
YZ		 3343 }
3344
865df576 3345 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 3346 return 0;
3347}
3348
95a8b6ef
MT		 3349/* Some architectures require additional programming to enable VGA */
3350static arch_set_vga_state_t arch_set_vga_state;
3351
3352void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3353{
3354 arch_set_vga_state = func; /* NULL disables */
3355}
3356
3357static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
7ad35cf2 3358 unsigned int command_bits, u32 flags)
95a8b6ef
MT		 3359{
3360 if (arch_set_vga_state)
3361 return arch_set_vga_state(dev, decode, command_bits,
7ad35cf2 3362 flags);
95a8b6ef
MT		 3363 return 0;
3364}
3365
deb2d2ec
BH		 3366/**
3367 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 3368 * @dev: the PCI device
3369 * @decode: true = enable decoding, false = disable decoding
3370 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3f37d622 3371 * @flags: traverse ancestors and change bridges
3448a19d 3372 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
deb2d2ec
BH		 3373 */
3374int pci_set_vga_state(struct pci_dev *dev, bool decode,
3448a19d 3375 unsigned int command_bits, u32 flags)
deb2d2ec
BH		 3376{
3377 struct pci_bus *bus;
3378 struct pci_dev *bridge;
3379 u16 cmd;
95a8b6ef 3380 int rc;
deb2d2ec 3381
3448a19d 3382 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
deb2d2ec 3383
95a8b6ef 3384 /* ARCH specific VGA enables */
3448a19d 3385 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
95a8b6ef
MT		 3386 if (rc)
3387 return rc;
3388
3448a19d
DA		 3389 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3390 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3391 if (decode == true)
3392 cmd |= command_bits;
3393 else
3394 cmd &= ~command_bits;
3395 pci_write_config_word(dev, PCI_COMMAND, cmd);
3396 }
deb2d2ec 3397
3448a19d 3398 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
deb2d2ec
BH		 3399 return 0;
3400
3401 bus = dev->bus;
3402 while (bus) {
3403 bridge = bus->self;
3404 if (bridge) {
3405 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3406 &cmd);
3407 if (decode == true)
3408 cmd |= PCI_BRIDGE_CTL_VGA;
3409 else
3410 cmd &= ~PCI_BRIDGE_CTL_VGA;
3411 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3412 cmd);
3413 }
3414 bus = bus->parent;
3415 }
3416 return 0;
3417}
3418
32a9a682
YS		 3419#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3420static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 3421static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 3422
3423/**
3424 * pci_specified_resource_alignment - get resource alignment specified by user.
3425 * @dev: the PCI device to get
3426 *
3427 * RETURNS: Resource alignment if it is specified.
3428 * Zero if it is not specified.
3429 */
3430resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3431{
3432 int seg, bus, slot, func, align_order, count;
3433 resource_size_t align = 0;
3434 char *p;
3435
3436 spin_lock(&resource_alignment_lock);
3437 p = resource_alignment_param;
3438 while (*p) {
3439 count = 0;
3440 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3441 p[count] == '@') {
3442 p += count + 1;
3443 } else {
3444 align_order = -1;
3445 }
3446 if (sscanf(p, "%x:%x:%x.%x%n",
3447 &seg, &bus, &slot, &func, &count) != 4) {
3448 seg = 0;
3449 if (sscanf(p, "%x:%x.%x%n",
3450 &bus, &slot, &func, &count) != 3) {
3451 /* Invalid format */
3452 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3453 p);
3454 break;
3455 }
3456 }
3457 p += count;
3458 if (seg == pci_domain_nr(dev->bus) &&
3459 bus == dev->bus->number &&
3460 slot == PCI_SLOT(dev->devfn) &&
3461 func == PCI_FUNC(dev->devfn)) {
3462 if (align_order == -1) {
3463 align = PAGE_SIZE;
3464 } else {
3465 align = 1 << align_order;
3466 }
3467 /* Found */
3468 break;
3469 }
3470 if (*p != ';' && *p != ',') {
3471 /* End of param or invalid format */
3472 break;
3473 }
3474 p++;
3475 }
3476 spin_unlock(&resource_alignment_lock);
3477 return align;
3478}
3479
3480/**
3481 * pci_is_reassigndev - check if specified PCI is target device to reassign
3482 * @dev: the PCI device to check
3483 *
3484 * RETURNS: non-zero for PCI device is a target device to reassign,
3485 * or zero is not.
3486 */
3487int pci_is_reassigndev(struct pci_dev *dev)
3488{
3489 return (pci_specified_resource_alignment(dev) != 0);
3490}
3491
3492ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3493{
3494 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3495 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3496 spin_lock(&resource_alignment_lock);
3497 strncpy(resource_alignment_param, buf, count);
3498 resource_alignment_param[count] = '\0';
3499 spin_unlock(&resource_alignment_lock);
3500 return count;
3501}
3502
3503ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3504{
3505 size_t count;
3506 spin_lock(&resource_alignment_lock);
3507 count = snprintf(buf, size, "%s", resource_alignment_param);
3508 spin_unlock(&resource_alignment_lock);
3509 return count;
3510}
3511
3512static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3513{
3514 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3515}
3516
3517static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3518 const char *buf, size_t count)
3519{
3520 return pci_set_resource_alignment_param(buf, count);
3521}
3522
3523BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3524 pci_resource_alignment_store);
3525
3526static int __init pci_resource_alignment_sysfs_init(void)
3527{
3528 return bus_create_file(&pci_bus_type,
3529 &bus_attr_resource_alignment);
3530}
3531
3532late_initcall(pci_resource_alignment_sysfs_init);
3533
32a2eea7
JG		 3534static void __devinit pci_no_domains(void)
3535{
3536#ifdef CONFIG_PCI_DOMAINS
3537 pci_domains_supported = 0;
3538#endif
3539}
3540
0ef5f8f6
AP		 3541/**
3542 * pci_ext_cfg_enabled - can we access extended PCI config space?
3543 * @dev: The PCI device of the root bridge.
3544 *
3545 * Returns 1 if we can access PCI extended config space (offsets
3546 * greater than 0xff). This is the default implementation. Architecture
3547 * implementations can override this.
3548 */
3549int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3550{
3551 return 1;
3552}
3553
2d1c8618
BH		 3554void __weak pci_fixup_cardbus(struct pci_bus *bus)
3555{
3556}
3557EXPORT_SYMBOL(pci_fixup_cardbus);
3558
ad04d31e 3559static int __init pci_setup(char *str)
1da177e4
LT		 3560{
3561 while (str) {
3562 char *k = strchr(str, ',');
3563 if (k)
3564 *k++ = 0;
3565 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3566 if (!strcmp(str, "nomsi")) {
3567 pci_no_msi();
7f785763
RD		 3568 } else if (!strcmp(str, "noaer")) {
3569 pci_no_aer();
f483d392
RP		 3570 } else if (!strncmp(str, "realloc", 7)) {
3571 pci_realloc();
32a2eea7
JG		 3572 } else if (!strcmp(str, "nodomains")) {
3573 pci_no_domains();
4516a618
AN		 3574 } else if (!strncmp(str, "cbiosize=", 9)) {
3575 pci_cardbus_io_size = memparse(str + 9, &str);
3576 } else if (!strncmp(str, "cbmemsize=", 10)) {
3577 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3578 } else if (!strncmp(str, "resource_alignment=", 19)) {
3579 pci_set_resource_alignment_param(str + 19,
3580 strlen(str + 19));
43c16408
AP		 3581 } else if (!strncmp(str, "ecrc=", 5)) {
3582 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3583 } else if (!strncmp(str, "hpiosize=", 9)) {
3584 pci_hotplug_io_size = memparse(str + 9, &str);
3585 } else if (!strncmp(str, "hpmemsize=", 10)) {
3586 pci_hotplug_mem_size = memparse(str + 10, &str);
5f39e670
JM		 3587 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3588 pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495
JM		 3589 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3590 pcie_bus_config = PCIE_BUS_SAFE;
3591 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3592 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5f39e670
JM		 3593 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3594 pcie_bus_config = PCIE_BUS_PEER2PEER;
309e57df
MW		 3595 } else {
3596 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3597 str);
3598 }
1da177e4
LT		 3599 }
3600 str = k;
3601 }
0637a70a 3602 return 0;
1da177e4 3603}
0637a70a 3604early_param("pci", pci_setup);
1da177e4 3605
0b62e13b 3606EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3607EXPORT_SYMBOL(pci_enable_device_io);
3608EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3609EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3610EXPORT_SYMBOL(pcim_enable_device);
3611EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3612EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3613EXPORT_SYMBOL(pci_find_capability);
3614EXPORT_SYMBOL(pci_bus_find_capability);
3615EXPORT_SYMBOL(pci_release_regions);
3616EXPORT_SYMBOL(pci_request_regions);
e8de1481 3617EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3618EXPORT_SYMBOL(pci_release_region);
3619EXPORT_SYMBOL(pci_request_region);
e8de1481 3620EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3621EXPORT_SYMBOL(pci_release_selected_regions);
3622EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3623EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3624EXPORT_SYMBOL(pci_set_master);
6a479079 3625EXPORT_SYMBOL(pci_clear_master);
1da177e4 3626EXPORT_SYMBOL(pci_set_mwi);
694625c0 3627EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3628EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3629EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 3630EXPORT_SYMBOL(pci_assign_resource);
3631EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3632EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3633
3634EXPORT_SYMBOL(pci_set_power_state);
3635EXPORT_SYMBOL(pci_save_state);
3636EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3637EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3638EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3639EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3640EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3641EXPORT_SYMBOL(pci_prepare_to_sleep);
3642EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3643EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linux kernel - Deliverables
This page took 1.28034 seconds and 5 git commands to generate.