Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
229f5afd | 19 | #include <linux/log2.h> |
7d715a6c | 20 | #include <linux/pci-aspm.h> |
c300bd2f | 21 | #include <linux/pm_wakeup.h> |
8dd7f803 | 22 | #include <linux/interrupt.h> |
32a9a682 | 23 | #include <linux/device.h> |
b67ea761 | 24 | #include <linux/pm_runtime.h> |
608c3881 | 25 | #include <linux/pci_hotplug.h> |
284f5f9d | 26 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 27 | #include <asm/setup.h> |
bc56b9e0 | 28 | #include "pci.h" |
1da177e4 | 29 | |
00240c38 AS |
30 | const char *pci_power_names[] = { |
31 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
32 | }; | |
33 | EXPORT_SYMBOL_GPL(pci_power_names); | |
34 | ||
93177a74 RW |
35 | int isa_dma_bridge_buggy; |
36 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
37 | ||
38 | int pci_pci_problems; | |
39 | EXPORT_SYMBOL(pci_pci_problems); | |
40 | ||
1ae861e6 RW |
41 | unsigned int pci_pm_d3_delay; |
42 | ||
df17e62e MG |
43 | static void pci_pme_list_scan(struct work_struct *work); |
44 | ||
45 | static LIST_HEAD(pci_pme_list); | |
46 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
47 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
48 | ||
49 | struct pci_pme_device { | |
50 | struct list_head list; | |
51 | struct pci_dev *dev; | |
52 | }; | |
53 | ||
54 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
55 | ||
1ae861e6 RW |
56 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
57 | { | |
58 | unsigned int delay = dev->d3_delay; | |
59 | ||
60 | if (delay < pci_pm_d3_delay) | |
61 | delay = pci_pm_d3_delay; | |
62 | ||
63 | msleep(delay); | |
64 | } | |
1da177e4 | 65 | |
32a2eea7 JG |
66 | #ifdef CONFIG_PCI_DOMAINS |
67 | int pci_domains_supported = 1; | |
68 | #endif | |
69 | ||
4516a618 AN |
70 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
71 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
72 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
73 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
74 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
75 | ||
28760489 EB |
76 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
77 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
78 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
79 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
80 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
81 | ||
5f39e670 | 82 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 83 | |
ac1aa47b JB |
84 | /* |
85 | * The default CLS is used if arch didn't set CLS explicitly and not | |
86 | * all pci devices agree on the same value. Arch can override either | |
87 | * the dfl or actual value as it sees fit. Don't forget this is | |
88 | * measured in 32-bit words, not bytes. | |
89 | */ | |
15856ad5 | 90 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
91 | u8 pci_cache_line_size; |
92 | ||
96c55900 MS |
93 | /* |
94 | * If we set up a device for bus mastering, we need to check the latency | |
95 | * timer as certain BIOSes forget to set it properly. | |
96 | */ | |
97 | unsigned int pcibios_max_latency = 255; | |
98 | ||
6748dcc2 RW |
99 | /* If set, the PCIe ARI capability will not be used. */ |
100 | static bool pcie_ari_disabled; | |
101 | ||
1da177e4 LT |
102 | /** |
103 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
104 | * @bus: pointer to PCI bus structure to search | |
105 | * | |
106 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
107 | * including the given PCI bus and its list of child PCI buses. | |
108 | */ | |
96bde06a | 109 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
110 | { |
111 | struct list_head *tmp; | |
112 | unsigned char max, n; | |
113 | ||
b918c62e | 114 | max = bus->busn_res.end; |
1da177e4 LT |
115 | list_for_each(tmp, &bus->children) { |
116 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
117 | if(n > max) | |
118 | max = n; | |
119 | } | |
120 | return max; | |
121 | } | |
b82db5ce | 122 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 123 | |
1684f5dd AM |
124 | #ifdef CONFIG_HAS_IOMEM |
125 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
126 | { | |
127 | /* | |
128 | * Make sure the BAR is actually a memory resource, not an IO resource | |
129 | */ | |
130 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
131 | WARN_ON(1); | |
132 | return NULL; | |
133 | } | |
134 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
135 | pci_resource_len(pdev, bar)); | |
136 | } | |
137 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
138 | #endif | |
139 | ||
687d5fe3 ME |
140 | #define PCI_FIND_CAP_TTL 48 |
141 | ||
142 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
143 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
144 | { |
145 | u8 id; | |
24a4e377 | 146 | |
687d5fe3 | 147 | while ((*ttl)--) { |
24a4e377 RD |
148 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
149 | if (pos < 0x40) | |
150 | break; | |
151 | pos &= ~3; | |
152 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
153 | &id); | |
154 | if (id == 0xff) | |
155 | break; | |
156 | if (id == cap) | |
157 | return pos; | |
158 | pos += PCI_CAP_LIST_NEXT; | |
159 | } | |
160 | return 0; | |
161 | } | |
162 | ||
687d5fe3 ME |
163 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
164 | u8 pos, int cap) | |
165 | { | |
166 | int ttl = PCI_FIND_CAP_TTL; | |
167 | ||
168 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
169 | } | |
170 | ||
24a4e377 RD |
171 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
172 | { | |
173 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
174 | pos + PCI_CAP_LIST_NEXT, cap); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
177 | ||
d3bac118 ME |
178 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
179 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
180 | { |
181 | u16 status; | |
1da177e4 LT |
182 | |
183 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
184 | if (!(status & PCI_STATUS_CAP_LIST)) | |
185 | return 0; | |
186 | ||
187 | switch (hdr_type) { | |
188 | case PCI_HEADER_TYPE_NORMAL: | |
189 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 190 | return PCI_CAPABILITY_LIST; |
1da177e4 | 191 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 192 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
193 | default: |
194 | return 0; | |
195 | } | |
d3bac118 ME |
196 | |
197 | return 0; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
201 | * pci_find_capability - query for devices' capabilities | |
202 | * @dev: PCI device to query | |
203 | * @cap: capability code | |
204 | * | |
205 | * Tell if a device supports a given PCI capability. | |
206 | * Returns the address of the requested capability structure within the | |
207 | * device's PCI configuration space or 0 in case the device does not | |
208 | * support it. Possible values for @cap: | |
209 | * | |
210 | * %PCI_CAP_ID_PM Power Management | |
211 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
212 | * %PCI_CAP_ID_VPD Vital Product Data | |
213 | * %PCI_CAP_ID_SLOTID Slot Identification | |
214 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
215 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
216 | * %PCI_CAP_ID_PCIX PCI-X | |
217 | * %PCI_CAP_ID_EXP PCI Express | |
218 | */ | |
219 | int pci_find_capability(struct pci_dev *dev, int cap) | |
220 | { | |
d3bac118 ME |
221 | int pos; |
222 | ||
223 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
224 | if (pos) | |
225 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
226 | ||
227 | return pos; | |
1da177e4 LT |
228 | } |
229 | ||
230 | /** | |
231 | * pci_bus_find_capability - query for devices' capabilities | |
232 | * @bus: the PCI bus to query | |
233 | * @devfn: PCI device to query | |
234 | * @cap: capability code | |
235 | * | |
236 | * Like pci_find_capability() but works for pci devices that do not have a | |
237 | * pci_dev structure set up yet. | |
238 | * | |
239 | * Returns the address of the requested capability structure within the | |
240 | * device's PCI configuration space or 0 in case the device does not | |
241 | * support it. | |
242 | */ | |
243 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
244 | { | |
d3bac118 | 245 | int pos; |
1da177e4 LT |
246 | u8 hdr_type; |
247 | ||
248 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
249 | ||
d3bac118 ME |
250 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
251 | if (pos) | |
252 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
253 | ||
254 | return pos; | |
1da177e4 LT |
255 | } |
256 | ||
257 | /** | |
44a9a36f | 258 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 259 | * @dev: PCI device to query |
44a9a36f | 260 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
261 | * @cap: capability code |
262 | * | |
44a9a36f | 263 | * Returns the address of the next matching extended capability structure |
1da177e4 | 264 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
265 | * not support it. Some capabilities can occur several times, e.g., the |
266 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 267 | */ |
44a9a36f | 268 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
269 | { |
270 | u32 header; | |
557848c3 ZY |
271 | int ttl; |
272 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 273 | |
557848c3 ZY |
274 | /* minimum 8 bytes per capability */ |
275 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
276 | ||
277 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
278 | return 0; |
279 | ||
44a9a36f BH |
280 | if (start) |
281 | pos = start; | |
282 | ||
1da177e4 LT |
283 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
284 | return 0; | |
285 | ||
286 | /* | |
287 | * If we have no capabilities, this is indicated by cap ID, | |
288 | * cap version and next pointer all being 0. | |
289 | */ | |
290 | if (header == 0) | |
291 | return 0; | |
292 | ||
293 | while (ttl-- > 0) { | |
44a9a36f | 294 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
295 | return pos; |
296 | ||
297 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 298 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
299 | break; |
300 | ||
301 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
302 | break; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
44a9a36f BH |
307 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
308 | ||
309 | /** | |
310 | * pci_find_ext_capability - Find an extended capability | |
311 | * @dev: PCI device to query | |
312 | * @cap: capability code | |
313 | * | |
314 | * Returns the address of the requested extended capability structure | |
315 | * within the device's PCI configuration space or 0 if the device does | |
316 | * not support it. Possible values for @cap: | |
317 | * | |
318 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
319 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
320 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
321 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
322 | */ | |
323 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
324 | { | |
325 | return pci_find_next_ext_capability(dev, 0, cap); | |
326 | } | |
3a720d72 | 327 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 328 | |
687d5fe3 ME |
329 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
330 | { | |
331 | int rc, ttl = PCI_FIND_CAP_TTL; | |
332 | u8 cap, mask; | |
333 | ||
334 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
335 | mask = HT_3BIT_CAP_MASK; | |
336 | else | |
337 | mask = HT_5BIT_CAP_MASK; | |
338 | ||
339 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
340 | PCI_CAP_ID_HT, &ttl); | |
341 | while (pos) { | |
342 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
343 | if (rc != PCIBIOS_SUCCESSFUL) | |
344 | return 0; | |
345 | ||
346 | if ((cap & mask) == ht_cap) | |
347 | return pos; | |
348 | ||
47a4d5be BG |
349 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
350 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
351 | PCI_CAP_ID_HT, &ttl); |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | /** | |
357 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
358 | * @dev: PCI device to query | |
359 | * @pos: Position from which to continue searching | |
360 | * @ht_cap: Hypertransport capability code | |
361 | * | |
362 | * To be used in conjunction with pci_find_ht_capability() to search for | |
363 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
364 | * from pci_find_ht_capability(). | |
365 | * | |
366 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
367 | * steps to avoid an infinite loop. | |
368 | */ | |
369 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
370 | { | |
371 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
372 | } | |
373 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
374 | ||
375 | /** | |
376 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
377 | * @dev: PCI device to query | |
378 | * @ht_cap: Hypertransport capability code | |
379 | * | |
380 | * Tell if a device supports a given Hypertransport capability. | |
381 | * Returns an address within the device's PCI configuration space | |
382 | * or 0 in case the device does not support the request capability. | |
383 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
384 | * which has a Hypertransport capability matching @ht_cap. | |
385 | */ | |
386 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
387 | { | |
388 | int pos; | |
389 | ||
390 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
391 | if (pos) | |
392 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
393 | ||
394 | return pos; | |
395 | } | |
396 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
397 | ||
1da177e4 LT |
398 | /** |
399 | * pci_find_parent_resource - return resource region of parent bus of given region | |
400 | * @dev: PCI device structure contains resources to be searched | |
401 | * @res: child resource record for which parent is sought | |
402 | * | |
403 | * For given resource region of given device, return the resource | |
404 | * region of parent bus the given region is contained in or where | |
405 | * it should be allocated from. | |
406 | */ | |
407 | struct resource * | |
408 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
409 | { | |
410 | const struct pci_bus *bus = dev->bus; | |
411 | int i; | |
89a74ecc | 412 | struct resource *best = NULL, *r; |
1da177e4 | 413 | |
89a74ecc | 414 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
415 | if (!r) |
416 | continue; | |
417 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
418 | continue; /* Not contained */ | |
419 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
420 | continue; /* Wrong type */ | |
421 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
422 | return r; /* Exact match */ | |
8c8def26 LT |
423 | /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ |
424 | if (r->flags & IORESOURCE_PREFETCH) | |
425 | continue; | |
426 | /* .. but we can put a prefetchable resource inside a non-prefetchable one */ | |
427 | if (!best) | |
428 | best = r; | |
1da177e4 LT |
429 | } |
430 | return best; | |
431 | } | |
432 | ||
064b53db JL |
433 | /** |
434 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
435 | * @dev: PCI device to have its BARs restored | |
436 | * | |
437 | * Restore the BAR values for a given device, so as to make it | |
438 | * accessible by its driver. | |
439 | */ | |
ad668599 | 440 | static void |
064b53db JL |
441 | pci_restore_bars(struct pci_dev *dev) |
442 | { | |
bc5f5a82 | 443 | int i; |
064b53db | 444 | |
bc5f5a82 | 445 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 446 | pci_update_resource(dev, i); |
064b53db JL |
447 | } |
448 | ||
961d9120 RW |
449 | static struct pci_platform_pm_ops *pci_platform_pm; |
450 | ||
451 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
452 | { | |
eb9d0fe4 | 453 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
d2e5f0c1 | 454 | || !ops->sleep_wake) |
961d9120 RW |
455 | return -EINVAL; |
456 | pci_platform_pm = ops; | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
461 | { | |
462 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
463 | } | |
464 | ||
465 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
466 | pci_power_t t) | |
467 | { | |
468 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
469 | } | |
470 | ||
471 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
472 | { | |
473 | return pci_platform_pm ? | |
474 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
475 | } | |
8f7020d3 | 476 | |
eb9d0fe4 RW |
477 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
478 | { | |
479 | return pci_platform_pm ? | |
480 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
481 | } | |
482 | ||
b67ea761 RW |
483 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
484 | { | |
485 | return pci_platform_pm ? | |
486 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
487 | } | |
488 | ||
1da177e4 | 489 | /** |
44e4e66e RW |
490 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
491 | * given PCI device | |
492 | * @dev: PCI device to handle. | |
44e4e66e | 493 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 494 | * |
44e4e66e RW |
495 | * RETURN VALUE: |
496 | * -EINVAL if the requested state is invalid. | |
497 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
498 | * wrong version, or device doesn't support the requested state. | |
499 | * 0 if device already is in the requested state. | |
500 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 501 | */ |
f00a20ef | 502 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 503 | { |
337001b6 | 504 | u16 pmcsr; |
44e4e66e | 505 | bool need_restore = false; |
1da177e4 | 506 | |
4a865905 RW |
507 | /* Check if we're already there */ |
508 | if (dev->current_state == state) | |
509 | return 0; | |
510 | ||
337001b6 | 511 | if (!dev->pm_cap) |
cca03dec AL |
512 | return -EIO; |
513 | ||
44e4e66e RW |
514 | if (state < PCI_D0 || state > PCI_D3hot) |
515 | return -EINVAL; | |
516 | ||
1da177e4 LT |
517 | /* Validate current state: |
518 | * Can enter D0 from any state, but if we can only go deeper | |
519 | * to sleep if we're already in a low power state | |
520 | */ | |
4a865905 | 521 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 522 | && dev->current_state > state) { |
80ccba11 BH |
523 | dev_err(&dev->dev, "invalid power transition " |
524 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 525 | return -EINVAL; |
44e4e66e | 526 | } |
1da177e4 | 527 | |
1da177e4 | 528 | /* check if this device supports the desired state */ |
337001b6 RW |
529 | if ((state == PCI_D1 && !dev->d1_support) |
530 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 531 | return -EIO; |
1da177e4 | 532 | |
337001b6 | 533 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 534 | |
32a36585 | 535 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
536 | * This doesn't affect PME_Status, disables PME_En, and |
537 | * sets PowerState to 0. | |
538 | */ | |
32a36585 | 539 | switch (dev->current_state) { |
d3535fbb JL |
540 | case PCI_D0: |
541 | case PCI_D1: | |
542 | case PCI_D2: | |
543 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
544 | pmcsr |= state; | |
545 | break; | |
f62795f1 RW |
546 | case PCI_D3hot: |
547 | case PCI_D3cold: | |
32a36585 JL |
548 | case PCI_UNKNOWN: /* Boot-up */ |
549 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 550 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 551 | need_restore = true; |
32a36585 | 552 | /* Fall-through: force to D0 */ |
32a36585 | 553 | default: |
d3535fbb | 554 | pmcsr = 0; |
32a36585 | 555 | break; |
1da177e4 LT |
556 | } |
557 | ||
558 | /* enter specified state */ | |
337001b6 | 559 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
560 | |
561 | /* Mandatory power management transition delays */ | |
562 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
563 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 564 | pci_dev_d3_sleep(dev); |
1da177e4 | 565 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 566 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 567 | |
e13cdbd7 RW |
568 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
569 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
570 | if (dev->current_state != state && printk_ratelimit()) | |
571 | dev_info(&dev->dev, "Refused to change power state, " | |
572 | "currently in D%d\n", dev->current_state); | |
064b53db | 573 | |
448bd857 HY |
574 | /* |
575 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
576 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
577 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
578 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
579 | * For example, at least some versions of the 3c905B and the | |
580 | * 3c556B exhibit this behaviour. | |
581 | * | |
582 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
583 | * devices in a D3hot state at boot. Consequently, we need to | |
584 | * restore at least the BARs so that the device will be | |
585 | * accessible to its driver. | |
586 | */ | |
587 | if (need_restore) | |
588 | pci_restore_bars(dev); | |
589 | ||
f00a20ef | 590 | if (dev->bus->self) |
7d715a6c SL |
591 | pcie_aspm_pm_state_change(dev->bus->self); |
592 | ||
1da177e4 LT |
593 | return 0; |
594 | } | |
595 | ||
44e4e66e RW |
596 | /** |
597 | * pci_update_current_state - Read PCI power state of given device from its | |
598 | * PCI PM registers and cache it | |
599 | * @dev: PCI device to handle. | |
f06fc0b6 | 600 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 601 | */ |
73410429 | 602 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 603 | { |
337001b6 | 604 | if (dev->pm_cap) { |
44e4e66e RW |
605 | u16 pmcsr; |
606 | ||
448bd857 HY |
607 | /* |
608 | * Configuration space is not accessible for device in | |
609 | * D3cold, so just keep or set D3cold for safety | |
610 | */ | |
611 | if (dev->current_state == PCI_D3cold) | |
612 | return; | |
613 | if (state == PCI_D3cold) { | |
614 | dev->current_state = PCI_D3cold; | |
615 | return; | |
616 | } | |
337001b6 | 617 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 618 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
619 | } else { |
620 | dev->current_state = state; | |
44e4e66e RW |
621 | } |
622 | } | |
623 | ||
db288c9c RW |
624 | /** |
625 | * pci_power_up - Put the given device into D0 forcibly | |
626 | * @dev: PCI device to power up | |
627 | */ | |
628 | void pci_power_up(struct pci_dev *dev) | |
629 | { | |
630 | if (platform_pci_power_manageable(dev)) | |
631 | platform_pci_set_power_state(dev, PCI_D0); | |
632 | ||
633 | pci_raw_set_power_state(dev, PCI_D0); | |
634 | pci_update_current_state(dev, PCI_D0); | |
635 | } | |
636 | ||
0e5dd46b RW |
637 | /** |
638 | * pci_platform_power_transition - Use platform to change device power state | |
639 | * @dev: PCI device to handle. | |
640 | * @state: State to put the device into. | |
641 | */ | |
642 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
643 | { | |
644 | int error; | |
645 | ||
646 | if (platform_pci_power_manageable(dev)) { | |
647 | error = platform_pci_set_power_state(dev, state); | |
648 | if (!error) | |
649 | pci_update_current_state(dev, state); | |
769ba721 | 650 | } else |
0e5dd46b | 651 | error = -ENODEV; |
769ba721 RW |
652 | |
653 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
654 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
655 | |
656 | return error; | |
657 | } | |
658 | ||
659 | /** | |
660 | * __pci_start_power_transition - Start power transition of a PCI device | |
661 | * @dev: PCI device to handle. | |
662 | * @state: State to put the device into. | |
663 | */ | |
664 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
665 | { | |
448bd857 | 666 | if (state == PCI_D0) { |
0e5dd46b | 667 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
668 | /* |
669 | * Mandatory power management transition delays, see | |
670 | * PCI Express Base Specification Revision 2.0 Section | |
671 | * 6.6.1: Conventional Reset. Do not delay for | |
672 | * devices powered on/off by corresponding bridge, | |
673 | * because have already delayed for the bridge. | |
674 | */ | |
675 | if (dev->runtime_d3cold) { | |
676 | msleep(dev->d3cold_delay); | |
677 | /* | |
678 | * When powering on a bridge from D3cold, the | |
679 | * whole hierarchy may be powered on into | |
680 | * D0uninitialized state, resume them to give | |
681 | * them a chance to suspend again | |
682 | */ | |
683 | pci_wakeup_bus(dev->subordinate); | |
684 | } | |
685 | } | |
686 | } | |
687 | ||
688 | /** | |
689 | * __pci_dev_set_current_state - Set current state of a PCI device | |
690 | * @dev: Device to handle | |
691 | * @data: pointer to state to be set | |
692 | */ | |
693 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
694 | { | |
695 | pci_power_t state = *(pci_power_t *)data; | |
696 | ||
697 | dev->current_state = state; | |
698 | return 0; | |
699 | } | |
700 | ||
701 | /** | |
702 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
703 | * @bus: Top bus of the subtree to walk. | |
704 | * @state: state to be set | |
705 | */ | |
706 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
707 | { | |
708 | if (bus) | |
709 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
710 | } |
711 | ||
712 | /** | |
713 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
714 | * @dev: PCI device to handle. | |
715 | * @state: State to put the device into. | |
716 | * | |
717 | * This function should not be called directly by device drivers. | |
718 | */ | |
719 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
720 | { | |
448bd857 HY |
721 | int ret; |
722 | ||
db288c9c | 723 | if (state <= PCI_D0) |
448bd857 HY |
724 | return -EINVAL; |
725 | ret = pci_platform_power_transition(dev, state); | |
726 | /* Power off the bridge may power off the whole hierarchy */ | |
727 | if (!ret && state == PCI_D3cold) | |
728 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
729 | return ret; | |
0e5dd46b RW |
730 | } |
731 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
732 | ||
44e4e66e RW |
733 | /** |
734 | * pci_set_power_state - Set the power state of a PCI device | |
735 | * @dev: PCI device to handle. | |
736 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
737 | * | |
877d0310 | 738 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
739 | * the device's PCI PM registers. |
740 | * | |
741 | * RETURN VALUE: | |
742 | * -EINVAL if the requested state is invalid. | |
743 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
744 | * wrong version, or device doesn't support the requested state. | |
745 | * 0 if device already is in the requested state. | |
746 | * 0 if device's power state has been successfully changed. | |
747 | */ | |
748 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
749 | { | |
337001b6 | 750 | int error; |
44e4e66e RW |
751 | |
752 | /* bound the state we're entering */ | |
448bd857 HY |
753 | if (state > PCI_D3cold) |
754 | state = PCI_D3cold; | |
44e4e66e RW |
755 | else if (state < PCI_D0) |
756 | state = PCI_D0; | |
757 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
758 | /* | |
759 | * If the device or the parent bridge do not support PCI PM, | |
760 | * ignore the request if we're doing anything other than putting | |
761 | * it into D0 (which would only happen on boot). | |
762 | */ | |
763 | return 0; | |
764 | ||
db288c9c RW |
765 | /* Check if we're already there */ |
766 | if (dev->current_state == state) | |
767 | return 0; | |
768 | ||
0e5dd46b RW |
769 | __pci_start_power_transition(dev, state); |
770 | ||
979b1791 AC |
771 | /* This device is quirked not to be put into D3, so |
772 | don't put it in D3 */ | |
448bd857 | 773 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 774 | return 0; |
44e4e66e | 775 | |
448bd857 HY |
776 | /* |
777 | * To put device in D3cold, we put device into D3hot in native | |
778 | * way, then put device into D3cold with platform ops | |
779 | */ | |
780 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
781 | PCI_D3hot : state); | |
44e4e66e | 782 | |
0e5dd46b RW |
783 | if (!__pci_complete_power_transition(dev, state)) |
784 | error = 0; | |
1a680b7c NC |
785 | /* |
786 | * When aspm_policy is "powersave" this call ensures | |
787 | * that ASPM is configured. | |
788 | */ | |
789 | if (!error && dev->bus->self) | |
790 | pcie_aspm_powersave_config_link(dev->bus->self); | |
44e4e66e RW |
791 | |
792 | return error; | |
793 | } | |
794 | ||
1da177e4 LT |
795 | /** |
796 | * pci_choose_state - Choose the power state of a PCI device | |
797 | * @dev: PCI device to be suspended | |
798 | * @state: target sleep state for the whole system. This is the value | |
799 | * that is passed to suspend() function. | |
800 | * | |
801 | * Returns PCI power state suitable for given device and given system | |
802 | * message. | |
803 | */ | |
804 | ||
805 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
806 | { | |
ab826ca4 | 807 | pci_power_t ret; |
0f64474b | 808 | |
728cdb75 | 809 | if (!dev->pm_cap) |
1da177e4 LT |
810 | return PCI_D0; |
811 | ||
961d9120 RW |
812 | ret = platform_pci_choose_state(dev); |
813 | if (ret != PCI_POWER_ERROR) | |
814 | return ret; | |
ca078bae PM |
815 | |
816 | switch (state.event) { | |
817 | case PM_EVENT_ON: | |
818 | return PCI_D0; | |
819 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
820 | case PM_EVENT_PRETHAW: |
821 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 822 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 823 | case PM_EVENT_HIBERNATE: |
ca078bae | 824 | return PCI_D3hot; |
1da177e4 | 825 | default: |
80ccba11 BH |
826 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
827 | state.event); | |
1da177e4 LT |
828 | BUG(); |
829 | } | |
830 | return PCI_D0; | |
831 | } | |
832 | ||
833 | EXPORT_SYMBOL(pci_choose_state); | |
834 | ||
89858517 YZ |
835 | #define PCI_EXP_SAVE_REGS 7 |
836 | ||
1b6b8ce2 | 837 | |
34a4876e YL |
838 | static struct pci_cap_saved_state *pci_find_saved_cap( |
839 | struct pci_dev *pci_dev, char cap) | |
840 | { | |
841 | struct pci_cap_saved_state *tmp; | |
34a4876e | 842 | |
b67bfe0d | 843 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
34a4876e YL |
844 | if (tmp->cap.cap_nr == cap) |
845 | return tmp; | |
846 | } | |
847 | return NULL; | |
848 | } | |
849 | ||
b56a5a23 MT |
850 | static int pci_save_pcie_state(struct pci_dev *dev) |
851 | { | |
59875ae4 | 852 | int i = 0; |
b56a5a23 MT |
853 | struct pci_cap_saved_state *save_state; |
854 | u16 *cap; | |
855 | ||
59875ae4 | 856 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
857 | return 0; |
858 | ||
9f35575d | 859 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 860 | if (!save_state) { |
e496b617 | 861 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
862 | return -ENOMEM; |
863 | } | |
63f4898a | 864 | |
59875ae4 JL |
865 | cap = (u16 *)&save_state->cap.data[0]; |
866 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
867 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
868 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
869 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
870 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
871 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
872 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 873 | |
b56a5a23 MT |
874 | return 0; |
875 | } | |
876 | ||
877 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
878 | { | |
59875ae4 | 879 | int i = 0; |
b56a5a23 MT |
880 | struct pci_cap_saved_state *save_state; |
881 | u16 *cap; | |
882 | ||
883 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 884 | if (!save_state) |
9cb604ed MS |
885 | return; |
886 | ||
59875ae4 JL |
887 | cap = (u16 *)&save_state->cap.data[0]; |
888 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
889 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
890 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
891 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
892 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
893 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
894 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
895 | } |
896 | ||
cc692a5f SH |
897 | |
898 | static int pci_save_pcix_state(struct pci_dev *dev) | |
899 | { | |
63f4898a | 900 | int pos; |
cc692a5f | 901 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
902 | |
903 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
904 | if (pos <= 0) | |
905 | return 0; | |
906 | ||
f34303de | 907 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 908 | if (!save_state) { |
e496b617 | 909 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
910 | return -ENOMEM; |
911 | } | |
cc692a5f | 912 | |
24a4742f AW |
913 | pci_read_config_word(dev, pos + PCI_X_CMD, |
914 | (u16 *)save_state->cap.data); | |
63f4898a | 915 | |
cc692a5f SH |
916 | return 0; |
917 | } | |
918 | ||
919 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
920 | { | |
921 | int i = 0, pos; | |
922 | struct pci_cap_saved_state *save_state; | |
923 | u16 *cap; | |
924 | ||
925 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
926 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
927 | if (!save_state || pos <= 0) | |
928 | return; | |
24a4742f | 929 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
930 | |
931 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
932 | } |
933 | ||
934 | ||
1da177e4 LT |
935 | /** |
936 | * pci_save_state - save the PCI configuration space of a device before suspending | |
937 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
938 | */ |
939 | int | |
940 | pci_save_state(struct pci_dev *dev) | |
941 | { | |
942 | int i; | |
943 | /* XXX: 100% dword access ok here? */ | |
944 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 945 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 946 | dev->state_saved = true; |
b56a5a23 MT |
947 | if ((i = pci_save_pcie_state(dev)) != 0) |
948 | return i; | |
cc692a5f SH |
949 | if ((i = pci_save_pcix_state(dev)) != 0) |
950 | return i; | |
1da177e4 LT |
951 | return 0; |
952 | } | |
953 | ||
ebfc5b80 RW |
954 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
955 | u32 saved_val, int retry) | |
956 | { | |
957 | u32 val; | |
958 | ||
959 | pci_read_config_dword(pdev, offset, &val); | |
960 | if (val == saved_val) | |
961 | return; | |
962 | ||
963 | for (;;) { | |
964 | dev_dbg(&pdev->dev, "restoring config space at offset " | |
965 | "%#x (was %#x, writing %#x)\n", offset, val, saved_val); | |
966 | pci_write_config_dword(pdev, offset, saved_val); | |
967 | if (retry-- <= 0) | |
968 | return; | |
969 | ||
970 | pci_read_config_dword(pdev, offset, &val); | |
971 | if (val == saved_val) | |
972 | return; | |
973 | ||
974 | mdelay(1); | |
975 | } | |
976 | } | |
977 | ||
a6cb9ee7 RW |
978 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
979 | int start, int end, int retry) | |
ebfc5b80 RW |
980 | { |
981 | int index; | |
982 | ||
983 | for (index = end; index >= start; index--) | |
984 | pci_restore_config_dword(pdev, 4 * index, | |
985 | pdev->saved_config_space[index], | |
986 | retry); | |
987 | } | |
988 | ||
a6cb9ee7 RW |
989 | static void pci_restore_config_space(struct pci_dev *pdev) |
990 | { | |
991 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
992 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
993 | /* Restore BARs before the command register. */ | |
994 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
995 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
996 | } else { | |
997 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
998 | } | |
999 | } | |
1000 | ||
1da177e4 LT |
1001 | /** |
1002 | * pci_restore_state - Restore the saved state of a PCI device | |
1003 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1004 | */ |
1d3c16a8 | 1005 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1006 | { |
c82f63e4 | 1007 | if (!dev->state_saved) |
1d3c16a8 | 1008 | return; |
4b77b0a2 | 1009 | |
b56a5a23 MT |
1010 | /* PCI Express register must be restored first */ |
1011 | pci_restore_pcie_state(dev); | |
1900ca13 | 1012 | pci_restore_ats_state(dev); |
b56a5a23 | 1013 | |
a6cb9ee7 | 1014 | pci_restore_config_space(dev); |
ebfc5b80 | 1015 | |
cc692a5f | 1016 | pci_restore_pcix_state(dev); |
41017f0c | 1017 | pci_restore_msi_state(dev); |
8c5cdb6a | 1018 | pci_restore_iov_state(dev); |
8fed4b65 | 1019 | |
4b77b0a2 | 1020 | dev->state_saved = false; |
1da177e4 LT |
1021 | } |
1022 | ||
ffbdd3f7 AW |
1023 | struct pci_saved_state { |
1024 | u32 config_space[16]; | |
1025 | struct pci_cap_saved_data cap[0]; | |
1026 | }; | |
1027 | ||
1028 | /** | |
1029 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1030 | * the device saved state. | |
1031 | * @dev: PCI device that we're dealing with | |
1032 | * | |
1033 | * Rerturn NULL if no state or error. | |
1034 | */ | |
1035 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1036 | { | |
1037 | struct pci_saved_state *state; | |
1038 | struct pci_cap_saved_state *tmp; | |
1039 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1040 | size_t size; |
1041 | ||
1042 | if (!dev->state_saved) | |
1043 | return NULL; | |
1044 | ||
1045 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1046 | ||
b67bfe0d | 1047 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1048 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1049 | ||
1050 | state = kzalloc(size, GFP_KERNEL); | |
1051 | if (!state) | |
1052 | return NULL; | |
1053 | ||
1054 | memcpy(state->config_space, dev->saved_config_space, | |
1055 | sizeof(state->config_space)); | |
1056 | ||
1057 | cap = state->cap; | |
b67bfe0d | 1058 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1059 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1060 | memcpy(cap, &tmp->cap, len); | |
1061 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1062 | } | |
1063 | /* Empty cap_save terminates list */ | |
1064 | ||
1065 | return state; | |
1066 | } | |
1067 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1068 | ||
1069 | /** | |
1070 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1071 | * @dev: PCI device that we're dealing with | |
1072 | * @state: Saved state returned from pci_store_saved_state() | |
1073 | */ | |
1074 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) | |
1075 | { | |
1076 | struct pci_cap_saved_data *cap; | |
1077 | ||
1078 | dev->state_saved = false; | |
1079 | ||
1080 | if (!state) | |
1081 | return 0; | |
1082 | ||
1083 | memcpy(dev->saved_config_space, state->config_space, | |
1084 | sizeof(state->config_space)); | |
1085 | ||
1086 | cap = state->cap; | |
1087 | while (cap->size) { | |
1088 | struct pci_cap_saved_state *tmp; | |
1089 | ||
1090 | tmp = pci_find_saved_cap(dev, cap->cap_nr); | |
1091 | if (!tmp || tmp->cap.size != cap->size) | |
1092 | return -EINVAL; | |
1093 | ||
1094 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1095 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1096 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1097 | } | |
1098 | ||
1099 | dev->state_saved = true; | |
1100 | return 0; | |
1101 | } | |
1102 | EXPORT_SYMBOL_GPL(pci_load_saved_state); | |
1103 | ||
1104 | /** | |
1105 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1106 | * and free the memory allocated for it. | |
1107 | * @dev: PCI device that we're dealing with | |
1108 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1109 | */ | |
1110 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1111 | struct pci_saved_state **state) | |
1112 | { | |
1113 | int ret = pci_load_saved_state(dev, *state); | |
1114 | kfree(*state); | |
1115 | *state = NULL; | |
1116 | return ret; | |
1117 | } | |
1118 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1119 | ||
38cc1302 HS |
1120 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1121 | { | |
1122 | int err; | |
1123 | ||
1124 | err = pci_set_power_state(dev, PCI_D0); | |
1125 | if (err < 0 && err != -EIO) | |
1126 | return err; | |
1127 | err = pcibios_enable_device(dev, bars); | |
1128 | if (err < 0) | |
1129 | return err; | |
1130 | pci_fixup_device(pci_fixup_enable, dev); | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | /** | |
0b62e13b | 1136 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1137 | * @dev: PCI device to be resumed |
1138 | * | |
1139 | * Note this function is a backend of pci_default_resume and is not supposed | |
1140 | * to be called by normal code, write proper resume handler and use it instead. | |
1141 | */ | |
0b62e13b | 1142 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1143 | { |
296ccb08 | 1144 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1145 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1146 | return 0; | |
1147 | } | |
1148 | ||
928bea96 YL |
1149 | static void pci_enable_bridge(struct pci_dev *dev) |
1150 | { | |
1151 | int retval; | |
1152 | ||
1153 | if (!dev) | |
1154 | return; | |
1155 | ||
1156 | pci_enable_bridge(dev->bus->self); | |
1157 | ||
cf3e1feb | 1158 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1159 | if (!dev->is_busmaster) |
cf3e1feb | 1160 | pci_set_master(dev); |
928bea96 | 1161 | return; |
cf3e1feb YL |
1162 | } |
1163 | ||
928bea96 YL |
1164 | retval = pci_enable_device(dev); |
1165 | if (retval) | |
1166 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1167 | retval); | |
1168 | pci_set_master(dev); | |
1169 | } | |
1170 | ||
b4b4fbba | 1171 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 LT |
1172 | { |
1173 | int err; | |
b718989d | 1174 | int i, bars = 0; |
1da177e4 | 1175 | |
97c145f7 JB |
1176 | /* |
1177 | * Power state could be unknown at this point, either due to a fresh | |
1178 | * boot or a device removal call. So get the current power state | |
1179 | * so that things like MSI message writing will behave as expected | |
1180 | * (e.g. if the device really is in D0 at enable time). | |
1181 | */ | |
1182 | if (dev->pm_cap) { | |
1183 | u16 pmcsr; | |
1184 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1185 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1186 | } | |
1187 | ||
cc7ba39b | 1188 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1189 | return 0; /* already enabled */ |
1190 | ||
928bea96 YL |
1191 | pci_enable_bridge(dev->bus->self); |
1192 | ||
497f16f2 YL |
1193 | /* only skip sriov related */ |
1194 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1195 | if (dev->resource[i].flags & flags) | |
1196 | bars |= (1 << i); | |
1197 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1198 | if (dev->resource[i].flags & flags) |
1199 | bars |= (1 << i); | |
1200 | ||
38cc1302 | 1201 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1202 | if (err < 0) |
38cc1302 | 1203 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1204 | return err; |
1da177e4 LT |
1205 | } |
1206 | ||
b718989d BH |
1207 | /** |
1208 | * pci_enable_device_io - Initialize a device for use with IO space | |
1209 | * @dev: PCI device to be initialized | |
1210 | * | |
1211 | * Initialize device before it's used by a driver. Ask low-level code | |
1212 | * to enable I/O resources. Wake up the device if it was suspended. | |
1213 | * Beware, this function can fail. | |
1214 | */ | |
1215 | int pci_enable_device_io(struct pci_dev *dev) | |
1216 | { | |
b4b4fbba | 1217 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d BH |
1218 | } |
1219 | ||
1220 | /** | |
1221 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1222 | * @dev: PCI device to be initialized | |
1223 | * | |
1224 | * Initialize device before it's used by a driver. Ask low-level code | |
1225 | * to enable Memory resources. Wake up the device if it was suspended. | |
1226 | * Beware, this function can fail. | |
1227 | */ | |
1228 | int pci_enable_device_mem(struct pci_dev *dev) | |
1229 | { | |
b4b4fbba | 1230 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d BH |
1231 | } |
1232 | ||
bae94d02 IPG |
1233 | /** |
1234 | * pci_enable_device - Initialize device before it's used by a driver. | |
1235 | * @dev: PCI device to be initialized | |
1236 | * | |
1237 | * Initialize device before it's used by a driver. Ask low-level code | |
1238 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1239 | * Beware, this function can fail. | |
1240 | * | |
1241 | * Note we don't actually enable the device many times if we call | |
1242 | * this function repeatedly (we just increment the count). | |
1243 | */ | |
1244 | int pci_enable_device(struct pci_dev *dev) | |
1245 | { | |
b4b4fbba | 1246 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
1247 | } |
1248 | ||
9ac7849e TH |
1249 | /* |
1250 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1251 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1252 | * there's no need to track it separately. pci_devres is initialized | |
1253 | * when a device is enabled using managed PCI device enable interface. | |
1254 | */ | |
1255 | struct pci_devres { | |
7f375f32 TH |
1256 | unsigned int enabled:1; |
1257 | unsigned int pinned:1; | |
9ac7849e TH |
1258 | unsigned int orig_intx:1; |
1259 | unsigned int restore_intx:1; | |
1260 | u32 region_mask; | |
1261 | }; | |
1262 | ||
1263 | static void pcim_release(struct device *gendev, void *res) | |
1264 | { | |
1265 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1266 | struct pci_devres *this = res; | |
1267 | int i; | |
1268 | ||
1269 | if (dev->msi_enabled) | |
1270 | pci_disable_msi(dev); | |
1271 | if (dev->msix_enabled) | |
1272 | pci_disable_msix(dev); | |
1273 | ||
1274 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1275 | if (this->region_mask & (1 << i)) | |
1276 | pci_release_region(dev, i); | |
1277 | ||
1278 | if (this->restore_intx) | |
1279 | pci_intx(dev, this->orig_intx); | |
1280 | ||
7f375f32 | 1281 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1282 | pci_disable_device(dev); |
1283 | } | |
1284 | ||
1285 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1286 | { | |
1287 | struct pci_devres *dr, *new_dr; | |
1288 | ||
1289 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1290 | if (dr) | |
1291 | return dr; | |
1292 | ||
1293 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1294 | if (!new_dr) | |
1295 | return NULL; | |
1296 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1297 | } | |
1298 | ||
1299 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1300 | { | |
1301 | if (pci_is_managed(pdev)) | |
1302 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1303 | return NULL; | |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * pcim_enable_device - Managed pci_enable_device() | |
1308 | * @pdev: PCI device to be initialized | |
1309 | * | |
1310 | * Managed pci_enable_device(). | |
1311 | */ | |
1312 | int pcim_enable_device(struct pci_dev *pdev) | |
1313 | { | |
1314 | struct pci_devres *dr; | |
1315 | int rc; | |
1316 | ||
1317 | dr = get_pci_dr(pdev); | |
1318 | if (unlikely(!dr)) | |
1319 | return -ENOMEM; | |
b95d58ea TH |
1320 | if (dr->enabled) |
1321 | return 0; | |
9ac7849e TH |
1322 | |
1323 | rc = pci_enable_device(pdev); | |
1324 | if (!rc) { | |
1325 | pdev->is_managed = 1; | |
7f375f32 | 1326 | dr->enabled = 1; |
9ac7849e TH |
1327 | } |
1328 | return rc; | |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * pcim_pin_device - Pin managed PCI device | |
1333 | * @pdev: PCI device to pin | |
1334 | * | |
1335 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1336 | * driver detach. @pdev must have been enabled with | |
1337 | * pcim_enable_device(). | |
1338 | */ | |
1339 | void pcim_pin_device(struct pci_dev *pdev) | |
1340 | { | |
1341 | struct pci_devres *dr; | |
1342 | ||
1343 | dr = find_pci_dr(pdev); | |
7f375f32 | 1344 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1345 | if (dr) |
7f375f32 | 1346 | dr->pinned = 1; |
9ac7849e TH |
1347 | } |
1348 | ||
eca0d467 MG |
1349 | /* |
1350 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1351 | * @dev: the PCI device being added | |
1352 | * | |
1353 | * Permits the platform to provide architecture specific functionality when | |
1354 | * devices are added. This is the default implementation. Architecture | |
1355 | * implementations can override this. | |
1356 | */ | |
1357 | int __weak pcibios_add_device (struct pci_dev *dev) | |
1358 | { | |
1359 | return 0; | |
1360 | } | |
1361 | ||
6ae32c53 SO |
1362 | /** |
1363 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1364 | * @dev: the PCI device being released | |
1365 | * | |
1366 | * Permits the platform to provide architecture specific functionality when | |
1367 | * devices are released. This is the default implementation. Architecture | |
1368 | * implementations can override this. | |
1369 | */ | |
1370 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1371 | ||
1da177e4 LT |
1372 | /** |
1373 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1374 | * @dev: the PCI device to disable | |
1375 | * | |
1376 | * Disables architecture specific PCI resources for the device. This | |
1377 | * is the default implementation. Architecture implementations can | |
1378 | * override this. | |
1379 | */ | |
d6d88c83 | 1380 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1381 | |
fa58d305 RW |
1382 | static void do_pci_disable_device(struct pci_dev *dev) |
1383 | { | |
1384 | u16 pci_command; | |
1385 | ||
1386 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1387 | if (pci_command & PCI_COMMAND_MASTER) { | |
1388 | pci_command &= ~PCI_COMMAND_MASTER; | |
1389 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1390 | } | |
1391 | ||
1392 | pcibios_disable_device(dev); | |
1393 | } | |
1394 | ||
1395 | /** | |
1396 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1397 | * @dev: PCI device to disable | |
1398 | * | |
1399 | * NOTE: This function is a backend of PCI power management routines and is | |
1400 | * not supposed to be called drivers. | |
1401 | */ | |
1402 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1403 | { | |
296ccb08 | 1404 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1405 | do_pci_disable_device(dev); |
1406 | } | |
1407 | ||
1da177e4 LT |
1408 | /** |
1409 | * pci_disable_device - Disable PCI device after use | |
1410 | * @dev: PCI device to be disabled | |
1411 | * | |
1412 | * Signal to the system that the PCI device is not in use by the system | |
1413 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1414 | * |
1415 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1416 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 LT |
1417 | */ |
1418 | void | |
1419 | pci_disable_device(struct pci_dev *dev) | |
1420 | { | |
9ac7849e | 1421 | struct pci_devres *dr; |
99dc804d | 1422 | |
9ac7849e TH |
1423 | dr = find_pci_dr(dev); |
1424 | if (dr) | |
7f375f32 | 1425 | dr->enabled = 0; |
9ac7849e | 1426 | |
fd6dceab KK |
1427 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1428 | "disabling already-disabled device"); | |
1429 | ||
cc7ba39b | 1430 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1431 | return; |
1432 | ||
fa58d305 | 1433 | do_pci_disable_device(dev); |
1da177e4 | 1434 | |
fa58d305 | 1435 | dev->is_busmaster = 0; |
1da177e4 LT |
1436 | } |
1437 | ||
f7bdd12d BK |
1438 | /** |
1439 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1440 | * @dev: the PCIe device reset |
f7bdd12d BK |
1441 | * @state: Reset state to enter into |
1442 | * | |
1443 | * | |
45e829ea | 1444 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1445 | * implementation. Architecture implementations can override this. |
1446 | */ | |
d6d88c83 BH |
1447 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1448 | enum pcie_reset_state state) | |
f7bdd12d BK |
1449 | { |
1450 | return -EINVAL; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1455 | * @dev: the PCIe device reset |
f7bdd12d BK |
1456 | * @state: Reset state to enter into |
1457 | * | |
1458 | * | |
1459 | * Sets the PCI reset state for the device. | |
1460 | */ | |
1461 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1462 | { | |
1463 | return pcibios_set_pcie_reset_state(dev, state); | |
1464 | } | |
1465 | ||
58ff4633 RW |
1466 | /** |
1467 | * pci_check_pme_status - Check if given device has generated PME. | |
1468 | * @dev: Device to check. | |
1469 | * | |
1470 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1471 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1472 | * 'false' otherwise. | |
1473 | */ | |
1474 | bool pci_check_pme_status(struct pci_dev *dev) | |
1475 | { | |
1476 | int pmcsr_pos; | |
1477 | u16 pmcsr; | |
1478 | bool ret = false; | |
1479 | ||
1480 | if (!dev->pm_cap) | |
1481 | return false; | |
1482 | ||
1483 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1484 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1485 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1486 | return false; | |
1487 | ||
1488 | /* Clear PME status. */ | |
1489 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1490 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1491 | /* Disable PME to avoid interrupt flood. */ | |
1492 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1493 | ret = true; | |
1494 | } | |
1495 | ||
1496 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1497 | ||
1498 | return ret; | |
1499 | } | |
1500 | ||
b67ea761 RW |
1501 | /** |
1502 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1503 | * @dev: Device to handle. | |
379021d5 | 1504 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1505 | * |
1506 | * Check if @dev has generated PME and queue a resume request for it in that | |
1507 | * case. | |
1508 | */ | |
379021d5 | 1509 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1510 | { |
379021d5 RW |
1511 | if (pme_poll_reset && dev->pme_poll) |
1512 | dev->pme_poll = false; | |
1513 | ||
c125e96f | 1514 | if (pci_check_pme_status(dev)) { |
c125e96f | 1515 | pci_wakeup_event(dev); |
0f953bf6 | 1516 | pm_request_resume(&dev->dev); |
c125e96f | 1517 | } |
b67ea761 RW |
1518 | return 0; |
1519 | } | |
1520 | ||
1521 | /** | |
1522 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1523 | * @bus: Top bus of the subtree to walk. | |
1524 | */ | |
1525 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1526 | { | |
1527 | if (bus) | |
379021d5 | 1528 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1529 | } |
1530 | ||
448bd857 HY |
1531 | /** |
1532 | * pci_wakeup - Wake up a PCI device | |
ceaf5b5f | 1533 | * @pci_dev: Device to handle. |
448bd857 HY |
1534 | * @ign: ignored parameter |
1535 | */ | |
1536 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
1537 | { | |
1538 | pci_wakeup_event(pci_dev); | |
1539 | pm_request_resume(&pci_dev->dev); | |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | /** | |
1544 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
1545 | * @bus: Top bus of the subtree to walk. | |
1546 | */ | |
1547 | void pci_wakeup_bus(struct pci_bus *bus) | |
1548 | { | |
1549 | if (bus) | |
1550 | pci_walk_bus(bus, pci_wakeup, NULL); | |
1551 | } | |
1552 | ||
eb9d0fe4 RW |
1553 | /** |
1554 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1555 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1556 | * @state: PCI state from which device will issue PME#. |
1557 | */ | |
e5899e1b | 1558 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1559 | { |
337001b6 | 1560 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1561 | return false; |
1562 | ||
337001b6 | 1563 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1564 | } |
1565 | ||
df17e62e MG |
1566 | static void pci_pme_list_scan(struct work_struct *work) |
1567 | { | |
379021d5 | 1568 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1569 | |
1570 | mutex_lock(&pci_pme_list_mutex); | |
1571 | if (!list_empty(&pci_pme_list)) { | |
379021d5 RW |
1572 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1573 | if (pme_dev->dev->pme_poll) { | |
71a83bd7 ZY |
1574 | struct pci_dev *bridge; |
1575 | ||
1576 | bridge = pme_dev->dev->bus->self; | |
1577 | /* | |
1578 | * If bridge is in low power state, the | |
1579 | * configuration space of subordinate devices | |
1580 | * may be not accessible | |
1581 | */ | |
1582 | if (bridge && bridge->current_state != PCI_D0) | |
1583 | continue; | |
379021d5 RW |
1584 | pci_pme_wakeup(pme_dev->dev, NULL); |
1585 | } else { | |
1586 | list_del(&pme_dev->list); | |
1587 | kfree(pme_dev); | |
1588 | } | |
1589 | } | |
1590 | if (!list_empty(&pci_pme_list)) | |
1591 | schedule_delayed_work(&pci_pme_work, | |
1592 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1593 | } |
1594 | mutex_unlock(&pci_pme_list_mutex); | |
1595 | } | |
1596 | ||
eb9d0fe4 RW |
1597 | /** |
1598 | * pci_pme_active - enable or disable PCI device's PME# function | |
1599 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1600 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1601 | * | |
1602 | * The caller must verify that the device is capable of generating PME# before | |
1603 | * calling this function with @enable equal to 'true'. | |
1604 | */ | |
5a6c9b60 | 1605 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1606 | { |
1607 | u16 pmcsr; | |
1608 | ||
ffaddbe8 | 1609 | if (!dev->pme_support) |
eb9d0fe4 RW |
1610 | return; |
1611 | ||
337001b6 | 1612 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1613 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1614 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1615 | if (!enable) | |
1616 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1617 | ||
337001b6 | 1618 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1619 | |
6e965e0d HY |
1620 | /* |
1621 | * PCI (as opposed to PCIe) PME requires that the device have | |
1622 | * its PME# line hooked up correctly. Not all hardware vendors | |
1623 | * do this, so the PME never gets delivered and the device | |
1624 | * remains asleep. The easiest way around this is to | |
1625 | * periodically walk the list of suspended devices and check | |
1626 | * whether any have their PME flag set. The assumption is that | |
1627 | * we'll wake up often enough anyway that this won't be a huge | |
1628 | * hit, and the power savings from the devices will still be a | |
1629 | * win. | |
1630 | * | |
1631 | * Although PCIe uses in-band PME message instead of PME# line | |
1632 | * to report PME, PME does not work for some PCIe devices in | |
1633 | * reality. For example, there are devices that set their PME | |
1634 | * status bits, but don't really bother to send a PME message; | |
1635 | * there are PCI Express Root Ports that don't bother to | |
1636 | * trigger interrupts when they receive PME messages from the | |
1637 | * devices below. So PME poll is used for PCIe devices too. | |
1638 | */ | |
df17e62e | 1639 | |
379021d5 | 1640 | if (dev->pme_poll) { |
df17e62e MG |
1641 | struct pci_pme_device *pme_dev; |
1642 | if (enable) { | |
1643 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1644 | GFP_KERNEL); | |
0394cb19 BH |
1645 | if (!pme_dev) { |
1646 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1647 | return; | |
1648 | } | |
df17e62e MG |
1649 | pme_dev->dev = dev; |
1650 | mutex_lock(&pci_pme_list_mutex); | |
1651 | list_add(&pme_dev->list, &pci_pme_list); | |
1652 | if (list_is_singular(&pci_pme_list)) | |
1653 | schedule_delayed_work(&pci_pme_work, | |
1654 | msecs_to_jiffies(PME_TIMEOUT)); | |
1655 | mutex_unlock(&pci_pme_list_mutex); | |
1656 | } else { | |
1657 | mutex_lock(&pci_pme_list_mutex); | |
1658 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1659 | if (pme_dev->dev == dev) { | |
1660 | list_del(&pme_dev->list); | |
1661 | kfree(pme_dev); | |
1662 | break; | |
1663 | } | |
1664 | } | |
1665 | mutex_unlock(&pci_pme_list_mutex); | |
1666 | } | |
1667 | } | |
1668 | ||
85b8582d | 1669 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 RW |
1670 | } |
1671 | ||
1da177e4 | 1672 | /** |
6cbf8214 | 1673 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1674 | * @dev: PCI device affected |
1675 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1676 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1677 | * @enable: True to enable event generation; false to disable |
1678 | * | |
1679 | * This enables the device as a wakeup event source, or disables it. | |
1680 | * When such events involves platform-specific hooks, those hooks are | |
1681 | * called automatically by this routine. | |
1682 | * | |
1683 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1684 | * always require such platform hooks. |
075c1771 | 1685 | * |
eb9d0fe4 RW |
1686 | * RETURN VALUE: |
1687 | * 0 is returned on success | |
1688 | * -EINVAL is returned if device is not supposed to wake up the system | |
1689 | * Error code depending on the platform is returned if both the platform and | |
1690 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1691 | */ |
6cbf8214 RW |
1692 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1693 | bool runtime, bool enable) | |
1da177e4 | 1694 | { |
5bcc2fb4 | 1695 | int ret = 0; |
075c1771 | 1696 | |
6cbf8214 | 1697 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1698 | return -EINVAL; |
1da177e4 | 1699 | |
e80bb09d RW |
1700 | /* Don't do the same thing twice in a row for one device. */ |
1701 | if (!!enable == !!dev->wakeup_prepared) | |
1702 | return 0; | |
1703 | ||
eb9d0fe4 RW |
1704 | /* |
1705 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1706 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1707 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1708 | */ |
1da177e4 | 1709 | |
5bcc2fb4 RW |
1710 | if (enable) { |
1711 | int error; | |
1da177e4 | 1712 | |
5bcc2fb4 RW |
1713 | if (pci_pme_capable(dev, state)) |
1714 | pci_pme_active(dev, true); | |
1715 | else | |
1716 | ret = 1; | |
6cbf8214 RW |
1717 | error = runtime ? platform_pci_run_wake(dev, true) : |
1718 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1719 | if (ret) |
1720 | ret = error; | |
e80bb09d RW |
1721 | if (!ret) |
1722 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1723 | } else { |
6cbf8214 RW |
1724 | if (runtime) |
1725 | platform_pci_run_wake(dev, false); | |
1726 | else | |
1727 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1728 | pci_pme_active(dev, false); |
e80bb09d | 1729 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1730 | } |
1da177e4 | 1731 | |
5bcc2fb4 | 1732 | return ret; |
eb9d0fe4 | 1733 | } |
6cbf8214 | 1734 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1735 | |
0235c4fc RW |
1736 | /** |
1737 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1738 | * @dev: PCI device to prepare | |
1739 | * @enable: True to enable wake-up event generation; false to disable | |
1740 | * | |
1741 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1742 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1743 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1744 | * ordering constraints. | |
1745 | * | |
1746 | * This function only returns error code if the device is not capable of | |
1747 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1748 | * enable wake-up power for it. | |
1749 | */ | |
1750 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1751 | { | |
1752 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1753 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1754 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1755 | } | |
1756 | ||
404cc2d8 | 1757 | /** |
37139074 JB |
1758 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1759 | * @dev: PCI device | |
1760 | * | |
1761 | * Use underlying platform code to find a supported low power state for @dev. | |
1762 | * If the platform can't manage @dev, return the deepest state from which it | |
1763 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1764 | */ |
e5899e1b | 1765 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1766 | { |
1767 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1768 | |
1769 | if (platform_pci_power_manageable(dev)) { | |
1770 | /* | |
1771 | * Call the platform to choose the target state of the device | |
1772 | * and enable wake-up from this state if supported. | |
1773 | */ | |
1774 | pci_power_t state = platform_pci_choose_state(dev); | |
1775 | ||
1776 | switch (state) { | |
1777 | case PCI_POWER_ERROR: | |
1778 | case PCI_UNKNOWN: | |
1779 | break; | |
1780 | case PCI_D1: | |
1781 | case PCI_D2: | |
1782 | if (pci_no_d1d2(dev)) | |
1783 | break; | |
1784 | default: | |
1785 | target_state = state; | |
404cc2d8 | 1786 | } |
d2abdf62 RW |
1787 | } else if (!dev->pm_cap) { |
1788 | target_state = PCI_D0; | |
404cc2d8 RW |
1789 | } else if (device_may_wakeup(&dev->dev)) { |
1790 | /* | |
1791 | * Find the deepest state from which the device can generate | |
1792 | * wake-up events, make it the target state and enable device | |
1793 | * to generate PME#. | |
1794 | */ | |
337001b6 RW |
1795 | if (dev->pme_support) { |
1796 | while (target_state | |
1797 | && !(dev->pme_support & (1 << target_state))) | |
1798 | target_state--; | |
404cc2d8 RW |
1799 | } |
1800 | } | |
1801 | ||
e5899e1b RW |
1802 | return target_state; |
1803 | } | |
1804 | ||
1805 | /** | |
1806 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1807 | * @dev: Device to handle. | |
1808 | * | |
1809 | * Choose the power state appropriate for the device depending on whether | |
1810 | * it can wake up the system and/or is power manageable by the platform | |
1811 | * (PCI_D3hot is the default) and put the device into that state. | |
1812 | */ | |
1813 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1814 | { | |
1815 | pci_power_t target_state = pci_target_state(dev); | |
1816 | int error; | |
1817 | ||
1818 | if (target_state == PCI_POWER_ERROR) | |
1819 | return -EIO; | |
1820 | ||
448bd857 HY |
1821 | /* D3cold during system suspend/hibernate is not supported */ |
1822 | if (target_state > PCI_D3hot) | |
1823 | target_state = PCI_D3hot; | |
1824 | ||
8efb8c76 | 1825 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1826 | |
404cc2d8 RW |
1827 | error = pci_set_power_state(dev, target_state); |
1828 | ||
1829 | if (error) | |
1830 | pci_enable_wake(dev, target_state, false); | |
1831 | ||
1832 | return error; | |
1833 | } | |
1834 | ||
1835 | /** | |
443bd1c4 | 1836 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1837 | * @dev: Device to handle. |
1838 | * | |
88393161 | 1839 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1840 | */ |
1841 | int pci_back_from_sleep(struct pci_dev *dev) | |
1842 | { | |
1843 | pci_enable_wake(dev, PCI_D0, false); | |
1844 | return pci_set_power_state(dev, PCI_D0); | |
1845 | } | |
1846 | ||
6cbf8214 RW |
1847 | /** |
1848 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1849 | * @dev: PCI device being suspended. | |
1850 | * | |
1851 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1852 | * power state. | |
1853 | */ | |
1854 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1855 | { | |
1856 | pci_power_t target_state = pci_target_state(dev); | |
1857 | int error; | |
1858 | ||
1859 | if (target_state == PCI_POWER_ERROR) | |
1860 | return -EIO; | |
1861 | ||
448bd857 HY |
1862 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1863 | ||
6cbf8214 RW |
1864 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1865 | ||
1866 | error = pci_set_power_state(dev, target_state); | |
1867 | ||
448bd857 | 1868 | if (error) { |
6cbf8214 | 1869 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1870 | dev->runtime_d3cold = false; |
1871 | } | |
6cbf8214 RW |
1872 | |
1873 | return error; | |
1874 | } | |
1875 | ||
b67ea761 RW |
1876 | /** |
1877 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1878 | * @dev: Device to check. | |
1879 | * | |
1880 | * Return true if the device itself is cabable of generating wake-up events | |
1881 | * (through the platform or using the native PCIe PME) or if the device supports | |
1882 | * PME and one of its upstream bridges can generate wake-up events. | |
1883 | */ | |
1884 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1885 | { | |
1886 | struct pci_bus *bus = dev->bus; | |
1887 | ||
1888 | if (device_run_wake(&dev->dev)) | |
1889 | return true; | |
1890 | ||
1891 | if (!dev->pme_support) | |
1892 | return false; | |
1893 | ||
1894 | while (bus->parent) { | |
1895 | struct pci_dev *bridge = bus->self; | |
1896 | ||
1897 | if (device_run_wake(&bridge->dev)) | |
1898 | return true; | |
1899 | ||
1900 | bus = bus->parent; | |
1901 | } | |
1902 | ||
1903 | /* We have reached the root bus. */ | |
1904 | if (bus->bridge) | |
1905 | return device_run_wake(bus->bridge); | |
1906 | ||
1907 | return false; | |
1908 | } | |
1909 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
1910 | ||
b3c32c4f HY |
1911 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
1912 | { | |
1913 | struct device *dev = &pdev->dev; | |
1914 | struct device *parent = dev->parent; | |
1915 | ||
1916 | if (parent) | |
1917 | pm_runtime_get_sync(parent); | |
1918 | pm_runtime_get_noresume(dev); | |
1919 | /* | |
1920 | * pdev->current_state is set to PCI_D3cold during suspending, | |
1921 | * so wait until suspending completes | |
1922 | */ | |
1923 | pm_runtime_barrier(dev); | |
1924 | /* | |
1925 | * Only need to resume devices in D3cold, because config | |
1926 | * registers are still accessible for devices suspended but | |
1927 | * not in D3cold. | |
1928 | */ | |
1929 | if (pdev->current_state == PCI_D3cold) | |
1930 | pm_runtime_resume(dev); | |
1931 | } | |
1932 | ||
1933 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
1934 | { | |
1935 | struct device *dev = &pdev->dev; | |
1936 | struct device *parent = dev->parent; | |
1937 | ||
1938 | pm_runtime_put(dev); | |
1939 | if (parent) | |
1940 | pm_runtime_put_sync(parent); | |
1941 | } | |
1942 | ||
eb9d0fe4 RW |
1943 | /** |
1944 | * pci_pm_init - Initialize PM functions of given PCI device | |
1945 | * @dev: PCI device to handle. | |
1946 | */ | |
1947 | void pci_pm_init(struct pci_dev *dev) | |
1948 | { | |
1949 | int pm; | |
1950 | u16 pmc; | |
1da177e4 | 1951 | |
bb910a70 | 1952 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
1953 | pm_runtime_set_active(&dev->dev); |
1954 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 1955 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 1956 | dev->wakeup_prepared = false; |
bb910a70 | 1957 | |
337001b6 | 1958 | dev->pm_cap = 0; |
ffaddbe8 | 1959 | dev->pme_support = 0; |
337001b6 | 1960 | |
eb9d0fe4 RW |
1961 | /* find PCI PM capability in list */ |
1962 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1963 | if (!pm) | |
50246dd4 | 1964 | return; |
eb9d0fe4 RW |
1965 | /* Check device's ability to generate PME# */ |
1966 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1967 | |
eb9d0fe4 RW |
1968 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1969 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1970 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 1971 | return; |
eb9d0fe4 RW |
1972 | } |
1973 | ||
337001b6 | 1974 | dev->pm_cap = pm; |
1ae861e6 | 1975 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 1976 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 1977 | dev->d3cold_allowed = true; |
337001b6 RW |
1978 | |
1979 | dev->d1_support = false; | |
1980 | dev->d2_support = false; | |
1981 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1982 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1983 | dev->d1_support = true; |
c9ed77ee | 1984 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1985 | dev->d2_support = true; |
c9ed77ee BH |
1986 | |
1987 | if (dev->d1_support || dev->d2_support) | |
1988 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1989 | dev->d1_support ? " D1" : "", |
1990 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1991 | } |
1992 | ||
1993 | pmc &= PCI_PM_CAP_PME_MASK; | |
1994 | if (pmc) { | |
10c3d71d BH |
1995 | dev_printk(KERN_DEBUG, &dev->dev, |
1996 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
1997 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
1998 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1999 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2000 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2001 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2002 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2003 | dev->pme_poll = true; |
eb9d0fe4 RW |
2004 | /* |
2005 | * Make device's PM flags reflect the wake-up capability, but | |
2006 | * let the user space enable it to wake up the system as needed. | |
2007 | */ | |
2008 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2009 | /* Disable the PME# generation functionality */ |
337001b6 | 2010 | pci_pme_active(dev, false); |
eb9d0fe4 | 2011 | } |
1da177e4 LT |
2012 | } |
2013 | ||
34a4876e YL |
2014 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2015 | struct pci_cap_saved_state *new_cap) | |
2016 | { | |
2017 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2018 | } | |
2019 | ||
63f4898a | 2020 | /** |
ce1be10b | 2021 | * pci_add_cap_save_buffer - allocate buffer for saving given capability registers |
63f4898a RW |
2022 | * @dev: the PCI device |
2023 | * @cap: the capability to allocate the buffer for | |
2024 | * @size: requested size of the buffer | |
2025 | */ | |
2026 | static int pci_add_cap_save_buffer( | |
2027 | struct pci_dev *dev, char cap, unsigned int size) | |
2028 | { | |
2029 | int pos; | |
2030 | struct pci_cap_saved_state *save_state; | |
2031 | ||
2032 | pos = pci_find_capability(dev, cap); | |
2033 | if (pos <= 0) | |
2034 | return 0; | |
2035 | ||
2036 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2037 | if (!save_state) | |
2038 | return -ENOMEM; | |
2039 | ||
24a4742f AW |
2040 | save_state->cap.cap_nr = cap; |
2041 | save_state->cap.size = size; | |
63f4898a RW |
2042 | pci_add_saved_cap(dev, save_state); |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | /** | |
2048 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2049 | * @dev: the PCI device | |
2050 | */ | |
2051 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2052 | { | |
2053 | int error; | |
2054 | ||
89858517 YZ |
2055 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2056 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2057 | if (error) |
2058 | dev_err(&dev->dev, | |
2059 | "unable to preallocate PCI Express save buffer\n"); | |
2060 | ||
2061 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2062 | if (error) | |
2063 | dev_err(&dev->dev, | |
2064 | "unable to preallocate PCI-X save buffer\n"); | |
2065 | } | |
2066 | ||
f796841e YL |
2067 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2068 | { | |
2069 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2070 | struct hlist_node *n; |
f796841e | 2071 | |
b67bfe0d | 2072 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2073 | kfree(tmp); |
2074 | } | |
2075 | ||
58c3a727 | 2076 | /** |
31ab2476 | 2077 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2078 | * @dev: the PCI device |
b0cc6020 YW |
2079 | * |
2080 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2081 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2082 | */ |
31ab2476 | 2083 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2084 | { |
58c3a727 | 2085 | u32 cap; |
8113587c | 2086 | struct pci_dev *bridge; |
58c3a727 | 2087 | |
6748dcc2 | 2088 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2089 | return; |
2090 | ||
8113587c | 2091 | bridge = dev->bus->self; |
cb97ae34 | 2092 | if (!bridge) |
8113587c ZY |
2093 | return; |
2094 | ||
59875ae4 | 2095 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2096 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2097 | return; | |
2098 | ||
b0cc6020 YW |
2099 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2100 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2101 | PCI_EXP_DEVCTL2_ARI); | |
2102 | bridge->ari_enabled = 1; | |
2103 | } else { | |
2104 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2105 | PCI_EXP_DEVCTL2_ARI); | |
2106 | bridge->ari_enabled = 0; | |
2107 | } | |
58c3a727 YZ |
2108 | } |
2109 | ||
b48d4425 | 2110 | /** |
c463b8cb | 2111 | * pci_enable_ido - enable ID-based Ordering on a device |
b48d4425 JB |
2112 | * @dev: the PCI device |
2113 | * @type: which types of IDO to enable | |
2114 | * | |
2115 | * Enable ID-based ordering on @dev. @type can contain the bits | |
2116 | * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate | |
2117 | * which types of transactions are allowed to be re-ordered. | |
2118 | */ | |
2119 | void pci_enable_ido(struct pci_dev *dev, unsigned long type) | |
2120 | { | |
59875ae4 | 2121 | u16 ctrl = 0; |
b48d4425 | 2122 | |
b48d4425 | 2123 | if (type & PCI_EXP_IDO_REQUEST) |
d2ab1fa6 | 2124 | ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN; |
b48d4425 | 2125 | if (type & PCI_EXP_IDO_COMPLETION) |
d2ab1fa6 | 2126 | ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN; |
59875ae4 JL |
2127 | if (ctrl) |
2128 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl); | |
b48d4425 JB |
2129 | } |
2130 | EXPORT_SYMBOL(pci_enable_ido); | |
2131 | ||
2132 | /** | |
2133 | * pci_disable_ido - disable ID-based ordering on a device | |
2134 | * @dev: the PCI device | |
2135 | * @type: which types of IDO to disable | |
2136 | */ | |
2137 | void pci_disable_ido(struct pci_dev *dev, unsigned long type) | |
2138 | { | |
59875ae4 | 2139 | u16 ctrl = 0; |
b48d4425 | 2140 | |
b48d4425 | 2141 | if (type & PCI_EXP_IDO_REQUEST) |
d2ab1fa6 | 2142 | ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN; |
b48d4425 | 2143 | if (type & PCI_EXP_IDO_COMPLETION) |
d2ab1fa6 | 2144 | ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN; |
59875ae4 JL |
2145 | if (ctrl) |
2146 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl); | |
b48d4425 JB |
2147 | } |
2148 | EXPORT_SYMBOL(pci_disable_ido); | |
2149 | ||
48a92a81 JB |
2150 | /** |
2151 | * pci_enable_obff - enable optimized buffer flush/fill | |
2152 | * @dev: PCI device | |
2153 | * @type: type of signaling to use | |
2154 | * | |
2155 | * Try to enable @type OBFF signaling on @dev. It will try using WAKE# | |
2156 | * signaling if possible, falling back to message signaling only if | |
2157 | * WAKE# isn't supported. @type should indicate whether the PCIe link | |
2158 | * be brought out of L0s or L1 to send the message. It should be either | |
2159 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. | |
2160 | * | |
2161 | * If your device can benefit from receiving all messages, even at the | |
2162 | * power cost of bringing the link back up from a low power state, use | |
2163 | * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the | |
2164 | * preferred type). | |
2165 | * | |
2166 | * RETURNS: | |
2167 | * Zero on success, appropriate error number on failure. | |
2168 | */ | |
2169 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) | |
2170 | { | |
48a92a81 JB |
2171 | u32 cap; |
2172 | u16 ctrl; | |
2173 | int ret; | |
2174 | ||
59875ae4 | 2175 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
d2ab1fa6 | 2176 | if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK)) |
48a92a81 JB |
2177 | return -ENOTSUPP; /* no OBFF support at all */ |
2178 | ||
2179 | /* Make sure the topology supports OBFF as well */ | |
8291550f | 2180 | if (dev->bus->self) { |
48a92a81 JB |
2181 | ret = pci_enable_obff(dev->bus->self, type); |
2182 | if (ret) | |
2183 | return ret; | |
2184 | } | |
2185 | ||
59875ae4 | 2186 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl); |
d2ab1fa6 BH |
2187 | if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE) |
2188 | ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN; | |
48a92a81 JB |
2189 | else { |
2190 | switch (type) { | |
2191 | case PCI_EXP_OBFF_SIGNAL_L0: | |
d2ab1fa6 BH |
2192 | if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN)) |
2193 | ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN; | |
48a92a81 JB |
2194 | break; |
2195 | case PCI_EXP_OBFF_SIGNAL_ALWAYS: | |
d2ab1fa6 BH |
2196 | ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN; |
2197 | ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN; | |
48a92a81 JB |
2198 | break; |
2199 | default: | |
2200 | WARN(1, "bad OBFF signal type\n"); | |
2201 | return -ENOTSUPP; | |
2202 | } | |
2203 | } | |
59875ae4 | 2204 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl); |
48a92a81 JB |
2205 | |
2206 | return 0; | |
2207 | } | |
2208 | EXPORT_SYMBOL(pci_enable_obff); | |
2209 | ||
2210 | /** | |
2211 | * pci_disable_obff - disable optimized buffer flush/fill | |
2212 | * @dev: PCI device | |
2213 | * | |
2214 | * Disable OBFF on @dev. | |
2215 | */ | |
2216 | void pci_disable_obff(struct pci_dev *dev) | |
2217 | { | |
d2ab1fa6 BH |
2218 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, |
2219 | PCI_EXP_DEVCTL2_OBFF_WAKE_EN); | |
48a92a81 JB |
2220 | } |
2221 | EXPORT_SYMBOL(pci_disable_obff); | |
2222 | ||
51c2e0a7 JB |
2223 | /** |
2224 | * pci_ltr_supported - check whether a device supports LTR | |
2225 | * @dev: PCI device | |
2226 | * | |
2227 | * RETURNS: | |
2228 | * True if @dev supports latency tolerance reporting, false otherwise. | |
2229 | */ | |
c32823f8 | 2230 | static bool pci_ltr_supported(struct pci_dev *dev) |
51c2e0a7 | 2231 | { |
51c2e0a7 JB |
2232 | u32 cap; |
2233 | ||
59875ae4 | 2234 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
51c2e0a7 JB |
2235 | |
2236 | return cap & PCI_EXP_DEVCAP2_LTR; | |
2237 | } | |
51c2e0a7 JB |
2238 | |
2239 | /** | |
2240 | * pci_enable_ltr - enable latency tolerance reporting | |
2241 | * @dev: PCI device | |
2242 | * | |
2243 | * Enable LTR on @dev if possible, which means enabling it first on | |
2244 | * upstream ports. | |
2245 | * | |
2246 | * RETURNS: | |
2247 | * Zero on success, errno on failure. | |
2248 | */ | |
2249 | int pci_enable_ltr(struct pci_dev *dev) | |
2250 | { | |
51c2e0a7 JB |
2251 | int ret; |
2252 | ||
51c2e0a7 JB |
2253 | /* Only primary function can enable/disable LTR */ |
2254 | if (PCI_FUNC(dev->devfn) != 0) | |
2255 | return -EINVAL; | |
2256 | ||
59875ae4 JL |
2257 | if (!pci_ltr_supported(dev)) |
2258 | return -ENOTSUPP; | |
2259 | ||
51c2e0a7 | 2260 | /* Enable upstream ports first */ |
8291550f | 2261 | if (dev->bus->self) { |
51c2e0a7 JB |
2262 | ret = pci_enable_ltr(dev->bus->self); |
2263 | if (ret) | |
2264 | return ret; | |
2265 | } | |
2266 | ||
d2ab1fa6 BH |
2267 | return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, |
2268 | PCI_EXP_DEVCTL2_LTR_EN); | |
51c2e0a7 JB |
2269 | } |
2270 | EXPORT_SYMBOL(pci_enable_ltr); | |
2271 | ||
2272 | /** | |
2273 | * pci_disable_ltr - disable latency tolerance reporting | |
2274 | * @dev: PCI device | |
2275 | */ | |
2276 | void pci_disable_ltr(struct pci_dev *dev) | |
2277 | { | |
51c2e0a7 JB |
2278 | /* Only primary function can enable/disable LTR */ |
2279 | if (PCI_FUNC(dev->devfn) != 0) | |
2280 | return; | |
2281 | ||
59875ae4 JL |
2282 | if (!pci_ltr_supported(dev)) |
2283 | return; | |
2284 | ||
d2ab1fa6 BH |
2285 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, |
2286 | PCI_EXP_DEVCTL2_LTR_EN); | |
51c2e0a7 JB |
2287 | } |
2288 | EXPORT_SYMBOL(pci_disable_ltr); | |
2289 | ||
2290 | static int __pci_ltr_scale(int *val) | |
2291 | { | |
2292 | int scale = 0; | |
2293 | ||
2294 | while (*val > 1023) { | |
2295 | *val = (*val + 31) / 32; | |
2296 | scale++; | |
2297 | } | |
2298 | return scale; | |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * pci_set_ltr - set LTR latency values | |
2303 | * @dev: PCI device | |
2304 | * @snoop_lat_ns: snoop latency in nanoseconds | |
2305 | * @nosnoop_lat_ns: nosnoop latency in nanoseconds | |
2306 | * | |
2307 | * Figure out the scale and set the LTR values accordingly. | |
2308 | */ | |
2309 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) | |
2310 | { | |
2311 | int pos, ret, snoop_scale, nosnoop_scale; | |
2312 | u16 val; | |
2313 | ||
2314 | if (!pci_ltr_supported(dev)) | |
2315 | return -ENOTSUPP; | |
2316 | ||
2317 | snoop_scale = __pci_ltr_scale(&snoop_lat_ns); | |
2318 | nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); | |
2319 | ||
2320 | if (snoop_lat_ns > PCI_LTR_VALUE_MASK || | |
2321 | nosnoop_lat_ns > PCI_LTR_VALUE_MASK) | |
2322 | return -EINVAL; | |
2323 | ||
2324 | if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || | |
2325 | (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) | |
2326 | return -EINVAL; | |
2327 | ||
2328 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
2329 | if (!pos) | |
2330 | return -ENOTSUPP; | |
2331 | ||
2332 | val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; | |
2333 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); | |
2334 | if (ret != 4) | |
2335 | return -EIO; | |
2336 | ||
2337 | val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; | |
2338 | ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); | |
2339 | if (ret != 4) | |
2340 | return -EIO; | |
2341 | ||
2342 | return 0; | |
2343 | } | |
2344 | EXPORT_SYMBOL(pci_set_ltr); | |
2345 | ||
5d990b62 CW |
2346 | static int pci_acs_enable; |
2347 | ||
2348 | /** | |
2349 | * pci_request_acs - ask for ACS to be enabled if supported | |
2350 | */ | |
2351 | void pci_request_acs(void) | |
2352 | { | |
2353 | pci_acs_enable = 1; | |
2354 | } | |
2355 | ||
ae21ee65 AK |
2356 | /** |
2357 | * pci_enable_acs - enable ACS if hardware support it | |
2358 | * @dev: the PCI device | |
2359 | */ | |
2360 | void pci_enable_acs(struct pci_dev *dev) | |
2361 | { | |
2362 | int pos; | |
2363 | u16 cap; | |
2364 | u16 ctrl; | |
2365 | ||
5d990b62 CW |
2366 | if (!pci_acs_enable) |
2367 | return; | |
2368 | ||
ae21ee65 AK |
2369 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2370 | if (!pos) | |
2371 | return; | |
2372 | ||
2373 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2374 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2375 | ||
2376 | /* Source Validation */ | |
2377 | ctrl |= (cap & PCI_ACS_SV); | |
2378 | ||
2379 | /* P2P Request Redirect */ | |
2380 | ctrl |= (cap & PCI_ACS_RR); | |
2381 | ||
2382 | /* P2P Completion Redirect */ | |
2383 | ctrl |= (cap & PCI_ACS_CR); | |
2384 | ||
2385 | /* Upstream Forwarding */ | |
2386 | ctrl |= (cap & PCI_ACS_UF); | |
2387 | ||
2388 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2389 | } | |
2390 | ||
0a67119f AW |
2391 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2392 | { | |
2393 | int pos; | |
83db7e0b | 2394 | u16 cap, ctrl; |
0a67119f AW |
2395 | |
2396 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2397 | if (!pos) | |
2398 | return false; | |
2399 | ||
83db7e0b AW |
2400 | /* |
2401 | * Except for egress control, capabilities are either required | |
2402 | * or only required if controllable. Features missing from the | |
2403 | * capability field can therefore be assumed as hard-wired enabled. | |
2404 | */ | |
2405 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2406 | acs_flags &= (cap | PCI_ACS_EC); | |
2407 | ||
0a67119f AW |
2408 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2409 | return (ctrl & acs_flags) == acs_flags; | |
2410 | } | |
2411 | ||
ad805758 AW |
2412 | /** |
2413 | * pci_acs_enabled - test ACS against required flags for a given device | |
2414 | * @pdev: device to test | |
2415 | * @acs_flags: required PCI ACS flags | |
2416 | * | |
2417 | * Return true if the device supports the provided flags. Automatically | |
2418 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2419 | * |
2420 | * Note that this interface checks the effective ACS capabilities of the | |
2421 | * device rather than the actual capabilities. For instance, most single | |
2422 | * function endpoints are not required to support ACS because they have no | |
2423 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2424 | * regardless of whether the device exposes an ACS capability. This makes | |
2425 | * it much easier for callers of this function to ignore the actual type | |
2426 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2427 | */ |
2428 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2429 | { | |
0a67119f | 2430 | int ret; |
ad805758 AW |
2431 | |
2432 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2433 | if (ret >= 0) | |
2434 | return ret > 0; | |
2435 | ||
0a67119f AW |
2436 | /* |
2437 | * Conventional PCI and PCI-X devices never support ACS, either | |
2438 | * effectively or actually. The shared bus topology implies that | |
2439 | * any device on the bus can receive or snoop DMA. | |
2440 | */ | |
ad805758 AW |
2441 | if (!pci_is_pcie(pdev)) |
2442 | return false; | |
2443 | ||
0a67119f AW |
2444 | switch (pci_pcie_type(pdev)) { |
2445 | /* | |
2446 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
2447 | * but since their primary inteface is PCI/X, we conservatively | |
2448 | * handle them as we would a non-PCIe device. | |
2449 | */ | |
2450 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2451 | /* | |
2452 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2453 | * applicable... must never implement an ACS Extended Capability...". | |
2454 | * This seems arbitrary, but we take a conservative interpretation | |
2455 | * of this statement. | |
2456 | */ | |
2457 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2458 | case PCI_EXP_TYPE_RC_EC: | |
2459 | return false; | |
2460 | /* | |
2461 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2462 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2463 | * regardless of whether they are single- or multi-function devices. | |
2464 | */ | |
2465 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2466 | case PCI_EXP_TYPE_ROOT_PORT: | |
2467 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2468 | /* | |
2469 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2470 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
2471 | * capabilities, but only when they are part of a multifunciton | |
2472 | * device. The footnote for section 6.12 indicates the specific | |
2473 | * PCIe types included here. | |
2474 | */ | |
2475 | case PCI_EXP_TYPE_ENDPOINT: | |
2476 | case PCI_EXP_TYPE_UPSTREAM: | |
2477 | case PCI_EXP_TYPE_LEG_END: | |
2478 | case PCI_EXP_TYPE_RC_END: | |
2479 | if (!pdev->multifunction) | |
2480 | break; | |
2481 | ||
0a67119f | 2482 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2483 | } |
2484 | ||
0a67119f AW |
2485 | /* |
2486 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable | |
2487 | * to single function devices with the exception of downstream ports. | |
2488 | */ | |
ad805758 AW |
2489 | return true; |
2490 | } | |
2491 | ||
2492 | /** | |
2493 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2494 | * @start: starting downstream device | |
2495 | * @end: ending upstream device or NULL to search to the root bus | |
2496 | * @acs_flags: required flags | |
2497 | * | |
2498 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2499 | * any step along the way does not support the required flags, return false. | |
2500 | */ | |
2501 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2502 | struct pci_dev *end, u16 acs_flags) | |
2503 | { | |
2504 | struct pci_dev *pdev, *parent = start; | |
2505 | ||
2506 | do { | |
2507 | pdev = parent; | |
2508 | ||
2509 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2510 | return false; | |
2511 | ||
2512 | if (pci_is_root_bus(pdev->bus)) | |
2513 | return (end == NULL); | |
2514 | ||
2515 | parent = pdev->bus->self; | |
2516 | } while (pdev != end); | |
2517 | ||
2518 | return true; | |
2519 | } | |
2520 | ||
57c2cf71 BH |
2521 | /** |
2522 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2523 | * @dev: the PCI device | |
bb5c2de2 | 2524 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2525 | * |
2526 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2527 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2528 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2529 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2530 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2531 | */ |
3df425f3 | 2532 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2533 | { |
46b952a3 MW |
2534 | int slot; |
2535 | ||
2536 | if (pci_ari_enabled(dev->bus)) | |
2537 | slot = 0; | |
2538 | else | |
2539 | slot = PCI_SLOT(dev->devfn); | |
2540 | ||
2541 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2542 | } |
2543 | ||
1da177e4 LT |
2544 | int |
2545 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
2546 | { | |
2547 | u8 pin; | |
2548 | ||
514d207d | 2549 | pin = dev->pin; |
1da177e4 LT |
2550 | if (!pin) |
2551 | return -1; | |
878f2e50 | 2552 | |
8784fd4d | 2553 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2554 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2555 | dev = dev->bus->self; |
2556 | } | |
2557 | *bridge = dev; | |
2558 | return pin; | |
2559 | } | |
2560 | ||
68feac87 BH |
2561 | /** |
2562 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2563 | * @dev: the PCI device | |
2564 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2565 | * | |
2566 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2567 | * bridges all the way up to a PCI root bus. | |
2568 | */ | |
2569 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2570 | { | |
2571 | u8 pin = *pinp; | |
2572 | ||
1eb39487 | 2573 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2574 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2575 | dev = dev->bus->self; | |
2576 | } | |
2577 | *pinp = pin; | |
2578 | return PCI_SLOT(dev->devfn); | |
2579 | } | |
2580 | ||
1da177e4 LT |
2581 | /** |
2582 | * pci_release_region - Release a PCI bar | |
2583 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2584 | * @bar: BAR to release | |
2585 | * | |
2586 | * Releases the PCI I/O and memory resources previously reserved by a | |
2587 | * successful call to pci_request_region. Call this function only | |
2588 | * after all use of the PCI regions has ceased. | |
2589 | */ | |
2590 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2591 | { | |
9ac7849e TH |
2592 | struct pci_devres *dr; |
2593 | ||
1da177e4 LT |
2594 | if (pci_resource_len(pdev, bar) == 0) |
2595 | return; | |
2596 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2597 | release_region(pci_resource_start(pdev, bar), | |
2598 | pci_resource_len(pdev, bar)); | |
2599 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2600 | release_mem_region(pci_resource_start(pdev, bar), | |
2601 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2602 | |
2603 | dr = find_pci_dr(pdev); | |
2604 | if (dr) | |
2605 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
2606 | } |
2607 | ||
2608 | /** | |
f5ddcac4 | 2609 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2610 | * @pdev: PCI device whose resources are to be reserved |
2611 | * @bar: BAR to be reserved | |
2612 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2613 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2614 | * |
2615 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2616 | * being reserved by owner @res_name. Do not access any | |
2617 | * address inside the PCI regions unless this call returns | |
2618 | * successfully. | |
2619 | * | |
f5ddcac4 RD |
2620 | * If @exclusive is set, then the region is marked so that userspace |
2621 | * is explicitly not allowed to map the resource via /dev/mem or | |
2622 | * sysfs MMIO access. | |
2623 | * | |
1da177e4 LT |
2624 | * Returns 0 on success, or %EBUSY on error. A warning |
2625 | * message is also printed on failure. | |
2626 | */ | |
e8de1481 AV |
2627 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
2628 | int exclusive) | |
1da177e4 | 2629 | { |
9ac7849e TH |
2630 | struct pci_devres *dr; |
2631 | ||
1da177e4 LT |
2632 | if (pci_resource_len(pdev, bar) == 0) |
2633 | return 0; | |
2634 | ||
2635 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
2636 | if (!request_region(pci_resource_start(pdev, bar), | |
2637 | pci_resource_len(pdev, bar), res_name)) | |
2638 | goto err_out; | |
2639 | } | |
2640 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
2641 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2642 | pci_resource_len(pdev, bar), res_name, | |
2643 | exclusive)) | |
1da177e4 LT |
2644 | goto err_out; |
2645 | } | |
9ac7849e TH |
2646 | |
2647 | dr = find_pci_dr(pdev); | |
2648 | if (dr) | |
2649 | dr->region_mask |= 1 << bar; | |
2650 | ||
1da177e4 LT |
2651 | return 0; |
2652 | ||
2653 | err_out: | |
c7dabef8 | 2654 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2655 | &pdev->resource[bar]); |
1da177e4 LT |
2656 | return -EBUSY; |
2657 | } | |
2658 | ||
e8de1481 | 2659 | /** |
f5ddcac4 | 2660 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2661 | * @pdev: PCI device whose resources are to be reserved |
2662 | * @bar: BAR to be reserved | |
f5ddcac4 | 2663 | * @res_name: Name to be associated with resource |
e8de1481 | 2664 | * |
f5ddcac4 | 2665 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2666 | * being reserved by owner @res_name. Do not access any |
2667 | * address inside the PCI regions unless this call returns | |
2668 | * successfully. | |
2669 | * | |
2670 | * Returns 0 on success, or %EBUSY on error. A warning | |
2671 | * message is also printed on failure. | |
2672 | */ | |
2673 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2674 | { | |
2675 | return __pci_request_region(pdev, bar, res_name, 0); | |
2676 | } | |
2677 | ||
2678 | /** | |
2679 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2680 | * @pdev: PCI device whose resources are to be reserved | |
2681 | * @bar: BAR to be reserved | |
2682 | * @res_name: Name to be associated with resource. | |
2683 | * | |
2684 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2685 | * being reserved by owner @res_name. Do not access any | |
2686 | * address inside the PCI regions unless this call returns | |
2687 | * successfully. | |
2688 | * | |
2689 | * Returns 0 on success, or %EBUSY on error. A warning | |
2690 | * message is also printed on failure. | |
2691 | * | |
2692 | * The key difference that _exclusive makes it that userspace is | |
2693 | * explicitly not allowed to map the resource via /dev/mem or | |
2694 | * sysfs. | |
2695 | */ | |
2696 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
2697 | { | |
2698 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2699 | } | |
c87deff7 HS |
2700 | /** |
2701 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2702 | * @pdev: PCI device whose resources were previously reserved | |
2703 | * @bars: Bitmask of BARs to be released | |
2704 | * | |
2705 | * Release selected PCI I/O and memory resources previously reserved. | |
2706 | * Call this function only after all use of the PCI regions has ceased. | |
2707 | */ | |
2708 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2709 | { | |
2710 | int i; | |
2711 | ||
2712 | for (i = 0; i < 6; i++) | |
2713 | if (bars & (1 << i)) | |
2714 | pci_release_region(pdev, i); | |
2715 | } | |
2716 | ||
9738abed | 2717 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
e8de1481 | 2718 | const char *res_name, int excl) |
c87deff7 HS |
2719 | { |
2720 | int i; | |
2721 | ||
2722 | for (i = 0; i < 6; i++) | |
2723 | if (bars & (1 << i)) | |
e8de1481 | 2724 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2725 | goto err_out; |
2726 | return 0; | |
2727 | ||
2728 | err_out: | |
2729 | while(--i >= 0) | |
2730 | if (bars & (1 << i)) | |
2731 | pci_release_region(pdev, i); | |
2732 | ||
2733 | return -EBUSY; | |
2734 | } | |
1da177e4 | 2735 | |
e8de1481 AV |
2736 | |
2737 | /** | |
2738 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2739 | * @pdev: PCI device whose resources are to be reserved | |
2740 | * @bars: Bitmask of BARs to be requested | |
2741 | * @res_name: Name to be associated with resource | |
2742 | */ | |
2743 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2744 | const char *res_name) | |
2745 | { | |
2746 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2747 | } | |
2748 | ||
2749 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
2750 | int bars, const char *res_name) | |
2751 | { | |
2752 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2753 | IORESOURCE_EXCLUSIVE); | |
2754 | } | |
2755 | ||
1da177e4 LT |
2756 | /** |
2757 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2758 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2759 | * | |
2760 | * Releases all PCI I/O and memory resources previously reserved by a | |
2761 | * successful call to pci_request_regions. Call this function only | |
2762 | * after all use of the PCI regions has ceased. | |
2763 | */ | |
2764 | ||
2765 | void pci_release_regions(struct pci_dev *pdev) | |
2766 | { | |
c87deff7 | 2767 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
2768 | } |
2769 | ||
2770 | /** | |
2771 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2772 | * @pdev: PCI device whose resources are to be reserved | |
2773 | * @res_name: Name to be associated with resource. | |
2774 | * | |
2775 | * Mark all PCI regions associated with PCI device @pdev as | |
2776 | * being reserved by owner @res_name. Do not access any | |
2777 | * address inside the PCI regions unless this call returns | |
2778 | * successfully. | |
2779 | * | |
2780 | * Returns 0 on success, or %EBUSY on error. A warning | |
2781 | * message is also printed on failure. | |
2782 | */ | |
3c990e92 | 2783 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2784 | { |
c87deff7 | 2785 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
2786 | } |
2787 | ||
e8de1481 AV |
2788 | /** |
2789 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2790 | * @pdev: PCI device whose resources are to be reserved | |
2791 | * @res_name: Name to be associated with resource. | |
2792 | * | |
2793 | * Mark all PCI regions associated with PCI device @pdev as | |
2794 | * being reserved by owner @res_name. Do not access any | |
2795 | * address inside the PCI regions unless this call returns | |
2796 | * successfully. | |
2797 | * | |
2798 | * pci_request_regions_exclusive() will mark the region so that | |
2799 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
2800 | * | |
2801 | * Returns 0 on success, or %EBUSY on error. A warning | |
2802 | * message is also printed on failure. | |
2803 | */ | |
2804 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2805 | { | |
2806 | return pci_request_selected_regions_exclusive(pdev, | |
2807 | ((1 << 6) - 1), res_name); | |
2808 | } | |
2809 | ||
6a479079 BH |
2810 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2811 | { | |
2812 | u16 old_cmd, cmd; | |
2813 | ||
2814 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2815 | if (enable) | |
2816 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2817 | else | |
2818 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2819 | if (cmd != old_cmd) { | |
2820 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2821 | enable ? "enabling" : "disabling"); | |
2822 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2823 | } | |
2824 | dev->is_busmaster = enable; | |
2825 | } | |
e8de1481 | 2826 | |
2b6f2c35 MS |
2827 | /** |
2828 | * pcibios_setup - process "pci=" kernel boot arguments | |
2829 | * @str: string used to pass in "pci=" kernel boot arguments | |
2830 | * | |
2831 | * Process kernel boot arguments. This is the default implementation. | |
2832 | * Architecture specific implementations can override this as necessary. | |
2833 | */ | |
2834 | char * __weak __init pcibios_setup(char *str) | |
2835 | { | |
2836 | return str; | |
2837 | } | |
2838 | ||
96c55900 MS |
2839 | /** |
2840 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2841 | * @dev: the PCI device to enable | |
2842 | * | |
2843 | * Enables PCI bus-mastering for the device. This is the default | |
2844 | * implementation. Architecture specific implementations can override | |
2845 | * this if necessary. | |
2846 | */ | |
2847 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2848 | { | |
2849 | u8 lat; | |
2850 | ||
f676678f MS |
2851 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2852 | if (pci_is_pcie(dev)) | |
2853 | return; | |
2854 | ||
96c55900 MS |
2855 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2856 | if (lat < 16) | |
2857 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2858 | else if (lat > pcibios_max_latency) | |
2859 | lat = pcibios_max_latency; | |
2860 | else | |
2861 | return; | |
a006482b | 2862 | |
96c55900 MS |
2863 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
2864 | } | |
2865 | ||
1da177e4 LT |
2866 | /** |
2867 | * pci_set_master - enables bus-mastering for device dev | |
2868 | * @dev: the PCI device to enable | |
2869 | * | |
2870 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2871 | * to do the needed arch specific settings. | |
2872 | */ | |
6a479079 | 2873 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2874 | { |
6a479079 | 2875 | __pci_set_master(dev, true); |
1da177e4 LT |
2876 | pcibios_set_master(dev); |
2877 | } | |
2878 | ||
6a479079 BH |
2879 | /** |
2880 | * pci_clear_master - disables bus-mastering for device dev | |
2881 | * @dev: the PCI device to disable | |
2882 | */ | |
2883 | void pci_clear_master(struct pci_dev *dev) | |
2884 | { | |
2885 | __pci_set_master(dev, false); | |
2886 | } | |
2887 | ||
1da177e4 | 2888 | /** |
edb2d97e MW |
2889 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2890 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2891 | * |
edb2d97e MW |
2892 | * Helper function for pci_set_mwi. |
2893 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2894 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2895 | * | |
2896 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2897 | */ | |
15ea76d4 | 2898 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2899 | { |
2900 | u8 cacheline_size; | |
2901 | ||
2902 | if (!pci_cache_line_size) | |
15ea76d4 | 2903 | return -EINVAL; |
1da177e4 LT |
2904 | |
2905 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2906 | equal to or multiple of the right value. */ | |
2907 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2908 | if (cacheline_size >= pci_cache_line_size && | |
2909 | (cacheline_size % pci_cache_line_size) == 0) | |
2910 | return 0; | |
2911 | ||
2912 | /* Write the correct value. */ | |
2913 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2914 | /* Read it back. */ | |
2915 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2916 | if (cacheline_size == pci_cache_line_size) | |
2917 | return 0; | |
2918 | ||
80ccba11 BH |
2919 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2920 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2921 | |
2922 | return -EINVAL; | |
2923 | } | |
15ea76d4 TH |
2924 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2925 | ||
2926 | #ifdef PCI_DISABLE_MWI | |
2927 | int pci_set_mwi(struct pci_dev *dev) | |
2928 | { | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | int pci_try_set_mwi(struct pci_dev *dev) | |
2933 | { | |
2934 | return 0; | |
2935 | } | |
2936 | ||
2937 | void pci_clear_mwi(struct pci_dev *dev) | |
2938 | { | |
2939 | } | |
2940 | ||
2941 | #else | |
1da177e4 LT |
2942 | |
2943 | /** | |
2944 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2945 | * @dev: the PCI device for which MWI is enabled | |
2946 | * | |
694625c0 | 2947 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2948 | * |
2949 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2950 | */ | |
2951 | int | |
2952 | pci_set_mwi(struct pci_dev *dev) | |
2953 | { | |
2954 | int rc; | |
2955 | u16 cmd; | |
2956 | ||
edb2d97e | 2957 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2958 | if (rc) |
2959 | return rc; | |
2960 | ||
2961 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2962 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2963 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2964 | cmd |= PCI_COMMAND_INVALIDATE; |
2965 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2966 | } | |
2967 | ||
2968 | return 0; | |
2969 | } | |
2970 | ||
694625c0 RD |
2971 | /** |
2972 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2973 | * @dev: the PCI device for which MWI is enabled | |
2974 | * | |
2975 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2976 | * Callers are not required to check the return value. | |
2977 | * | |
2978 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2979 | */ | |
2980 | int pci_try_set_mwi(struct pci_dev *dev) | |
2981 | { | |
2982 | int rc = pci_set_mwi(dev); | |
2983 | return rc; | |
2984 | } | |
2985 | ||
1da177e4 LT |
2986 | /** |
2987 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2988 | * @dev: the PCI device to disable | |
2989 | * | |
2990 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2991 | */ | |
2992 | void | |
2993 | pci_clear_mwi(struct pci_dev *dev) | |
2994 | { | |
2995 | u16 cmd; | |
2996 | ||
2997 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2998 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2999 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
3000 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3001 | } | |
3002 | } | |
edb2d97e | 3003 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 3004 | |
a04ce0ff BR |
3005 | /** |
3006 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
3007 | * @pdev: the PCI device to operate on |
3008 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
3009 | * |
3010 | * Enables/disables PCI INTx for device dev | |
3011 | */ | |
3012 | void | |
3013 | pci_intx(struct pci_dev *pdev, int enable) | |
3014 | { | |
3015 | u16 pci_command, new; | |
3016 | ||
3017 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
3018 | ||
3019 | if (enable) { | |
3020 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
3021 | } else { | |
3022 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
3023 | } | |
3024 | ||
3025 | if (new != pci_command) { | |
9ac7849e TH |
3026 | struct pci_devres *dr; |
3027 | ||
2fd9d74b | 3028 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
3029 | |
3030 | dr = find_pci_dr(pdev); | |
3031 | if (dr && !dr->restore_intx) { | |
3032 | dr->restore_intx = 1; | |
3033 | dr->orig_intx = !enable; | |
3034 | } | |
a04ce0ff BR |
3035 | } |
3036 | } | |
3037 | ||
a2e27787 JK |
3038 | /** |
3039 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 3040 | * @dev: the PCI device to operate on |
a2e27787 JK |
3041 | * |
3042 | * Check if the device dev support INTx masking via the config space | |
3043 | * command word. | |
3044 | */ | |
3045 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
3046 | { | |
3047 | bool mask_supported = false; | |
3048 | u16 orig, new; | |
3049 | ||
fbebb9fd BH |
3050 | if (dev->broken_intx_masking) |
3051 | return false; | |
3052 | ||
a2e27787 JK |
3053 | pci_cfg_access_lock(dev); |
3054 | ||
3055 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
3056 | pci_write_config_word(dev, PCI_COMMAND, | |
3057 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
3058 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
3059 | ||
3060 | /* | |
3061 | * There's no way to protect against hardware bugs or detect them | |
3062 | * reliably, but as long as we know what the value should be, let's | |
3063 | * go ahead and check it. | |
3064 | */ | |
3065 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
3066 | dev_err(&dev->dev, "Command register changed from " | |
3067 | "0x%x to 0x%x: driver or hardware bug?\n", orig, new); | |
3068 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { | |
3069 | mask_supported = true; | |
3070 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
3071 | } | |
3072 | ||
3073 | pci_cfg_access_unlock(dev); | |
3074 | return mask_supported; | |
3075 | } | |
3076 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
3077 | ||
3078 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
3079 | { | |
3080 | struct pci_bus *bus = dev->bus; | |
3081 | bool mask_updated = true; | |
3082 | u32 cmd_status_dword; | |
3083 | u16 origcmd, newcmd; | |
3084 | unsigned long flags; | |
3085 | bool irq_pending; | |
3086 | ||
3087 | /* | |
3088 | * We do a single dword read to retrieve both command and status. | |
3089 | * Document assumptions that make this possible. | |
3090 | */ | |
3091 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3092 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3093 | ||
3094 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3095 | ||
3096 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3097 | ||
3098 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3099 | ||
3100 | /* | |
3101 | * Check interrupt status register to see whether our device | |
3102 | * triggered the interrupt (when masking) or the next IRQ is | |
3103 | * already pending (when unmasking). | |
3104 | */ | |
3105 | if (mask != irq_pending) { | |
3106 | mask_updated = false; | |
3107 | goto done; | |
3108 | } | |
3109 | ||
3110 | origcmd = cmd_status_dword; | |
3111 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3112 | if (mask) | |
3113 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3114 | if (newcmd != origcmd) | |
3115 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3116 | ||
3117 | done: | |
3118 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3119 | ||
3120 | return mask_updated; | |
3121 | } | |
3122 | ||
3123 | /** | |
3124 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3125 | * @dev: the PCI device to operate on |
a2e27787 JK |
3126 | * |
3127 | * Check if the device dev has its INTx line asserted, mask it and | |
3128 | * return true in that case. False is returned if not interrupt was | |
3129 | * pending. | |
3130 | */ | |
3131 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3132 | { | |
3133 | return pci_check_and_set_intx_mask(dev, true); | |
3134 | } | |
3135 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3136 | ||
3137 | /** | |
3138 | * pci_check_and_mask_intx - unmask INTx of no interrupt is pending | |
6e9292c5 | 3139 | * @dev: the PCI device to operate on |
a2e27787 JK |
3140 | * |
3141 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3142 | * and return true. False is returned and the mask remains active if | |
3143 | * there was still an interrupt pending. | |
3144 | */ | |
3145 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3146 | { | |
3147 | return pci_check_and_set_intx_mask(dev, false); | |
3148 | } | |
3149 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3150 | ||
f5f2b131 | 3151 | /** |
da27f4b3 | 3152 | * pci_msi_off - disables any MSI or MSI-X capabilities |
8d7d86e9 | 3153 | * @dev: the PCI device to operate on |
f5f2b131 | 3154 | * |
da27f4b3 BH |
3155 | * If you want to use MSI, see pci_enable_msi() and friends. |
3156 | * This is a lower-level primitive that allows us to disable | |
3157 | * MSI operation at the device level. | |
f5f2b131 EB |
3158 | */ |
3159 | void pci_msi_off(struct pci_dev *dev) | |
3160 | { | |
3161 | int pos; | |
3162 | u16 control; | |
3163 | ||
da27f4b3 BH |
3164 | /* |
3165 | * This looks like it could go in msi.c, but we need it even when | |
3166 | * CONFIG_PCI_MSI=n. For the same reason, we can't use | |
3167 | * dev->msi_cap or dev->msix_cap here. | |
3168 | */ | |
f5f2b131 EB |
3169 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
3170 | if (pos) { | |
3171 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3172 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3173 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3174 | } | |
3175 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3176 | if (pos) { | |
3177 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3178 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3179 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3180 | } | |
3181 | } | |
b03214d5 | 3182 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3183 | |
4d57cdfa FT |
3184 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3185 | { | |
3186 | return dma_set_max_seg_size(&dev->dev, size); | |
3187 | } | |
3188 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3189 | |
59fc67de FT |
3190 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3191 | { | |
3192 | return dma_set_seg_boundary(&dev->dev, mask); | |
3193 | } | |
3194 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3195 | |
3775a209 CL |
3196 | /** |
3197 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3198 | * @dev: the PCI device to operate on | |
3199 | * | |
3200 | * Return 0 if transaction is pending 1 otherwise. | |
3201 | */ | |
3202 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3203 | { |
8c1c699f | 3204 | int i; |
59875ae4 | 3205 | u16 status; |
8c1c699f | 3206 | |
8dd7f803 | 3207 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
3208 | for (i = 0; i < 4; i++) { |
3209 | if (i) | |
3210 | msleep((1 << (i - 1)) * 100); | |
5fe5db05 | 3211 | |
59875ae4 | 3212 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); |
8c1c699f | 3213 | if (!(status & PCI_EXP_DEVSTA_TRPND)) |
3775a209 | 3214 | return 1; |
8c1c699f YZ |
3215 | } |
3216 | ||
3775a209 CL |
3217 | return 0; |
3218 | } | |
3219 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3220 | ||
3221 | static int pcie_flr(struct pci_dev *dev, int probe) | |
3222 | { | |
3223 | u32 cap; | |
3224 | ||
3225 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3226 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3227 | return -ENOTTY; | |
3228 | ||
3229 | if (probe) | |
3230 | return 0; | |
3231 | ||
3232 | if (!pci_wait_for_pending_transaction(dev)) | |
3233 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
8c1c699f | 3234 | |
59875ae4 | 3235 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
04b55c47 | 3236 | |
8c1c699f | 3237 | msleep(100); |
8dd7f803 | 3238 | |
8dd7f803 SY |
3239 | return 0; |
3240 | } | |
d91cdc74 | 3241 | |
8c1c699f | 3242 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3243 | { |
8c1c699f YZ |
3244 | int i; |
3245 | int pos; | |
1ca88797 | 3246 | u8 cap; |
8c1c699f | 3247 | u8 status; |
1ca88797 | 3248 | |
8c1c699f YZ |
3249 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3250 | if (!pos) | |
1ca88797 | 3251 | return -ENOTTY; |
8c1c699f YZ |
3252 | |
3253 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3254 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3255 | return -ENOTTY; | |
3256 | ||
3257 | if (probe) | |
3258 | return 0; | |
3259 | ||
1ca88797 | 3260 | /* Wait for Transaction Pending bit clean */ |
8c1c699f YZ |
3261 | for (i = 0; i < 4; i++) { |
3262 | if (i) | |
3263 | msleep((1 << (i - 1)) * 100); | |
3264 | ||
3265 | pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); | |
3266 | if (!(status & PCI_AF_STATUS_TP)) | |
3267 | goto clear; | |
3268 | } | |
5fe5db05 | 3269 | |
8c1c699f YZ |
3270 | dev_err(&dev->dev, "transaction is not cleared; " |
3271 | "proceeding with reset anyway\n"); | |
5fe5db05 | 3272 | |
8c1c699f YZ |
3273 | clear: |
3274 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 3275 | msleep(100); |
8c1c699f | 3276 | |
1ca88797 SY |
3277 | return 0; |
3278 | } | |
3279 | ||
83d74e03 RW |
3280 | /** |
3281 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3282 | * @dev: Device to reset. | |
3283 | * @probe: If set, only check if the device can be reset this way. | |
3284 | * | |
3285 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3286 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3287 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3288 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3289 | * | |
3290 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3291 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
3292 | * by devault (i.e. unless the @dev's d3_delay field has a different value). | |
3293 | * Moreover, only devices in D0 can be reset by this function. | |
3294 | */ | |
f85876ba | 3295 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3296 | { |
f85876ba YZ |
3297 | u16 csr; |
3298 | ||
3299 | if (!dev->pm_cap) | |
3300 | return -ENOTTY; | |
d91cdc74 | 3301 | |
f85876ba YZ |
3302 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3303 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3304 | return -ENOTTY; | |
d91cdc74 | 3305 | |
f85876ba YZ |
3306 | if (probe) |
3307 | return 0; | |
1ca88797 | 3308 | |
f85876ba YZ |
3309 | if (dev->current_state != PCI_D0) |
3310 | return -EINVAL; | |
3311 | ||
3312 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3313 | csr |= PCI_D3hot; | |
3314 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3315 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3316 | |
3317 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3318 | csr |= PCI_D0; | |
3319 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3320 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3321 | |
3322 | return 0; | |
3323 | } | |
3324 | ||
64e8674f AW |
3325 | /** |
3326 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3327 | * @dev: Bridge device | |
3328 | * | |
3329 | * Use the bridge control register to assert reset on the secondary bus. | |
3330 | * Devices on the secondary bus are left in power-on state. | |
3331 | */ | |
3332 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
c12ff1df YZ |
3333 | { |
3334 | u16 ctrl; | |
64e8674f AW |
3335 | |
3336 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3337 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3338 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3339 | /* |
3340 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
3341 | * this to 2ms to ensure that we meet the minium requirement. | |
3342 | */ | |
3343 | msleep(2); | |
64e8674f AW |
3344 | |
3345 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3346 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3347 | |
3348 | /* | |
3349 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3350 | * Assuming a minimum 33MHz clock this results in a 1s | |
3351 | * delay before we can consider subordinate devices to | |
3352 | * be re-initialized. PCIe has some ways to shorten this, | |
3353 | * but we don't make use of them yet. | |
3354 | */ | |
3355 | ssleep(1); | |
64e8674f AW |
3356 | } |
3357 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); | |
3358 | ||
3359 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3360 | { | |
c12ff1df YZ |
3361 | struct pci_dev *pdev; |
3362 | ||
654b75e0 | 3363 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
3364 | return -ENOTTY; |
3365 | ||
3366 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3367 | if (pdev != dev) | |
3368 | return -ENOTTY; | |
3369 | ||
3370 | if (probe) | |
3371 | return 0; | |
3372 | ||
64e8674f | 3373 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3374 | |
3375 | return 0; | |
3376 | } | |
3377 | ||
608c3881 AW |
3378 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3379 | { | |
3380 | int rc = -ENOTTY; | |
3381 | ||
3382 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3383 | return rc; | |
3384 | ||
3385 | if (hotplug->ops->reset_slot) | |
3386 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3387 | ||
3388 | module_put(hotplug->ops->owner); | |
3389 | ||
3390 | return rc; | |
3391 | } | |
3392 | ||
3393 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3394 | { | |
3395 | struct pci_dev *pdev; | |
3396 | ||
3397 | if (dev->subordinate || !dev->slot) | |
3398 | return -ENOTTY; | |
3399 | ||
3400 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3401 | if (pdev != dev && pdev->slot == dev->slot) | |
3402 | return -ENOTTY; | |
3403 | ||
3404 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3405 | } | |
3406 | ||
977f857c | 3407 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3408 | { |
8c1c699f YZ |
3409 | int rc; |
3410 | ||
3411 | might_sleep(); | |
3412 | ||
b9c3b266 DC |
3413 | rc = pci_dev_specific_reset(dev, probe); |
3414 | if (rc != -ENOTTY) | |
3415 | goto done; | |
3416 | ||
8c1c699f YZ |
3417 | rc = pcie_flr(dev, probe); |
3418 | if (rc != -ENOTTY) | |
3419 | goto done; | |
d91cdc74 | 3420 | |
8c1c699f | 3421 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3422 | if (rc != -ENOTTY) |
3423 | goto done; | |
3424 | ||
3425 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3426 | if (rc != -ENOTTY) |
3427 | goto done; | |
3428 | ||
608c3881 AW |
3429 | rc = pci_dev_reset_slot_function(dev, probe); |
3430 | if (rc != -ENOTTY) | |
3431 | goto done; | |
3432 | ||
c12ff1df | 3433 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3434 | done: |
977f857c KRW |
3435 | return rc; |
3436 | } | |
3437 | ||
77cb985a AW |
3438 | static void pci_dev_lock(struct pci_dev *dev) |
3439 | { | |
3440 | pci_cfg_access_lock(dev); | |
3441 | /* block PM suspend, driver probe, etc. */ | |
3442 | device_lock(&dev->dev); | |
3443 | } | |
3444 | ||
3445 | static void pci_dev_unlock(struct pci_dev *dev) | |
3446 | { | |
3447 | device_unlock(&dev->dev); | |
3448 | pci_cfg_access_unlock(dev); | |
3449 | } | |
3450 | ||
3451 | static void pci_dev_save_and_disable(struct pci_dev *dev) | |
3452 | { | |
a6cbaade AW |
3453 | /* |
3454 | * Wake-up device prior to save. PM registers default to D0 after | |
3455 | * reset and a simple register restore doesn't reliably return | |
3456 | * to a non-D0 state anyway. | |
3457 | */ | |
3458 | pci_set_power_state(dev, PCI_D0); | |
3459 | ||
77cb985a AW |
3460 | pci_save_state(dev); |
3461 | /* | |
3462 | * Disable the device by clearing the Command register, except for | |
3463 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
3464 | * BARs, but also prevents the device from being Bus Master, preventing | |
3465 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
3466 | * compliant devices, INTx-disable prevents legacy interrupts. | |
3467 | */ | |
3468 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
3469 | } | |
3470 | ||
3471 | static void pci_dev_restore(struct pci_dev *dev) | |
3472 | { | |
3473 | pci_restore_state(dev); | |
3474 | } | |
3475 | ||
977f857c KRW |
3476 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
3477 | { | |
3478 | int rc; | |
3479 | ||
77cb985a AW |
3480 | if (!probe) |
3481 | pci_dev_lock(dev); | |
977f857c KRW |
3482 | |
3483 | rc = __pci_dev_reset(dev, probe); | |
3484 | ||
77cb985a AW |
3485 | if (!probe) |
3486 | pci_dev_unlock(dev); | |
3487 | ||
8c1c699f | 3488 | return rc; |
d91cdc74 | 3489 | } |
d91cdc74 | 3490 | /** |
8c1c699f YZ |
3491 | * __pci_reset_function - reset a PCI device function |
3492 | * @dev: PCI device to reset | |
d91cdc74 SY |
3493 | * |
3494 | * Some devices allow an individual function to be reset without affecting | |
3495 | * other functions in the same device. The PCI device must be responsive | |
3496 | * to PCI config space in order to use this function. | |
3497 | * | |
3498 | * The device function is presumed to be unused when this function is called. | |
3499 | * Resetting the device will make the contents of PCI configuration space | |
3500 | * random, so any caller of this must be prepared to reinitialise the | |
3501 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3502 | * etc. | |
3503 | * | |
8c1c699f | 3504 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3505 | * device doesn't support resetting a single function. |
3506 | */ | |
8c1c699f | 3507 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3508 | { |
8c1c699f | 3509 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3510 | } |
8c1c699f | 3511 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3512 | |
6fbf9e7a KRW |
3513 | /** |
3514 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3515 | * the @dev mutex lock. | |
3516 | * @dev: PCI device to reset | |
3517 | * | |
3518 | * Some devices allow an individual function to be reset without affecting | |
3519 | * other functions in the same device. The PCI device must be responsive | |
3520 | * to PCI config space in order to use this function. | |
3521 | * | |
3522 | * The device function is presumed to be unused and the caller is holding | |
3523 | * the device mutex lock when this function is called. | |
3524 | * Resetting the device will make the contents of PCI configuration space | |
3525 | * random, so any caller of this must be prepared to reinitialise the | |
3526 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3527 | * etc. | |
3528 | * | |
3529 | * Returns 0 if the device function was successfully reset or negative if the | |
3530 | * device doesn't support resetting a single function. | |
3531 | */ | |
3532 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3533 | { | |
977f857c | 3534 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3535 | } |
3536 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3537 | ||
711d5779 MT |
3538 | /** |
3539 | * pci_probe_reset_function - check whether the device can be safely reset | |
3540 | * @dev: PCI device to reset | |
3541 | * | |
3542 | * Some devices allow an individual function to be reset without affecting | |
3543 | * other functions in the same device. The PCI device must be responsive | |
3544 | * to PCI config space in order to use this function. | |
3545 | * | |
3546 | * Returns 0 if the device function can be reset or negative if the | |
3547 | * device doesn't support resetting a single function. | |
3548 | */ | |
3549 | int pci_probe_reset_function(struct pci_dev *dev) | |
3550 | { | |
3551 | return pci_dev_reset(dev, 1); | |
3552 | } | |
3553 | ||
8dd7f803 | 3554 | /** |
8c1c699f YZ |
3555 | * pci_reset_function - quiesce and reset a PCI device function |
3556 | * @dev: PCI device to reset | |
8dd7f803 SY |
3557 | * |
3558 | * Some devices allow an individual function to be reset without affecting | |
3559 | * other functions in the same device. The PCI device must be responsive | |
3560 | * to PCI config space in order to use this function. | |
3561 | * | |
3562 | * This function does not just reset the PCI portion of a device, but | |
3563 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3564 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3565 | * over the reset. |
3566 | * | |
8c1c699f | 3567 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3568 | * device doesn't support resetting a single function. |
3569 | */ | |
3570 | int pci_reset_function(struct pci_dev *dev) | |
3571 | { | |
8c1c699f | 3572 | int rc; |
8dd7f803 | 3573 | |
8c1c699f YZ |
3574 | rc = pci_dev_reset(dev, 1); |
3575 | if (rc) | |
3576 | return rc; | |
8dd7f803 | 3577 | |
77cb985a | 3578 | pci_dev_save_and_disable(dev); |
8dd7f803 | 3579 | |
8c1c699f | 3580 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 3581 | |
77cb985a | 3582 | pci_dev_restore(dev); |
8dd7f803 | 3583 | |
8c1c699f | 3584 | return rc; |
8dd7f803 SY |
3585 | } |
3586 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3587 | ||
090a3c53 AW |
3588 | /* Lock devices from the top of the tree down */ |
3589 | static void pci_bus_lock(struct pci_bus *bus) | |
3590 | { | |
3591 | struct pci_dev *dev; | |
3592 | ||
3593 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3594 | pci_dev_lock(dev); | |
3595 | if (dev->subordinate) | |
3596 | pci_bus_lock(dev->subordinate); | |
3597 | } | |
3598 | } | |
3599 | ||
3600 | /* Unlock devices from the bottom of the tree up */ | |
3601 | static void pci_bus_unlock(struct pci_bus *bus) | |
3602 | { | |
3603 | struct pci_dev *dev; | |
3604 | ||
3605 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3606 | if (dev->subordinate) | |
3607 | pci_bus_unlock(dev->subordinate); | |
3608 | pci_dev_unlock(dev); | |
3609 | } | |
3610 | } | |
3611 | ||
3612 | /* Lock devices from the top of the tree down */ | |
3613 | static void pci_slot_lock(struct pci_slot *slot) | |
3614 | { | |
3615 | struct pci_dev *dev; | |
3616 | ||
3617 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3618 | if (!dev->slot || dev->slot != slot) | |
3619 | continue; | |
3620 | pci_dev_lock(dev); | |
3621 | if (dev->subordinate) | |
3622 | pci_bus_lock(dev->subordinate); | |
3623 | } | |
3624 | } | |
3625 | ||
3626 | /* Unlock devices from the bottom of the tree up */ | |
3627 | static void pci_slot_unlock(struct pci_slot *slot) | |
3628 | { | |
3629 | struct pci_dev *dev; | |
3630 | ||
3631 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3632 | if (!dev->slot || dev->slot != slot) | |
3633 | continue; | |
3634 | if (dev->subordinate) | |
3635 | pci_bus_unlock(dev->subordinate); | |
3636 | pci_dev_unlock(dev); | |
3637 | } | |
3638 | } | |
3639 | ||
3640 | /* Save and disable devices from the top of the tree down */ | |
3641 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
3642 | { | |
3643 | struct pci_dev *dev; | |
3644 | ||
3645 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3646 | pci_dev_save_and_disable(dev); | |
3647 | if (dev->subordinate) | |
3648 | pci_bus_save_and_disable(dev->subordinate); | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | /* | |
3653 | * Restore devices from top of the tree down - parent bridges need to be | |
3654 | * restored before we can get to subordinate devices. | |
3655 | */ | |
3656 | static void pci_bus_restore(struct pci_bus *bus) | |
3657 | { | |
3658 | struct pci_dev *dev; | |
3659 | ||
3660 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3661 | pci_dev_restore(dev); | |
3662 | if (dev->subordinate) | |
3663 | pci_bus_restore(dev->subordinate); | |
3664 | } | |
3665 | } | |
3666 | ||
3667 | /* Save and disable devices from the top of the tree down */ | |
3668 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
3669 | { | |
3670 | struct pci_dev *dev; | |
3671 | ||
3672 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3673 | if (!dev->slot || dev->slot != slot) | |
3674 | continue; | |
3675 | pci_dev_save_and_disable(dev); | |
3676 | if (dev->subordinate) | |
3677 | pci_bus_save_and_disable(dev->subordinate); | |
3678 | } | |
3679 | } | |
3680 | ||
3681 | /* | |
3682 | * Restore devices from top of the tree down - parent bridges need to be | |
3683 | * restored before we can get to subordinate devices. | |
3684 | */ | |
3685 | static void pci_slot_restore(struct pci_slot *slot) | |
3686 | { | |
3687 | struct pci_dev *dev; | |
3688 | ||
3689 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3690 | if (!dev->slot || dev->slot != slot) | |
3691 | continue; | |
3692 | pci_dev_restore(dev); | |
3693 | if (dev->subordinate) | |
3694 | pci_bus_restore(dev->subordinate); | |
3695 | } | |
3696 | } | |
3697 | ||
3698 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
3699 | { | |
3700 | int rc; | |
3701 | ||
3702 | if (!slot) | |
3703 | return -ENOTTY; | |
3704 | ||
3705 | if (!probe) | |
3706 | pci_slot_lock(slot); | |
3707 | ||
3708 | might_sleep(); | |
3709 | ||
3710 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
3711 | ||
3712 | if (!probe) | |
3713 | pci_slot_unlock(slot); | |
3714 | ||
3715 | return rc; | |
3716 | } | |
3717 | ||
9a3d2b9b AW |
3718 | /** |
3719 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
3720 | * @slot: PCI slot to probe | |
3721 | * | |
3722 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
3723 | */ | |
3724 | int pci_probe_reset_slot(struct pci_slot *slot) | |
3725 | { | |
3726 | return pci_slot_reset(slot, 1); | |
3727 | } | |
3728 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
3729 | ||
090a3c53 AW |
3730 | /** |
3731 | * pci_reset_slot - reset a PCI slot | |
3732 | * @slot: PCI slot to reset | |
3733 | * | |
3734 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
3735 | * independent of other slots. For instance, some slots may support slot power | |
3736 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
3737 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
3738 | * Generally a slot reset should be attempted before a bus reset. All of the | |
3739 | * function of the slot and any subordinate buses behind the slot are reset | |
3740 | * through this function. PCI config space of all devices in the slot and | |
3741 | * behind the slot is saved before and restored after reset. | |
3742 | * | |
3743 | * Return 0 on success, non-zero on error. | |
3744 | */ | |
3745 | int pci_reset_slot(struct pci_slot *slot) | |
3746 | { | |
3747 | int rc; | |
3748 | ||
3749 | rc = pci_slot_reset(slot, 1); | |
3750 | if (rc) | |
3751 | return rc; | |
3752 | ||
3753 | pci_slot_save_and_disable(slot); | |
3754 | ||
3755 | rc = pci_slot_reset(slot, 0); | |
3756 | ||
3757 | pci_slot_restore(slot); | |
3758 | ||
3759 | return rc; | |
3760 | } | |
3761 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
3762 | ||
3763 | static int pci_bus_reset(struct pci_bus *bus, int probe) | |
3764 | { | |
3765 | if (!bus->self) | |
3766 | return -ENOTTY; | |
3767 | ||
3768 | if (probe) | |
3769 | return 0; | |
3770 | ||
3771 | pci_bus_lock(bus); | |
3772 | ||
3773 | might_sleep(); | |
3774 | ||
3775 | pci_reset_bridge_secondary_bus(bus->self); | |
3776 | ||
3777 | pci_bus_unlock(bus); | |
3778 | ||
3779 | return 0; | |
3780 | } | |
3781 | ||
9a3d2b9b AW |
3782 | /** |
3783 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
3784 | * @bus: PCI bus to probe | |
3785 | * | |
3786 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
3787 | */ | |
3788 | int pci_probe_reset_bus(struct pci_bus *bus) | |
3789 | { | |
3790 | return pci_bus_reset(bus, 1); | |
3791 | } | |
3792 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
3793 | ||
090a3c53 AW |
3794 | /** |
3795 | * pci_reset_bus - reset a PCI bus | |
3796 | * @bus: top level PCI bus to reset | |
3797 | * | |
3798 | * Do a bus reset on the given bus and any subordinate buses, saving | |
3799 | * and restoring state of all devices. | |
3800 | * | |
3801 | * Return 0 on success, non-zero on error. | |
3802 | */ | |
3803 | int pci_reset_bus(struct pci_bus *bus) | |
3804 | { | |
3805 | int rc; | |
3806 | ||
3807 | rc = pci_bus_reset(bus, 1); | |
3808 | if (rc) | |
3809 | return rc; | |
3810 | ||
3811 | pci_bus_save_and_disable(bus); | |
3812 | ||
3813 | rc = pci_bus_reset(bus, 0); | |
3814 | ||
3815 | pci_bus_restore(bus); | |
3816 | ||
3817 | return rc; | |
3818 | } | |
3819 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
3820 | ||
d556ad4b PO |
3821 | /** |
3822 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3823 | * @dev: PCI device to query | |
3824 | * | |
3825 | * Returns mmrbc: maximum designed memory read count in bytes | |
3826 | * or appropriate error value. | |
3827 | */ | |
3828 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3829 | { | |
7c9e2b1c | 3830 | int cap; |
d556ad4b PO |
3831 | u32 stat; |
3832 | ||
3833 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3834 | if (!cap) | |
3835 | return -EINVAL; | |
3836 | ||
7c9e2b1c | 3837 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3838 | return -EINVAL; |
3839 | ||
25daeb55 | 3840 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3841 | } |
3842 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3843 | ||
3844 | /** | |
3845 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3846 | * @dev: PCI device to query | |
3847 | * | |
3848 | * Returns mmrbc: maximum memory read count in bytes | |
3849 | * or appropriate error value. | |
3850 | */ | |
3851 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3852 | { | |
7c9e2b1c | 3853 | int cap; |
bdc2bda7 | 3854 | u16 cmd; |
d556ad4b PO |
3855 | |
3856 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3857 | if (!cap) | |
3858 | return -EINVAL; | |
3859 | ||
7c9e2b1c DN |
3860 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3861 | return -EINVAL; | |
d556ad4b | 3862 | |
7c9e2b1c | 3863 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
3864 | } |
3865 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
3866 | ||
3867 | /** | |
3868 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
3869 | * @dev: PCI device to query | |
3870 | * @mmrbc: maximum memory read count in bytes | |
3871 | * valid values are 512, 1024, 2048, 4096 | |
3872 | * | |
3873 | * If possible sets maximum memory read byte count, some bridges have erratas | |
3874 | * that prevent this. | |
3875 | */ | |
3876 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
3877 | { | |
7c9e2b1c | 3878 | int cap; |
bdc2bda7 DN |
3879 | u32 stat, v, o; |
3880 | u16 cmd; | |
d556ad4b | 3881 | |
229f5afd | 3882 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 3883 | return -EINVAL; |
d556ad4b PO |
3884 | |
3885 | v = ffs(mmrbc) - 10; | |
3886 | ||
3887 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3888 | if (!cap) | |
7c9e2b1c | 3889 | return -EINVAL; |
d556ad4b | 3890 | |
7c9e2b1c DN |
3891 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
3892 | return -EINVAL; | |
d556ad4b PO |
3893 | |
3894 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
3895 | return -E2BIG; | |
3896 | ||
7c9e2b1c DN |
3897 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3898 | return -EINVAL; | |
d556ad4b PO |
3899 | |
3900 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
3901 | if (o != v) { | |
809a3bf9 | 3902 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
3903 | return -EIO; |
3904 | ||
3905 | cmd &= ~PCI_X_CMD_MAX_READ; | |
3906 | cmd |= v << 2; | |
7c9e2b1c DN |
3907 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
3908 | return -EIO; | |
d556ad4b | 3909 | } |
7c9e2b1c | 3910 | return 0; |
d556ad4b PO |
3911 | } |
3912 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
3913 | ||
3914 | /** | |
3915 | * pcie_get_readrq - get PCI Express read request size | |
3916 | * @dev: PCI device to query | |
3917 | * | |
3918 | * Returns maximum memory read request in bytes | |
3919 | * or appropriate error value. | |
3920 | */ | |
3921 | int pcie_get_readrq(struct pci_dev *dev) | |
3922 | { | |
d556ad4b PO |
3923 | u16 ctl; |
3924 | ||
59875ae4 | 3925 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 3926 | |
59875ae4 | 3927 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
3928 | } |
3929 | EXPORT_SYMBOL(pcie_get_readrq); | |
3930 | ||
3931 | /** | |
3932 | * pcie_set_readrq - set PCI Express maximum memory read request | |
3933 | * @dev: PCI device to query | |
42e61f4a | 3934 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
3935 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3936 | * | |
c9b378c7 | 3937 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
3938 | */ |
3939 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
3940 | { | |
59875ae4 | 3941 | u16 v; |
d556ad4b | 3942 | |
229f5afd | 3943 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 3944 | return -EINVAL; |
d556ad4b | 3945 | |
a1c473aa BH |
3946 | /* |
3947 | * If using the "performance" PCIe config, we clamp the | |
3948 | * read rq size to the max packet size to prevent the | |
3949 | * host bridge generating requests larger than we can | |
3950 | * cope with | |
3951 | */ | |
3952 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
3953 | int mps = pcie_get_mps(dev); | |
3954 | ||
a1c473aa BH |
3955 | if (mps < rq) |
3956 | rq = mps; | |
3957 | } | |
3958 | ||
3959 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 3960 | |
59875ae4 JL |
3961 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
3962 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
3963 | } |
3964 | EXPORT_SYMBOL(pcie_set_readrq); | |
3965 | ||
b03e7495 JM |
3966 | /** |
3967 | * pcie_get_mps - get PCI Express maximum payload size | |
3968 | * @dev: PCI device to query | |
3969 | * | |
3970 | * Returns maximum payload size in bytes | |
b03e7495 JM |
3971 | */ |
3972 | int pcie_get_mps(struct pci_dev *dev) | |
3973 | { | |
b03e7495 JM |
3974 | u16 ctl; |
3975 | ||
59875ae4 | 3976 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 3977 | |
59875ae4 | 3978 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 JM |
3979 | } |
3980 | ||
3981 | /** | |
3982 | * pcie_set_mps - set PCI Express maximum payload size | |
3983 | * @dev: PCI device to query | |
47c08f31 | 3984 | * @mps: maximum payload size in bytes |
b03e7495 JM |
3985 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3986 | * | |
3987 | * If possible sets maximum payload size | |
3988 | */ | |
3989 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
3990 | { | |
59875ae4 | 3991 | u16 v; |
b03e7495 JM |
3992 | |
3993 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 3994 | return -EINVAL; |
b03e7495 JM |
3995 | |
3996 | v = ffs(mps) - 8; | |
3997 | if (v > dev->pcie_mpss) | |
59875ae4 | 3998 | return -EINVAL; |
b03e7495 JM |
3999 | v <<= 5; |
4000 | ||
59875ae4 JL |
4001 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4002 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 JM |
4003 | } |
4004 | ||
81377c8d JK |
4005 | /** |
4006 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4007 | * @dev: PCI device to query | |
4008 | * @speed: storage for minimum speed | |
4009 | * @width: storage for minimum width | |
4010 | * | |
4011 | * This function will walk up the PCI device chain and determine the minimum | |
4012 | * link width and speed of the device. | |
4013 | */ | |
4014 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4015 | enum pcie_link_width *width) | |
4016 | { | |
4017 | int ret; | |
4018 | ||
4019 | *speed = PCI_SPEED_UNKNOWN; | |
4020 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4021 | ||
4022 | while (dev) { | |
4023 | u16 lnksta; | |
4024 | enum pci_bus_speed next_speed; | |
4025 | enum pcie_link_width next_width; | |
4026 | ||
4027 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4028 | if (ret) | |
4029 | return ret; | |
4030 | ||
4031 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4032 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4033 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4034 | ||
4035 | if (next_speed < *speed) | |
4036 | *speed = next_speed; | |
4037 | ||
4038 | if (next_width < *width) | |
4039 | *width = next_width; | |
4040 | ||
4041 | dev = dev->bus->self; | |
4042 | } | |
4043 | ||
4044 | return 0; | |
4045 | } | |
4046 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4047 | ||
c87deff7 HS |
4048 | /** |
4049 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4050 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4051 | * @flags: resource type mask to be selected |
4052 | * | |
4053 | * This helper routine makes bar mask from the type of resource. | |
4054 | */ | |
4055 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4056 | { | |
4057 | int i, bars = 0; | |
4058 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4059 | if (pci_resource_flags(dev, i) & flags) | |
4060 | bars |= (1 << i); | |
4061 | return bars; | |
4062 | } | |
4063 | ||
613e7ed6 YZ |
4064 | /** |
4065 | * pci_resource_bar - get position of the BAR associated with a resource | |
4066 | * @dev: the PCI device | |
4067 | * @resno: the resource number | |
4068 | * @type: the BAR type to be filled in | |
4069 | * | |
4070 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4071 | */ | |
4072 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4073 | { | |
d1b054da YZ |
4074 | int reg; |
4075 | ||
613e7ed6 YZ |
4076 | if (resno < PCI_ROM_RESOURCE) { |
4077 | *type = pci_bar_unknown; | |
4078 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4079 | } else if (resno == PCI_ROM_RESOURCE) { | |
4080 | *type = pci_bar_mem32; | |
4081 | return dev->rom_base_reg; | |
d1b054da YZ |
4082 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4083 | /* device specific resource */ | |
4084 | reg = pci_iov_resource_bar(dev, resno, type); | |
4085 | if (reg) | |
4086 | return reg; | |
613e7ed6 YZ |
4087 | } |
4088 | ||
865df576 | 4089 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4090 | return 0; |
4091 | } | |
4092 | ||
95a8b6ef MT |
4093 | /* Some architectures require additional programming to enable VGA */ |
4094 | static arch_set_vga_state_t arch_set_vga_state; | |
4095 | ||
4096 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4097 | { | |
4098 | arch_set_vga_state = func; /* NULL disables */ | |
4099 | } | |
4100 | ||
4101 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
7ad35cf2 | 4102 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4103 | { |
4104 | if (arch_set_vga_state) | |
4105 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4106 | flags); |
95a8b6ef MT |
4107 | return 0; |
4108 | } | |
4109 | ||
deb2d2ec BH |
4110 | /** |
4111 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4112 | * @dev: the PCI device |
4113 | * @decode: true = enable decoding, false = disable decoding | |
4114 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4115 | * @flags: traverse ancestors and change bridges |
3448a19d | 4116 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4117 | */ |
4118 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4119 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4120 | { |
4121 | struct pci_bus *bus; | |
4122 | struct pci_dev *bridge; | |
4123 | u16 cmd; | |
95a8b6ef | 4124 | int rc; |
deb2d2ec | 4125 | |
3448a19d | 4126 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4127 | |
95a8b6ef | 4128 | /* ARCH specific VGA enables */ |
3448a19d | 4129 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4130 | if (rc) |
4131 | return rc; | |
4132 | ||
3448a19d DA |
4133 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4134 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4135 | if (decode == true) | |
4136 | cmd |= command_bits; | |
4137 | else | |
4138 | cmd &= ~command_bits; | |
4139 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4140 | } | |
deb2d2ec | 4141 | |
3448a19d | 4142 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4143 | return 0; |
4144 | ||
4145 | bus = dev->bus; | |
4146 | while (bus) { | |
4147 | bridge = bus->self; | |
4148 | if (bridge) { | |
4149 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4150 | &cmd); | |
4151 | if (decode == true) | |
4152 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4153 | else | |
4154 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4155 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4156 | cmd); | |
4157 | } | |
4158 | bus = bus->parent; | |
4159 | } | |
4160 | return 0; | |
4161 | } | |
4162 | ||
32a9a682 YS |
4163 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4164 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4165 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4166 | |
4167 | /** | |
4168 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4169 | * @dev: the PCI device to get | |
4170 | * | |
4171 | * RETURNS: Resource alignment if it is specified. | |
4172 | * Zero if it is not specified. | |
4173 | */ | |
9738abed | 4174 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4175 | { |
4176 | int seg, bus, slot, func, align_order, count; | |
4177 | resource_size_t align = 0; | |
4178 | char *p; | |
4179 | ||
4180 | spin_lock(&resource_alignment_lock); | |
4181 | p = resource_alignment_param; | |
4182 | while (*p) { | |
4183 | count = 0; | |
4184 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4185 | p[count] == '@') { | |
4186 | p += count + 1; | |
4187 | } else { | |
4188 | align_order = -1; | |
4189 | } | |
4190 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4191 | &seg, &bus, &slot, &func, &count) != 4) { | |
4192 | seg = 0; | |
4193 | if (sscanf(p, "%x:%x.%x%n", | |
4194 | &bus, &slot, &func, &count) != 3) { | |
4195 | /* Invalid format */ | |
4196 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
4197 | p); | |
4198 | break; | |
4199 | } | |
4200 | } | |
4201 | p += count; | |
4202 | if (seg == pci_domain_nr(dev->bus) && | |
4203 | bus == dev->bus->number && | |
4204 | slot == PCI_SLOT(dev->devfn) && | |
4205 | func == PCI_FUNC(dev->devfn)) { | |
4206 | if (align_order == -1) { | |
4207 | align = PAGE_SIZE; | |
4208 | } else { | |
4209 | align = 1 << align_order; | |
4210 | } | |
4211 | /* Found */ | |
4212 | break; | |
4213 | } | |
4214 | if (*p != ';' && *p != ',') { | |
4215 | /* End of param or invalid format */ | |
4216 | break; | |
4217 | } | |
4218 | p++; | |
4219 | } | |
4220 | spin_unlock(&resource_alignment_lock); | |
4221 | return align; | |
4222 | } | |
4223 | ||
2069ecfb YL |
4224 | /* |
4225 | * This function disables memory decoding and releases memory resources | |
4226 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
4227 | * It also rounds up size to specified alignment. | |
4228 | * Later on, the kernel will assign page-aligned memory resource back | |
4229 | * to the device. | |
4230 | */ | |
4231 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
4232 | { | |
4233 | int i; | |
4234 | struct resource *r; | |
4235 | resource_size_t align, size; | |
4236 | u16 command; | |
4237 | ||
10c463a7 YL |
4238 | /* check if specified PCI is target device to reassign */ |
4239 | align = pci_specified_resource_alignment(dev); | |
4240 | if (!align) | |
2069ecfb YL |
4241 | return; |
4242 | ||
4243 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
4244 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
4245 | dev_warn(&dev->dev, | |
4246 | "Can't reassign resources to host bridge.\n"); | |
4247 | return; | |
4248 | } | |
4249 | ||
4250 | dev_info(&dev->dev, | |
4251 | "Disabling memory decoding and releasing memory resources.\n"); | |
4252 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
4253 | command &= ~PCI_COMMAND_MEMORY; | |
4254 | pci_write_config_word(dev, PCI_COMMAND, command); | |
4255 | ||
2069ecfb YL |
4256 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
4257 | r = &dev->resource[i]; | |
4258 | if (!(r->flags & IORESOURCE_MEM)) | |
4259 | continue; | |
4260 | size = resource_size(r); | |
4261 | if (size < align) { | |
4262 | size = align; | |
4263 | dev_info(&dev->dev, | |
4264 | "Rounding up size of resource #%d to %#llx.\n", | |
4265 | i, (unsigned long long)size); | |
4266 | } | |
4267 | r->end = size - 1; | |
4268 | r->start = 0; | |
4269 | } | |
4270 | /* Need to disable bridge's resource window, | |
4271 | * to enable the kernel to reassign new resource | |
4272 | * window later on. | |
4273 | */ | |
4274 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4275 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4276 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
4277 | r = &dev->resource[i]; | |
4278 | if (!(r->flags & IORESOURCE_MEM)) | |
4279 | continue; | |
4280 | r->end = resource_size(r) - 1; | |
4281 | r->start = 0; | |
4282 | } | |
4283 | pci_disable_bridge_window(dev); | |
4284 | } | |
4285 | } | |
4286 | ||
9738abed | 4287 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
4288 | { |
4289 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
4290 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
4291 | spin_lock(&resource_alignment_lock); | |
4292 | strncpy(resource_alignment_param, buf, count); | |
4293 | resource_alignment_param[count] = '\0'; | |
4294 | spin_unlock(&resource_alignment_lock); | |
4295 | return count; | |
4296 | } | |
4297 | ||
9738abed | 4298 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
4299 | { |
4300 | size_t count; | |
4301 | spin_lock(&resource_alignment_lock); | |
4302 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
4303 | spin_unlock(&resource_alignment_lock); | |
4304 | return count; | |
4305 | } | |
4306 | ||
4307 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
4308 | { | |
4309 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
4310 | } | |
4311 | ||
4312 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
4313 | const char *buf, size_t count) | |
4314 | { | |
4315 | return pci_set_resource_alignment_param(buf, count); | |
4316 | } | |
4317 | ||
4318 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
4319 | pci_resource_alignment_store); | |
4320 | ||
4321 | static int __init pci_resource_alignment_sysfs_init(void) | |
4322 | { | |
4323 | return bus_create_file(&pci_bus_type, | |
4324 | &bus_attr_resource_alignment); | |
4325 | } | |
4326 | ||
4327 | late_initcall(pci_resource_alignment_sysfs_init); | |
4328 | ||
15856ad5 | 4329 | static void pci_no_domains(void) |
32a2eea7 JG |
4330 | { |
4331 | #ifdef CONFIG_PCI_DOMAINS | |
4332 | pci_domains_supported = 0; | |
4333 | #endif | |
4334 | } | |
4335 | ||
0ef5f8f6 | 4336 | /** |
642c92da | 4337 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
4338 | * |
4339 | * Returns 1 if we can access PCI extended config space (offsets | |
4340 | * greater than 0xff). This is the default implementation. Architecture | |
4341 | * implementations can override this. | |
4342 | */ | |
642c92da | 4343 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
4344 | { |
4345 | return 1; | |
4346 | } | |
4347 | ||
2d1c8618 BH |
4348 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
4349 | { | |
4350 | } | |
4351 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
4352 | ||
ad04d31e | 4353 | static int __init pci_setup(char *str) |
1da177e4 LT |
4354 | { |
4355 | while (str) { | |
4356 | char *k = strchr(str, ','); | |
4357 | if (k) | |
4358 | *k++ = 0; | |
4359 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
4360 | if (!strcmp(str, "nomsi")) { |
4361 | pci_no_msi(); | |
7f785763 RD |
4362 | } else if (!strcmp(str, "noaer")) { |
4363 | pci_no_aer(); | |
b55438fd YL |
4364 | } else if (!strncmp(str, "realloc=", 8)) { |
4365 | pci_realloc_get_opt(str + 8); | |
f483d392 | 4366 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 4367 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
4368 | } else if (!strcmp(str, "nodomains")) { |
4369 | pci_no_domains(); | |
6748dcc2 RW |
4370 | } else if (!strncmp(str, "noari", 5)) { |
4371 | pcie_ari_disabled = true; | |
4516a618 AN |
4372 | } else if (!strncmp(str, "cbiosize=", 9)) { |
4373 | pci_cardbus_io_size = memparse(str + 9, &str); | |
4374 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
4375 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
4376 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
4377 | pci_set_resource_alignment_param(str + 19, | |
4378 | strlen(str + 19)); | |
43c16408 AP |
4379 | } else if (!strncmp(str, "ecrc=", 5)) { |
4380 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
4381 | } else if (!strncmp(str, "hpiosize=", 9)) { |
4382 | pci_hotplug_io_size = memparse(str + 9, &str); | |
4383 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
4384 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
4385 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
4386 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
4387 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
4388 | pcie_bus_config = PCIE_BUS_SAFE; | |
4389 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
4390 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
4391 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
4392 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
4393 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
4394 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
4395 | } else { |
4396 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
4397 | str); | |
4398 | } | |
1da177e4 LT |
4399 | } |
4400 | str = k; | |
4401 | } | |
0637a70a | 4402 | return 0; |
1da177e4 | 4403 | } |
0637a70a | 4404 | early_param("pci", pci_setup); |
1da177e4 | 4405 | |
0b62e13b | 4406 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
4407 | EXPORT_SYMBOL(pci_enable_device_io); |
4408 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 4409 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
4410 | EXPORT_SYMBOL(pcim_enable_device); |
4411 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 4412 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
4413 | EXPORT_SYMBOL(pci_find_capability); |
4414 | EXPORT_SYMBOL(pci_bus_find_capability); | |
4415 | EXPORT_SYMBOL(pci_release_regions); | |
4416 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 4417 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
4418 | EXPORT_SYMBOL(pci_release_region); |
4419 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 4420 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
4421 | EXPORT_SYMBOL(pci_release_selected_regions); |
4422 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 4423 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 4424 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 4425 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 4426 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 4427 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 4428 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 4429 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 LT |
4430 | EXPORT_SYMBOL(pci_assign_resource); |
4431 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 4432 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
4433 | |
4434 | EXPORT_SYMBOL(pci_set_power_state); | |
4435 | EXPORT_SYMBOL(pci_save_state); | |
4436 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 4437 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 4438 | EXPORT_SYMBOL(pci_pme_active); |
0235c4fc | 4439 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 4440 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
4441 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
4442 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 4443 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |