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PCI: Remove pci_find_parent_resource() use for allocation
[deliverable/linux.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
608c3881 25#include <linux/pci_hotplug.h>
284f5f9d 26#include <asm-generic/pci-bridge.h>
32a9a682 27#include <asm/setup.h>
bc56b9e0 28#include "pci.h"
1da177e4 29
00240c38
AS		 30const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32};
33EXPORT_SYMBOL_GPL(pci_power_names);
34
93177a74
RW		 35int isa_dma_bridge_buggy;
36EXPORT_SYMBOL(isa_dma_bridge_buggy);
37
38int pci_pci_problems;
39EXPORT_SYMBOL(pci_pci_problems);
40
1ae861e6
RW		 41unsigned int pci_pm_d3_delay;
42
df17e62e
MG		 43static void pci_pme_list_scan(struct work_struct *work);
44
45static LIST_HEAD(pci_pme_list);
46static DEFINE_MUTEX(pci_pme_list_mutex);
47static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48
49struct pci_pme_device {
50 struct list_head list;
51 struct pci_dev *dev;
52};
53
54#define PME_TIMEOUT 1000 /* How long between PME checks */
55
1ae861e6
RW		 56static void pci_dev_d3_sleep(struct pci_dev *dev)
57{
58 unsigned int delay = dev->d3_delay;
59
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
62
63 msleep(delay);
64}
1da177e4 65
32a2eea7
JG		 66#ifdef CONFIG_PCI_DOMAINS
67int pci_domains_supported = 1;
68#endif
69
4516a618
AN		 70#define DEFAULT_CARDBUS_IO_SIZE (256)
71#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72/* pci=cbmemsize=nnM,cbiosize=nn can override this */
73unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75
28760489
EB		 76#define DEFAULT_HOTPLUG_IO_SIZE (256)
77#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78/* pci=hpmemsize=nnM,hpiosize=nn can override this */
79unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81
5f39e670 82enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495 83
ac1aa47b
JB		 84/*
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
89 */
15856ad5 90u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 91u8 pci_cache_line_size;
92
96c55900
MS		 93/*
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
96 */
97unsigned int pcibios_max_latency = 255;
98
6748dcc2
RW		 99/* If set, the PCIe ARI capability will not be used. */
100static bool pcie_ari_disabled;
101
1da177e4
LT		 102/**
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
105 *
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
108 */
96bde06a 109unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 110{
111 struct list_head *tmp;
112 unsigned char max, n;
113
b918c62e 114 max = bus->busn_res.end;
1da177e4
LT		 115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
117 if(n > max)
118 max = n;
119 }
120 return max;
121}
b82db5ce 122EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 123
1684f5dd
AM		 124#ifdef CONFIG_HAS_IOMEM
125void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
126{
127 /*
128 * Make sure the BAR is actually a memory resource, not an IO resource
129 */
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
131 WARN_ON(1);
132 return NULL;
133 }
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
136}
137EXPORT_SYMBOL_GPL(pci_ioremap_bar);
138#endif
139
687d5fe3
ME		 140#define PCI_FIND_CAP_TTL 48
141
142static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
24a4e377
RD		 144{
145 u8 id;
24a4e377 146
687d5fe3 147 while ((*ttl)--) {
24a4e377
RD		 148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
149 if (pos < 0x40)
150 break;
151 pos &= ~3;
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
153 &id);
154 if (id == 0xff)
155 break;
156 if (id == cap)
157 return pos;
158 pos += PCI_CAP_LIST_NEXT;
159 }
160 return 0;
161}
162
687d5fe3
ME		 163static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
164 u8 pos, int cap)
165{
166 int ttl = PCI_FIND_CAP_TTL;
167
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
169}
170
24a4e377
RD		 171int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172{
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
175}
176EXPORT_SYMBOL_GPL(pci_find_next_capability);
177
d3bac118
ME		 178static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 180{
181 u16 status;
1da177e4
LT		 182
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
185 return 0;
186
187 switch (hdr_type) {
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 190 return PCI_CAPABILITY_LIST;
1da177e4 191 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 192 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 193 default:
194 return 0;
195 }
d3bac118
ME		 196
197 return 0;
1da177e4
LT		 198}
199
200/**
f7625980 201 * pci_find_capability - query for devices' capabilities
1da177e4
LT		 202 * @dev: PCI device to query
203 * @cap: capability code
204 *
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
209 *
f7625980
BH		 210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
1da177e4 214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
f7625980 215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
1da177e4
LT		 216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
218 */
219int pci_find_capability(struct pci_dev *dev, int cap)
220{
d3bac118
ME		 221 int pos;
222
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 if (pos)
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
226
227 return pos;
1da177e4
LT		 228}
229
230/**
f7625980 231 * pci_bus_find_capability - query for devices' capabilities
1da177e4
LT		 232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
235 *
236 * Like pci_find_capability() but works for pci devices that do not have a
f7625980 237 * pci_dev structure set up yet.
1da177e4
LT		 238 *
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
241 * support it.
242 */
243int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
244{
d3bac118 245 int pos;
1da177e4
LT		 246 u8 hdr_type;
247
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249
d3bac118
ME		 250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 if (pos)
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
253
254 return pos;
1da177e4
LT		 255}
256
257/**
44a9a36f 258 * pci_find_next_ext_capability - Find an extended capability
1da177e4 259 * @dev: PCI device to query
44a9a36f 260 * @start: address at which to start looking (0 to start at beginning of list)
1da177e4
LT		 261 * @cap: capability code
262 *
44a9a36f 263 * Returns the address of the next matching extended capability structure
1da177e4 264 * within the device's PCI configuration space or 0 if the device does
44a9a36f
BH		 265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
1da177e4 267 */
44a9a36f 268int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
1da177e4
LT		 269{
270 u32 header;
557848c3
ZY		 271 int ttl;
272 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 273
557848c3
ZY		 274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 278 return 0;
279
44a9a36f
BH		 280 if (start)
281 pos = start;
282
1da177e4
LT		 283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
284 return 0;
285
286 /*
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
289 */
290 if (header == 0)
291 return 0;
292
293 while (ttl-- > 0) {
44a9a36f 294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
1da177e4
LT		 295 return pos;
296
297 pos = PCI_EXT_CAP_NEXT(header);
557848c3 298 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 299 break;
300
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
302 break;
303 }
304
305 return 0;
306}
44a9a36f
BH		 307EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
308
309/**
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
313 *
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
317 *
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
322 */
323int pci_find_ext_capability(struct pci_dev *dev, int cap)
324{
325 return pci_find_next_ext_capability(dev, 0, cap);
326}
3a720d72 327EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 328
687d5fe3
ME		 329static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330{
331 int rc, ttl = PCI_FIND_CAP_TTL;
332 u8 cap, mask;
333
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
336 else
337 mask = HT_5BIT_CAP_MASK;
338
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
341 while (pos) {
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
344 return 0;
345
346 if ((cap & mask) == ht_cap)
347 return pos;
348
47a4d5be
BG		 349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 351 PCI_CAP_ID_HT, &ttl);
352 }
353
354 return 0;
355}
356/**
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
361 *
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
365 *
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
368 */
369int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370{
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372}
373EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
374
375/**
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
379 *
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
385 */
386int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
387{
388 int pos;
389
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 if (pos)
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
393
394 return pos;
395}
396EXPORT_SYMBOL_GPL(pci_find_ht_capability);
397
1da177e4
LT		 398/**
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
402 *
403 * For given resource region of given device, return the resource
f44116ae 404 * region of parent bus the given region is contained in.
1da177e4
LT		 405 */
406struct resource *
407pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
408{
409 const struct pci_bus *bus = dev->bus;
f44116ae 410 struct resource *r;
1da177e4 411 int i;
1da177e4 412
89a74ecc 413 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 414 if (!r)
415 continue;
f44116ae
BH		 416 if (res->start && resource_contains(r, res)) {
417
418 /*
419 * If the window is prefetchable but the BAR is
420 * not, the allocator made a mistake.
421 */
422 if (r->flags & IORESOURCE_PREFETCH &&
423 !(res->flags & IORESOURCE_PREFETCH))
424 return NULL;
425
426 /*
427 * If we're below a transparent bridge, there may
428 * be both a positively-decoded aperture and a
429 * subtractively-decoded region that contain the BAR.
430 * We want the positively-decoded one, so this depends
431 * on pci_bus_for_each_resource() giving us those
432 * first.
433 */
434 return r;
435 }
1da177e4 436 }
f44116ae 437 return NULL;
1da177e4
LT		 438}
439
157e876f
AW		 440/**
441 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
442 * @dev: the PCI device to operate on
443 * @pos: config space offset of status word
444 * @mask: mask of bit(s) to care about in status word
445 *
446 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
447 */
448int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
449{
450 int i;
451
452 /* Wait for Transaction Pending bit clean */
453 for (i = 0; i < 4; i++) {
454 u16 status;
455 if (i)
456 msleep((1 << (i - 1)) * 100);
457
458 pci_read_config_word(dev, pos, &status);
459 if (!(status & mask))
460 return 1;
461 }
462
463 return 0;
464}
465
064b53db
JL		 466/**
467 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
468 * @dev: PCI device to have its BARs restored
469 *
470 * Restore the BAR values for a given device, so as to make it
471 * accessible by its driver.
472 */
ad668599 473static void
064b53db
JL		 474pci_restore_bars(struct pci_dev *dev)
475{
bc5f5a82 476 int i;
064b53db 477
bc5f5a82 478 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 479 pci_update_resource(dev, i);
064b53db
JL		 480}
481
961d9120
RW		 482static struct pci_platform_pm_ops *pci_platform_pm;
483
484int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
485{
eb9d0fe4 486 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
d2e5f0c1 487 || !ops->sleep_wake)
961d9120
RW		 488 return -EINVAL;
489 pci_platform_pm = ops;
490 return 0;
491}
492
493static inline bool platform_pci_power_manageable(struct pci_dev *dev)
494{
495 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
496}
497
498static inline int platform_pci_set_power_state(struct pci_dev *dev,
499 pci_power_t t)
500{
501 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
502}
503
504static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
505{
506 return pci_platform_pm ?
507 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
508}
8f7020d3 509
eb9d0fe4
RW		 510static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
511{
512 return pci_platform_pm ?
513 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
514}
515
b67ea761
RW		 516static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
517{
518 return pci_platform_pm ?
519 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
520}
521
1da177e4 522/**
44e4e66e
RW		 523 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
524 * given PCI device
525 * @dev: PCI device to handle.
44e4e66e 526 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 527 *
44e4e66e
RW		 528 * RETURN VALUE:
529 * -EINVAL if the requested state is invalid.
530 * -EIO if device does not support PCI PM or its PM capabilities register has a
531 * wrong version, or device doesn't support the requested state.
532 * 0 if device already is in the requested state.
533 * 0 if device's power state has been successfully changed.
1da177e4 534 */
f00a20ef 535static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 536{
337001b6 537 u16 pmcsr;
44e4e66e 538 bool need_restore = false;
1da177e4 539
4a865905
RW		 540 /* Check if we're already there */
541 if (dev->current_state == state)
542 return 0;
543
337001b6 544 if (!dev->pm_cap)
cca03dec
AL		 545 return -EIO;
546
44e4e66e
RW		 547 if (state < PCI_D0 || state > PCI_D3hot)
548 return -EINVAL;
549
1da177e4 550 /* Validate current state:
f7625980 551 * Can enter D0 from any state, but if we can only go deeper
1da177e4
LT		 552 * to sleep if we're already in a low power state
553 */
4a865905 554 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 555 && dev->current_state > state) {
80ccba11
BH		 556 dev_err(&dev->dev, "invalid power transition "
557 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 558 return -EINVAL;
44e4e66e 559 }
1da177e4 560
1da177e4 561 /* check if this device supports the desired state */
337001b6
RW		 562 if ((state == PCI_D1 && !dev->d1_support)
563 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 564 return -EIO;
1da177e4 565
337001b6 566 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 567
32a36585 568 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 569 * This doesn't affect PME_Status, disables PME_En, and
570 * sets PowerState to 0.
571 */
32a36585 572 switch (dev->current_state) {
d3535fbb
JL		 573 case PCI_D0:
574 case PCI_D1:
575 case PCI_D2:
576 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
577 pmcsr |= state;
578 break;
f62795f1
RW		 579 case PCI_D3hot:
580 case PCI_D3cold:
32a36585
JL		 581 case PCI_UNKNOWN: /* Boot-up */
582 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 583 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 584 need_restore = true;
32a36585 585 /* Fall-through: force to D0 */
32a36585 586 default:
d3535fbb 587 pmcsr = 0;
32a36585 588 break;
1da177e4
LT		 589 }
590
591 /* enter specified state */
337001b6 592 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 593
594 /* Mandatory power management transition delays */
595 /* see PCI PM 1.1 5.6.1 table 18 */
596 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 597 pci_dev_d3_sleep(dev);
1da177e4 598 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 599 udelay(PCI_PM_D2_DELAY);
1da177e4 600
e13cdbd7
RW		 601 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
602 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
603 if (dev->current_state != state && printk_ratelimit())
604 dev_info(&dev->dev, "Refused to change power state, "
605 "currently in D%d\n", dev->current_state);
064b53db 606
448bd857
HY		 607 /*
608 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
064b53db
JL		 609 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
610 * from D3hot to D0 _may_ perform an internal reset, thereby
611 * going to "D0 Uninitialized" rather than "D0 Initialized".
612 * For example, at least some versions of the 3c905B and the
613 * 3c556B exhibit this behaviour.
614 *
615 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
616 * devices in a D3hot state at boot. Consequently, we need to
617 * restore at least the BARs so that the device will be
618 * accessible to its driver.
619 */
620 if (need_restore)
621 pci_restore_bars(dev);
622
f00a20ef 623 if (dev->bus->self)
7d715a6c
SL		 624 pcie_aspm_pm_state_change(dev->bus->self);
625
1da177e4
LT		 626 return 0;
627}
628
44e4e66e
RW		 629/**
630 * pci_update_current_state - Read PCI power state of given device from its
631 * PCI PM registers and cache it
632 * @dev: PCI device to handle.
f06fc0b6 633 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 634 */
73410429 635void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 636{
337001b6 637 if (dev->pm_cap) {
44e4e66e
RW		 638 u16 pmcsr;
639
448bd857
HY		 640 /*
641 * Configuration space is not accessible for device in
642 * D3cold, so just keep or set D3cold for safety
643 */
644 if (dev->current_state == PCI_D3cold)
645 return;
646 if (state == PCI_D3cold) {
647 dev->current_state = PCI_D3cold;
648 return;
649 }
337001b6 650 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 651 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 652 } else {
653 dev->current_state = state;
44e4e66e
RW		 654 }
655}
656
db288c9c
RW		 657/**
658 * pci_power_up - Put the given device into D0 forcibly
659 * @dev: PCI device to power up
660 */
661void pci_power_up(struct pci_dev *dev)
662{
663 if (platform_pci_power_manageable(dev))
664 platform_pci_set_power_state(dev, PCI_D0);
665
666 pci_raw_set_power_state(dev, PCI_D0);
667 pci_update_current_state(dev, PCI_D0);
668}
669
0e5dd46b
RW		 670/**
671 * pci_platform_power_transition - Use platform to change device power state
672 * @dev: PCI device to handle.
673 * @state: State to put the device into.
674 */
675static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
676{
677 int error;
678
679 if (platform_pci_power_manageable(dev)) {
680 error = platform_pci_set_power_state(dev, state);
681 if (!error)
682 pci_update_current_state(dev, state);
769ba721 683 } else
0e5dd46b 684 error = -ENODEV;
769ba721
RW		 685
686 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
687 dev->current_state = PCI_D0;
0e5dd46b
RW		 688
689 return error;
690}
691
0b950f0f
SH		 692/**
693 * pci_wakeup - Wake up a PCI device
694 * @pci_dev: Device to handle.
695 * @ign: ignored parameter
696 */
697static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
698{
699 pci_wakeup_event(pci_dev);
700 pm_request_resume(&pci_dev->dev);
701 return 0;
702}
703
704/**
705 * pci_wakeup_bus - Walk given bus and wake up devices on it
706 * @bus: Top bus of the subtree to walk.
707 */
708static void pci_wakeup_bus(struct pci_bus *bus)
709{
710 if (bus)
711 pci_walk_bus(bus, pci_wakeup, NULL);
712}
713
0e5dd46b
RW		 714/**
715 * __pci_start_power_transition - Start power transition of a PCI device
716 * @dev: PCI device to handle.
717 * @state: State to put the device into.
718 */
719static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
720{
448bd857 721 if (state == PCI_D0) {
0e5dd46b 722 pci_platform_power_transition(dev, PCI_D0);
448bd857
HY		 723 /*
724 * Mandatory power management transition delays, see
725 * PCI Express Base Specification Revision 2.0 Section
726 * 6.6.1: Conventional Reset. Do not delay for
727 * devices powered on/off by corresponding bridge,
728 * because have already delayed for the bridge.
729 */
730 if (dev->runtime_d3cold) {
731 msleep(dev->d3cold_delay);
732 /*
733 * When powering on a bridge from D3cold, the
734 * whole hierarchy may be powered on into
735 * D0uninitialized state, resume them to give
736 * them a chance to suspend again
737 */
738 pci_wakeup_bus(dev->subordinate);
739 }
740 }
741}
742
743/**
744 * __pci_dev_set_current_state - Set current state of a PCI device
745 * @dev: Device to handle
746 * @data: pointer to state to be set
747 */
748static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
749{
750 pci_power_t state = *(pci_power_t *)data;
751
752 dev->current_state = state;
753 return 0;
754}
755
756/**
757 * __pci_bus_set_current_state - Walk given bus and set current state of devices
758 * @bus: Top bus of the subtree to walk.
759 * @state: state to be set
760 */
761static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
762{
763 if (bus)
764 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
0e5dd46b
RW		 765}
766
767/**
768 * __pci_complete_power_transition - Complete power transition of a PCI device
769 * @dev: PCI device to handle.
770 * @state: State to put the device into.
771 *
772 * This function should not be called directly by device drivers.
773 */
774int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
775{
448bd857
HY		 776 int ret;
777
db288c9c 778 if (state <= PCI_D0)
448bd857
HY		 779 return -EINVAL;
780 ret = pci_platform_power_transition(dev, state);
781 /* Power off the bridge may power off the whole hierarchy */
782 if (!ret && state == PCI_D3cold)
783 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
784 return ret;
0e5dd46b
RW		 785}
786EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
787
44e4e66e
RW		 788/**
789 * pci_set_power_state - Set the power state of a PCI device
790 * @dev: PCI device to handle.
791 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
792 *
877d0310 793 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 794 * the device's PCI PM registers.
795 *
796 * RETURN VALUE:
797 * -EINVAL if the requested state is invalid.
798 * -EIO if device does not support PCI PM or its PM capabilities register has a
799 * wrong version, or device doesn't support the requested state.
800 * 0 if device already is in the requested state.
801 * 0 if device's power state has been successfully changed.
802 */
803int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
804{
337001b6 805 int error;
44e4e66e
RW		 806
807 /* bound the state we're entering */
448bd857
HY		 808 if (state > PCI_D3cold)
809 state = PCI_D3cold;
44e4e66e
RW		 810 else if (state < PCI_D0)
811 state = PCI_D0;
812 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
813 /*
814 * If the device or the parent bridge do not support PCI PM,
815 * ignore the request if we're doing anything other than putting
816 * it into D0 (which would only happen on boot).
817 */
818 return 0;
819
db288c9c
RW		 820 /* Check if we're already there */
821 if (dev->current_state == state)
822 return 0;
823
0e5dd46b
RW		 824 __pci_start_power_transition(dev, state);
825
979b1791
AC		 826 /* This device is quirked not to be put into D3, so
827 don't put it in D3 */
448bd857 828 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
979b1791 829 return 0;
44e4e66e 830
448bd857
HY		 831 /*
832 * To put device in D3cold, we put device into D3hot in native
833 * way, then put device into D3cold with platform ops
834 */
835 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
836 PCI_D3hot : state);
44e4e66e 837
0e5dd46b
RW		 838 if (!__pci_complete_power_transition(dev, state))
839 error = 0;
1a680b7c
NC		 840 /*
841 * When aspm_policy is "powersave" this call ensures
842 * that ASPM is configured.
843 */
844 if (!error && dev->bus->self)
845 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 846
847 return error;
848}
849
1da177e4
LT		 850/**
851 * pci_choose_state - Choose the power state of a PCI device
852 * @dev: PCI device to be suspended
853 * @state: target sleep state for the whole system. This is the value
854 * that is passed to suspend() function.
855 *
856 * Returns PCI power state suitable for given device and given system
857 * message.
858 */
859
860pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
861{
ab826ca4 862 pci_power_t ret;
0f64474b 863
728cdb75 864 if (!dev->pm_cap)
1da177e4
LT		 865 return PCI_D0;
866
961d9120
RW		 867 ret = platform_pci_choose_state(dev);
868 if (ret != PCI_POWER_ERROR)
869 return ret;
ca078bae
PM		 870
871 switch (state.event) {
872 case PM_EVENT_ON:
873 return PCI_D0;
874 case PM_EVENT_FREEZE:
b887d2e6
DB		 875 case PM_EVENT_PRETHAW:
876 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 877 case PM_EVENT_SUSPEND:
3a2d5b70 878 case PM_EVENT_HIBERNATE:
ca078bae 879 return PCI_D3hot;
1da177e4 880 default:
80ccba11
BH		 881 dev_info(&dev->dev, "unrecognized suspend event %d\n",
882 state.event);
1da177e4
LT		 883 BUG();
884 }
885 return PCI_D0;
886}
887
888EXPORT_SYMBOL(pci_choose_state);
889
89858517
YZ		 890#define PCI_EXP_SAVE_REGS 7
891
1b6b8ce2 892
fd0f7f73
AW		 893static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
894 u16 cap, bool extended)
34a4876e
YL		 895{
896 struct pci_cap_saved_state *tmp;
34a4876e 897
b67bfe0d 898 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
fd0f7f73 899 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
34a4876e
YL		 900 return tmp;
901 }
902 return NULL;
903}
904
fd0f7f73
AW		 905struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
906{
907 return _pci_find_saved_cap(dev, cap, false);
908}
909
910struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
911{
912 return _pci_find_saved_cap(dev, cap, true);
913}
914
b56a5a23
MT		 915static int pci_save_pcie_state(struct pci_dev *dev)
916{
59875ae4 917 int i = 0;
b56a5a23
MT		 918 struct pci_cap_saved_state *save_state;
919 u16 *cap;
920
59875ae4 921 if (!pci_is_pcie(dev))
b56a5a23
MT		 922 return 0;
923
9f35575d 924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 925 if (!save_state) {
e496b617 926 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 927 return -ENOMEM;
928 }
63f4898a 929
59875ae4
JL		 930 cap = (u16 *)&save_state->cap.data[0];
931 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
932 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
933 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
934 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
935 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
936 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
937 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
9cb604ed 938
b56a5a23
MT		 939 return 0;
940}
941
942static void pci_restore_pcie_state(struct pci_dev *dev)
943{
59875ae4 944 int i = 0;
b56a5a23
MT		 945 struct pci_cap_saved_state *save_state;
946 u16 *cap;
947
948 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
59875ae4 949 if (!save_state)
9cb604ed
MS		 950 return;
951
59875ae4
JL		 952 cap = (u16 *)&save_state->cap.data[0];
953 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
954 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
955 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
956 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
957 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
958 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
959 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 960}
961
cc692a5f
SH		 962
963static int pci_save_pcix_state(struct pci_dev *dev)
964{
63f4898a 965 int pos;
cc692a5f 966 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 967
968 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
969 if (pos <= 0)
970 return 0;
971
f34303de 972 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 973 if (!save_state) {
e496b617 974 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 975 return -ENOMEM;
976 }
cc692a5f 977
24a4742f
AW		 978 pci_read_config_word(dev, pos + PCI_X_CMD,
979 (u16 *)save_state->cap.data);
63f4898a 980
cc692a5f
SH		 981 return 0;
982}
983
984static void pci_restore_pcix_state(struct pci_dev *dev)
985{
986 int i = 0, pos;
987 struct pci_cap_saved_state *save_state;
988 u16 *cap;
989
990 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
991 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
992 if (!save_state || pos <= 0)
993 return;
24a4742f 994 cap = (u16 *)&save_state->cap.data[0];
cc692a5f
SH		 995
996 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 997}
998
999
1da177e4
LT		 1000/**
1001 * pci_save_state - save the PCI configuration space of a device before suspending
1002 * @dev: - PCI device that we're dealing with
1da177e4
LT		 1003 */
1004int
1005pci_save_state(struct pci_dev *dev)
1006{
1007 int i;
1008 /* XXX: 100% dword access ok here? */
1009 for (i = 0; i < 16; i++)
9e0b5b2c 1010 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 1011 dev->state_saved = true;
b56a5a23
MT		 1012 if ((i = pci_save_pcie_state(dev)) != 0)
1013 return i;
cc692a5f
SH		 1014 if ((i = pci_save_pcix_state(dev)) != 0)
1015 return i;
425c1b22
AW		 1016 if ((i = pci_save_vc_state(dev)) != 0)
1017 return i;
1da177e4
LT		 1018 return 0;
1019}
1020
ebfc5b80
RW		 1021static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1022 u32 saved_val, int retry)
1023{
1024 u32 val;
1025
1026 pci_read_config_dword(pdev, offset, &val);
1027 if (val == saved_val)
1028 return;
1029
1030 for (;;) {
1031 dev_dbg(&pdev->dev, "restoring config space at offset "
1032 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
1033 pci_write_config_dword(pdev, offset, saved_val);
1034 if (retry-- <= 0)
1035 return;
1036
1037 pci_read_config_dword(pdev, offset, &val);
1038 if (val == saved_val)
1039 return;
1040
1041 mdelay(1);
1042 }
1043}
1044
a6cb9ee7
RW		 1045static void pci_restore_config_space_range(struct pci_dev *pdev,
1046 int start, int end, int retry)
ebfc5b80
RW		 1047{
1048 int index;
1049
1050 for (index = end; index >= start; index--)
1051 pci_restore_config_dword(pdev, 4 * index,
1052 pdev->saved_config_space[index],
1053 retry);
1054}
1055
a6cb9ee7
RW		 1056static void pci_restore_config_space(struct pci_dev *pdev)
1057{
1058 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1059 pci_restore_config_space_range(pdev, 10, 15, 0);
1060 /* Restore BARs before the command register. */
1061 pci_restore_config_space_range(pdev, 4, 9, 10);
1062 pci_restore_config_space_range(pdev, 0, 3, 0);
1063 } else {
1064 pci_restore_config_space_range(pdev, 0, 15, 0);
1065 }
1066}
1067
f7625980 1068/**
1da177e4
LT		 1069 * pci_restore_state - Restore the saved state of a PCI device
1070 * @dev: - PCI device that we're dealing with
1da177e4 1071 */
1d3c16a8 1072void pci_restore_state(struct pci_dev *dev)
1da177e4 1073{
c82f63e4 1074 if (!dev->state_saved)
1d3c16a8 1075 return;
4b77b0a2 1076
b56a5a23
MT		 1077 /* PCI Express register must be restored first */
1078 pci_restore_pcie_state(dev);
1900ca13 1079 pci_restore_ats_state(dev);
425c1b22 1080 pci_restore_vc_state(dev);
b56a5a23 1081
a6cb9ee7 1082 pci_restore_config_space(dev);
ebfc5b80 1083
cc692a5f 1084 pci_restore_pcix_state(dev);
41017f0c 1085 pci_restore_msi_state(dev);
8c5cdb6a 1086 pci_restore_iov_state(dev);
8fed4b65 1087
4b77b0a2 1088 dev->state_saved = false;
1da177e4
LT		 1089}
1090
ffbdd3f7
AW		 1091struct pci_saved_state {
1092 u32 config_space[16];
1093 struct pci_cap_saved_data cap[0];
1094};
1095
1096/**
1097 * pci_store_saved_state - Allocate and return an opaque struct containing
1098 * the device saved state.
1099 * @dev: PCI device that we're dealing with
1100 *
f7625980 1101 * Return NULL if no state or error.
ffbdd3f7
AW		 1102 */
1103struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1104{
1105 struct pci_saved_state *state;
1106 struct pci_cap_saved_state *tmp;
1107 struct pci_cap_saved_data *cap;
ffbdd3f7
AW		 1108 size_t size;
1109
1110 if (!dev->state_saved)
1111 return NULL;
1112
1113 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1114
b67bfe0d 1115 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
ffbdd3f7
AW		 1116 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1117
1118 state = kzalloc(size, GFP_KERNEL);
1119 if (!state)
1120 return NULL;
1121
1122 memcpy(state->config_space, dev->saved_config_space,
1123 sizeof(state->config_space));
1124
1125 cap = state->cap;
b67bfe0d 1126 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
ffbdd3f7
AW		 1127 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1128 memcpy(cap, &tmp->cap, len);
1129 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1130 }
1131 /* Empty cap_save terminates list */
1132
1133 return state;
1134}
1135EXPORT_SYMBOL_GPL(pci_store_saved_state);
1136
1137/**
1138 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1139 * @dev: PCI device that we're dealing with
1140 * @state: Saved state returned from pci_store_saved_state()
1141 */
0b950f0f
SH		 1142static int pci_load_saved_state(struct pci_dev *dev,
1143 struct pci_saved_state *state)
ffbdd3f7
AW		 1144{
1145 struct pci_cap_saved_data *cap;
1146
1147 dev->state_saved = false;
1148
1149 if (!state)
1150 return 0;
1151
1152 memcpy(dev->saved_config_space, state->config_space,
1153 sizeof(state->config_space));
1154
1155 cap = state->cap;
1156 while (cap->size) {
1157 struct pci_cap_saved_state *tmp;
1158
fd0f7f73 1159 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
ffbdd3f7
AW		 1160 if (!tmp || tmp->cap.size != cap->size)
1161 return -EINVAL;
1162
1163 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1164 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1165 sizeof(struct pci_cap_saved_data) + cap->size);
1166 }
1167
1168 dev->state_saved = true;
1169 return 0;
1170}
ffbdd3f7
AW		 1171
1172/**
1173 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1174 * and free the memory allocated for it.
1175 * @dev: PCI device that we're dealing with
1176 * @state: Pointer to saved state returned from pci_store_saved_state()
1177 */
1178int pci_load_and_free_saved_state(struct pci_dev *dev,
1179 struct pci_saved_state **state)
1180{
1181 int ret = pci_load_saved_state(dev, *state);
1182 kfree(*state);
1183 *state = NULL;
1184 return ret;
1185}
1186EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1187
38cc1302
HS		 1188static int do_pci_enable_device(struct pci_dev *dev, int bars)
1189{
1190 int err;
1191
1192 err = pci_set_power_state(dev, PCI_D0);
1193 if (err < 0 && err != -EIO)
1194 return err;
1195 err = pcibios_enable_device(dev, bars);
1196 if (err < 0)
1197 return err;
1198 pci_fixup_device(pci_fixup_enable, dev);
1199
1200 return 0;
1201}
1202
1203/**
0b62e13b 1204 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 1205 * @dev: PCI device to be resumed
1206 *
1207 * Note this function is a backend of pci_default_resume and is not supposed
1208 * to be called by normal code, write proper resume handler and use it instead.
1209 */
0b62e13b 1210int pci_reenable_device(struct pci_dev *dev)
38cc1302 1211{
296ccb08 1212 if (pci_is_enabled(dev))
38cc1302
HS		 1213 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1214 return 0;
1215}
1216
928bea96
YL		 1217static void pci_enable_bridge(struct pci_dev *dev)
1218{
79272138 1219 struct pci_dev *bridge;
928bea96
YL		 1220 int retval;
1221
79272138
BH		 1222 bridge = pci_upstream_bridge(dev);
1223 if (bridge)
1224 pci_enable_bridge(bridge);
928bea96 1225
cf3e1feb 1226 if (pci_is_enabled(dev)) {
fbeeb822 1227 if (!dev->is_busmaster)
cf3e1feb 1228 pci_set_master(dev);
928bea96 1229 return;
cf3e1feb
YL		 1230 }
1231
928bea96
YL		 1232 retval = pci_enable_device(dev);
1233 if (retval)
1234 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1235 retval);
1236 pci_set_master(dev);
1237}
1238
b4b4fbba 1239static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1da177e4 1240{
79272138 1241 struct pci_dev *bridge;
1da177e4 1242 int err;
b718989d 1243 int i, bars = 0;
1da177e4 1244
97c145f7
JB		 1245 /*
1246 * Power state could be unknown at this point, either due to a fresh
1247 * boot or a device removal call. So get the current power state
1248 * so that things like MSI message writing will behave as expected
1249 * (e.g. if the device really is in D0 at enable time).
1250 */
1251 if (dev->pm_cap) {
1252 u16 pmcsr;
1253 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1254 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1255 }
1256
cc7ba39b 1257 if (atomic_inc_return(&dev->enable_cnt) > 1)
9fb625c3
HS		 1258 return 0; /* already enabled */
1259
79272138
BH		 1260 bridge = pci_upstream_bridge(dev);
1261 if (bridge)
1262 pci_enable_bridge(bridge);
928bea96 1263
497f16f2
YL		 1264 /* only skip sriov related */
1265 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1266 if (dev->resource[i].flags & flags)
1267 bars |= (1 << i);
1268 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
b718989d
BH		 1269 if (dev->resource[i].flags & flags)
1270 bars |= (1 << i);
1271
38cc1302 1272 err = do_pci_enable_device(dev, bars);
95a62965 1273 if (err < 0)
38cc1302 1274 atomic_dec(&dev->enable_cnt);
9fb625c3 1275 return err;
1da177e4
LT		 1276}
1277
b718989d
BH		 1278/**
1279 * pci_enable_device_io - Initialize a device for use with IO space
1280 * @dev: PCI device to be initialized
1281 *
1282 * Initialize device before it's used by a driver. Ask low-level code
1283 * to enable I/O resources. Wake up the device if it was suspended.
1284 * Beware, this function can fail.
1285 */
1286int pci_enable_device_io(struct pci_dev *dev)
1287{
b4b4fbba 1288 return pci_enable_device_flags(dev, IORESOURCE_IO);
b718989d
BH		 1289}
1290
1291/**
1292 * pci_enable_device_mem - Initialize a device for use with Memory space
1293 * @dev: PCI device to be initialized
1294 *
1295 * Initialize device before it's used by a driver. Ask low-level code
1296 * to enable Memory resources. Wake up the device if it was suspended.
1297 * Beware, this function can fail.
1298 */
1299int pci_enable_device_mem(struct pci_dev *dev)
1300{
b4b4fbba 1301 return pci_enable_device_flags(dev, IORESOURCE_MEM);
b718989d
BH		 1302}
1303
bae94d02
IPG		 1304/**
1305 * pci_enable_device - Initialize device before it's used by a driver.
1306 * @dev: PCI device to be initialized
1307 *
1308 * Initialize device before it's used by a driver. Ask low-level code
1309 * to enable I/O and memory. Wake up the device if it was suspended.
1310 * Beware, this function can fail.
1311 *
1312 * Note we don't actually enable the device many times if we call
1313 * this function repeatedly (we just increment the count).
1314 */
1315int pci_enable_device(struct pci_dev *dev)
1316{
b4b4fbba 1317 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1318}
1319
9ac7849e
TH		 1320/*
1321 * Managed PCI resources. This manages device on/off, intx/msi/msix
1322 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1323 * there's no need to track it separately. pci_devres is initialized
1324 * when a device is enabled using managed PCI device enable interface.
1325 */
1326struct pci_devres {
7f375f32
TH		 1327 unsigned int enabled:1;
1328 unsigned int pinned:1;
9ac7849e
TH		 1329 unsigned int orig_intx:1;
1330 unsigned int restore_intx:1;
1331 u32 region_mask;
1332};
1333
1334static void pcim_release(struct device *gendev, void *res)
1335{
1336 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1337 struct pci_devres *this = res;
1338 int i;
1339
1340 if (dev->msi_enabled)
1341 pci_disable_msi(dev);
1342 if (dev->msix_enabled)
1343 pci_disable_msix(dev);
1344
1345 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1346 if (this->region_mask & (1 << i))
1347 pci_release_region(dev, i);
1348
1349 if (this->restore_intx)
1350 pci_intx(dev, this->orig_intx);
1351
7f375f32 1352 if (this->enabled && !this->pinned)
9ac7849e
TH		 1353 pci_disable_device(dev);
1354}
1355
1356static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1357{
1358 struct pci_devres *dr, *new_dr;
1359
1360 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1361 if (dr)
1362 return dr;
1363
1364 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1365 if (!new_dr)
1366 return NULL;
1367 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1368}
1369
1370static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1371{
1372 if (pci_is_managed(pdev))
1373 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1374 return NULL;
1375}
1376
1377/**
1378 * pcim_enable_device - Managed pci_enable_device()
1379 * @pdev: PCI device to be initialized
1380 *
1381 * Managed pci_enable_device().
1382 */
1383int pcim_enable_device(struct pci_dev *pdev)
1384{
1385 struct pci_devres *dr;
1386 int rc;
1387
1388 dr = get_pci_dr(pdev);
1389 if (unlikely(!dr))
1390 return -ENOMEM;
b95d58ea
TH		 1391 if (dr->enabled)
1392 return 0;
9ac7849e
TH		 1393
1394 rc = pci_enable_device(pdev);
1395 if (!rc) {
1396 pdev->is_managed = 1;
7f375f32 1397 dr->enabled = 1;
9ac7849e
TH		 1398 }
1399 return rc;
1400}
1401
1402/**
1403 * pcim_pin_device - Pin managed PCI device
1404 * @pdev: PCI device to pin
1405 *
1406 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1407 * driver detach. @pdev must have been enabled with
1408 * pcim_enable_device().
1409 */
1410void pcim_pin_device(struct pci_dev *pdev)
1411{
1412 struct pci_devres *dr;
1413
1414 dr = find_pci_dr(pdev);
7f375f32 1415 WARN_ON(!dr || !dr->enabled);
9ac7849e 1416 if (dr)
7f375f32 1417 dr->pinned = 1;
9ac7849e
TH		 1418}
1419
eca0d467
MG		 1420/*
1421 * pcibios_add_device - provide arch specific hooks when adding device dev
1422 * @dev: the PCI device being added
1423 *
1424 * Permits the platform to provide architecture specific functionality when
1425 * devices are added. This is the default implementation. Architecture
1426 * implementations can override this.
1427 */
1428int __weak pcibios_add_device (struct pci_dev *dev)
1429{
1430 return 0;
1431}
1432
6ae32c53
SO		 1433/**
1434 * pcibios_release_device - provide arch specific hooks when releasing device dev
1435 * @dev: the PCI device being released
1436 *
1437 * Permits the platform to provide architecture specific functionality when
1438 * devices are released. This is the default implementation. Architecture
1439 * implementations can override this.
1440 */
1441void __weak pcibios_release_device(struct pci_dev *dev) {}
1442
1da177e4
LT		 1443/**
1444 * pcibios_disable_device - disable arch specific PCI resources for device dev
1445 * @dev: the PCI device to disable
1446 *
1447 * Disables architecture specific PCI resources for the device. This
1448 * is the default implementation. Architecture implementations can
1449 * override this.
1450 */
d6d88c83 1451void __weak pcibios_disable_device (struct pci_dev *dev) {}
1da177e4 1452
fa58d305
RW		 1453static void do_pci_disable_device(struct pci_dev *dev)
1454{
1455 u16 pci_command;
1456
1457 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1458 if (pci_command & PCI_COMMAND_MASTER) {
1459 pci_command &= ~PCI_COMMAND_MASTER;
1460 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1461 }
1462
1463 pcibios_disable_device(dev);
1464}
1465
1466/**
1467 * pci_disable_enabled_device - Disable device without updating enable_cnt
1468 * @dev: PCI device to disable
1469 *
1470 * NOTE: This function is a backend of PCI power management routines and is
1471 * not supposed to be called drivers.
1472 */
1473void pci_disable_enabled_device(struct pci_dev *dev)
1474{
296ccb08 1475 if (pci_is_enabled(dev))
fa58d305
RW		 1476 do_pci_disable_device(dev);
1477}
1478
1da177e4
LT		 1479/**
1480 * pci_disable_device - Disable PCI device after use
1481 * @dev: PCI device to be disabled
1482 *
1483 * Signal to the system that the PCI device is not in use by the system
1484 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1485 *
1486 * Note we don't actually disable the device until all callers of
ee6583f6 1487 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1488 */
1489void
1490pci_disable_device(struct pci_dev *dev)
1491{
9ac7849e 1492 struct pci_devres *dr;
99dc804d 1493
9ac7849e
TH		 1494 dr = find_pci_dr(dev);
1495 if (dr)
7f375f32 1496 dr->enabled = 0;
9ac7849e 1497
fd6dceab
KK		 1498 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1499 "disabling already-disabled device");
1500
cc7ba39b 1501 if (atomic_dec_return(&dev->enable_cnt) != 0)
bae94d02
IPG		 1502 return;
1503
fa58d305 1504 do_pci_disable_device(dev);
1da177e4 1505
fa58d305 1506 dev->is_busmaster = 0;
1da177e4
LT		 1507}
1508
f7bdd12d
BK		 1509/**
1510 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1511 * @dev: the PCIe device reset
f7bdd12d
BK		 1512 * @state: Reset state to enter into
1513 *
1514 *
45e829ea 1515 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1516 * implementation. Architecture implementations can override this.
1517 */
d6d88c83
BH		 1518int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1519 enum pcie_reset_state state)
f7bdd12d
BK		 1520{
1521 return -EINVAL;
1522}
1523
1524/**
1525 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1526 * @dev: the PCIe device reset
f7bdd12d
BK		 1527 * @state: Reset state to enter into
1528 *
1529 *
1530 * Sets the PCI reset state for the device.
1531 */
1532int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1533{
1534 return pcibios_set_pcie_reset_state(dev, state);
1535}
1536
58ff4633
RW		 1537/**
1538 * pci_check_pme_status - Check if given device has generated PME.
1539 * @dev: Device to check.
1540 *
1541 * Check the PME status of the device and if set, clear it and clear PME enable
1542 * (if set). Return 'true' if PME status and PME enable were both set or
1543 * 'false' otherwise.
1544 */
1545bool pci_check_pme_status(struct pci_dev *dev)
1546{
1547 int pmcsr_pos;
1548 u16 pmcsr;
1549 bool ret = false;
1550
1551 if (!dev->pm_cap)
1552 return false;
1553
1554 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1555 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1556 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1557 return false;
1558
1559 /* Clear PME status. */
1560 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1561 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1562 /* Disable PME to avoid interrupt flood. */
1563 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1564 ret = true;
1565 }
1566
1567 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1568
1569 return ret;
1570}
1571
b67ea761
RW		 1572/**
1573 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1574 * @dev: Device to handle.
379021d5 1575 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
b67ea761
RW		 1576 *
1577 * Check if @dev has generated PME and queue a resume request for it in that
1578 * case.
1579 */
379021d5 1580static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
b67ea761 1581{
379021d5
RW		 1582 if (pme_poll_reset && dev->pme_poll)
1583 dev->pme_poll = false;
1584
c125e96f 1585 if (pci_check_pme_status(dev)) {
c125e96f 1586 pci_wakeup_event(dev);
0f953bf6 1587 pm_request_resume(&dev->dev);
c125e96f 1588 }
b67ea761
RW		 1589 return 0;
1590}
1591
1592/**
1593 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1594 * @bus: Top bus of the subtree to walk.
1595 */
1596void pci_pme_wakeup_bus(struct pci_bus *bus)
1597{
1598 if (bus)
379021d5 1599 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
b67ea761
RW		 1600}
1601
448bd857 1602
eb9d0fe4
RW		 1603/**
1604 * pci_pme_capable - check the capability of PCI device to generate PME#
1605 * @dev: PCI device to handle.
eb9d0fe4
RW		 1606 * @state: PCI state from which device will issue PME#.
1607 */
e5899e1b 1608bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1609{
337001b6 1610 if (!dev->pm_cap)
eb9d0fe4
RW		 1611 return false;
1612
337001b6 1613 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1614}
1615
df17e62e
MG		 1616static void pci_pme_list_scan(struct work_struct *work)
1617{
379021d5 1618 struct pci_pme_device *pme_dev, *n;
df17e62e
MG		 1619
1620 mutex_lock(&pci_pme_list_mutex);
1621 if (!list_empty(&pci_pme_list)) {
379021d5
RW		 1622 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1623 if (pme_dev->dev->pme_poll) {
71a83bd7
ZY		 1624 struct pci_dev *bridge;
1625
1626 bridge = pme_dev->dev->bus->self;
1627 /*
1628 * If bridge is in low power state, the
1629 * configuration space of subordinate devices
1630 * may be not accessible
1631 */
1632 if (bridge && bridge->current_state != PCI_D0)
1633 continue;
379021d5
RW		 1634 pci_pme_wakeup(pme_dev->dev, NULL);
1635 } else {
1636 list_del(&pme_dev->list);
1637 kfree(pme_dev);
1638 }
1639 }
1640 if (!list_empty(&pci_pme_list))
1641 schedule_delayed_work(&pci_pme_work,
1642 msecs_to_jiffies(PME_TIMEOUT));
df17e62e
MG		 1643 }
1644 mutex_unlock(&pci_pme_list_mutex);
1645}
1646
eb9d0fe4
RW		 1647/**
1648 * pci_pme_active - enable or disable PCI device's PME# function
1649 * @dev: PCI device to handle.
eb9d0fe4
RW		 1650 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1651 *
1652 * The caller must verify that the device is capable of generating PME# before
1653 * calling this function with @enable equal to 'true'.
1654 */
5a6c9b60 1655void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1656{
1657 u16 pmcsr;
1658
ffaddbe8 1659 if (!dev->pme_support)
eb9d0fe4
RW		 1660 return;
1661
337001b6 1662 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1663 /* Clear PME_Status by writing 1 to it and enable PME# */
1664 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1665 if (!enable)
1666 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1667
337001b6 1668 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1669
6e965e0d
HY		 1670 /*
1671 * PCI (as opposed to PCIe) PME requires that the device have
1672 * its PME# line hooked up correctly. Not all hardware vendors
1673 * do this, so the PME never gets delivered and the device
1674 * remains asleep. The easiest way around this is to
1675 * periodically walk the list of suspended devices and check
1676 * whether any have their PME flag set. The assumption is that
1677 * we'll wake up often enough anyway that this won't be a huge
1678 * hit, and the power savings from the devices will still be a
1679 * win.
1680 *
1681 * Although PCIe uses in-band PME message instead of PME# line
1682 * to report PME, PME does not work for some PCIe devices in
1683 * reality. For example, there are devices that set their PME
1684 * status bits, but don't really bother to send a PME message;
1685 * there are PCI Express Root Ports that don't bother to
1686 * trigger interrupts when they receive PME messages from the
1687 * devices below. So PME poll is used for PCIe devices too.
1688 */
df17e62e 1689
379021d5 1690 if (dev->pme_poll) {
df17e62e
MG		 1691 struct pci_pme_device *pme_dev;
1692 if (enable) {
1693 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1694 GFP_KERNEL);
0394cb19
BH		 1695 if (!pme_dev) {
1696 dev_warn(&dev->dev, "can't enable PME#\n");
1697 return;
1698 }
df17e62e
MG		 1699 pme_dev->dev = dev;
1700 mutex_lock(&pci_pme_list_mutex);
1701 list_add(&pme_dev->list, &pci_pme_list);
1702 if (list_is_singular(&pci_pme_list))
1703 schedule_delayed_work(&pci_pme_work,
1704 msecs_to_jiffies(PME_TIMEOUT));
1705 mutex_unlock(&pci_pme_list_mutex);
1706 } else {
1707 mutex_lock(&pci_pme_list_mutex);
1708 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1709 if (pme_dev->dev == dev) {
1710 list_del(&pme_dev->list);
1711 kfree(pme_dev);
1712 break;
1713 }
1714 }
1715 mutex_unlock(&pci_pme_list_mutex);
1716 }
1717 }
1718
85b8582d 1719 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
eb9d0fe4
RW		 1720}
1721
1da177e4 1722/**
6cbf8214 1723 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1724 * @dev: PCI device affected
1725 * @state: PCI state from which device will issue wakeup events
6cbf8214 1726 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1727 * @enable: True to enable event generation; false to disable
1728 *
1729 * This enables the device as a wakeup event source, or disables it.
1730 * When such events involves platform-specific hooks, those hooks are
1731 * called automatically by this routine.
1732 *
1733 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1734 * always require such platform hooks.
075c1771 1735 *
eb9d0fe4
RW		 1736 * RETURN VALUE:
1737 * 0 is returned on success
1738 * -EINVAL is returned if device is not supposed to wake up the system
1739 * Error code depending on the platform is returned if both the platform and
1740 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1741 */
6cbf8214
RW		 1742int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1743 bool runtime, bool enable)
1da177e4 1744{
5bcc2fb4 1745 int ret = 0;
075c1771 1746
6cbf8214 1747 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1748 return -EINVAL;
1da177e4 1749
e80bb09d
RW		 1750 /* Don't do the same thing twice in a row for one device. */
1751 if (!!enable == !!dev->wakeup_prepared)
1752 return 0;
1753
eb9d0fe4
RW		 1754 /*
1755 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1756 * Anderson we should be doing PME# wake enable followed by ACPI wake
1757 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1758 */
1da177e4 1759
5bcc2fb4
RW		 1760 if (enable) {
1761 int error;
1da177e4 1762
5bcc2fb4
RW		 1763 if (pci_pme_capable(dev, state))
1764 pci_pme_active(dev, true);
1765 else
1766 ret = 1;
6cbf8214
RW		 1767 error = runtime ? platform_pci_run_wake(dev, true) :
1768 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1769 if (ret)
1770 ret = error;
e80bb09d
RW		 1771 if (!ret)
1772 dev->wakeup_prepared = true;
5bcc2fb4 1773 } else {
6cbf8214
RW		 1774 if (runtime)
1775 platform_pci_run_wake(dev, false);
1776 else
1777 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1778 pci_pme_active(dev, false);
e80bb09d 1779 dev->wakeup_prepared = false;
5bcc2fb4 1780 }
1da177e4 1781
5bcc2fb4 1782 return ret;
eb9d0fe4 1783}
6cbf8214 1784EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1785
0235c4fc
RW		 1786/**
1787 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1788 * @dev: PCI device to prepare
1789 * @enable: True to enable wake-up event generation; false to disable
1790 *
1791 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1792 * and this function allows them to set that up cleanly - pci_enable_wake()
1793 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1794 * ordering constraints.
1795 *
1796 * This function only returns error code if the device is not capable of
1797 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1798 * enable wake-up power for it.
1799 */
1800int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1801{
1802 return pci_pme_capable(dev, PCI_D3cold) ?
1803 pci_enable_wake(dev, PCI_D3cold, enable) :
1804 pci_enable_wake(dev, PCI_D3hot, enable);
1805}
1806
404cc2d8 1807/**
37139074
JB		 1808 * pci_target_state - find an appropriate low power state for a given PCI dev
1809 * @dev: PCI device
1810 *
1811 * Use underlying platform code to find a supported low power state for @dev.
1812 * If the platform can't manage @dev, return the deepest state from which it
1813 * can generate wake events, based on any available PME info.
404cc2d8 1814 */
0b950f0f 1815static pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1816{
1817 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1818
1819 if (platform_pci_power_manageable(dev)) {
1820 /*
1821 * Call the platform to choose the target state of the device
1822 * and enable wake-up from this state if supported.
1823 */
1824 pci_power_t state = platform_pci_choose_state(dev);
1825
1826 switch (state) {
1827 case PCI_POWER_ERROR:
1828 case PCI_UNKNOWN:
1829 break;
1830 case PCI_D1:
1831 case PCI_D2:
1832 if (pci_no_d1d2(dev))
1833 break;
1834 default:
1835 target_state = state;
404cc2d8 1836 }
d2abdf62
RW		 1837 } else if (!dev->pm_cap) {
1838 target_state = PCI_D0;
404cc2d8
RW		 1839 } else if (device_may_wakeup(&dev->dev)) {
1840 /*
1841 * Find the deepest state from which the device can generate
1842 * wake-up events, make it the target state and enable device
1843 * to generate PME#.
1844 */
337001b6
RW		 1845 if (dev->pme_support) {
1846 while (target_state
1847 && !(dev->pme_support & (1 << target_state)))
1848 target_state--;
404cc2d8
RW		 1849 }
1850 }
1851
e5899e1b
RW		 1852 return target_state;
1853}
1854
1855/**
1856 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1857 * @dev: Device to handle.
1858 *
1859 * Choose the power state appropriate for the device depending on whether
1860 * it can wake up the system and/or is power manageable by the platform
1861 * (PCI_D3hot is the default) and put the device into that state.
1862 */
1863int pci_prepare_to_sleep(struct pci_dev *dev)
1864{
1865 pci_power_t target_state = pci_target_state(dev);
1866 int error;
1867
1868 if (target_state == PCI_POWER_ERROR)
1869 return -EIO;
1870
448bd857
HY		 1871 /* D3cold during system suspend/hibernate is not supported */
1872 if (target_state > PCI_D3hot)
1873 target_state = PCI_D3hot;
1874
8efb8c76 1875 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1876
404cc2d8
RW		 1877 error = pci_set_power_state(dev, target_state);
1878
1879 if (error)
1880 pci_enable_wake(dev, target_state, false);
1881
1882 return error;
1883}
1884
1885/**
443bd1c4 1886 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1887 * @dev: Device to handle.
1888 *
88393161 1889 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1890 */
1891int pci_back_from_sleep(struct pci_dev *dev)
1892{
1893 pci_enable_wake(dev, PCI_D0, false);
1894 return pci_set_power_state(dev, PCI_D0);
1895}
1896
6cbf8214
RW		 1897/**
1898 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1899 * @dev: PCI device being suspended.
1900 *
1901 * Prepare @dev to generate wake-up events at run time and put it into a low
1902 * power state.
1903 */
1904int pci_finish_runtime_suspend(struct pci_dev *dev)
1905{
1906 pci_power_t target_state = pci_target_state(dev);
1907 int error;
1908
1909 if (target_state == PCI_POWER_ERROR)
1910 return -EIO;
1911
448bd857
HY		 1912 dev->runtime_d3cold = target_state == PCI_D3cold;
1913
6cbf8214
RW		 1914 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1915
1916 error = pci_set_power_state(dev, target_state);
1917
448bd857 1918 if (error) {
6cbf8214 1919 __pci_enable_wake(dev, target_state, true, false);
448bd857
HY		 1920 dev->runtime_d3cold = false;
1921 }
6cbf8214
RW		 1922
1923 return error;
1924}
1925
b67ea761
RW		 1926/**
1927 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1928 * @dev: Device to check.
1929 *
f7625980 1930 * Return true if the device itself is capable of generating wake-up events
b67ea761
RW		 1931 * (through the platform or using the native PCIe PME) or if the device supports
1932 * PME and one of its upstream bridges can generate wake-up events.
1933 */
1934bool pci_dev_run_wake(struct pci_dev *dev)
1935{
1936 struct pci_bus *bus = dev->bus;
1937
1938 if (device_run_wake(&dev->dev))
1939 return true;
1940
1941 if (!dev->pme_support)
1942 return false;
1943
1944 while (bus->parent) {
1945 struct pci_dev *bridge = bus->self;
1946
1947 if (device_run_wake(&bridge->dev))
1948 return true;
1949
1950 bus = bus->parent;
1951 }
1952
1953 /* We have reached the root bus. */
1954 if (bus->bridge)
1955 return device_run_wake(bus->bridge);
1956
1957 return false;
1958}
1959EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1960
b3c32c4f
HY		 1961void pci_config_pm_runtime_get(struct pci_dev *pdev)
1962{
1963 struct device *dev = &pdev->dev;
1964 struct device *parent = dev->parent;
1965
1966 if (parent)
1967 pm_runtime_get_sync(parent);
1968 pm_runtime_get_noresume(dev);
1969 /*
1970 * pdev->current_state is set to PCI_D3cold during suspending,
1971 * so wait until suspending completes
1972 */
1973 pm_runtime_barrier(dev);
1974 /*
1975 * Only need to resume devices in D3cold, because config
1976 * registers are still accessible for devices suspended but
1977 * not in D3cold.
1978 */
1979 if (pdev->current_state == PCI_D3cold)
1980 pm_runtime_resume(dev);
1981}
1982
1983void pci_config_pm_runtime_put(struct pci_dev *pdev)
1984{
1985 struct device *dev = &pdev->dev;
1986 struct device *parent = dev->parent;
1987
1988 pm_runtime_put(dev);
1989 if (parent)
1990 pm_runtime_put_sync(parent);
1991}
1992
eb9d0fe4
RW		 1993/**
1994 * pci_pm_init - Initialize PM functions of given PCI device
1995 * @dev: PCI device to handle.
1996 */
1997void pci_pm_init(struct pci_dev *dev)
1998{
1999 int pm;
2000 u16 pmc;
1da177e4 2001
bb910a70 2002 pm_runtime_forbid(&dev->dev);
967577b0
HY		 2003 pm_runtime_set_active(&dev->dev);
2004 pm_runtime_enable(&dev->dev);
a1e4d72c 2005 device_enable_async_suspend(&dev->dev);
e80bb09d 2006 dev->wakeup_prepared = false;
bb910a70 2007
337001b6 2008 dev->pm_cap = 0;
ffaddbe8 2009 dev->pme_support = 0;
337001b6 2010
eb9d0fe4
RW		 2011 /* find PCI PM capability in list */
2012 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2013 if (!pm)
50246dd4 2014 return;
eb9d0fe4
RW		 2015 /* Check device's ability to generate PME# */
2016 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 2017
eb9d0fe4
RW		 2018 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2019 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2020 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 2021 return;
eb9d0fe4
RW		 2022 }
2023
337001b6 2024 dev->pm_cap = pm;
1ae861e6 2025 dev->d3_delay = PCI_PM_D3_WAIT;
448bd857 2026 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
4f9c1397 2027 dev->d3cold_allowed = true;
337001b6
RW		 2028
2029 dev->d1_support = false;
2030 dev->d2_support = false;
2031 if (!pci_no_d1d2(dev)) {
c9ed77ee 2032 if (pmc & PCI_PM_CAP_D1)
337001b6 2033 dev->d1_support = true;
c9ed77ee 2034 if (pmc & PCI_PM_CAP_D2)
337001b6 2035 dev->d2_support = true;
c9ed77ee
BH		 2036
2037 if (dev->d1_support || dev->d2_support)
2038 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 2039 dev->d1_support ? " D1" : "",
2040 dev->d2_support ? " D2" : "");
337001b6
RW		 2041 }
2042
2043 pmc &= PCI_PM_CAP_PME_MASK;
2044 if (pmc) {
10c3d71d
BH		 2045 dev_printk(KERN_DEBUG, &dev->dev,
2046 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 2047 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2048 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2049 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2050 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2051 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 2052 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
379021d5 2053 dev->pme_poll = true;
eb9d0fe4
RW		 2054 /*
2055 * Make device's PM flags reflect the wake-up capability, but
2056 * let the user space enable it to wake up the system as needed.
2057 */
2058 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 2059 /* Disable the PME# generation functionality */
337001b6 2060 pci_pme_active(dev, false);
eb9d0fe4 2061 }
1da177e4
LT		 2062}
2063
34a4876e
YL		 2064static void pci_add_saved_cap(struct pci_dev *pci_dev,
2065 struct pci_cap_saved_state *new_cap)
2066{
2067 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2068}
2069
63f4898a 2070/**
fd0f7f73
AW		 2071 * _pci_add_cap_save_buffer - allocate buffer for saving given
2072 * capability registers
63f4898a
RW		 2073 * @dev: the PCI device
2074 * @cap: the capability to allocate the buffer for
fd0f7f73 2075 * @extended: Standard or Extended capability ID
63f4898a
RW		 2076 * @size: requested size of the buffer
2077 */
fd0f7f73
AW		 2078static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2079 bool extended, unsigned int size)
63f4898a
RW		 2080{
2081 int pos;
2082 struct pci_cap_saved_state *save_state;
2083
fd0f7f73
AW		 2084 if (extended)
2085 pos = pci_find_ext_capability(dev, cap);
2086 else
2087 pos = pci_find_capability(dev, cap);
2088
63f4898a
RW		 2089 if (pos <= 0)
2090 return 0;
2091
2092 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2093 if (!save_state)
2094 return -ENOMEM;
2095
24a4742f 2096 save_state->cap.cap_nr = cap;
fd0f7f73 2097 save_state->cap.cap_extended = extended;
24a4742f 2098 save_state->cap.size = size;
63f4898a
RW		 2099 pci_add_saved_cap(dev, save_state);
2100
2101 return 0;
2102}
2103
fd0f7f73
AW		 2104int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2105{
2106 return _pci_add_cap_save_buffer(dev, cap, false, size);
2107}
2108
2109int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2110{
2111 return _pci_add_cap_save_buffer(dev, cap, true, size);
2112}
2113
63f4898a
RW		 2114/**
2115 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2116 * @dev: the PCI device
2117 */
2118void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2119{
2120 int error;
2121
89858517
YZ		 2122 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2123 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 2124 if (error)
2125 dev_err(&dev->dev,
2126 "unable to preallocate PCI Express save buffer\n");
2127
2128 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2129 if (error)
2130 dev_err(&dev->dev,
2131 "unable to preallocate PCI-X save buffer\n");
425c1b22
AW		 2132
2133 pci_allocate_vc_save_buffers(dev);
63f4898a
RW		 2134}
2135
f796841e
YL		 2136void pci_free_cap_save_buffers(struct pci_dev *dev)
2137{
2138 struct pci_cap_saved_state *tmp;
b67bfe0d 2139 struct hlist_node *n;
f796841e 2140
b67bfe0d 2141 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
f796841e
YL		 2142 kfree(tmp);
2143}
2144
58c3a727 2145/**
31ab2476 2146 * pci_configure_ari - enable or disable ARI forwarding
58c3a727 2147 * @dev: the PCI device
b0cc6020
YW		 2148 *
2149 * If @dev and its upstream bridge both support ARI, enable ARI in the
2150 * bridge. Otherwise, disable ARI in the bridge.
58c3a727 2151 */
31ab2476 2152void pci_configure_ari(struct pci_dev *dev)
58c3a727 2153{
58c3a727 2154 u32 cap;
8113587c 2155 struct pci_dev *bridge;
58c3a727 2156
6748dcc2 2157 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 2158 return;
2159
8113587c 2160 bridge = dev->bus->self;
cb97ae34 2161 if (!bridge)
8113587c
ZY		 2162 return;
2163
59875ae4 2164 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 2165 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2166 return;
2167
b0cc6020
YW		 2168 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2169 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2170 PCI_EXP_DEVCTL2_ARI);
2171 bridge->ari_enabled = 1;
2172 } else {
2173 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2174 PCI_EXP_DEVCTL2_ARI);
2175 bridge->ari_enabled = 0;
2176 }
58c3a727
YZ		 2177}
2178
5d990b62
CW		 2179static int pci_acs_enable;
2180
2181/**
2182 * pci_request_acs - ask for ACS to be enabled if supported
2183 */
2184void pci_request_acs(void)
2185{
2186 pci_acs_enable = 1;
2187}
2188
ae21ee65
AK		 2189/**
2190 * pci_enable_acs - enable ACS if hardware support it
2191 * @dev: the PCI device
2192 */
2193void pci_enable_acs(struct pci_dev *dev)
2194{
2195 int pos;
2196 u16 cap;
2197 u16 ctrl;
2198
5d990b62
CW		 2199 if (!pci_acs_enable)
2200 return;
2201
ae21ee65
AK		 2202 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2203 if (!pos)
2204 return;
2205
2206 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2207 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2208
2209 /* Source Validation */
2210 ctrl |= (cap & PCI_ACS_SV);
2211
2212 /* P2P Request Redirect */
2213 ctrl |= (cap & PCI_ACS_RR);
2214
2215 /* P2P Completion Redirect */
2216 ctrl |= (cap & PCI_ACS_CR);
2217
2218 /* Upstream Forwarding */
2219 ctrl |= (cap & PCI_ACS_UF);
2220
2221 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2222}
2223
0a67119f
AW		 2224static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2225{
2226 int pos;
83db7e0b 2227 u16 cap, ctrl;
0a67119f
AW		 2228
2229 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2230 if (!pos)
2231 return false;
2232
83db7e0b
AW		 2233 /*
2234 * Except for egress control, capabilities are either required
2235 * or only required if controllable. Features missing from the
2236 * capability field can therefore be assumed as hard-wired enabled.
2237 */
2238 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2239 acs_flags &= (cap | PCI_ACS_EC);
2240
0a67119f
AW		 2241 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2242 return (ctrl & acs_flags) == acs_flags;
2243}
2244
ad805758
AW		 2245/**
2246 * pci_acs_enabled - test ACS against required flags for a given device
2247 * @pdev: device to test
2248 * @acs_flags: required PCI ACS flags
2249 *
2250 * Return true if the device supports the provided flags. Automatically
2251 * filters out flags that are not implemented on multifunction devices.
0a67119f
AW		 2252 *
2253 * Note that this interface checks the effective ACS capabilities of the
2254 * device rather than the actual capabilities. For instance, most single
2255 * function endpoints are not required to support ACS because they have no
2256 * opportunity for peer-to-peer access. We therefore return 'true'
2257 * regardless of whether the device exposes an ACS capability. This makes
2258 * it much easier for callers of this function to ignore the actual type
2259 * or topology of the device when testing ACS support.
ad805758
AW		 2260 */
2261bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2262{
0a67119f 2263 int ret;
ad805758
AW		 2264
2265 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2266 if (ret >= 0)
2267 return ret > 0;
2268
0a67119f
AW		 2269 /*
2270 * Conventional PCI and PCI-X devices never support ACS, either
2271 * effectively or actually. The shared bus topology implies that
2272 * any device on the bus can receive or snoop DMA.
2273 */
ad805758
AW		 2274 if (!pci_is_pcie(pdev))
2275 return false;
2276
0a67119f
AW		 2277 switch (pci_pcie_type(pdev)) {
2278 /*
2279 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
f7625980 2280 * but since their primary interface is PCI/X, we conservatively
0a67119f
AW		 2281 * handle them as we would a non-PCIe device.
2282 */
2283 case PCI_EXP_TYPE_PCIE_BRIDGE:
2284 /*
2285 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2286 * applicable... must never implement an ACS Extended Capability...".
2287 * This seems arbitrary, but we take a conservative interpretation
2288 * of this statement.
2289 */
2290 case PCI_EXP_TYPE_PCI_BRIDGE:
2291 case PCI_EXP_TYPE_RC_EC:
2292 return false;
2293 /*
2294 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2295 * implement ACS in order to indicate their peer-to-peer capabilities,
2296 * regardless of whether they are single- or multi-function devices.
2297 */
2298 case PCI_EXP_TYPE_DOWNSTREAM:
2299 case PCI_EXP_TYPE_ROOT_PORT:
2300 return pci_acs_flags_enabled(pdev, acs_flags);
2301 /*
2302 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2303 * implemented by the remaining PCIe types to indicate peer-to-peer
f7625980 2304 * capabilities, but only when they are part of a multifunction
0a67119f
AW		 2305 * device. The footnote for section 6.12 indicates the specific
2306 * PCIe types included here.
2307 */
2308 case PCI_EXP_TYPE_ENDPOINT:
2309 case PCI_EXP_TYPE_UPSTREAM:
2310 case PCI_EXP_TYPE_LEG_END:
2311 case PCI_EXP_TYPE_RC_END:
2312 if (!pdev->multifunction)
2313 break;
2314
0a67119f 2315 return pci_acs_flags_enabled(pdev, acs_flags);
ad805758
AW		 2316 }
2317
0a67119f 2318 /*
f7625980 2319 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
0a67119f
AW		 2320 * to single function devices with the exception of downstream ports.
2321 */
ad805758
AW		 2322 return true;
2323}
2324
2325/**
2326 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2327 * @start: starting downstream device
2328 * @end: ending upstream device or NULL to search to the root bus
2329 * @acs_flags: required flags
2330 *
2331 * Walk up a device tree from start to end testing PCI ACS support. If
2332 * any step along the way does not support the required flags, return false.
2333 */
2334bool pci_acs_path_enabled(struct pci_dev *start,
2335 struct pci_dev *end, u16 acs_flags)
2336{
2337 struct pci_dev *pdev, *parent = start;
2338
2339 do {
2340 pdev = parent;
2341
2342 if (!pci_acs_enabled(pdev, acs_flags))
2343 return false;
2344
2345 if (pci_is_root_bus(pdev->bus))
2346 return (end == NULL);
2347
2348 parent = pdev->bus->self;
2349 } while (pdev != end);
2350
2351 return true;
2352}
2353
57c2cf71
BH		 2354/**
2355 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2356 * @dev: the PCI device
bb5c2de2 2357 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
57c2cf71
BH		 2358 *
2359 * Perform INTx swizzling for a device behind one level of bridge. This is
2360 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2361 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2362 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2363 * the PCI Express Base Specification, Revision 2.1)
57c2cf71 2364 */
3df425f3 2365u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
57c2cf71 2366{
46b952a3
MW		 2367 int slot;
2368
2369 if (pci_ari_enabled(dev->bus))
2370 slot = 0;
2371 else
2372 slot = PCI_SLOT(dev->devfn);
2373
2374 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2375}
2376
1da177e4
LT		 2377int
2378pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2379{
2380 u8 pin;
2381
514d207d 2382 pin = dev->pin;
1da177e4
LT		 2383 if (!pin)
2384 return -1;
878f2e50 2385
8784fd4d 2386 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2387 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2388 dev = dev->bus->self;
2389 }
2390 *bridge = dev;
2391 return pin;
2392}
2393
68feac87
BH		 2394/**
2395 * pci_common_swizzle - swizzle INTx all the way to root bridge
2396 * @dev: the PCI device
2397 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2398 *
2399 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2400 * bridges all the way up to a PCI root bus.
2401 */
2402u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2403{
2404 u8 pin = *pinp;
2405
1eb39487 2406 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2407 pin = pci_swizzle_interrupt_pin(dev, pin);
2408 dev = dev->bus->self;
2409 }
2410 *pinp = pin;
2411 return PCI_SLOT(dev->devfn);
2412}
2413
1da177e4
LT		 2414/**
2415 * pci_release_region - Release a PCI bar
2416 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2417 * @bar: BAR to release
2418 *
2419 * Releases the PCI I/O and memory resources previously reserved by a
2420 * successful call to pci_request_region. Call this function only
2421 * after all use of the PCI regions has ceased.
2422 */
2423void pci_release_region(struct pci_dev *pdev, int bar)
2424{
9ac7849e
TH		 2425 struct pci_devres *dr;
2426
1da177e4
LT		 2427 if (pci_resource_len(pdev, bar) == 0)
2428 return;
2429 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2430 release_region(pci_resource_start(pdev, bar),
2431 pci_resource_len(pdev, bar));
2432 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2433 release_mem_region(pci_resource_start(pdev, bar),
2434 pci_resource_len(pdev, bar));
9ac7849e
TH		 2435
2436 dr = find_pci_dr(pdev);
2437 if (dr)
2438 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2439}
2440
2441/**
f5ddcac4 2442 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2443 * @pdev: PCI device whose resources are to be reserved
2444 * @bar: BAR to be reserved
2445 * @res_name: Name to be associated with resource.
f5ddcac4 2446 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2447 *
2448 * Mark the PCI region associated with PCI device @pdev BR @bar as
2449 * being reserved by owner @res_name. Do not access any
2450 * address inside the PCI regions unless this call returns
2451 * successfully.
2452 *
f5ddcac4
RD		 2453 * If @exclusive is set, then the region is marked so that userspace
2454 * is explicitly not allowed to map the resource via /dev/mem or
f7625980 2455 * sysfs MMIO access.
f5ddcac4 2456 *
1da177e4
LT		 2457 * Returns 0 on success, or %EBUSY on error. A warning
2458 * message is also printed on failure.
2459 */
e8de1481
AV		 2460static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2461 int exclusive)
1da177e4 2462{
9ac7849e
TH		 2463 struct pci_devres *dr;
2464
1da177e4
LT		 2465 if (pci_resource_len(pdev, bar) == 0)
2466 return 0;
f7625980 2467
1da177e4
LT		 2468 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2469 if (!request_region(pci_resource_start(pdev, bar),
2470 pci_resource_len(pdev, bar), res_name))
2471 goto err_out;
2472 }
2473 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2474 if (!__request_mem_region(pci_resource_start(pdev, bar),
2475 pci_resource_len(pdev, bar), res_name,
2476 exclusive))
1da177e4
LT		 2477 goto err_out;
2478 }
9ac7849e
TH		 2479
2480 dr = find_pci_dr(pdev);
2481 if (dr)
2482 dr->region_mask |= 1 << bar;
2483
1da177e4
LT		 2484 return 0;
2485
2486err_out:
c7dabef8 2487 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2488 &pdev->resource[bar]);
1da177e4
LT		 2489 return -EBUSY;
2490}
2491
e8de1481 2492/**
f5ddcac4 2493 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2494 * @pdev: PCI device whose resources are to be reserved
2495 * @bar: BAR to be reserved
f5ddcac4 2496 * @res_name: Name to be associated with resource
e8de1481 2497 *
f5ddcac4 2498 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2499 * being reserved by owner @res_name. Do not access any
2500 * address inside the PCI regions unless this call returns
2501 * successfully.
2502 *
2503 * Returns 0 on success, or %EBUSY on error. A warning
2504 * message is also printed on failure.
2505 */
2506int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2507{
2508 return __pci_request_region(pdev, bar, res_name, 0);
2509}
2510
2511/**
2512 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2513 * @pdev: PCI device whose resources are to be reserved
2514 * @bar: BAR to be reserved
2515 * @res_name: Name to be associated with resource.
2516 *
2517 * Mark the PCI region associated with PCI device @pdev BR @bar as
2518 * being reserved by owner @res_name. Do not access any
2519 * address inside the PCI regions unless this call returns
2520 * successfully.
2521 *
2522 * Returns 0 on success, or %EBUSY on error. A warning
2523 * message is also printed on failure.
2524 *
2525 * The key difference that _exclusive makes it that userspace is
2526 * explicitly not allowed to map the resource via /dev/mem or
f7625980 2527 * sysfs.
e8de1481
AV		 2528 */
2529int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2530{
2531 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2532}
c87deff7
HS		 2533/**
2534 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2535 * @pdev: PCI device whose resources were previously reserved
2536 * @bars: Bitmask of BARs to be released
2537 *
2538 * Release selected PCI I/O and memory resources previously reserved.
2539 * Call this function only after all use of the PCI regions has ceased.
2540 */
2541void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2542{
2543 int i;
2544
2545 for (i = 0; i < 6; i++)
2546 if (bars & (1 << i))
2547 pci_release_region(pdev, i);
2548}
2549
9738abed 2550static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
e8de1481 2551 const char *res_name, int excl)
c87deff7
HS		 2552{
2553 int i;
2554
2555 for (i = 0; i < 6; i++)
2556 if (bars & (1 << i))
e8de1481 2557 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2558 goto err_out;
2559 return 0;
2560
2561err_out:
2562 while(--i >= 0)
2563 if (bars & (1 << i))
2564 pci_release_region(pdev, i);
2565
2566 return -EBUSY;
2567}
1da177e4 2568
e8de1481
AV		 2569
2570/**
2571 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2572 * @pdev: PCI device whose resources are to be reserved
2573 * @bars: Bitmask of BARs to be requested
2574 * @res_name: Name to be associated with resource
2575 */
2576int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2577 const char *res_name)
2578{
2579 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2580}
2581
2582int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2583 int bars, const char *res_name)
2584{
2585 return __pci_request_selected_regions(pdev, bars, res_name,
2586 IORESOURCE_EXCLUSIVE);
2587}
2588
1da177e4
LT		 2589/**
2590 * pci_release_regions - Release reserved PCI I/O and memory resources
2591 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2592 *
2593 * Releases all PCI I/O and memory resources previously reserved by a
2594 * successful call to pci_request_regions. Call this function only
2595 * after all use of the PCI regions has ceased.
2596 */
2597
2598void pci_release_regions(struct pci_dev *pdev)
2599{
c87deff7 2600 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2601}
2602
2603/**
2604 * pci_request_regions - Reserved PCI I/O and memory resources
2605 * @pdev: PCI device whose resources are to be reserved
2606 * @res_name: Name to be associated with resource.
2607 *
2608 * Mark all PCI regions associated with PCI device @pdev as
2609 * being reserved by owner @res_name. Do not access any
2610 * address inside the PCI regions unless this call returns
2611 * successfully.
2612 *
2613 * Returns 0 on success, or %EBUSY on error. A warning
2614 * message is also printed on failure.
2615 */
3c990e92 2616int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2617{
c87deff7 2618 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2619}
2620
e8de1481
AV		 2621/**
2622 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2623 * @pdev: PCI device whose resources are to be reserved
2624 * @res_name: Name to be associated with resource.
2625 *
2626 * Mark all PCI regions associated with PCI device @pdev as
2627 * being reserved by owner @res_name. Do not access any
2628 * address inside the PCI regions unless this call returns
2629 * successfully.
2630 *
2631 * pci_request_regions_exclusive() will mark the region so that
f7625980 2632 * /dev/mem and the sysfs MMIO access will not be allowed.
e8de1481
AV		 2633 *
2634 * Returns 0 on success, or %EBUSY on error. A warning
2635 * message is also printed on failure.
2636 */
2637int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2638{
2639 return pci_request_selected_regions_exclusive(pdev,
2640 ((1 << 6) - 1), res_name);
2641}
2642
6a479079
BH		 2643static void __pci_set_master(struct pci_dev *dev, bool enable)
2644{
2645 u16 old_cmd, cmd;
2646
2647 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2648 if (enable)
2649 cmd = old_cmd | PCI_COMMAND_MASTER;
2650 else
2651 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2652 if (cmd != old_cmd) {
2653 dev_dbg(&dev->dev, "%s bus mastering\n",
2654 enable ? "enabling" : "disabling");
2655 pci_write_config_word(dev, PCI_COMMAND, cmd);
2656 }
2657 dev->is_busmaster = enable;
2658}
e8de1481 2659
2b6f2c35
MS		 2660/**
2661 * pcibios_setup - process "pci=" kernel boot arguments
2662 * @str: string used to pass in "pci=" kernel boot arguments
2663 *
2664 * Process kernel boot arguments. This is the default implementation.
2665 * Architecture specific implementations can override this as necessary.
2666 */
2667char * __weak __init pcibios_setup(char *str)
2668{
2669 return str;
2670}
2671
96c55900
MS		 2672/**
2673 * pcibios_set_master - enable PCI bus-mastering for device dev
2674 * @dev: the PCI device to enable
2675 *
2676 * Enables PCI bus-mastering for the device. This is the default
2677 * implementation. Architecture specific implementations can override
2678 * this if necessary.
2679 */
2680void __weak pcibios_set_master(struct pci_dev *dev)
2681{
2682 u8 lat;
2683
f676678f
MS		 2684 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2685 if (pci_is_pcie(dev))
2686 return;
2687
96c55900
MS		 2688 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2689 if (lat < 16)
2690 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2691 else if (lat > pcibios_max_latency)
2692 lat = pcibios_max_latency;
2693 else
2694 return;
a006482b 2695
96c55900
MS		 2696 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2697}
2698
1da177e4
LT		 2699/**
2700 * pci_set_master - enables bus-mastering for device dev
2701 * @dev: the PCI device to enable
2702 *
2703 * Enables bus-mastering on the device and calls pcibios_set_master()
2704 * to do the needed arch specific settings.
2705 */
6a479079 2706void pci_set_master(struct pci_dev *dev)
1da177e4 2707{
6a479079 2708 __pci_set_master(dev, true);
1da177e4
LT		 2709 pcibios_set_master(dev);
2710}
2711
6a479079
BH		 2712/**
2713 * pci_clear_master - disables bus-mastering for device dev
2714 * @dev: the PCI device to disable
2715 */
2716void pci_clear_master(struct pci_dev *dev)
2717{
2718 __pci_set_master(dev, false);
2719}
2720
1da177e4 2721/**
edb2d97e
MW		 2722 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2723 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2724 *
edb2d97e
MW		 2725 * Helper function for pci_set_mwi.
2726 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2727 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2728 *
2729 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2730 */
15ea76d4 2731int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2732{
2733 u8 cacheline_size;
2734
2735 if (!pci_cache_line_size)
15ea76d4 2736 return -EINVAL;
1da177e4
LT		 2737
2738 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2739 equal to or multiple of the right value. */
2740 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2741 if (cacheline_size >= pci_cache_line_size &&
2742 (cacheline_size % pci_cache_line_size) == 0)
2743 return 0;
2744
2745 /* Write the correct value. */
2746 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2747 /* Read it back. */
2748 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2749 if (cacheline_size == pci_cache_line_size)
2750 return 0;
2751
80ccba11
BH		 2752 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2753 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2754
2755 return -EINVAL;
2756}
15ea76d4
TH		 2757EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2758
2759#ifdef PCI_DISABLE_MWI
2760int pci_set_mwi(struct pci_dev *dev)
2761{
2762 return 0;
2763}
2764
2765int pci_try_set_mwi(struct pci_dev *dev)
2766{
2767 return 0;
2768}
2769
2770void pci_clear_mwi(struct pci_dev *dev)
2771{
2772}
2773
2774#else
1da177e4
LT		 2775
2776/**
2777 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2778 * @dev: the PCI device for which MWI is enabled
2779 *
694625c0 2780 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2781 *
2782 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2783 */
2784int
2785pci_set_mwi(struct pci_dev *dev)
2786{
2787 int rc;
2788 u16 cmd;
2789
edb2d97e 2790 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2791 if (rc)
2792 return rc;
2793
2794 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2795 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2796 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2797 cmd |= PCI_COMMAND_INVALIDATE;
2798 pci_write_config_word(dev, PCI_COMMAND, cmd);
2799 }
f7625980 2800
1da177e4
LT		 2801 return 0;
2802}
2803
694625c0
RD		 2804/**
2805 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2806 * @dev: the PCI device for which MWI is enabled
2807 *
2808 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2809 * Callers are not required to check the return value.
2810 *
2811 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2812 */
2813int pci_try_set_mwi(struct pci_dev *dev)
2814{
2815 int rc = pci_set_mwi(dev);
2816 return rc;
2817}
2818
1da177e4
LT		 2819/**
2820 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2821 * @dev: the PCI device to disable
2822 *
2823 * Disables PCI Memory-Write-Invalidate transaction on the device
2824 */
2825void
2826pci_clear_mwi(struct pci_dev *dev)
2827{
2828 u16 cmd;
2829
2830 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2831 if (cmd & PCI_COMMAND_INVALIDATE) {
2832 cmd &= ~PCI_COMMAND_INVALIDATE;
2833 pci_write_config_word(dev, PCI_COMMAND, cmd);
2834 }
2835}
edb2d97e 2836#endif /* ! PCI_DISABLE_MWI */
1da177e4 2837
a04ce0ff
BR		 2838/**
2839 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2840 * @pdev: the PCI device to operate on
2841 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2842 *
2843 * Enables/disables PCI INTx for device dev
2844 */
2845void
2846pci_intx(struct pci_dev *pdev, int enable)
2847{
2848 u16 pci_command, new;
2849
2850 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2851
2852 if (enable) {
2853 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2854 } else {
2855 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2856 }
2857
2858 if (new != pci_command) {
9ac7849e
TH		 2859 struct pci_devres *dr;
2860
2fd9d74b 2861 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2862
2863 dr = find_pci_dr(pdev);
2864 if (dr && !dr->restore_intx) {
2865 dr->restore_intx = 1;
2866 dr->orig_intx = !enable;
2867 }
a04ce0ff
BR		 2868 }
2869}
2870
a2e27787
JK		 2871/**
2872 * pci_intx_mask_supported - probe for INTx masking support
6e9292c5 2873 * @dev: the PCI device to operate on
a2e27787
JK		 2874 *
2875 * Check if the device dev support INTx masking via the config space
2876 * command word.
2877 */
2878bool pci_intx_mask_supported(struct pci_dev *dev)
2879{
2880 bool mask_supported = false;
2881 u16 orig, new;
2882
fbebb9fd
BH		 2883 if (dev->broken_intx_masking)
2884 return false;
2885
a2e27787
JK		 2886 pci_cfg_access_lock(dev);
2887
2888 pci_read_config_word(dev, PCI_COMMAND, &orig);
2889 pci_write_config_word(dev, PCI_COMMAND,
2890 orig ^ PCI_COMMAND_INTX_DISABLE);
2891 pci_read_config_word(dev, PCI_COMMAND, &new);
2892
2893 /*
2894 * There's no way to protect against hardware bugs or detect them
2895 * reliably, but as long as we know what the value should be, let's
2896 * go ahead and check it.
2897 */
2898 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2899 dev_err(&dev->dev, "Command register changed from "
2900 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2901 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2902 mask_supported = true;
2903 pci_write_config_word(dev, PCI_COMMAND, orig);
2904 }
2905
2906 pci_cfg_access_unlock(dev);
2907 return mask_supported;
2908}
2909EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2910
2911static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2912{
2913 struct pci_bus *bus = dev->bus;
2914 bool mask_updated = true;
2915 u32 cmd_status_dword;
2916 u16 origcmd, newcmd;
2917 unsigned long flags;
2918 bool irq_pending;
2919
2920 /*
2921 * We do a single dword read to retrieve both command and status.
2922 * Document assumptions that make this possible.
2923 */
2924 BUILD_BUG_ON(PCI_COMMAND % 4);
2925 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2926
2927 raw_spin_lock_irqsave(&pci_lock, flags);
2928
2929 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2930
2931 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2932
2933 /*
2934 * Check interrupt status register to see whether our device
2935 * triggered the interrupt (when masking) or the next IRQ is
2936 * already pending (when unmasking).
2937 */
2938 if (mask != irq_pending) {
2939 mask_updated = false;
2940 goto done;
2941 }
2942
2943 origcmd = cmd_status_dword;
2944 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2945 if (mask)
2946 newcmd |= PCI_COMMAND_INTX_DISABLE;
2947 if (newcmd != origcmd)
2948 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2949
2950done:
2951 raw_spin_unlock_irqrestore(&pci_lock, flags);
2952
2953 return mask_updated;
2954}
2955
2956/**
2957 * pci_check_and_mask_intx - mask INTx on pending interrupt
6e9292c5 2958 * @dev: the PCI device to operate on
a2e27787
JK		 2959 *
2960 * Check if the device dev has its INTx line asserted, mask it and
2961 * return true in that case. False is returned if not interrupt was
2962 * pending.
2963 */
2964bool pci_check_and_mask_intx(struct pci_dev *dev)
2965{
2966 return pci_check_and_set_intx_mask(dev, true);
2967}
2968EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2969
2970/**
ebd50b93 2971 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
6e9292c5 2972 * @dev: the PCI device to operate on
a2e27787
JK		 2973 *
2974 * Check if the device dev has its INTx line asserted, unmask it if not
2975 * and return true. False is returned and the mask remains active if
2976 * there was still an interrupt pending.
2977 */
2978bool pci_check_and_unmask_intx(struct pci_dev *dev)
2979{
2980 return pci_check_and_set_intx_mask(dev, false);
2981}
2982EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2983
f5f2b131 2984/**
da27f4b3 2985 * pci_msi_off - disables any MSI or MSI-X capabilities
8d7d86e9 2986 * @dev: the PCI device to operate on
f5f2b131 2987 *
da27f4b3
BH		 2988 * If you want to use MSI, see pci_enable_msi() and friends.
2989 * This is a lower-level primitive that allows us to disable
2990 * MSI operation at the device level.
f5f2b131
EB		 2991 */
2992void pci_msi_off(struct pci_dev *dev)
2993{
2994 int pos;
2995 u16 control;
2996
da27f4b3
BH		 2997 /*
2998 * This looks like it could go in msi.c, but we need it even when
2999 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3000 * dev->msi_cap or dev->msix_cap here.
3001 */
f5f2b131
EB		 3002 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3003 if (pos) {
3004 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3005 control &= ~PCI_MSI_FLAGS_ENABLE;
3006 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3007 }
3008 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3009 if (pos) {
3010 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3011 control &= ~PCI_MSIX_FLAGS_ENABLE;
3012 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3013 }
3014}
b03214d5 3015EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 3016
4d57cdfa
FT		 3017int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3018{
3019 return dma_set_max_seg_size(&dev->dev, size);
3020}
3021EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 3022
59fc67de
FT		 3023int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3024{
3025 return dma_set_seg_boundary(&dev->dev, mask);
3026}
3027EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 3028
3775a209
CL		 3029/**
3030 * pci_wait_for_pending_transaction - waits for pending transaction
3031 * @dev: the PCI device to operate on
3032 *
3033 * Return 0 if transaction is pending 1 otherwise.
3034 */
3035int pci_wait_for_pending_transaction(struct pci_dev *dev)
8dd7f803 3036{
157e876f
AW		 3037 if (!pci_is_pcie(dev))
3038 return 1;
8c1c699f 3039
157e876f 3040 return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
3775a209
CL		 3041}
3042EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3043
3044static int pcie_flr(struct pci_dev *dev, int probe)
3045{
3046 u32 cap;
3047
3048 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3049 if (!(cap & PCI_EXP_DEVCAP_FLR))
3050 return -ENOTTY;
3051
3052 if (probe)
3053 return 0;
3054
3055 if (!pci_wait_for_pending_transaction(dev))
3056 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
8c1c699f 3057
59875ae4 3058 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
04b55c47 3059
8c1c699f 3060 msleep(100);
8dd7f803 3061
8dd7f803
SY		 3062 return 0;
3063}
d91cdc74 3064
8c1c699f 3065static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 3066{
8c1c699f 3067 int pos;
1ca88797
SY		 3068 u8 cap;
3069
8c1c699f
YZ		 3070 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3071 if (!pos)
1ca88797 3072 return -ENOTTY;
8c1c699f
YZ		 3073
3074 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 3075 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3076 return -ENOTTY;
3077
3078 if (probe)
3079 return 0;
3080
1ca88797 3081 /* Wait for Transaction Pending bit clean */
157e876f
AW		 3082 if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
3083 goto clear;
5fe5db05 3084
8c1c699f
YZ		 3085 dev_err(&dev->dev, "transaction is not cleared; "
3086 "proceeding with reset anyway\n");
5fe5db05 3087
8c1c699f
YZ		 3088clear:
3089 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 3090 msleep(100);
8c1c699f 3091
1ca88797
SY		 3092 return 0;
3093}
3094
83d74e03
RW		 3095/**
3096 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3097 * @dev: Device to reset.
3098 * @probe: If set, only check if the device can be reset this way.
3099 *
3100 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3101 * unset, it will be reinitialized internally when going from PCI_D3hot to
3102 * PCI_D0. If that's the case and the device is not in a low-power state
3103 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3104 *
3105 * NOTE: This causes the caller to sleep for twice the device power transition
3106 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
f7625980 3107 * by default (i.e. unless the @dev's d3_delay field has a different value).
83d74e03
RW		 3108 * Moreover, only devices in D0 can be reset by this function.
3109 */
f85876ba 3110static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 3111{
f85876ba
YZ		 3112 u16 csr;
3113
3114 if (!dev->pm_cap)
3115 return -ENOTTY;
d91cdc74 3116
f85876ba
YZ		 3117 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3118 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3119 return -ENOTTY;
d91cdc74 3120
f85876ba
YZ		 3121 if (probe)
3122 return 0;
1ca88797 3123
f85876ba
YZ		 3124 if (dev->current_state != PCI_D0)
3125 return -EINVAL;
3126
3127 csr &= ~PCI_PM_CTRL_STATE_MASK;
3128 csr |= PCI_D3hot;
3129 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3130 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3131
3132 csr &= ~PCI_PM_CTRL_STATE_MASK;
3133 csr |= PCI_D0;
3134 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3135 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3136
3137 return 0;
3138}
3139
64e8674f
AW		 3140/**
3141 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3142 * @dev: Bridge device
3143 *
3144 * Use the bridge control register to assert reset on the secondary bus.
3145 * Devices on the secondary bus are left in power-on state.
3146 */
3147void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
c12ff1df
YZ		 3148{
3149 u16 ctrl;
64e8674f
AW		 3150
3151 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3152 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3153 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
de0c548c
AW		 3154 /*
3155 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
f7625980 3156 * this to 2ms to ensure that we meet the minimum requirement.
de0c548c
AW		 3157 */
3158 msleep(2);
64e8674f
AW		 3159
3160 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3161 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
de0c548c
AW		 3162
3163 /*
3164 * Trhfa for conventional PCI is 2^25 clock cycles.
3165 * Assuming a minimum 33MHz clock this results in a 1s
3166 * delay before we can consider subordinate devices to
3167 * be re-initialized. PCIe has some ways to shorten this,
3168 * but we don't make use of them yet.
3169 */
3170 ssleep(1);
64e8674f
AW		 3171}
3172EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3173
3174static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3175{
c12ff1df
YZ		 3176 struct pci_dev *pdev;
3177
654b75e0 3178 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 3179 return -ENOTTY;
3180
3181 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3182 if (pdev != dev)
3183 return -ENOTTY;
3184
3185 if (probe)
3186 return 0;
3187
64e8674f 3188 pci_reset_bridge_secondary_bus(dev->bus->self);
c12ff1df
YZ		 3189
3190 return 0;
3191}
3192
608c3881
AW		 3193static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3194{
3195 int rc = -ENOTTY;
3196
3197 if (!hotplug || !try_module_get(hotplug->ops->owner))
3198 return rc;
3199
3200 if (hotplug->ops->reset_slot)
3201 rc = hotplug->ops->reset_slot(hotplug, probe);
3202
3203 module_put(hotplug->ops->owner);
3204
3205 return rc;
3206}
3207
3208static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3209{
3210 struct pci_dev *pdev;
3211
3212 if (dev->subordinate || !dev->slot)
3213 return -ENOTTY;
3214
3215 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3216 if (pdev != dev && pdev->slot == dev->slot)
3217 return -ENOTTY;
3218
3219 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3220}
3221
977f857c 3222static int __pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 3223{
8c1c699f
YZ		 3224 int rc;
3225
3226 might_sleep();
3227
b9c3b266
DC		 3228 rc = pci_dev_specific_reset(dev, probe);
3229 if (rc != -ENOTTY)
3230 goto done;
3231
8c1c699f
YZ		 3232 rc = pcie_flr(dev, probe);
3233 if (rc != -ENOTTY)
3234 goto done;
d91cdc74 3235
8c1c699f 3236 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 3237 if (rc != -ENOTTY)
3238 goto done;
3239
3240 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 3241 if (rc != -ENOTTY)
3242 goto done;
3243
608c3881
AW		 3244 rc = pci_dev_reset_slot_function(dev, probe);
3245 if (rc != -ENOTTY)
3246 goto done;
3247
c12ff1df 3248 rc = pci_parent_bus_reset(dev, probe);
8c1c699f 3249done:
977f857c
KRW		 3250 return rc;
3251}
3252
77cb985a
AW		 3253static void pci_dev_lock(struct pci_dev *dev)
3254{
3255 pci_cfg_access_lock(dev);
3256 /* block PM suspend, driver probe, etc. */
3257 device_lock(&dev->dev);
3258}
3259
61cf16d8
AW		 3260/* Return 1 on successful lock, 0 on contention */
3261static int pci_dev_trylock(struct pci_dev *dev)
3262{
3263 if (pci_cfg_access_trylock(dev)) {
3264 if (device_trylock(&dev->dev))
3265 return 1;
3266 pci_cfg_access_unlock(dev);
3267 }
3268
3269 return 0;
3270}
3271
77cb985a
AW		 3272static void pci_dev_unlock(struct pci_dev *dev)
3273{
3274 device_unlock(&dev->dev);
3275 pci_cfg_access_unlock(dev);
3276}
3277
3278static void pci_dev_save_and_disable(struct pci_dev *dev)
3279{
a6cbaade
AW		 3280 /*
3281 * Wake-up device prior to save. PM registers default to D0 after
3282 * reset and a simple register restore doesn't reliably return
3283 * to a non-D0 state anyway.
3284 */
3285 pci_set_power_state(dev, PCI_D0);
3286
77cb985a
AW		 3287 pci_save_state(dev);
3288 /*
3289 * Disable the device by clearing the Command register, except for
3290 * INTx-disable which is set. This not only disables MMIO and I/O port
3291 * BARs, but also prevents the device from being Bus Master, preventing
3292 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3293 * compliant devices, INTx-disable prevents legacy interrupts.
3294 */
3295 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3296}
3297
3298static void pci_dev_restore(struct pci_dev *dev)
3299{
3300 pci_restore_state(dev);
3301}
3302
977f857c
KRW		 3303static int pci_dev_reset(struct pci_dev *dev, int probe)
3304{
3305 int rc;
3306
77cb985a
AW		 3307 if (!probe)
3308 pci_dev_lock(dev);
977f857c
KRW		 3309
3310 rc = __pci_dev_reset(dev, probe);
3311
77cb985a
AW		 3312 if (!probe)
3313 pci_dev_unlock(dev);
3314
8c1c699f 3315 return rc;
d91cdc74 3316}
d91cdc74 3317/**
8c1c699f
YZ		 3318 * __pci_reset_function - reset a PCI device function
3319 * @dev: PCI device to reset
d91cdc74
SY		 3320 *
3321 * Some devices allow an individual function to be reset without affecting
3322 * other functions in the same device. The PCI device must be responsive
3323 * to PCI config space in order to use this function.
3324 *
3325 * The device function is presumed to be unused when this function is called.
3326 * Resetting the device will make the contents of PCI configuration space
3327 * random, so any caller of this must be prepared to reinitialise the
3328 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3329 * etc.
3330 *
8c1c699f 3331 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 3332 * device doesn't support resetting a single function.
3333 */
8c1c699f 3334int __pci_reset_function(struct pci_dev *dev)
d91cdc74 3335{
8c1c699f 3336 return pci_dev_reset(dev, 0);
d91cdc74 3337}
8c1c699f 3338EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 3339
6fbf9e7a
KRW		 3340/**
3341 * __pci_reset_function_locked - reset a PCI device function while holding
3342 * the @dev mutex lock.
3343 * @dev: PCI device to reset
3344 *
3345 * Some devices allow an individual function to be reset without affecting
3346 * other functions in the same device. The PCI device must be responsive
3347 * to PCI config space in order to use this function.
3348 *
3349 * The device function is presumed to be unused and the caller is holding
3350 * the device mutex lock when this function is called.
3351 * Resetting the device will make the contents of PCI configuration space
3352 * random, so any caller of this must be prepared to reinitialise the
3353 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3354 * etc.
3355 *
3356 * Returns 0 if the device function was successfully reset or negative if the
3357 * device doesn't support resetting a single function.
3358 */
3359int __pci_reset_function_locked(struct pci_dev *dev)
3360{
977f857c 3361 return __pci_dev_reset(dev, 0);
6fbf9e7a
KRW		 3362}
3363EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3364
711d5779
MT		 3365/**
3366 * pci_probe_reset_function - check whether the device can be safely reset
3367 * @dev: PCI device to reset
3368 *
3369 * Some devices allow an individual function to be reset without affecting
3370 * other functions in the same device. The PCI device must be responsive
3371 * to PCI config space in order to use this function.
3372 *
3373 * Returns 0 if the device function can be reset or negative if the
3374 * device doesn't support resetting a single function.
3375 */
3376int pci_probe_reset_function(struct pci_dev *dev)
3377{
3378 return pci_dev_reset(dev, 1);
3379}
3380
8dd7f803 3381/**
8c1c699f
YZ		 3382 * pci_reset_function - quiesce and reset a PCI device function
3383 * @dev: PCI device to reset
8dd7f803
SY		 3384 *
3385 * Some devices allow an individual function to be reset without affecting
3386 * other functions in the same device. The PCI device must be responsive
3387 * to PCI config space in order to use this function.
3388 *
3389 * This function does not just reset the PCI portion of a device, but
3390 * clears all the state associated with the device. This function differs
8c1c699f 3391 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 3392 * over the reset.
3393 *
8c1c699f 3394 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 3395 * device doesn't support resetting a single function.
3396 */
3397int pci_reset_function(struct pci_dev *dev)
3398{
8c1c699f 3399 int rc;
8dd7f803 3400
8c1c699f
YZ		 3401 rc = pci_dev_reset(dev, 1);
3402 if (rc)
3403 return rc;
8dd7f803 3404
77cb985a 3405 pci_dev_save_and_disable(dev);
8dd7f803 3406
8c1c699f 3407 rc = pci_dev_reset(dev, 0);
8dd7f803 3408
77cb985a 3409 pci_dev_restore(dev);
8dd7f803 3410
8c1c699f 3411 return rc;
8dd7f803
SY		 3412}
3413EXPORT_SYMBOL_GPL(pci_reset_function);
3414
61cf16d8
AW		 3415/**
3416 * pci_try_reset_function - quiesce and reset a PCI device function
3417 * @dev: PCI device to reset
3418 *
3419 * Same as above, except return -EAGAIN if unable to lock device.
3420 */
3421int pci_try_reset_function(struct pci_dev *dev)
3422{
3423 int rc;
3424
3425 rc = pci_dev_reset(dev, 1);
3426 if (rc)
3427 return rc;
3428
3429 pci_dev_save_and_disable(dev);
3430
3431 if (pci_dev_trylock(dev)) {
3432 rc = __pci_dev_reset(dev, 0);
3433 pci_dev_unlock(dev);
3434 } else
3435 rc = -EAGAIN;
3436
3437 pci_dev_restore(dev);
3438
3439 return rc;
3440}
3441EXPORT_SYMBOL_GPL(pci_try_reset_function);
3442
090a3c53
AW		 3443/* Lock devices from the top of the tree down */
3444static void pci_bus_lock(struct pci_bus *bus)
3445{
3446 struct pci_dev *dev;
3447
3448 list_for_each_entry(dev, &bus->devices, bus_list) {
3449 pci_dev_lock(dev);
3450 if (dev->subordinate)
3451 pci_bus_lock(dev->subordinate);
3452 }
3453}
3454
3455/* Unlock devices from the bottom of the tree up */
3456static void pci_bus_unlock(struct pci_bus *bus)
3457{
3458 struct pci_dev *dev;
3459
3460 list_for_each_entry(dev, &bus->devices, bus_list) {
3461 if (dev->subordinate)
3462 pci_bus_unlock(dev->subordinate);
3463 pci_dev_unlock(dev);
3464 }
3465}
3466
61cf16d8
AW		 3467/* Return 1 on successful lock, 0 on contention */
3468static int pci_bus_trylock(struct pci_bus *bus)
3469{
3470 struct pci_dev *dev;
3471
3472 list_for_each_entry(dev, &bus->devices, bus_list) {
3473 if (!pci_dev_trylock(dev))
3474 goto unlock;
3475 if (dev->subordinate) {
3476 if (!pci_bus_trylock(dev->subordinate)) {
3477 pci_dev_unlock(dev);
3478 goto unlock;
3479 }
3480 }
3481 }
3482 return 1;
3483
3484unlock:
3485 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3486 if (dev->subordinate)
3487 pci_bus_unlock(dev->subordinate);
3488 pci_dev_unlock(dev);
3489 }
3490 return 0;
3491}
3492
090a3c53
AW		 3493/* Lock devices from the top of the tree down */
3494static void pci_slot_lock(struct pci_slot *slot)
3495{
3496 struct pci_dev *dev;
3497
3498 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3499 if (!dev->slot || dev->slot != slot)
3500 continue;
3501 pci_dev_lock(dev);
3502 if (dev->subordinate)
3503 pci_bus_lock(dev->subordinate);
3504 }
3505}
3506
3507/* Unlock devices from the bottom of the tree up */
3508static void pci_slot_unlock(struct pci_slot *slot)
3509{
3510 struct pci_dev *dev;
3511
3512 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3513 if (!dev->slot || dev->slot != slot)
3514 continue;
3515 if (dev->subordinate)
3516 pci_bus_unlock(dev->subordinate);
3517 pci_dev_unlock(dev);
3518 }
3519}
3520
61cf16d8
AW		 3521/* Return 1 on successful lock, 0 on contention */
3522static int pci_slot_trylock(struct pci_slot *slot)
3523{
3524 struct pci_dev *dev;
3525
3526 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3527 if (!dev->slot || dev->slot != slot)
3528 continue;
3529 if (!pci_dev_trylock(dev))
3530 goto unlock;
3531 if (dev->subordinate) {
3532 if (!pci_bus_trylock(dev->subordinate)) {
3533 pci_dev_unlock(dev);
3534 goto unlock;
3535 }
3536 }
3537 }
3538 return 1;
3539
3540unlock:
3541 list_for_each_entry_continue_reverse(dev,
3542 &slot->bus->devices, bus_list) {
3543 if (!dev->slot || dev->slot != slot)
3544 continue;
3545 if (dev->subordinate)
3546 pci_bus_unlock(dev->subordinate);
3547 pci_dev_unlock(dev);
3548 }
3549 return 0;
3550}
3551
090a3c53
AW		 3552/* Save and disable devices from the top of the tree down */
3553static void pci_bus_save_and_disable(struct pci_bus *bus)
3554{
3555 struct pci_dev *dev;
3556
3557 list_for_each_entry(dev, &bus->devices, bus_list) {
3558 pci_dev_save_and_disable(dev);
3559 if (dev->subordinate)
3560 pci_bus_save_and_disable(dev->subordinate);
3561 }
3562}
3563
3564/*
3565 * Restore devices from top of the tree down - parent bridges need to be
3566 * restored before we can get to subordinate devices.
3567 */
3568static void pci_bus_restore(struct pci_bus *bus)
3569{
3570 struct pci_dev *dev;
3571
3572 list_for_each_entry(dev, &bus->devices, bus_list) {
3573 pci_dev_restore(dev);
3574 if (dev->subordinate)
3575 pci_bus_restore(dev->subordinate);
3576 }
3577}
3578
3579/* Save and disable devices from the top of the tree down */
3580static void pci_slot_save_and_disable(struct pci_slot *slot)
3581{
3582 struct pci_dev *dev;
3583
3584 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3585 if (!dev->slot || dev->slot != slot)
3586 continue;
3587 pci_dev_save_and_disable(dev);
3588 if (dev->subordinate)
3589 pci_bus_save_and_disable(dev->subordinate);
3590 }
3591}
3592
3593/*
3594 * Restore devices from top of the tree down - parent bridges need to be
3595 * restored before we can get to subordinate devices.
3596 */
3597static void pci_slot_restore(struct pci_slot *slot)
3598{
3599 struct pci_dev *dev;
3600
3601 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3602 if (!dev->slot || dev->slot != slot)
3603 continue;
3604 pci_dev_restore(dev);
3605 if (dev->subordinate)
3606 pci_bus_restore(dev->subordinate);
3607 }
3608}
3609
3610static int pci_slot_reset(struct pci_slot *slot, int probe)
3611{
3612 int rc;
3613
3614 if (!slot)
3615 return -ENOTTY;
3616
3617 if (!probe)
3618 pci_slot_lock(slot);
3619
3620 might_sleep();
3621
3622 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3623
3624 if (!probe)
3625 pci_slot_unlock(slot);
3626
3627 return rc;
3628}
3629
9a3d2b9b
AW		 3630/**
3631 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3632 * @slot: PCI slot to probe
3633 *
3634 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3635 */
3636int pci_probe_reset_slot(struct pci_slot *slot)
3637{
3638 return pci_slot_reset(slot, 1);
3639}
3640EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3641
090a3c53
AW		 3642/**
3643 * pci_reset_slot - reset a PCI slot
3644 * @slot: PCI slot to reset
3645 *
3646 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3647 * independent of other slots. For instance, some slots may support slot power
3648 * control. In the case of a 1:1 bus to slot architecture, this function may
3649 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3650 * Generally a slot reset should be attempted before a bus reset. All of the
3651 * function of the slot and any subordinate buses behind the slot are reset
3652 * through this function. PCI config space of all devices in the slot and
3653 * behind the slot is saved before and restored after reset.
3654 *
3655 * Return 0 on success, non-zero on error.
3656 */
3657int pci_reset_slot(struct pci_slot *slot)
3658{
3659 int rc;
3660
3661 rc = pci_slot_reset(slot, 1);
3662 if (rc)
3663 return rc;
3664
3665 pci_slot_save_and_disable(slot);
3666
3667 rc = pci_slot_reset(slot, 0);
3668
3669 pci_slot_restore(slot);
3670
3671 return rc;
3672}
3673EXPORT_SYMBOL_GPL(pci_reset_slot);
3674
61cf16d8
AW		 3675/**
3676 * pci_try_reset_slot - Try to reset a PCI slot
3677 * @slot: PCI slot to reset
3678 *
3679 * Same as above except return -EAGAIN if the slot cannot be locked
3680 */
3681int pci_try_reset_slot(struct pci_slot *slot)
3682{
3683 int rc;
3684
3685 rc = pci_slot_reset(slot, 1);
3686 if (rc)
3687 return rc;
3688
3689 pci_slot_save_and_disable(slot);
3690
3691 if (pci_slot_trylock(slot)) {
3692 might_sleep();
3693 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3694 pci_slot_unlock(slot);
3695 } else
3696 rc = -EAGAIN;
3697
3698 pci_slot_restore(slot);
3699
3700 return rc;
3701}
3702EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3703
090a3c53
AW		 3704static int pci_bus_reset(struct pci_bus *bus, int probe)
3705{
3706 if (!bus->self)
3707 return -ENOTTY;
3708
3709 if (probe)
3710 return 0;
3711
3712 pci_bus_lock(bus);
3713
3714 might_sleep();
3715
3716 pci_reset_bridge_secondary_bus(bus->self);
3717
3718 pci_bus_unlock(bus);
3719
3720 return 0;
3721}
3722
9a3d2b9b
AW		 3723/**
3724 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3725 * @bus: PCI bus to probe
3726 *
3727 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3728 */
3729int pci_probe_reset_bus(struct pci_bus *bus)
3730{
3731 return pci_bus_reset(bus, 1);
3732}
3733EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3734
090a3c53
AW		 3735/**
3736 * pci_reset_bus - reset a PCI bus
3737 * @bus: top level PCI bus to reset
3738 *
3739 * Do a bus reset on the given bus and any subordinate buses, saving
3740 * and restoring state of all devices.
3741 *
3742 * Return 0 on success, non-zero on error.
3743 */
3744int pci_reset_bus(struct pci_bus *bus)
3745{
3746 int rc;
3747
3748 rc = pci_bus_reset(bus, 1);
3749 if (rc)
3750 return rc;
3751
3752 pci_bus_save_and_disable(bus);
3753
3754 rc = pci_bus_reset(bus, 0);
3755
3756 pci_bus_restore(bus);
3757
3758 return rc;
3759}
3760EXPORT_SYMBOL_GPL(pci_reset_bus);
3761
61cf16d8
AW		 3762/**
3763 * pci_try_reset_bus - Try to reset a PCI bus
3764 * @bus: top level PCI bus to reset
3765 *
3766 * Same as above except return -EAGAIN if the bus cannot be locked
3767 */
3768int pci_try_reset_bus(struct pci_bus *bus)
3769{
3770 int rc;
3771
3772 rc = pci_bus_reset(bus, 1);
3773 if (rc)
3774 return rc;
3775
3776 pci_bus_save_and_disable(bus);
3777
3778 if (pci_bus_trylock(bus)) {
3779 might_sleep();
3780 pci_reset_bridge_secondary_bus(bus->self);
3781 pci_bus_unlock(bus);
3782 } else
3783 rc = -EAGAIN;
3784
3785 pci_bus_restore(bus);
3786
3787 return rc;
3788}
3789EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3790
d556ad4b
PO		 3791/**
3792 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3793 * @dev: PCI device to query
3794 *
3795 * Returns mmrbc: maximum designed memory read count in bytes
3796 * or appropriate error value.
3797 */
3798int pcix_get_max_mmrbc(struct pci_dev *dev)
3799{
7c9e2b1c 3800 int cap;
d556ad4b
PO		 3801 u32 stat;
3802
3803 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3804 if (!cap)
3805 return -EINVAL;
3806
7c9e2b1c 3807 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 3808 return -EINVAL;
3809
25daeb55 3810 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 3811}
3812EXPORT_SYMBOL(pcix_get_max_mmrbc);
3813
3814/**
3815 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3816 * @dev: PCI device to query
3817 *
3818 * Returns mmrbc: maximum memory read count in bytes
3819 * or appropriate error value.
3820 */
3821int pcix_get_mmrbc(struct pci_dev *dev)
3822{
7c9e2b1c 3823 int cap;
bdc2bda7 3824 u16 cmd;
d556ad4b
PO		 3825
3826 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3827 if (!cap)
3828 return -EINVAL;
3829
7c9e2b1c
DN		 3830 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3831 return -EINVAL;
d556ad4b 3832
7c9e2b1c 3833 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3834}
3835EXPORT_SYMBOL(pcix_get_mmrbc);
3836
3837/**
3838 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3839 * @dev: PCI device to query
3840 * @mmrbc: maximum memory read count in bytes
3841 * valid values are 512, 1024, 2048, 4096
3842 *
3843 * If possible sets maximum memory read byte count, some bridges have erratas
3844 * that prevent this.
3845 */
3846int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3847{
7c9e2b1c 3848 int cap;
bdc2bda7
DN		 3849 u32 stat, v, o;
3850 u16 cmd;
d556ad4b 3851
229f5afd 3852 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3853 return -EINVAL;
d556ad4b
PO		 3854
3855 v = ffs(mmrbc) - 10;
3856
3857 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3858 if (!cap)
7c9e2b1c 3859 return -EINVAL;
d556ad4b 3860
7c9e2b1c
DN		 3861 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3862 return -EINVAL;
d556ad4b
PO		 3863
3864 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3865 return -E2BIG;
3866
7c9e2b1c
DN		 3867 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3868 return -EINVAL;
d556ad4b
PO		 3869
3870 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3871 if (o != v) {
809a3bf9 3872 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
d556ad4b
PO		 3873 return -EIO;
3874
3875 cmd &= ~PCI_X_CMD_MAX_READ;
3876 cmd |= v << 2;
7c9e2b1c
DN		 3877 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3878 return -EIO;
d556ad4b 3879 }
7c9e2b1c 3880 return 0;
d556ad4b
PO		 3881}
3882EXPORT_SYMBOL(pcix_set_mmrbc);
3883
3884/**
3885 * pcie_get_readrq - get PCI Express read request size
3886 * @dev: PCI device to query
3887 *
3888 * Returns maximum memory read request in bytes
3889 * or appropriate error value.
3890 */
3891int pcie_get_readrq(struct pci_dev *dev)
3892{
d556ad4b
PO		 3893 u16 ctl;
3894
59875ae4 3895 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
d556ad4b 3896
59875ae4 3897 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3898}
3899EXPORT_SYMBOL(pcie_get_readrq);
3900
3901/**
3902 * pcie_set_readrq - set PCI Express maximum memory read request
3903 * @dev: PCI device to query
42e61f4a 3904 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3905 * valid values are 128, 256, 512, 1024, 2048, 4096
3906 *
c9b378c7 3907 * If possible sets maximum memory read request in bytes
d556ad4b
PO		 3908 */
3909int pcie_set_readrq(struct pci_dev *dev, int rq)
3910{
59875ae4 3911 u16 v;
d556ad4b 3912
229f5afd 3913 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
59875ae4 3914 return -EINVAL;
d556ad4b 3915
a1c473aa
BH		 3916 /*
3917 * If using the "performance" PCIe config, we clamp the
3918 * read rq size to the max packet size to prevent the
3919 * host bridge generating requests larger than we can
3920 * cope with
3921 */
3922 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3923 int mps = pcie_get_mps(dev);
3924
a1c473aa
BH		 3925 if (mps < rq)
3926 rq = mps;
3927 }
3928
3929 v = (ffs(rq) - 8) << 12;
d556ad4b 3930
59875ae4
JL		 3931 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3932 PCI_EXP_DEVCTL_READRQ, v);
d556ad4b
PO		 3933}
3934EXPORT_SYMBOL(pcie_set_readrq);
3935
b03e7495
JM		 3936/**
3937 * pcie_get_mps - get PCI Express maximum payload size
3938 * @dev: PCI device to query
3939 *
3940 * Returns maximum payload size in bytes
b03e7495
JM		 3941 */
3942int pcie_get_mps(struct pci_dev *dev)
3943{
b03e7495
JM		 3944 u16 ctl;
3945
59875ae4 3946 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
b03e7495 3947
59875ae4 3948 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
b03e7495 3949}
f1c66c46 3950EXPORT_SYMBOL(pcie_get_mps);
b03e7495
JM		 3951
3952/**
3953 * pcie_set_mps - set PCI Express maximum payload size
3954 * @dev: PCI device to query
47c08f31 3955 * @mps: maximum payload size in bytes
b03e7495
JM		 3956 * valid values are 128, 256, 512, 1024, 2048, 4096
3957 *
3958 * If possible sets maximum payload size
3959 */
3960int pcie_set_mps(struct pci_dev *dev, int mps)
3961{
59875ae4 3962 u16 v;
b03e7495
JM		 3963
3964 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
59875ae4 3965 return -EINVAL;
b03e7495
JM		 3966
3967 v = ffs(mps) - 8;
f7625980 3968 if (v > dev->pcie_mpss)
59875ae4 3969 return -EINVAL;
b03e7495
JM		 3970 v <<= 5;
3971
59875ae4
JL		 3972 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3973 PCI_EXP_DEVCTL_PAYLOAD, v);
b03e7495 3974}
f1c66c46 3975EXPORT_SYMBOL(pcie_set_mps);
b03e7495 3976
81377c8d
JK		 3977/**
3978 * pcie_get_minimum_link - determine minimum link settings of a PCI device
3979 * @dev: PCI device to query
3980 * @speed: storage for minimum speed
3981 * @width: storage for minimum width
3982 *
3983 * This function will walk up the PCI device chain and determine the minimum
3984 * link width and speed of the device.
3985 */
3986int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
3987 enum pcie_link_width *width)
3988{
3989 int ret;
3990
3991 *speed = PCI_SPEED_UNKNOWN;
3992 *width = PCIE_LNK_WIDTH_UNKNOWN;
3993
3994 while (dev) {
3995 u16 lnksta;
3996 enum pci_bus_speed next_speed;
3997 enum pcie_link_width next_width;
3998
3999 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4000 if (ret)
4001 return ret;
4002
4003 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4004 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4005 PCI_EXP_LNKSTA_NLW_SHIFT;
4006
4007 if (next_speed < *speed)
4008 *speed = next_speed;
4009
4010 if (next_width < *width)
4011 *width = next_width;
4012
4013 dev = dev->bus->self;
4014 }
4015
4016 return 0;
4017}
4018EXPORT_SYMBOL(pcie_get_minimum_link);
4019
c87deff7
HS		 4020/**
4021 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 4022 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 4023 * @flags: resource type mask to be selected
4024 *
4025 * This helper routine makes bar mask from the type of resource.
4026 */
4027int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4028{
4029 int i, bars = 0;
4030 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4031 if (pci_resource_flags(dev, i) & flags)
4032 bars |= (1 << i);
4033 return bars;
4034}
4035
613e7ed6
YZ		 4036/**
4037 * pci_resource_bar - get position of the BAR associated with a resource
4038 * @dev: the PCI device
4039 * @resno: the resource number
4040 * @type: the BAR type to be filled in
4041 *
4042 * Returns BAR position in config space, or 0 if the BAR is invalid.
4043 */
4044int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4045{
d1b054da
YZ		 4046 int reg;
4047
613e7ed6
YZ		 4048 if (resno < PCI_ROM_RESOURCE) {
4049 *type = pci_bar_unknown;
4050 return PCI_BASE_ADDRESS_0 + 4 * resno;
4051 } else if (resno == PCI_ROM_RESOURCE) {
4052 *type = pci_bar_mem32;
4053 return dev->rom_base_reg;
d1b054da
YZ		 4054 } else if (resno < PCI_BRIDGE_RESOURCES) {
4055 /* device specific resource */
4056 reg = pci_iov_resource_bar(dev, resno, type);
4057 if (reg)
4058 return reg;
613e7ed6
YZ		 4059 }
4060
865df576 4061 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 4062 return 0;
4063}
4064
95a8b6ef
MT		 4065/* Some architectures require additional programming to enable VGA */
4066static arch_set_vga_state_t arch_set_vga_state;
4067
4068void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4069{
4070 arch_set_vga_state = func; /* NULL disables */
4071}
4072
4073static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
7ad35cf2 4074 unsigned int command_bits, u32 flags)
95a8b6ef
MT		 4075{
4076 if (arch_set_vga_state)
4077 return arch_set_vga_state(dev, decode, command_bits,
7ad35cf2 4078 flags);
95a8b6ef
MT		 4079 return 0;
4080}
4081
deb2d2ec
BH		 4082/**
4083 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 4084 * @dev: the PCI device
4085 * @decode: true = enable decoding, false = disable decoding
4086 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3f37d622 4087 * @flags: traverse ancestors and change bridges
3448a19d 4088 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
deb2d2ec
BH		 4089 */
4090int pci_set_vga_state(struct pci_dev *dev, bool decode,
3448a19d 4091 unsigned int command_bits, u32 flags)
deb2d2ec
BH		 4092{
4093 struct pci_bus *bus;
4094 struct pci_dev *bridge;
4095 u16 cmd;
95a8b6ef 4096 int rc;
deb2d2ec 4097
3448a19d 4098 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
deb2d2ec 4099
95a8b6ef 4100 /* ARCH specific VGA enables */
3448a19d 4101 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
95a8b6ef
MT		 4102 if (rc)
4103 return rc;
4104
3448a19d
DA		 4105 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4106 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4107 if (decode == true)
4108 cmd |= command_bits;
4109 else
4110 cmd &= ~command_bits;
4111 pci_write_config_word(dev, PCI_COMMAND, cmd);
4112 }
deb2d2ec 4113
3448a19d 4114 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
deb2d2ec
BH		 4115 return 0;
4116
4117 bus = dev->bus;
4118 while (bus) {
4119 bridge = bus->self;
4120 if (bridge) {
4121 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4122 &cmd);
4123 if (decode == true)
4124 cmd |= PCI_BRIDGE_CTL_VGA;
4125 else
4126 cmd &= ~PCI_BRIDGE_CTL_VGA;
4127 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4128 cmd);
4129 }
4130 bus = bus->parent;
4131 }
4132 return 0;
4133}
4134
8496e85c
RW		 4135bool pci_device_is_present(struct pci_dev *pdev)
4136{
4137 u32 v;
4138
4139 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4140}
4141EXPORT_SYMBOL_GPL(pci_device_is_present);
4142
32a9a682
YS		 4143#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4144static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 4145static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 4146
4147/**
4148 * pci_specified_resource_alignment - get resource alignment specified by user.
4149 * @dev: the PCI device to get
4150 *
4151 * RETURNS: Resource alignment if it is specified.
4152 * Zero if it is not specified.
4153 */
9738abed 4154static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
32a9a682
YS		 4155{
4156 int seg, bus, slot, func, align_order, count;
4157 resource_size_t align = 0;
4158 char *p;
4159
4160 spin_lock(&resource_alignment_lock);
4161 p = resource_alignment_param;
4162 while (*p) {
4163 count = 0;
4164 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4165 p[count] == '@') {
4166 p += count + 1;
4167 } else {
4168 align_order = -1;
4169 }
4170 if (sscanf(p, "%x:%x:%x.%x%n",
4171 &seg, &bus, &slot, &func, &count) != 4) {
4172 seg = 0;
4173 if (sscanf(p, "%x:%x.%x%n",
4174 &bus, &slot, &func, &count) != 3) {
4175 /* Invalid format */
4176 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4177 p);
4178 break;
4179 }
4180 }
4181 p += count;
4182 if (seg == pci_domain_nr(dev->bus) &&
4183 bus == dev->bus->number &&
4184 slot == PCI_SLOT(dev->devfn) &&
4185 func == PCI_FUNC(dev->devfn)) {
4186 if (align_order == -1) {
4187 align = PAGE_SIZE;
4188 } else {
4189 align = 1 << align_order;
4190 }
4191 /* Found */
4192 break;
4193 }
4194 if (*p != ';' && *p != ',') {
4195 /* End of param or invalid format */
4196 break;
4197 }
4198 p++;
4199 }
4200 spin_unlock(&resource_alignment_lock);
4201 return align;
4202}
4203
2069ecfb
YL		 4204/*
4205 * This function disables memory decoding and releases memory resources
4206 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4207 * It also rounds up size to specified alignment.
4208 * Later on, the kernel will assign page-aligned memory resource back
4209 * to the device.
4210 */
4211void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4212{
4213 int i;
4214 struct resource *r;
4215 resource_size_t align, size;
4216 u16 command;
4217
10c463a7
YL		 4218 /* check if specified PCI is target device to reassign */
4219 align = pci_specified_resource_alignment(dev);
4220 if (!align)
2069ecfb
YL		 4221 return;
4222
4223 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4224 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4225 dev_warn(&dev->dev,
4226 "Can't reassign resources to host bridge.\n");
4227 return;
4228 }
4229
4230 dev_info(&dev->dev,
4231 "Disabling memory decoding and releasing memory resources.\n");
4232 pci_read_config_word(dev, PCI_COMMAND, &command);
4233 command &= ~PCI_COMMAND_MEMORY;
4234 pci_write_config_word(dev, PCI_COMMAND, command);
4235
2069ecfb
YL		 4236 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4237 r = &dev->resource[i];
4238 if (!(r->flags & IORESOURCE_MEM))
4239 continue;
4240 size = resource_size(r);
4241 if (size < align) {
4242 size = align;
4243 dev_info(&dev->dev,
4244 "Rounding up size of resource #%d to %#llx.\n",
4245 i, (unsigned long long)size);
4246 }
4247 r->end = size - 1;
4248 r->start = 0;
4249 }
4250 /* Need to disable bridge's resource window,
4251 * to enable the kernel to reassign new resource
4252 * window later on.
4253 */
4254 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4255 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4256 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4257 r = &dev->resource[i];
4258 if (!(r->flags & IORESOURCE_MEM))
4259 continue;
4260 r->end = resource_size(r) - 1;
4261 r->start = 0;
4262 }
4263 pci_disable_bridge_window(dev);
4264 }
4265}
4266
9738abed 4267static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
32a9a682
YS		 4268{
4269 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4270 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4271 spin_lock(&resource_alignment_lock);
4272 strncpy(resource_alignment_param, buf, count);
4273 resource_alignment_param[count] = '\0';
4274 spin_unlock(&resource_alignment_lock);
4275 return count;
4276}
4277
9738abed 4278static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
32a9a682
YS		 4279{
4280 size_t count;
4281 spin_lock(&resource_alignment_lock);
4282 count = snprintf(buf, size, "%s", resource_alignment_param);
4283 spin_unlock(&resource_alignment_lock);
4284 return count;
4285}
4286
4287static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4288{
4289 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4290}
4291
4292static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4293 const char *buf, size_t count)
4294{
4295 return pci_set_resource_alignment_param(buf, count);
4296}
4297
4298BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4299 pci_resource_alignment_store);
4300
4301static int __init pci_resource_alignment_sysfs_init(void)
4302{
4303 return bus_create_file(&pci_bus_type,
4304 &bus_attr_resource_alignment);
4305}
4306
4307late_initcall(pci_resource_alignment_sysfs_init);
4308
15856ad5 4309static void pci_no_domains(void)
32a2eea7
JG		 4310{
4311#ifdef CONFIG_PCI_DOMAINS
4312 pci_domains_supported = 0;
4313#endif
4314}
4315
0ef5f8f6 4316/**
642c92da 4317 * pci_ext_cfg_avail - can we access extended PCI config space?
0ef5f8f6
AP		 4318 *
4319 * Returns 1 if we can access PCI extended config space (offsets
4320 * greater than 0xff). This is the default implementation. Architecture
4321 * implementations can override this.
4322 */
642c92da 4323int __weak pci_ext_cfg_avail(void)
0ef5f8f6
AP		 4324{
4325 return 1;
4326}
4327
2d1c8618
BH		 4328void __weak pci_fixup_cardbus(struct pci_bus *bus)
4329{
4330}
4331EXPORT_SYMBOL(pci_fixup_cardbus);
4332
ad04d31e 4333static int __init pci_setup(char *str)
1da177e4
LT		 4334{
4335 while (str) {
4336 char *k = strchr(str, ',');
4337 if (k)
4338 *k++ = 0;
4339 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 4340 if (!strcmp(str, "nomsi")) {
4341 pci_no_msi();
7f785763
RD		 4342 } else if (!strcmp(str, "noaer")) {
4343 pci_no_aer();
b55438fd
YL		 4344 } else if (!strncmp(str, "realloc=", 8)) {
4345 pci_realloc_get_opt(str + 8);
f483d392 4346 } else if (!strncmp(str, "realloc", 7)) {
b55438fd 4347 pci_realloc_get_opt("on");
32a2eea7
JG		 4348 } else if (!strcmp(str, "nodomains")) {
4349 pci_no_domains();
6748dcc2
RW		 4350 } else if (!strncmp(str, "noari", 5)) {
4351 pcie_ari_disabled = true;
4516a618
AN		 4352 } else if (!strncmp(str, "cbiosize=", 9)) {
4353 pci_cardbus_io_size = memparse(str + 9, &str);
4354 } else if (!strncmp(str, "cbmemsize=", 10)) {
4355 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 4356 } else if (!strncmp(str, "resource_alignment=", 19)) {
4357 pci_set_resource_alignment_param(str + 19,
4358 strlen(str + 19));
43c16408
AP		 4359 } else if (!strncmp(str, "ecrc=", 5)) {
4360 pcie_ecrc_get_policy(str + 5);
28760489
EB		 4361 } else if (!strncmp(str, "hpiosize=", 9)) {
4362 pci_hotplug_io_size = memparse(str + 9, &str);
4363 } else if (!strncmp(str, "hpmemsize=", 10)) {
4364 pci_hotplug_mem_size = memparse(str + 10, &str);
5f39e670
JM		 4365 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4366 pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495
JM		 4367 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4368 pcie_bus_config = PCIE_BUS_SAFE;
4369 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4370 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5f39e670
JM		 4371 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4372 pcie_bus_config = PCIE_BUS_PEER2PEER;
284f5f9d
BH		 4373 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4374 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
309e57df
MW		 4375 } else {
4376 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4377 str);
4378 }
1da177e4
LT		 4379 }
4380 str = k;
4381 }
0637a70a 4382 return 0;
1da177e4 4383}
0637a70a 4384early_param("pci", pci_setup);
1da177e4 4385
0b62e13b 4386EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 4387EXPORT_SYMBOL(pci_enable_device_io);
4388EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 4389EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 4390EXPORT_SYMBOL(pcim_enable_device);
4391EXPORT_SYMBOL(pcim_pin_device);
1da177e4 4392EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 4393EXPORT_SYMBOL(pci_find_capability);
4394EXPORT_SYMBOL(pci_bus_find_capability);
4395EXPORT_SYMBOL(pci_release_regions);
4396EXPORT_SYMBOL(pci_request_regions);
e8de1481 4397EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 4398EXPORT_SYMBOL(pci_release_region);
4399EXPORT_SYMBOL(pci_request_region);
e8de1481 4400EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 4401EXPORT_SYMBOL(pci_release_selected_regions);
4402EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 4403EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 4404EXPORT_SYMBOL(pci_set_master);
6a479079 4405EXPORT_SYMBOL(pci_clear_master);
1da177e4 4406EXPORT_SYMBOL(pci_set_mwi);
694625c0 4407EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 4408EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 4409EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 4410EXPORT_SYMBOL(pci_assign_resource);
4411EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 4412EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 4413
4414EXPORT_SYMBOL(pci_set_power_state);
4415EXPORT_SYMBOL(pci_save_state);
4416EXPORT_SYMBOL(pci_restore_state);
e5899e1b 4417EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 4418EXPORT_SYMBOL(pci_pme_active);
0235c4fc 4419EXPORT_SYMBOL(pci_wake_from_d3);
404cc2d8
RW		 4420EXPORT_SYMBOL(pci_prepare_to_sleep);
4421EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 4422EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linux kernel - Deliverables
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